drivers/gpu/drm/radeon/radeon_drv.c

   1 /**
   2  * \file radeon_drv.c
   3  * ATI Radeon driver
   4  *
   5  * \author Gareth Hughes <gareth@valinux.com>
   6  */
   7
   8 /*
   9  * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
  10  * All Rights Reserved.
  11  *
  12  * Permission is hereby granted, free of charge, to any person obtaining a
  13  * copy of this software and associated documentation files (the "Software"),
  14  * to deal in the Software without restriction, including without limitation
  15  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  16  * and/or sell copies of the Software, and to permit persons to whom the
  17  * Software is furnished to do so, subject to the following conditions:
  18  *
  19  * The above copyright notice and this permission notice (including the next
  20  * paragraph) shall be included in all copies or substantial portions of the
  21  * Software.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  24  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  25  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  26  * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  27  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  28  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  29  * OTHER DEALINGS IN THE SOFTWARE.
  30  */
  31
  32 #include <drm/drmP.h>
  33 #include <drm/radeon_drm.h>
  34 #include "radeon_drv.h"
  35
  36 #include <drm/drm_pciids.h>
  37 #include <linux/console.h>
  38 #include <linux/module.h>
  39 #include <linux/pm_runtime.h>
  40 #include <linux/vga_switcheroo.h>
  41 #include "drm_crtc_helper.h"
  42 /*
  43  * KMS wrapper.
  44  * - 2.0.0 - initial interface
  45  * - 2.1.0 - add square tiling interface
  46  * - 2.2.0 - add r6xx/r7xx const buffer support
  47  * - 2.3.0 - add MSPOS + 3D texture + r500 VAP regs
  48  * - 2.4.0 - add crtc id query
  49  * - 2.5.0 - add get accel 2 to work around ddx breakage for evergreen
  50  * - 2.6.0 - add tiling config query (r6xx+), add initial HiZ support (r300->r500)
  51  *   2.7.0 - fixups for r600 2D tiling support. (no external ABI change), add eg dyn gpr regs
  52  *   2.8.0 - pageflip support, r500 US_FORMAT regs. r500 ARGB2101010 colorbuf, r300->r500 CMASK, clock crystal query
  53  *   2.9.0 - r600 tiling (s3tc,rgtc) working, SET_PREDICATION packet 3 on r600 + eg, backend query
  54  *   2.10.0 - fusion 2D tiling
  55  *   2.11.0 - backend map, initial compute support for the CS checker
  56  *   2.12.0 - RADEON_CS_KEEP_TILING_FLAGS
  57  *   2.13.0 - virtual memory support, streamout
  58  *   2.14.0 - add evergreen tiling informations
  59  *   2.15.0 - add max_pipes query
  60  *   2.16.0 - fix evergreen 2D tiled surface calculation
  61  *   2.17.0 - add STRMOUT_BASE_UPDATE for r7xx
  62  *   2.18.0 - r600-eg: allow "invalid" DB formats
  63  *   2.19.0 - r600-eg: MSAA textures
  64  *   2.20.0 - r600-si: RADEON_INFO_TIMESTAMP query
  65  *   2.21.0 - r600-r700: FMASK and CMASK
  66  *   2.22.0 - r600 only: RESOLVE_BOX allowed
  67  *   2.23.0 - allow STRMOUT_BASE_UPDATE on RS780 and RS880
  68  *   2.24.0 - eg only: allow MIP_ADDRESS=0 for MSAA textures
  69  *   2.25.0 - eg+: new info request for num SE and num SH
  70  *   2.26.0 - r600-eg: fix htile size computation
  71  *   2.27.0 - r600-SI: Add CS ioctl support for async DMA
  72  *   2.28.0 - r600-eg: Add MEM_WRITE packet support
  73  *   2.29.0 - R500 FP16 color clear registers
  74  *   2.30.0 - fix for FMASK texturing
  75  *   2.31.0 - Add fastfb support for rs690
  76  *   2.32.0 - new info request for rings working
  77  *   2.33.0 - Add SI tiling mode array query
  78  *   2.34.0 - Add CIK tiling mode array query
  79  *   2.35.0 - Add CIK macrotile mode array query
  80  *   2.36.0 - Fix CIK DCE tiling setup
  81  *   2.37.0 - allow GS ring setup on r6xx/r7xx
  82  *   2.38.0 - RADEON_GEM_OP (GET_INITIAL_DOMAIN, SET_INITIAL_DOMAIN),
  83  *            CIK: 1D and linear tiling modes contain valid PIPE_CONFIG
  84  *   2.39.0 - Add INFO query for number of active CUs
  85  *   2.40.0 - Add RADEON_GEM_GTT_WC/UC, flush HDP cache before submitting
  86  *            CS to GPU
  87  */
  88 #define KMS_DRIVER_MAJOR        2
  89 #define KMS_DRIVER_MINOR        40
  90 #define KMS_DRIVER_PATCHLEVEL   0
  91 int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags);
  92 int radeon_driver_unload_kms(struct drm_device *dev);
  93 void radeon_driver_lastclose_kms(struct drm_device *dev);
  94 int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);
  95 void radeon_driver_postclose_kms(struct drm_device *dev,
  96                                  struct drm_file *file_priv);
  97 void radeon_driver_preclose_kms(struct drm_device *dev,
  98                                 struct drm_file *file_priv);
  99 int radeon_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon);
 100 int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
 101 u32 radeon_get_vblank_counter_kms(struct drm_device *dev, int crtc);
 102 int radeon_enable_vblank_kms(struct drm_device *dev, int crtc);
 103 void radeon_disable_vblank_kms(struct drm_device *dev, int crtc);
 104 int radeon_get_vblank_timestamp_kms(struct drm_device *dev, int crtc,
 105                                     int *max_error,
 106                                     struct timeval *vblank_time,
 107                                     unsigned flags);
 108 void radeon_driver_irq_preinstall_kms(struct drm_device *dev);
 109 int radeon_driver_irq_postinstall_kms(struct drm_device *dev);
 110 void radeon_driver_irq_uninstall_kms(struct drm_device *dev);
 111 irqreturn_t radeon_driver_irq_handler_kms(int irq, void *arg);
 112 void radeon_gem_object_free(struct drm_gem_object *obj);
 113 int radeon_gem_object_open(struct drm_gem_object *obj,
 114                                 struct drm_file *file_priv);
 115 void radeon_gem_object_close(struct drm_gem_object *obj,
 116                                 struct drm_file *file_priv);
 117 extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc,
 118                                       unsigned int flags,
 119                                       int *vpos, int *hpos, ktime_t *stime,
 120                                       ktime_t *etime);
 121 extern bool radeon_is_px(struct drm_device *dev);
 122 extern const struct drm_ioctl_desc radeon_ioctls_kms[];
 123 extern int radeon_max_kms_ioctl;
 124 int radeon_mmap(struct file *filp, struct vm_area_struct *vma);
 125 int radeon_mode_dumb_mmap(struct drm_file *filp,
 126                           struct drm_device *dev,
 127                           uint32_t handle, uint64_t *offset_p);
 128 int radeon_mode_dumb_create(struct drm_file *file_priv,
 129                             struct drm_device *dev,
 130                             struct drm_mode_create_dumb *args);
 131 struct sg_table *radeon_gem_prime_get_sg_table(struct drm_gem_object *obj);
 132 struct drm_gem_object *radeon_gem_prime_import_sg_table(struct drm_device *dev,
 133                                                         size_t size,
 134                                                         struct sg_table *sg);
 135 int radeon_gem_prime_pin(struct drm_gem_object *obj);
 136 void radeon_gem_prime_unpin(struct drm_gem_object *obj);
 137 struct reservation_object *radeon_gem_prime_res_obj(struct drm_gem_object *);
 138 void *radeon_gem_prime_vmap(struct drm_gem_object *obj);
 139 void radeon_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
 140 extern long radeon_kms_compat_ioctl(struct file *filp, unsigned int cmd,
 141                                     unsigned long arg);
 142
 143 #if defined(CONFIG_DEBUG_FS)
 144 int radeon_debugfs_init(struct drm_minor *minor);
 145 void radeon_debugfs_cleanup(struct drm_minor *minor);
 146 #endif
 147
 148 /* atpx handler */
 149 #if defined(CONFIG_VGA_SWITCHEROO)
 150 void radeon_register_atpx_handler(void);
 151 void radeon_unregister_atpx_handler(void);
 152 #else
 153 static inline void radeon_register_atpx_handler(void) {}
 154 static inline void radeon_unregister_atpx_handler(void) {}
 155 #endif
 156
 157 int radeon_no_wb;
 158 int radeon_modeset = -1;
 159 int radeon_dynclks = -1;
 160 int radeon_r4xx_atom = 0;
 161 int radeon_agpmode = 0;
 162 int radeon_vram_limit = 0;
 163 int radeon_gart_size = -1; /* auto */
 164 int radeon_benchmarking = 0;
 165 int radeon_testing = 0;
 166 int radeon_connector_table = 0;
 167 int radeon_tv = 1;
 168 int radeon_audio = -1;
 169 int radeon_disp_priority = 0;
 170 int radeon_hw_i2c = 0;
 171 int radeon_pcie_gen2 = -1;
 172 int radeon_msi = -1;
 173 int radeon_lockup_timeout = 10000;
 174 int radeon_fastfb = 0;
 175 int radeon_dpm = -1;
 176 int radeon_aspm = -1;
 177 int radeon_runtime_pm = -1;
 178 int radeon_hard_reset = 0;
 179 int radeon_vm_size = 8;
 180 int radeon_vm_block_size = -1;
 181 int radeon_deep_color = 0;
 182 int radeon_use_pflipirq = 2;
 183
 184 MODULE_PARM_DESC(no_wb, "Disable AGP writeback for scratch registers");
 185 module_param_named(no_wb, radeon_no_wb, int, 0444);
 186
 187 MODULE_PARM_DESC(modeset, "Disable/Enable modesetting");
 188 module_param_named(modeset, radeon_modeset, int, 0400);
 189
 190 MODULE_PARM_DESC(dynclks, "Disable/Enable dynamic clocks");
 191 module_param_named(dynclks, radeon_dynclks, int, 0444);
 192
 193 MODULE_PARM_DESC(r4xx_atom, "Enable ATOMBIOS modesetting for R4xx");
 194 module_param_named(r4xx_atom, radeon_r4xx_atom, int, 0444);
 195
 196 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes");
 197 module_param_named(vramlimit, radeon_vram_limit, int, 0600);
 198
 199 MODULE_PARM_DESC(agpmode, "AGP Mode (-1 == PCI)");
 200 module_param_named(agpmode, radeon_agpmode, int, 0444);
 201
 202 MODULE_PARM_DESC(gartsize, "Size of PCIE/IGP gart to setup in megabytes (32, 64, etc., -1 = auto)");
 203 module_param_named(gartsize, radeon_gart_size, int, 0600);
 204
 205 MODULE_PARM_DESC(benchmark, "Run benchmark");
 206 module_param_named(benchmark, radeon_benchmarking, int, 0444);
 207
 208 MODULE_PARM_DESC(test, "Run tests");
 209 module_param_named(test, radeon_testing, int, 0444);
 210
 211 MODULE_PARM_DESC(connector_table, "Force connector table");
 212 module_param_named(connector_table, radeon_connector_table, int, 0444);
 213
 214 MODULE_PARM_DESC(tv, "TV enable (0 = disable)");
 215 module_param_named(tv, radeon_tv, int, 0444);
 216
 217 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)");
 218 module_param_named(audio, radeon_audio, int, 0444);
 219
 220 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)");
 221 module_param_named(disp_priority, radeon_disp_priority, int, 0444);
 222
 223 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)");
 224 module_param_named(hw_i2c, radeon_hw_i2c, int, 0444);
 225
 226 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)");
 227 module_param_named(pcie_gen2, radeon_pcie_gen2, int, 0444);
 228
 229 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)");
 230 module_param_named(msi, radeon_msi, int, 0444);
 231
 232 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (defaul 10000 = 10 seconds, 0 = disable)");
 233 module_param_named(lockup_timeout, radeon_lockup_timeout, int, 0444);
 234
 235 MODULE_PARM_DESC(fastfb, "Direct FB access for IGP chips (0 = disable, 1 = enable)");
 236 module_param_named(fastfb, radeon_fastfb, int, 0444);
 237
 238 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)");
 239 module_param_named(dpm, radeon_dpm, int, 0444);
 240
 241 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)");
 242 module_param_named(aspm, radeon_aspm, int, 0444);
 243
 244 MODULE_PARM_DESC(runpm, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)");
 245 module_param_named(runpm, radeon_runtime_pm, int, 0444);
 246
 247 MODULE_PARM_DESC(hard_reset, "PCI config reset (1 = force enable, 0 = disable (default))");
 248 module_param_named(hard_reset, radeon_hard_reset, int, 0444);
 249
 250 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 4GB)");
 251 module_param_named(vm_size, radeon_vm_size, int, 0444);
 252
 253 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)");
 254 module_param_named(vm_block_size, radeon_vm_block_size, int, 0444);
 255
 256 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))");
 257 module_param_named(deep_color, radeon_deep_color, int, 0444);
 258
 259 MODULE_PARM_DESC(use_pflipirq, "Pflip irqs for pageflip completion (0 = disable, 1 = as fallback, 2 = exclusive (default))");
 260 module_param_named(use_pflipirq, radeon_use_pflipirq, int, 0444);
 261
 262 static struct pci_device_id pciidlist[] = {
 263         radeon_PCI_IDS
 264 };
 265
 266 MODULE_DEVICE_TABLE(pci, pciidlist);
 267
 268 #ifdef CONFIG_DRM_RADEON_UMS
 269
 270 static int radeon_suspend(struct drm_device *dev, pm_message_t state)
 271 {
 272         drm_radeon_private_t *dev_priv = dev->dev_private;
 273
 274         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
 275                 return 0;
 276
 277         /* Disable *all* interrupts */
 278         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600)
 279                 RADEON_WRITE(R500_DxMODE_INT_MASK, 0);
 280         RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
 281         return 0;
 282 }
 283
 284 static int radeon_resume(struct drm_device *dev)
 285 {
 286         drm_radeon_private_t *dev_priv = dev->dev_private;
 287
 288         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
 289                 return 0;
 290
 291         /* Restore interrupt registers */
 292         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600)
 293                 RADEON_WRITE(R500_DxMODE_INT_MASK, dev_priv->r500_disp_irq_reg);
 294         RADEON_WRITE(RADEON_GEN_INT_CNTL, dev_priv->irq_enable_reg);
 295         return 0;
 296 }
 297
 298
 299 static const struct file_operations radeon_driver_old_fops = {
 300         .owner = THIS_MODULE,
 301         .open = drm_open,
 302         .release = drm_release,
 303         .unlocked_ioctl = drm_ioctl,
 304         .mmap = drm_mmap,
 305         .poll = drm_poll,
 306         .read = drm_read,
 307 #ifdef CONFIG_COMPAT
 308         .compat_ioctl = radeon_compat_ioctl,
 309 #endif
 310         .llseek = noop_llseek,
 311 };
 312
 313 static struct drm_driver driver_old = {
 314         .driver_features =
 315             DRIVER_USE_AGP | DRIVER_PCI_DMA | DRIVER_SG |
 316             DRIVER_HAVE_IRQ | DRIVER_HAVE_DMA | DRIVER_IRQ_SHARED,
 317         .dev_priv_size = sizeof(drm_radeon_buf_priv_t),
 318         .load = radeon_driver_load,
 319         .firstopen = radeon_driver_firstopen,
 320         .open = radeon_driver_open,
 321         .preclose = radeon_driver_preclose,
 322         .postclose = radeon_driver_postclose,
 323         .lastclose = radeon_driver_lastclose,
 324         .unload = radeon_driver_unload,
 325         .suspend = radeon_suspend,
 326         .resume = radeon_resume,
 327         .get_vblank_counter = radeon_get_vblank_counter,
 328         .enable_vblank = radeon_enable_vblank,
 329         .disable_vblank = radeon_disable_vblank,
 330         .master_create = radeon_master_create,
 331         .master_destroy = radeon_master_destroy,
 332         .irq_preinstall = radeon_driver_irq_preinstall,
 333         .irq_postinstall = radeon_driver_irq_postinstall,
 334         .irq_uninstall = radeon_driver_irq_uninstall,
 335         .irq_handler = radeon_driver_irq_handler,
 336         .ioctls = radeon_ioctls,
 337         .dma_ioctl = radeon_cp_buffers,
 338         .fops = &radeon_driver_old_fops,
 339         .name = DRIVER_NAME,
 340         .desc = DRIVER_DESC,
 341         .date = DRIVER_DATE,
 342         .major = DRIVER_MAJOR,
 343         .minor = DRIVER_MINOR,
 344         .patchlevel = DRIVER_PATCHLEVEL,
 345 };
 346
 347 #endif
 348
 349 static struct drm_driver kms_driver;
 350
 351 static int radeon_kick_out_firmware_fb(struct pci_dev *pdev)
 352 {
 353         struct apertures_struct *ap;
 354         bool primary = false;
 355
 356         ap = alloc_apertures(1);
 357         if (!ap)
 358                 return -ENOMEM;
 359
 360         ap->ranges[0].base = pci_resource_start(pdev, 0);
 361         ap->ranges[0].size = pci_resource_len(pdev, 0);
 362
 363 #ifdef CONFIG_X86
 364         primary = pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
 365 #endif
 366         remove_conflicting_framebuffers(ap, "radeondrmfb", primary);
 367         kfree(ap);
 368
 369         return 0;
 370 }
 371
 372 static int radeon_pci_probe(struct pci_dev *pdev,
 373                             const struct pci_device_id *ent)
 374 {
 375         int ret;
 376
 377         /* Get rid of things like offb */
 378         ret = radeon_kick_out_firmware_fb(pdev);
 379         if (ret)
 380                 return ret;
 381
 382         return drm_get_pci_dev(pdev, ent, &kms_driver);
 383 }
 384
 385 static void
 386 radeon_pci_remove(struct pci_dev *pdev)
 387 {
 388         struct drm_device *dev = pci_get_drvdata(pdev);
 389
 390         drm_put_dev(dev);
 391 }
 392
 393 static int radeon_pmops_suspend(struct device *dev)
 394 {
 395         struct pci_dev *pdev = to_pci_dev(dev);
 396         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 397         return radeon_suspend_kms(drm_dev, true, true);
 398 }
 399
 400 static int radeon_pmops_resume(struct device *dev)
 401 {
 402         struct pci_dev *pdev = to_pci_dev(dev);
 403         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 404         return radeon_resume_kms(drm_dev, true, true);
 405 }
 406
 407 static int radeon_pmops_freeze(struct device *dev)
 408 {
 409         struct pci_dev *pdev = to_pci_dev(dev);
 410         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 411         return radeon_suspend_kms(drm_dev, false, true);
 412 }
 413
 414 static int radeon_pmops_thaw(struct device *dev)
 415 {
 416         struct pci_dev *pdev = to_pci_dev(dev);
 417         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 418         return radeon_resume_kms(drm_dev, false, true);
 419 }
 420
 421 static int radeon_pmops_runtime_suspend(struct device *dev)
 422 {
 423         struct pci_dev *pdev = to_pci_dev(dev);
 424         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 425         int ret;
 426
 427         if (!radeon_is_px(drm_dev)) {
 428                 pm_runtime_forbid(dev);
 429                 return -EBUSY;
 430         }
 431
 432         drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 433         drm_kms_helper_poll_disable(drm_dev);
 434         vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_OFF);
 435
 436         ret = radeon_suspend_kms(drm_dev, false, false);
 437         pci_save_state(pdev);
 438         pci_disable_device(pdev);
 439         pci_set_power_state(pdev, PCI_D3cold);
 440         drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF;
 441
 442         return 0;
 443 }
 444
 445 static int radeon_pmops_runtime_resume(struct device *dev)
 446 {
 447         struct pci_dev *pdev = to_pci_dev(dev);
 448         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 449         int ret;
 450
 451         if (!radeon_is_px(drm_dev))
 452                 return -EINVAL;
 453
 454         drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 455
 456         pci_set_power_state(pdev, PCI_D0);
 457         pci_restore_state(pdev);
 458         ret = pci_enable_device(pdev);
 459         if (ret)
 460                 return ret;
 461         pci_set_master(pdev);
 462
 463         ret = radeon_resume_kms(drm_dev, false, false);
 464         drm_kms_helper_poll_enable(drm_dev);
 465         vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_ON);
 466         drm_dev->switch_power_state = DRM_SWITCH_POWER_ON;
 467         return 0;
 468 }
 469
 470 static int radeon_pmops_runtime_idle(struct device *dev)
 471 {
 472         struct pci_dev *pdev = to_pci_dev(dev);
 473         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 474         struct drm_crtc *crtc;
 475
 476         if (!radeon_is_px(drm_dev)) {
 477                 pm_runtime_forbid(dev);
 478                 return -EBUSY;
 479         }
 480
 481         list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head) {
 482                 if (crtc->enabled) {
 483                         DRM_DEBUG_DRIVER("failing to power off - crtc active\n");
 484                         return -EBUSY;
 485                 }
 486         }
 487
 488         pm_runtime_mark_last_busy(dev);
 489         pm_runtime_autosuspend(dev);
 490         /* we don't want the main rpm_idle to call suspend - we want to autosuspend */
 491         return 1;
 492 }
 493
 494 long radeon_drm_ioctl(struct file *filp,
 495                       unsigned int cmd, unsigned long arg)
 496 {
 497         struct drm_file *file_priv = filp->private_data;
 498         struct drm_device *dev;
 499         long ret;
 500         dev = file_priv->minor->dev;
 501         ret = pm_runtime_get_sync(dev->dev);
 502         if (ret < 0)
 503                 return ret;
 504
 505         ret = drm_ioctl(filp, cmd, arg);
 506
 507         pm_runtime_mark_last_busy(dev->dev);
 508         pm_runtime_put_autosuspend(dev->dev);
 509         return ret;
 510 }
 511
 512 static const struct dev_pm_ops radeon_pm_ops = {
 513         .suspend = radeon_pmops_suspend,
 514         .resume = radeon_pmops_resume,
 515         .freeze = radeon_pmops_freeze,
 516         .thaw = radeon_pmops_thaw,
 517         .poweroff = radeon_pmops_freeze,
 518         .restore = radeon_pmops_resume,
 519         .runtime_suspend = radeon_pmops_runtime_suspend,
 520         .runtime_resume = radeon_pmops_runtime_resume,
 521         .runtime_idle = radeon_pmops_runtime_idle,
 522 };
 523
 524 static const struct file_operations radeon_driver_kms_fops = {
 525         .owner = THIS_MODULE,
 526         .open = drm_open,
 527         .release = drm_release,
 528         .unlocked_ioctl = radeon_drm_ioctl,
 529         .mmap = radeon_mmap,
 530         .poll = drm_poll,
 531         .read = drm_read,
 532 #ifdef CONFIG_COMPAT
 533         .compat_ioctl = radeon_kms_compat_ioctl,
 534 #endif
 535 };
 536
 537 static struct drm_driver kms_driver = {
 538         .driver_features =
 539             DRIVER_USE_AGP |
 540             DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM |
 541             DRIVER_PRIME | DRIVER_RENDER,
 542         .load = radeon_driver_load_kms,
 543         .open = radeon_driver_open_kms,
 544         .preclose = radeon_driver_preclose_kms,
 545         .postclose = radeon_driver_postclose_kms,
 546         .lastclose = radeon_driver_lastclose_kms,
 547         .unload = radeon_driver_unload_kms,
 548         .get_vblank_counter = radeon_get_vblank_counter_kms,
 549         .enable_vblank = radeon_enable_vblank_kms,
 550         .disable_vblank = radeon_disable_vblank_kms,
 551         .get_vblank_timestamp = radeon_get_vblank_timestamp_kms,
 552         .get_scanout_position = radeon_get_crtc_scanoutpos,
 553 #if defined(CONFIG_DEBUG_FS)
 554         .debugfs_init = radeon_debugfs_init,
 555         .debugfs_cleanup = radeon_debugfs_cleanup,
 556 #endif
 557         .irq_preinstall = radeon_driver_irq_preinstall_kms,
 558         .irq_postinstall = radeon_driver_irq_postinstall_kms,
 559         .irq_uninstall = radeon_driver_irq_uninstall_kms,
 560         .irq_handler = radeon_driver_irq_handler_kms,
 561         .ioctls = radeon_ioctls_kms,
 562         .gem_free_object = radeon_gem_object_free,
 563         .gem_open_object = radeon_gem_object_open,
 564         .gem_close_object = radeon_gem_object_close,
 565         .dumb_create = radeon_mode_dumb_create,
 566         .dumb_map_offset = radeon_mode_dumb_mmap,
 567         .dumb_destroy = drm_gem_dumb_destroy,
 568         .fops = &radeon_driver_kms_fops,
 569
 570         .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
 571         .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
 572         .gem_prime_export = drm_gem_prime_export,
 573         .gem_prime_import = drm_gem_prime_import,
 574         .gem_prime_pin = radeon_gem_prime_pin,
 575         .gem_prime_unpin = radeon_gem_prime_unpin,
 576         .gem_prime_res_obj = radeon_gem_prime_res_obj,
 577         .gem_prime_get_sg_table = radeon_gem_prime_get_sg_table,
 578         .gem_prime_import_sg_table = radeon_gem_prime_import_sg_table,
 579         .gem_prime_vmap = radeon_gem_prime_vmap,
 580         .gem_prime_vunmap = radeon_gem_prime_vunmap,
 581
 582         .name = DRIVER_NAME,
 583         .desc = DRIVER_DESC,
 584         .date = DRIVER_DATE,
 585         .major = KMS_DRIVER_MAJOR,
 586         .minor = KMS_DRIVER_MINOR,
 587         .patchlevel = KMS_DRIVER_PATCHLEVEL,
 588 };
 589
 590 static struct drm_driver *driver;
 591 static struct pci_driver *pdriver;
 592
 593 #ifdef CONFIG_DRM_RADEON_UMS
 594 static struct pci_driver radeon_pci_driver = {
 595         .name = DRIVER_NAME,
 596         .id_table = pciidlist,
 597 };
 598 #endif
 599
 600 static struct pci_driver radeon_kms_pci_driver = {
 601         .name = DRIVER_NAME,
 602         .id_table = pciidlist,
 603         .probe = radeon_pci_probe,
 604         .remove = radeon_pci_remove,
 605         .driver.pm = &radeon_pm_ops,
 606 };
 607
 608 static int __init radeon_init(void)
 609 {
 610 #ifdef CONFIG_VGA_CONSOLE
 611         if (vgacon_text_force() && radeon_modeset == -1) {
 612                 DRM_INFO("VGACON disable radeon kernel modesetting.\n");
 613                 radeon_modeset = 0;
 614         }
 615 #endif
 616         /* set to modesetting by default if not nomodeset */
 617         if (radeon_modeset == -1)
 618                 radeon_modeset = 1;
 619
 620         if (radeon_modeset == 1) {
 621                 DRM_INFO("radeon kernel modesetting enabled.\n");
 622                 driver = &kms_driver;
 623                 pdriver = &radeon_kms_pci_driver;
 624                 driver->driver_features |= DRIVER_MODESET;
 625                 driver->num_ioctls = radeon_max_kms_ioctl;
 626                 radeon_register_atpx_handler();
 627
 628         } else {
 629 #ifdef CONFIG_DRM_RADEON_UMS
 630                 DRM_INFO("radeon userspace modesetting enabled.\n");
 631                 driver = &driver_old;
 632                 pdriver = &radeon_pci_driver;
 633                 driver->driver_features &= ~DRIVER_MODESET;
 634                 driver->num_ioctls = radeon_max_ioctl;
 635 #else
 636                 DRM_ERROR("No UMS support in radeon module!\n");
 637                 return -EINVAL;
 638 #endif
 639         }
 640
 641         /* let modprobe override vga console setting */
 642         return drm_pci_init(driver, pdriver);
 643 }
 644
 645 static void __exit radeon_exit(void)
 646 {
 647         drm_pci_exit(driver, pdriver);
 648         radeon_unregister_atpx_handler();
 649 }
 650
 651 module_init(radeon_init);
 652 module_exit(radeon_exit);
 653
 654 MODULE_AUTHOR(DRIVER_AUTHOR);
 655 MODULE_DESCRIPTION(DRIVER_DESC);
 656 MODULE_LICENSE("GPL and additional rights");