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Merge branch 'for-linux-next' of git://linux-c6x.org/git/projects/linux-c6x-upstreaming
[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon_drv.h
1 /* radeon_drv.h -- Private header for radeon driver -*- linux-c -*-
2 *
3 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
5 * All rights reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
16 * Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
24 * DEALINGS IN THE SOFTWARE.
25 *
26 * Authors:
27 * Kevin E. Martin <martin@valinux.com>
28 * Gareth Hughes <gareth@valinux.com>
29 */
30
31 #ifndef __RADEON_DRV_H__
32 #define __RADEON_DRV_H__
33
34 #include <linux/firmware.h>
35 #include <linux/platform_device.h>
36 #include <drm/drm_legacy.h>
37
38 #include <drm/ati_pcigart.h>
39 #include "radeon_family.h"
40
41 /* General customization:
42 */
43
44 #define DRIVER_AUTHOR "Gareth Hughes, Keith Whitwell, others."
45
46 #define DRIVER_NAME "radeon"
47 #define DRIVER_DESC "ATI Radeon"
48 #define DRIVER_DATE "20080528"
49
50 /* Interface history:
51 *
52 * 1.1 - ??
53 * 1.2 - Add vertex2 ioctl (keith)
54 * - Add stencil capability to clear ioctl (gareth, keith)
55 * - Increase MAX_TEXTURE_LEVELS (brian)
56 * 1.3 - Add cmdbuf ioctl (keith)
57 * - Add support for new radeon packets (keith)
58 * - Add getparam ioctl (keith)
59 * - Add flip-buffers ioctl, deprecate fullscreen foo (keith).
60 * 1.4 - Add scratch registers to get_param ioctl.
61 * 1.5 - Add r200 packets to cmdbuf ioctl
62 * - Add r200 function to init ioctl
63 * - Add 'scalar2' instruction to cmdbuf
64 * 1.6 - Add static GART memory manager
65 * Add irq handler (won't be turned on unless X server knows to)
66 * Add irq ioctls and irq_active getparam.
67 * Add wait command for cmdbuf ioctl
68 * Add GART offset query for getparam
69 * 1.7 - Add support for cube map registers: R200_PP_CUBIC_FACES_[0..5]
70 * and R200_PP_CUBIC_OFFSET_F1_[0..5].
71 * Added packets R200_EMIT_PP_CUBIC_FACES_[0..5] and
72 * R200_EMIT_PP_CUBIC_OFFSETS_[0..5]. (brian)
73 * 1.8 - Remove need to call cleanup ioctls on last client exit (keith)
74 * Add 'GET' queries for starting additional clients on different VT's.
75 * 1.9 - Add DRM_IOCTL_RADEON_CP_RESUME ioctl.
76 * Add texture rectangle support for r100.
77 * 1.10- Add SETPARAM ioctl; first parameter to set is FB_LOCATION, which
78 * clients use to tell the DRM where they think the framebuffer is
79 * located in the card's address space
80 * 1.11- Add packet R200_EMIT_RB3D_BLENDCOLOR to support GL_EXT_blend_color
81 * and GL_EXT_blend_[func|equation]_separate on r200
82 * 1.12- Add R300 CP microcode support - this just loads the CP on r300
83 * (No 3D support yet - just microcode loading).
84 * 1.13- Add packet R200_EMIT_TCL_POINT_SPRITE_CNTL for ARB_point_parameters
85 * - Add hyperz support, add hyperz flags to clear ioctl.
86 * 1.14- Add support for color tiling
87 * - Add R100/R200 surface allocation/free support
88 * 1.15- Add support for texture micro tiling
89 * - Add support for r100 cube maps
90 * 1.16- Add R200_EMIT_PP_TRI_PERF_CNTL packet to support brilinear
91 * texture filtering on r200
92 * 1.17- Add initial support for R300 (3D).
93 * 1.18- Add support for GL_ATI_fragment_shader, new packets
94 * R200_EMIT_PP_AFS_0/1, R200_EMIT_PP_TXCTLALL_0-5 (replaces
95 * R200_EMIT_PP_TXFILTER_0-5, 2 more regs) and R200_EMIT_ATF_TFACTOR
96 * (replaces R200_EMIT_TFACTOR_0 (8 consts instead of 6)
97 * 1.19- Add support for gart table in FB memory and PCIE r300
98 * 1.20- Add support for r300 texrect
99 * 1.21- Add support for card type getparam
100 * 1.22- Add support for texture cache flushes (R300_TX_CNTL)
101 * 1.23- Add new radeon memory map work from benh
102 * 1.24- Add general-purpose packet for manipulating scratch registers (r300)
103 * 1.25- Add support for r200 vertex programs (R200_EMIT_VAP_PVS_CNTL,
104 * new packet type)
105 * 1.26- Add support for variable size PCI(E) gart aperture
106 * 1.27- Add support for IGP GART
107 * 1.28- Add support for VBL on CRTC2
108 * 1.29- R500 3D cmd buffer support
109 * 1.30- Add support for occlusion queries
110 * 1.31- Add support for num Z pipes from GET_PARAM
111 * 1.32- fixes for rv740 setup
112 * 1.33- Add r6xx/r7xx const buffer support
113 * 1.34- fix evergreen/cayman GS register
114 */
115 #define DRIVER_MAJOR 1
116 #define DRIVER_MINOR 34
117 #define DRIVER_PATCHLEVEL 0
118
119 long radeon_drm_ioctl(struct file *filp,
120 unsigned int cmd, unsigned long arg);
121
122 /* The rest of the file is DEPRECATED! */
123 #ifdef CONFIG_DRM_RADEON_UMS
124
125 enum radeon_cp_microcode_version {
126 UCODE_R100,
127 UCODE_R200,
128 UCODE_R300,
129 };
130
131 typedef struct drm_radeon_freelist {
132 unsigned int age;
133 struct drm_buf *buf;
134 struct drm_radeon_freelist *next;
135 struct drm_radeon_freelist *prev;
136 } drm_radeon_freelist_t;
137
138 typedef struct drm_radeon_ring_buffer {
139 u32 *start;
140 u32 *end;
141 int size;
142 int size_l2qw;
143
144 int rptr_update; /* Double Words */
145 int rptr_update_l2qw; /* log2 Quad Words */
146
147 int fetch_size; /* Double Words */
148 int fetch_size_l2ow; /* log2 Oct Words */
149
150 u32 tail;
151 u32 tail_mask;
152 int space;
153
154 int high_mark;
155 } drm_radeon_ring_buffer_t;
156
157 typedef struct drm_radeon_depth_clear_t {
158 u32 rb3d_cntl;
159 u32 rb3d_zstencilcntl;
160 u32 se_cntl;
161 } drm_radeon_depth_clear_t;
162
163 struct drm_radeon_driver_file_fields {
164 int64_t radeon_fb_delta;
165 };
166
167 struct mem_block {
168 struct mem_block *next;
169 struct mem_block *prev;
170 int start;
171 int size;
172 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
173 };
174
175 struct radeon_surface {
176 int refcount;
177 u32 lower;
178 u32 upper;
179 u32 flags;
180 };
181
182 struct radeon_virt_surface {
183 int surface_index;
184 u32 lower;
185 u32 upper;
186 u32 flags;
187 struct drm_file *file_priv;
188 #define PCIGART_FILE_PRIV ((void *) -1L)
189 };
190
191 #define RADEON_FLUSH_EMITED (1 << 0)
192 #define RADEON_PURGE_EMITED (1 << 1)
193
194 struct drm_radeon_master_private {
195 drm_local_map_t *sarea;
196 drm_radeon_sarea_t *sarea_priv;
197 };
198
199 typedef struct drm_radeon_private {
200 drm_radeon_ring_buffer_t ring;
201
202 u32 fb_location;
203 u32 fb_size;
204 int new_memmap;
205
206 int gart_size;
207 u32 gart_vm_start;
208 unsigned long gart_buffers_offset;
209
210 int cp_mode;
211 int cp_running;
212
213 drm_radeon_freelist_t *head;
214 drm_radeon_freelist_t *tail;
215 int last_buf;
216 int writeback_works;
217
218 int usec_timeout;
219
220 int microcode_version;
221
222 struct {
223 u32 boxes;
224 int freelist_timeouts;
225 int freelist_loops;
226 int requested_bufs;
227 int last_frame_reads;
228 int last_clear_reads;
229 int clears;
230 int texture_uploads;
231 } stats;
232
233 int do_boxes;
234 int page_flipping;
235
236 u32 color_fmt;
237 unsigned int front_offset;
238 unsigned int front_pitch;
239 unsigned int back_offset;
240 unsigned int back_pitch;
241
242 u32 depth_fmt;
243 unsigned int depth_offset;
244 unsigned int depth_pitch;
245
246 u32 front_pitch_offset;
247 u32 back_pitch_offset;
248 u32 depth_pitch_offset;
249
250 drm_radeon_depth_clear_t depth_clear;
251
252 unsigned long ring_offset;
253 unsigned long ring_rptr_offset;
254 unsigned long buffers_offset;
255 unsigned long gart_textures_offset;
256
257 drm_local_map_t *sarea;
258 drm_local_map_t *cp_ring;
259 drm_local_map_t *ring_rptr;
260 drm_local_map_t *gart_textures;
261
262 struct mem_block *gart_heap;
263 struct mem_block *fb_heap;
264
265 /* SW interrupt */
266 wait_queue_head_t swi_queue;
267 atomic_t swi_emitted;
268 int vblank_crtc;
269 uint32_t irq_enable_reg;
270 uint32_t r500_disp_irq_reg;
271
272 struct radeon_surface surfaces[RADEON_MAX_SURFACES];
273 struct radeon_virt_surface virt_surfaces[2 * RADEON_MAX_SURFACES];
274
275 unsigned long pcigart_offset;
276 unsigned int pcigart_offset_set;
277 struct drm_ati_pcigart_info gart_info;
278
279 u32 scratch_ages[5];
280
281 int have_z_offset;
282
283 /* starting from here on, data is preserved across an open */
284 uint32_t flags; /* see radeon_chip_flags */
285 resource_size_t fb_aper_offset;
286
287 int num_gb_pipes;
288 int num_z_pipes;
289 int track_flush;
290 drm_local_map_t *mmio;
291
292 /* r6xx/r7xx pipe/shader config */
293 int r600_max_pipes;
294 int r600_max_tile_pipes;
295 int r600_max_simds;
296 int r600_max_backends;
297 int r600_max_gprs;
298 int r600_max_threads;
299 int r600_max_stack_entries;
300 int r600_max_hw_contexts;
301 int r600_max_gs_threads;
302 int r600_sx_max_export_size;
303 int r600_sx_max_export_pos_size;
304 int r600_sx_max_export_smx_size;
305 int r600_sq_num_cf_insts;
306 int r700_sx_num_of_sets;
307 int r700_sc_prim_fifo_size;
308 int r700_sc_hiz_tile_fifo_size;
309 int r700_sc_earlyz_tile_fifo_fize;
310 int r600_group_size;
311 int r600_npipes;
312 int r600_nbanks;
313
314 struct mutex cs_mutex;
315 u32 cs_id_scnt;
316 u32 cs_id_wcnt;
317 /* r6xx/r7xx drm blit vertex buffer */
318 struct drm_buf *blit_vb;
319
320 /* firmware */
321 const struct firmware *me_fw, *pfp_fw;
322 } drm_radeon_private_t;
323
324 typedef struct drm_radeon_buf_priv {
325 u32 age;
326 } drm_radeon_buf_priv_t;
327
328 struct drm_buffer;
329
330 typedef struct drm_radeon_kcmd_buffer {
331 int bufsz;
332 struct drm_buffer *buffer;
333 int nbox;
334 struct drm_clip_rect __user *boxes;
335 } drm_radeon_kcmd_buffer_t;
336
337 extern int radeon_no_wb;
338 extern struct drm_ioctl_desc radeon_ioctls[];
339 extern int radeon_max_ioctl;
340
341 extern u32 radeon_get_ring_head(drm_radeon_private_t *dev_priv);
342 extern void radeon_set_ring_head(drm_radeon_private_t *dev_priv, u32 val);
343
344 #define GET_RING_HEAD(dev_priv) radeon_get_ring_head(dev_priv)
345 #define SET_RING_HEAD(dev_priv, val) radeon_set_ring_head(dev_priv, val)
346
347 /* Check whether the given hardware address is inside the framebuffer or the
348 * GART area.
349 */
350 static __inline__ int radeon_check_offset(drm_radeon_private_t *dev_priv,
351 u64 off)
352 {
353 u32 fb_start = dev_priv->fb_location;
354 u32 fb_end = fb_start + dev_priv->fb_size - 1;
355 u32 gart_start = dev_priv->gart_vm_start;
356 u32 gart_end = gart_start + dev_priv->gart_size - 1;
357
358 return ((off >= fb_start && off <= fb_end) ||
359 (off >= gart_start && off <= gart_end));
360 }
361
362 /* radeon_state.c */
363 extern void radeon_cp_discard_buffer(struct drm_device *dev, struct drm_master *master, struct drm_buf *buf);
364
365 /* radeon_cp.c */
366 extern int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_priv);
367 extern int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_priv);
368 extern int radeon_cp_stop(struct drm_device *dev, void *data, struct drm_file *file_priv);
369 extern int radeon_cp_reset(struct drm_device *dev, void *data, struct drm_file *file_priv);
370 extern int radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_priv);
371 extern int radeon_cp_resume(struct drm_device *dev, void *data, struct drm_file *file_priv);
372 extern int radeon_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv);
373 extern int radeon_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv);
374 extern int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv);
375 extern u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv);
376 extern void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_loc);
377 extern void radeon_write_agp_base(drm_radeon_private_t *dev_priv, u64 agp_base);
378
379 extern void radeon_freelist_reset(struct drm_device * dev);
380 extern struct drm_buf *radeon_freelist_get(struct drm_device * dev);
381
382 extern int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n);
383
384 extern int radeon_do_cp_idle(drm_radeon_private_t * dev_priv);
385
386 extern int radeon_driver_preinit(struct drm_device *dev, unsigned long flags);
387 extern int radeon_presetup(struct drm_device *dev);
388 extern int radeon_driver_postcleanup(struct drm_device *dev);
389
390 extern int radeon_mem_alloc(struct drm_device *dev, void *data, struct drm_file *file_priv);
391 extern int radeon_mem_free(struct drm_device *dev, void *data, struct drm_file *file_priv);
392 extern int radeon_mem_init_heap(struct drm_device *dev, void *data, struct drm_file *file_priv);
393 extern void radeon_mem_takedown(struct mem_block **heap);
394 extern void radeon_mem_release(struct drm_file *file_priv,
395 struct mem_block *heap);
396
397 extern void radeon_enable_bm(struct drm_radeon_private *dev_priv);
398 extern u32 radeon_read_ring_rptr(drm_radeon_private_t *dev_priv, u32 off);
399 extern void radeon_write_ring_rptr(drm_radeon_private_t *dev_priv, u32 off, u32 val);
400
401 /* radeon_irq.c */
402 extern void radeon_irq_set_state(struct drm_device *dev, u32 mask, int state);
403 extern int radeon_irq_emit(struct drm_device *dev, void *data, struct drm_file *file_priv);
404 extern int radeon_irq_wait(struct drm_device *dev, void *data, struct drm_file *file_priv);
405
406 extern void radeon_do_release(struct drm_device * dev);
407 extern u32 radeon_get_vblank_counter(struct drm_device *dev, unsigned int pipe);
408 extern int radeon_enable_vblank(struct drm_device *dev, unsigned int pipe);
409 extern void radeon_disable_vblank(struct drm_device *dev, unsigned int pipe);
410 extern irqreturn_t radeon_driver_irq_handler(int irq, void *arg);
411 extern void radeon_driver_irq_preinstall(struct drm_device * dev);
412 extern int radeon_driver_irq_postinstall(struct drm_device *dev);
413 extern void radeon_driver_irq_uninstall(struct drm_device * dev);
414 extern void radeon_enable_interrupt(struct drm_device *dev);
415 extern int radeon_vblank_crtc_get(struct drm_device *dev);
416 extern int radeon_vblank_crtc_set(struct drm_device *dev, int64_t value);
417
418 extern int radeon_driver_load(struct drm_device *dev, unsigned long flags);
419 extern int radeon_driver_unload(struct drm_device *dev);
420 extern int radeon_driver_firstopen(struct drm_device *dev);
421 extern void radeon_driver_preclose(struct drm_device *dev,
422 struct drm_file *file_priv);
423 extern void radeon_driver_postclose(struct drm_device *dev,
424 struct drm_file *file_priv);
425 extern void radeon_driver_lastclose(struct drm_device * dev);
426 extern int radeon_driver_open(struct drm_device *dev,
427 struct drm_file *file_priv);
428 extern long radeon_compat_ioctl(struct file *filp, unsigned int cmd,
429 unsigned long arg);
430
431 extern int radeon_master_create(struct drm_device *dev, struct drm_master *master);
432 extern void radeon_master_destroy(struct drm_device *dev, struct drm_master *master);
433 extern void radeon_cp_dispatch_flip(struct drm_device *dev, struct drm_master *master);
434 /* r300_cmdbuf.c */
435 extern void r300_init_reg_flags(struct drm_device *dev);
436
437 extern int r300_do_cp_cmdbuf(struct drm_device *dev,
438 struct drm_file *file_priv,
439 drm_radeon_kcmd_buffer_t *cmdbuf);
440
441 /* r600_cp.c */
442 extern int r600_do_engine_reset(struct drm_device *dev);
443 extern int r600_do_cleanup_cp(struct drm_device *dev);
444 extern int r600_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init,
445 struct drm_file *file_priv);
446 extern int r600_do_resume_cp(struct drm_device *dev, struct drm_file *file_priv);
447 extern int r600_do_cp_idle(drm_radeon_private_t *dev_priv);
448 extern void r600_do_cp_start(drm_radeon_private_t *dev_priv);
449 extern void r600_do_cp_reset(drm_radeon_private_t *dev_priv);
450 extern void r600_do_cp_stop(drm_radeon_private_t *dev_priv);
451 extern int r600_cp_dispatch_indirect(struct drm_device *dev,
452 struct drm_buf *buf, int start, int end);
453 extern int r600_page_table_init(struct drm_device *dev);
454 extern void r600_page_table_cleanup(struct drm_device *dev, struct drm_ati_pcigart_info *gart_info);
455 extern int r600_cs_legacy_ioctl(struct drm_device *dev, void *data, struct drm_file *fpriv);
456 extern void r600_cp_dispatch_swap(struct drm_device *dev, struct drm_file *file_priv);
457 extern int r600_cp_dispatch_texture(struct drm_device *dev,
458 struct drm_file *file_priv,
459 drm_radeon_texture_t *tex,
460 drm_radeon_tex_image_t *image);
461 /* r600_blit.c */
462 extern int r600_prepare_blit_copy(struct drm_device *dev, struct drm_file *file_priv);
463 extern void r600_done_blit_copy(struct drm_device *dev);
464 extern void r600_blit_copy(struct drm_device *dev,
465 uint64_t src_gpu_addr, uint64_t dst_gpu_addr,
466 int size_bytes);
467 extern void r600_blit_swap(struct drm_device *dev,
468 uint64_t src_gpu_addr, uint64_t dst_gpu_addr,
469 int sx, int sy, int dx, int dy,
470 int w, int h, int src_pitch, int dst_pitch, int cpp);
471
472 /* Flags for stats.boxes
473 */
474 #define RADEON_BOX_DMA_IDLE 0x1
475 #define RADEON_BOX_RING_FULL 0x2
476 #define RADEON_BOX_FLIP 0x4
477 #define RADEON_BOX_WAIT_IDLE 0x8
478 #define RADEON_BOX_TEXTURE_LOAD 0x10
479
480 /* Register definitions, register access macros and drmAddMap constants
481 * for Radeon kernel driver.
482 */
483 #define RADEON_MM_INDEX 0x0000
484 #define RADEON_MM_DATA 0x0004
485
486 #define RADEON_AGP_COMMAND 0x0f60
487 #define RADEON_AGP_COMMAND_PCI_CONFIG 0x0060 /* offset in PCI config */
488 # define RADEON_AGP_ENABLE (1<<8)
489 #define RADEON_AUX_SCISSOR_CNTL 0x26f0
490 # define RADEON_EXCLUSIVE_SCISSOR_0 (1 << 24)
491 # define RADEON_EXCLUSIVE_SCISSOR_1 (1 << 25)
492 # define RADEON_EXCLUSIVE_SCISSOR_2 (1 << 26)
493 # define RADEON_SCISSOR_0_ENABLE (1 << 28)
494 # define RADEON_SCISSOR_1_ENABLE (1 << 29)
495 # define RADEON_SCISSOR_2_ENABLE (1 << 30)
496
497 /*
498 * PCIE radeons (rv370/rv380, rv410, r423/r430/r480, r5xx)
499 * don't have an explicit bus mastering disable bit. It's handled
500 * by the PCI D-states. PMI_BM_DIS disables D-state bus master
501 * handling, not bus mastering itself.
502 */
503 #define RADEON_BUS_CNTL 0x0030
504 /* r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
505 # define RADEON_BUS_MASTER_DIS (1 << 6)
506 /* rs600/rs690/rs740 */
507 # define RS600_BUS_MASTER_DIS (1 << 14)
508 # define RS600_MSI_REARM (1 << 20)
509 /* see RS400_MSI_REARM in AIC_CNTL for rs480 */
510
511 #define RADEON_BUS_CNTL1 0x0034
512 # define RADEON_PMI_BM_DIS (1 << 2)
513 # define RADEON_PMI_INT_DIS (1 << 3)
514
515 #define RV370_BUS_CNTL 0x004c
516 # define RV370_PMI_BM_DIS (1 << 5)
517 # define RV370_PMI_INT_DIS (1 << 6)
518
519 #define RADEON_MSI_REARM_EN 0x0160
520 /* rv370/rv380, rv410, r423/r430/r480, r5xx */
521 # define RV370_MSI_REARM_EN (1 << 0)
522
523 #define RADEON_CLOCK_CNTL_DATA 0x000c
524 # define RADEON_PLL_WR_EN (1 << 7)
525 #define RADEON_CLOCK_CNTL_INDEX 0x0008
526 #define RADEON_CONFIG_APER_SIZE 0x0108
527 #define RADEON_CONFIG_MEMSIZE 0x00f8
528 #define RADEON_CRTC_OFFSET 0x0224
529 #define RADEON_CRTC_OFFSET_CNTL 0x0228
530 # define RADEON_CRTC_TILE_EN (1 << 15)
531 # define RADEON_CRTC_OFFSET_FLIP_CNTL (1 << 16)
532 #define RADEON_CRTC2_OFFSET 0x0324
533 #define RADEON_CRTC2_OFFSET_CNTL 0x0328
534
535 #define RADEON_PCIE_INDEX 0x0030
536 #define RADEON_PCIE_DATA 0x0034
537 #define RADEON_PCIE_TX_GART_CNTL 0x10
538 # define RADEON_PCIE_TX_GART_EN (1 << 0)
539 # define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_PASS_THRU (0 << 1)
540 # define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_CLAMP_LO (1 << 1)
541 # define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD (3 << 1)
542 # define RADEON_PCIE_TX_GART_MODE_32_128_CACHE (0 << 3)
543 # define RADEON_PCIE_TX_GART_MODE_8_4_128_CACHE (1 << 3)
544 # define RADEON_PCIE_TX_GART_CHK_RW_VALID_EN (1 << 5)
545 # define RADEON_PCIE_TX_GART_INVALIDATE_TLB (1 << 8)
546 #define RADEON_PCIE_TX_DISCARD_RD_ADDR_LO 0x11
547 #define RADEON_PCIE_TX_DISCARD_RD_ADDR_HI 0x12
548 #define RADEON_PCIE_TX_GART_BASE 0x13
549 #define RADEON_PCIE_TX_GART_START_LO 0x14
550 #define RADEON_PCIE_TX_GART_START_HI 0x15
551 #define RADEON_PCIE_TX_GART_END_LO 0x16
552 #define RADEON_PCIE_TX_GART_END_HI 0x17
553
554 #define RS480_NB_MC_INDEX 0x168
555 # define RS480_NB_MC_IND_WR_EN (1 << 8)
556 #define RS480_NB_MC_DATA 0x16c
557
558 #define RS690_MC_INDEX 0x78
559 # define RS690_MC_INDEX_MASK 0x1ff
560 # define RS690_MC_INDEX_WR_EN (1 << 9)
561 # define RS690_MC_INDEX_WR_ACK 0x7f
562 #define RS690_MC_DATA 0x7c
563
564 /* MC indirect registers */
565 #define RS480_MC_MISC_CNTL 0x18
566 # define RS480_DISABLE_GTW (1 << 1)
567 /* switch between MCIND GART and MM GART registers. 0 = mmgart, 1 = mcind gart */
568 # define RS480_GART_INDEX_REG_EN (1 << 12)
569 # define RS690_BLOCK_GFX_D3_EN (1 << 14)
570 #define RS480_K8_FB_LOCATION 0x1e
571 #define RS480_GART_FEATURE_ID 0x2b
572 # define RS480_HANG_EN (1 << 11)
573 # define RS480_TLB_ENABLE (1 << 18)
574 # define RS480_P2P_ENABLE (1 << 19)
575 # define RS480_GTW_LAC_EN (1 << 25)
576 # define RS480_2LEVEL_GART (0 << 30)
577 # define RS480_1LEVEL_GART (1 << 30)
578 # define RS480_PDC_EN (1 << 31)
579 #define RS480_GART_BASE 0x2c
580 #define RS480_GART_CACHE_CNTRL 0x2e
581 # define RS480_GART_CACHE_INVALIDATE (1 << 0) /* wait for it to clear */
582 #define RS480_AGP_ADDRESS_SPACE_SIZE 0x38
583 # define RS480_GART_EN (1 << 0)
584 # define RS480_VA_SIZE_32MB (0 << 1)
585 # define RS480_VA_SIZE_64MB (1 << 1)
586 # define RS480_VA_SIZE_128MB (2 << 1)
587 # define RS480_VA_SIZE_256MB (3 << 1)
588 # define RS480_VA_SIZE_512MB (4 << 1)
589 # define RS480_VA_SIZE_1GB (5 << 1)
590 # define RS480_VA_SIZE_2GB (6 << 1)
591 #define RS480_AGP_MODE_CNTL 0x39
592 # define RS480_POST_GART_Q_SIZE (1 << 18)
593 # define RS480_NONGART_SNOOP (1 << 19)
594 # define RS480_AGP_RD_BUF_SIZE (1 << 20)
595 # define RS480_REQ_TYPE_SNOOP_SHIFT 22
596 # define RS480_REQ_TYPE_SNOOP_MASK 0x3
597 # define RS480_REQ_TYPE_SNOOP_DIS (1 << 24)
598 #define RS480_MC_MISC_UMA_CNTL 0x5f
599 #define RS480_MC_MCLK_CNTL 0x7a
600 #define RS480_MC_UMA_DUALCH_CNTL 0x86
601
602 #define RS690_MC_FB_LOCATION 0x100
603 #define RS690_MC_AGP_LOCATION 0x101
604 #define RS690_MC_AGP_BASE 0x102
605 #define RS690_MC_AGP_BASE_2 0x103
606
607 #define RS600_MC_INDEX 0x70
608 # define RS600_MC_ADDR_MASK 0xffff
609 # define RS600_MC_IND_SEQ_RBS_0 (1 << 16)
610 # define RS600_MC_IND_SEQ_RBS_1 (1 << 17)
611 # define RS600_MC_IND_SEQ_RBS_2 (1 << 18)
612 # define RS600_MC_IND_SEQ_RBS_3 (1 << 19)
613 # define RS600_MC_IND_AIC_RBS (1 << 20)
614 # define RS600_MC_IND_CITF_ARB0 (1 << 21)
615 # define RS600_MC_IND_CITF_ARB1 (1 << 22)
616 # define RS600_MC_IND_WR_EN (1 << 23)
617 #define RS600_MC_DATA 0x74
618
619 #define RS600_MC_STATUS 0x0
620 # define RS600_MC_IDLE (1 << 1)
621 #define RS600_MC_FB_LOCATION 0x4
622 #define RS600_MC_AGP_LOCATION 0x5
623 #define RS600_AGP_BASE 0x6
624 #define RS600_AGP_BASE_2 0x7
625 #define RS600_MC_CNTL1 0x9
626 # define RS600_ENABLE_PAGE_TABLES (1 << 26)
627 #define RS600_MC_PT0_CNTL 0x100
628 # define RS600_ENABLE_PT (1 << 0)
629 # define RS600_EFFECTIVE_L2_CACHE_SIZE(x) ((x) << 15)
630 # define RS600_EFFECTIVE_L2_QUEUE_SIZE(x) ((x) << 21)
631 # define RS600_INVALIDATE_ALL_L1_TLBS (1 << 28)
632 # define RS600_INVALIDATE_L2_CACHE (1 << 29)
633 #define RS600_MC_PT0_CONTEXT0_CNTL 0x102
634 # define RS600_ENABLE_PAGE_TABLE (1 << 0)
635 # define RS600_PAGE_TABLE_TYPE_FLAT (0 << 1)
636 #define RS600_MC_PT0_SYSTEM_APERTURE_LOW_ADDR 0x112
637 #define RS600_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR 0x114
638 #define RS600_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR 0x11c
639 #define RS600_MC_PT0_CONTEXT0_FLAT_BASE_ADDR 0x12c
640 #define RS600_MC_PT0_CONTEXT0_FLAT_START_ADDR 0x13c
641 #define RS600_MC_PT0_CONTEXT0_FLAT_END_ADDR 0x14c
642 #define RS600_MC_PT0_CLIENT0_CNTL 0x16c
643 # define RS600_ENABLE_TRANSLATION_MODE_OVERRIDE (1 << 0)
644 # define RS600_TRANSLATION_MODE_OVERRIDE (1 << 1)
645 # define RS600_SYSTEM_ACCESS_MODE_MASK (3 << 8)
646 # define RS600_SYSTEM_ACCESS_MODE_PA_ONLY (0 << 8)
647 # define RS600_SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 8)
648 # define RS600_SYSTEM_ACCESS_MODE_IN_SYS (2 << 8)
649 # define RS600_SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 8)
650 # define RS600_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASSTHROUGH (0 << 10)
651 # define RS600_SYSTEM_APERTURE_UNMAPPED_ACCESS_DEFAULT_PAGE (1 << 10)
652 # define RS600_EFFECTIVE_L1_CACHE_SIZE(x) ((x) << 11)
653 # define RS600_ENABLE_FRAGMENT_PROCESSING (1 << 14)
654 # define RS600_EFFECTIVE_L1_QUEUE_SIZE(x) ((x) << 15)
655 # define RS600_INVALIDATE_L1_TLB (1 << 20)
656
657 #define R520_MC_IND_INDEX 0x70
658 #define R520_MC_IND_WR_EN (1 << 24)
659 #define R520_MC_IND_DATA 0x74
660
661 #define RV515_MC_FB_LOCATION 0x01
662 #define RV515_MC_AGP_LOCATION 0x02
663 #define RV515_MC_AGP_BASE 0x03
664 #define RV515_MC_AGP_BASE_2 0x04
665
666 #define R520_MC_FB_LOCATION 0x04
667 #define R520_MC_AGP_LOCATION 0x05
668 #define R520_MC_AGP_BASE 0x06
669 #define R520_MC_AGP_BASE_2 0x07
670
671 #define RADEON_MPP_TB_CONFIG 0x01c0
672 #define RADEON_MEM_CNTL 0x0140
673 #define RADEON_MEM_SDRAM_MODE_REG 0x0158
674 #define RADEON_AGP_BASE_2 0x015c /* r200+ only */
675 #define RS480_AGP_BASE_2 0x0164
676 #define RADEON_AGP_BASE 0x0170
677
678 /* pipe config regs */
679 #define R400_GB_PIPE_SELECT 0x402c
680 #define RV530_GB_PIPE_SELECT2 0x4124
681 #define R500_DYN_SCLK_PWMEM_PIPE 0x000d /* PLL */
682 #define R300_GB_TILE_CONFIG 0x4018
683 # define R300_ENABLE_TILING (1 << 0)
684 # define R300_PIPE_COUNT_RV350 (0 << 1)
685 # define R300_PIPE_COUNT_R300 (3 << 1)
686 # define R300_PIPE_COUNT_R420_3P (6 << 1)
687 # define R300_PIPE_COUNT_R420 (7 << 1)
688 # define R300_TILE_SIZE_8 (0 << 4)
689 # define R300_TILE_SIZE_16 (1 << 4)
690 # define R300_TILE_SIZE_32 (2 << 4)
691 # define R300_SUBPIXEL_1_12 (0 << 16)
692 # define R300_SUBPIXEL_1_16 (1 << 16)
693 #define R300_DST_PIPE_CONFIG 0x170c
694 # define R300_PIPE_AUTO_CONFIG (1 << 31)
695 #define R300_RB2D_DSTCACHE_MODE 0x3428
696 # define R300_DC_AUTOFLUSH_ENABLE (1 << 8)
697 # define R300_DC_DC_DISABLE_IGNORE_PE (1 << 17)
698
699 #define RADEON_RB3D_COLOROFFSET 0x1c40
700 #define RADEON_RB3D_COLORPITCH 0x1c48
701
702 #define RADEON_SRC_X_Y 0x1590
703
704 #define RADEON_DP_GUI_MASTER_CNTL 0x146c
705 # define RADEON_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0)
706 # define RADEON_GMC_DST_PITCH_OFFSET_CNTL (1 << 1)
707 # define RADEON_GMC_BRUSH_SOLID_COLOR (13 << 4)
708 # define RADEON_GMC_BRUSH_NONE (15 << 4)
709 # define RADEON_GMC_DST_16BPP (4 << 8)
710 # define RADEON_GMC_DST_24BPP (5 << 8)
711 # define RADEON_GMC_DST_32BPP (6 << 8)
712 # define RADEON_GMC_DST_DATATYPE_SHIFT 8
713 # define RADEON_GMC_SRC_DATATYPE_COLOR (3 << 12)
714 # define RADEON_DP_SRC_SOURCE_MEMORY (2 << 24)
715 # define RADEON_DP_SRC_SOURCE_HOST_DATA (3 << 24)
716 # define RADEON_GMC_CLR_CMP_CNTL_DIS (1 << 28)
717 # define RADEON_GMC_WR_MSK_DIS (1 << 30)
718 # define RADEON_ROP3_S 0x00cc0000
719 # define RADEON_ROP3_P 0x00f00000
720 #define RADEON_DP_WRITE_MASK 0x16cc
721 #define RADEON_SRC_PITCH_OFFSET 0x1428
722 #define RADEON_DST_PITCH_OFFSET 0x142c
723 #define RADEON_DST_PITCH_OFFSET_C 0x1c80
724 # define RADEON_DST_TILE_LINEAR (0 << 30)
725 # define RADEON_DST_TILE_MACRO (1 << 30)
726 # define RADEON_DST_TILE_MICRO (2 << 30)
727 # define RADEON_DST_TILE_BOTH (3 << 30)
728
729 #define RADEON_SCRATCH_REG0 0x15e0
730 #define RADEON_SCRATCH_REG1 0x15e4
731 #define RADEON_SCRATCH_REG2 0x15e8
732 #define RADEON_SCRATCH_REG3 0x15ec
733 #define RADEON_SCRATCH_REG4 0x15f0
734 #define RADEON_SCRATCH_REG5 0x15f4
735 #define RADEON_SCRATCH_UMSK 0x0770
736 #define RADEON_SCRATCH_ADDR 0x0774
737
738 #define RADEON_SCRATCHOFF( x ) (RADEON_SCRATCH_REG_OFFSET + 4*(x))
739
740 extern u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index);
741
742 #define GET_SCRATCH(dev_priv, x) radeon_get_scratch(dev_priv, x)
743
744 #define R600_SCRATCH_REG0 0x8500
745 #define R600_SCRATCH_REG1 0x8504
746 #define R600_SCRATCH_REG2 0x8508
747 #define R600_SCRATCH_REG3 0x850c
748 #define R600_SCRATCH_REG4 0x8510
749 #define R600_SCRATCH_REG5 0x8514
750 #define R600_SCRATCH_REG6 0x8518
751 #define R600_SCRATCH_REG7 0x851c
752 #define R600_SCRATCH_UMSK 0x8540
753 #define R600_SCRATCH_ADDR 0x8544
754
755 #define R600_SCRATCHOFF(x) (R600_SCRATCH_REG_OFFSET + 4*(x))
756
757 #define RADEON_GEN_INT_CNTL 0x0040
758 # define RADEON_CRTC_VBLANK_MASK (1 << 0)
759 # define RADEON_CRTC2_VBLANK_MASK (1 << 9)
760 # define RADEON_GUI_IDLE_INT_ENABLE (1 << 19)
761 # define RADEON_SW_INT_ENABLE (1 << 25)
762
763 #define RADEON_GEN_INT_STATUS 0x0044
764 # define RADEON_CRTC_VBLANK_STAT (1 << 0)
765 # define RADEON_CRTC_VBLANK_STAT_ACK (1 << 0)
766 # define RADEON_CRTC2_VBLANK_STAT (1 << 9)
767 # define RADEON_CRTC2_VBLANK_STAT_ACK (1 << 9)
768 # define RADEON_GUI_IDLE_INT_TEST_ACK (1 << 19)
769 # define RADEON_SW_INT_TEST (1 << 25)
770 # define RADEON_SW_INT_TEST_ACK (1 << 25)
771 # define RADEON_SW_INT_FIRE (1 << 26)
772 # define R500_DISPLAY_INT_STATUS (1 << 0)
773
774 #define RADEON_HOST_PATH_CNTL 0x0130
775 # define RADEON_HDP_SOFT_RESET (1 << 26)
776 # define RADEON_HDP_WC_TIMEOUT_MASK (7 << 28)
777 # define RADEON_HDP_WC_TIMEOUT_28BCLK (7 << 28)
778
779 #define RADEON_ISYNC_CNTL 0x1724
780 # define RADEON_ISYNC_ANY2D_IDLE3D (1 << 0)
781 # define RADEON_ISYNC_ANY3D_IDLE2D (1 << 1)
782 # define RADEON_ISYNC_TRIG2D_IDLE3D (1 << 2)
783 # define RADEON_ISYNC_TRIG3D_IDLE2D (1 << 3)
784 # define RADEON_ISYNC_WAIT_IDLEGUI (1 << 4)
785 # define RADEON_ISYNC_CPSCRATCH_IDLEGUI (1 << 5)
786
787 #define RADEON_RBBM_GUICNTL 0x172c
788 # define RADEON_HOST_DATA_SWAP_NONE (0 << 0)
789 # define RADEON_HOST_DATA_SWAP_16BIT (1 << 0)
790 # define RADEON_HOST_DATA_SWAP_32BIT (2 << 0)
791 # define RADEON_HOST_DATA_SWAP_HDW (3 << 0)
792
793 #define RADEON_MC_AGP_LOCATION 0x014c
794 #define RADEON_MC_FB_LOCATION 0x0148
795 #define RADEON_MCLK_CNTL 0x0012
796 # define RADEON_FORCEON_MCLKA (1 << 16)
797 # define RADEON_FORCEON_MCLKB (1 << 17)
798 # define RADEON_FORCEON_YCLKA (1 << 18)
799 # define RADEON_FORCEON_YCLKB (1 << 19)
800 # define RADEON_FORCEON_MC (1 << 20)
801 # define RADEON_FORCEON_AIC (1 << 21)
802
803 #define RADEON_PP_BORDER_COLOR_0 0x1d40
804 #define RADEON_PP_BORDER_COLOR_1 0x1d44
805 #define RADEON_PP_BORDER_COLOR_2 0x1d48
806 #define RADEON_PP_CNTL 0x1c38
807 # define RADEON_SCISSOR_ENABLE (1 << 1)
808 #define RADEON_PP_LUM_MATRIX 0x1d00
809 #define RADEON_PP_MISC 0x1c14
810 #define RADEON_PP_ROT_MATRIX_0 0x1d58
811 #define RADEON_PP_TXFILTER_0 0x1c54
812 #define RADEON_PP_TXOFFSET_0 0x1c5c
813 #define RADEON_PP_TXFILTER_1 0x1c6c
814 #define RADEON_PP_TXFILTER_2 0x1c84
815
816 #define R300_RB2D_DSTCACHE_CTLSTAT 0x342c /* use R300_DSTCACHE_CTLSTAT */
817 #define R300_DSTCACHE_CTLSTAT 0x1714
818 # define R300_RB2D_DC_FLUSH (3 << 0)
819 # define R300_RB2D_DC_FREE (3 << 2)
820 # define R300_RB2D_DC_FLUSH_ALL 0xf
821 # define R300_RB2D_DC_BUSY (1 << 31)
822 #define RADEON_RB3D_CNTL 0x1c3c
823 # define RADEON_ALPHA_BLEND_ENABLE (1 << 0)
824 # define RADEON_PLANE_MASK_ENABLE (1 << 1)
825 # define RADEON_DITHER_ENABLE (1 << 2)
826 # define RADEON_ROUND_ENABLE (1 << 3)
827 # define RADEON_SCALE_DITHER_ENABLE (1 << 4)
828 # define RADEON_DITHER_INIT (1 << 5)
829 # define RADEON_ROP_ENABLE (1 << 6)
830 # define RADEON_STENCIL_ENABLE (1 << 7)
831 # define RADEON_Z_ENABLE (1 << 8)
832 # define RADEON_ZBLOCK16 (1 << 15)
833 #define RADEON_RB3D_DEPTHOFFSET 0x1c24
834 #define RADEON_RB3D_DEPTHCLEARVALUE 0x3230
835 #define RADEON_RB3D_DEPTHPITCH 0x1c28
836 #define RADEON_RB3D_PLANEMASK 0x1d84
837 #define RADEON_RB3D_STENCILREFMASK 0x1d7c
838 #define RADEON_RB3D_ZCACHE_MODE 0x3250
839 #define RADEON_RB3D_ZCACHE_CTLSTAT 0x3254
840 # define RADEON_RB3D_ZC_FLUSH (1 << 0)
841 # define RADEON_RB3D_ZC_FREE (1 << 2)
842 # define RADEON_RB3D_ZC_FLUSH_ALL 0x5
843 # define RADEON_RB3D_ZC_BUSY (1 << 31)
844 #define R300_ZB_ZCACHE_CTLSTAT 0x4f18
845 # define R300_ZC_FLUSH (1 << 0)
846 # define R300_ZC_FREE (1 << 1)
847 # define R300_ZC_BUSY (1 << 31)
848 #define RADEON_RB3D_DSTCACHE_CTLSTAT 0x325c
849 # define RADEON_RB3D_DC_FLUSH (3 << 0)
850 # define RADEON_RB3D_DC_FREE (3 << 2)
851 # define RADEON_RB3D_DC_FLUSH_ALL 0xf
852 # define RADEON_RB3D_DC_BUSY (1 << 31)
853 #define R300_RB3D_DSTCACHE_CTLSTAT 0x4e4c
854 # define R300_RB3D_DC_FLUSH (2 << 0)
855 # define R300_RB3D_DC_FREE (2 << 2)
856 # define R300_RB3D_DC_FINISH (1 << 4)
857 #define RADEON_RB3D_ZSTENCILCNTL 0x1c2c
858 # define RADEON_Z_TEST_MASK (7 << 4)
859 # define RADEON_Z_TEST_ALWAYS (7 << 4)
860 # define RADEON_Z_HIERARCHY_ENABLE (1 << 8)
861 # define RADEON_STENCIL_TEST_ALWAYS (7 << 12)
862 # define RADEON_STENCIL_S_FAIL_REPLACE (2 << 16)
863 # define RADEON_STENCIL_ZPASS_REPLACE (2 << 20)
864 # define RADEON_STENCIL_ZFAIL_REPLACE (2 << 24)
865 # define RADEON_Z_COMPRESSION_ENABLE (1 << 28)
866 # define RADEON_FORCE_Z_DIRTY (1 << 29)
867 # define RADEON_Z_WRITE_ENABLE (1 << 30)
868 # define RADEON_Z_DECOMPRESSION_ENABLE (1 << 31)
869 #define RADEON_RBBM_SOFT_RESET 0x00f0
870 # define RADEON_SOFT_RESET_CP (1 << 0)
871 # define RADEON_SOFT_RESET_HI (1 << 1)
872 # define RADEON_SOFT_RESET_SE (1 << 2)
873 # define RADEON_SOFT_RESET_RE (1 << 3)
874 # define RADEON_SOFT_RESET_PP (1 << 4)
875 # define RADEON_SOFT_RESET_E2 (1 << 5)
876 # define RADEON_SOFT_RESET_RB (1 << 6)
877 # define RADEON_SOFT_RESET_HDP (1 << 7)
878 /*
879 * 6:0 Available slots in the FIFO
880 * 8 Host Interface active
881 * 9 CP request active
882 * 10 FIFO request active
883 * 11 Host Interface retry active
884 * 12 CP retry active
885 * 13 FIFO retry active
886 * 14 FIFO pipeline busy
887 * 15 Event engine busy
888 * 16 CP command stream busy
889 * 17 2D engine busy
890 * 18 2D portion of render backend busy
891 * 20 3D setup engine busy
892 * 26 GA engine busy
893 * 27 CBA 2D engine busy
894 * 31 2D engine busy or 3D engine busy or FIFO not empty or CP busy or
895 * command stream queue not empty or Ring Buffer not empty
896 */
897 #define RADEON_RBBM_STATUS 0x0e40
898 /* Same as the previous RADEON_RBBM_STATUS; this is a mirror of that register. */
899 /* #define RADEON_RBBM_STATUS 0x1740 */
900 /* bits 6:0 are dword slots available in the cmd fifo */
901 # define RADEON_RBBM_FIFOCNT_MASK 0x007f
902 # define RADEON_HIRQ_ON_RBB (1 << 8)
903 # define RADEON_CPRQ_ON_RBB (1 << 9)
904 # define RADEON_CFRQ_ON_RBB (1 << 10)
905 # define RADEON_HIRQ_IN_RTBUF (1 << 11)
906 # define RADEON_CPRQ_IN_RTBUF (1 << 12)
907 # define RADEON_CFRQ_IN_RTBUF (1 << 13)
908 # define RADEON_PIPE_BUSY (1 << 14)
909 # define RADEON_ENG_EV_BUSY (1 << 15)
910 # define RADEON_CP_CMDSTRM_BUSY (1 << 16)
911 # define RADEON_E2_BUSY (1 << 17)
912 # define RADEON_RB2D_BUSY (1 << 18)
913 # define RADEON_RB3D_BUSY (1 << 19) /* not used on r300 */
914 # define RADEON_VAP_BUSY (1 << 20)
915 # define RADEON_RE_BUSY (1 << 21) /* not used on r300 */
916 # define RADEON_TAM_BUSY (1 << 22) /* not used on r300 */
917 # define RADEON_TDM_BUSY (1 << 23) /* not used on r300 */
918 # define RADEON_PB_BUSY (1 << 24) /* not used on r300 */
919 # define RADEON_TIM_BUSY (1 << 25) /* not used on r300 */
920 # define RADEON_GA_BUSY (1 << 26)
921 # define RADEON_CBA2D_BUSY (1 << 27)
922 # define RADEON_RBBM_ACTIVE (1 << 31)
923 #define RADEON_RE_LINE_PATTERN 0x1cd0
924 #define RADEON_RE_MISC 0x26c4
925 #define RADEON_RE_TOP_LEFT 0x26c0
926 #define RADEON_RE_WIDTH_HEIGHT 0x1c44
927 #define RADEON_RE_STIPPLE_ADDR 0x1cc8
928 #define RADEON_RE_STIPPLE_DATA 0x1ccc
929
930 #define RADEON_SCISSOR_TL_0 0x1cd8
931 #define RADEON_SCISSOR_BR_0 0x1cdc
932 #define RADEON_SCISSOR_TL_1 0x1ce0
933 #define RADEON_SCISSOR_BR_1 0x1ce4
934 #define RADEON_SCISSOR_TL_2 0x1ce8
935 #define RADEON_SCISSOR_BR_2 0x1cec
936 #define RADEON_SE_COORD_FMT 0x1c50
937 #define RADEON_SE_CNTL 0x1c4c
938 # define RADEON_FFACE_CULL_CW (0 << 0)
939 # define RADEON_BFACE_SOLID (3 << 1)
940 # define RADEON_FFACE_SOLID (3 << 3)
941 # define RADEON_FLAT_SHADE_VTX_LAST (3 << 6)
942 # define RADEON_DIFFUSE_SHADE_FLAT (1 << 8)
943 # define RADEON_DIFFUSE_SHADE_GOURAUD (2 << 8)
944 # define RADEON_ALPHA_SHADE_FLAT (1 << 10)
945 # define RADEON_ALPHA_SHADE_GOURAUD (2 << 10)
946 # define RADEON_SPECULAR_SHADE_FLAT (1 << 12)
947 # define RADEON_SPECULAR_SHADE_GOURAUD (2 << 12)
948 # define RADEON_FOG_SHADE_FLAT (1 << 14)
949 # define RADEON_FOG_SHADE_GOURAUD (2 << 14)
950 # define RADEON_VPORT_XY_XFORM_ENABLE (1 << 24)
951 # define RADEON_VPORT_Z_XFORM_ENABLE (1 << 25)
952 # define RADEON_VTX_PIX_CENTER_OGL (1 << 27)
953 # define RADEON_ROUND_MODE_TRUNC (0 << 28)
954 # define RADEON_ROUND_PREC_8TH_PIX (1 << 30)
955 #define RADEON_SE_CNTL_STATUS 0x2140
956 #define RADEON_SE_LINE_WIDTH 0x1db8
957 #define RADEON_SE_VPORT_XSCALE 0x1d98
958 #define RADEON_SE_ZBIAS_FACTOR 0x1db0
959 #define RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED 0x2210
960 #define RADEON_SE_TCL_OUTPUT_VTX_FMT 0x2254
961 #define RADEON_SE_TCL_VECTOR_INDX_REG 0x2200
962 # define RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT 16
963 # define RADEON_VEC_INDX_DWORD_COUNT_SHIFT 28
964 #define RADEON_SE_TCL_VECTOR_DATA_REG 0x2204
965 #define RADEON_SE_TCL_SCALAR_INDX_REG 0x2208
966 # define RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT 16
967 #define RADEON_SE_TCL_SCALAR_DATA_REG 0x220C
968 #define RADEON_SURFACE_ACCESS_FLAGS 0x0bf8
969 #define RADEON_SURFACE_ACCESS_CLR 0x0bfc
970 #define RADEON_SURFACE_CNTL 0x0b00
971 # define RADEON_SURF_TRANSLATION_DIS (1 << 8)
972 # define RADEON_NONSURF_AP0_SWP_MASK (3 << 20)
973 # define RADEON_NONSURF_AP0_SWP_LITTLE (0 << 20)
974 # define RADEON_NONSURF_AP0_SWP_BIG16 (1 << 20)
975 # define RADEON_NONSURF_AP0_SWP_BIG32 (2 << 20)
976 # define RADEON_NONSURF_AP1_SWP_MASK (3 << 22)
977 # define RADEON_NONSURF_AP1_SWP_LITTLE (0 << 22)
978 # define RADEON_NONSURF_AP1_SWP_BIG16 (1 << 22)
979 # define RADEON_NONSURF_AP1_SWP_BIG32 (2 << 22)
980 #define RADEON_SURFACE0_INFO 0x0b0c
981 # define RADEON_SURF_PITCHSEL_MASK (0x1ff << 0)
982 # define RADEON_SURF_TILE_MODE_MASK (3 << 16)
983 # define RADEON_SURF_TILE_MODE_MACRO (0 << 16)
984 # define RADEON_SURF_TILE_MODE_MICRO (1 << 16)
985 # define RADEON_SURF_TILE_MODE_32BIT_Z (2 << 16)
986 # define RADEON_SURF_TILE_MODE_16BIT_Z (3 << 16)
987 #define RADEON_SURFACE0_LOWER_BOUND 0x0b04
988 #define RADEON_SURFACE0_UPPER_BOUND 0x0b08
989 # define RADEON_SURF_ADDRESS_FIXED_MASK (0x3ff << 0)
990 #define RADEON_SURFACE1_INFO 0x0b1c
991 #define RADEON_SURFACE1_LOWER_BOUND 0x0b14
992 #define RADEON_SURFACE1_UPPER_BOUND 0x0b18
993 #define RADEON_SURFACE2_INFO 0x0b2c
994 #define RADEON_SURFACE2_LOWER_BOUND 0x0b24
995 #define RADEON_SURFACE2_UPPER_BOUND 0x0b28
996 #define RADEON_SURFACE3_INFO 0x0b3c
997 #define RADEON_SURFACE3_LOWER_BOUND 0x0b34
998 #define RADEON_SURFACE3_UPPER_BOUND 0x0b38
999 #define RADEON_SURFACE4_INFO 0x0b4c
1000 #define RADEON_SURFACE4_LOWER_BOUND 0x0b44
1001 #define RADEON_SURFACE4_UPPER_BOUND 0x0b48
1002 #define RADEON_SURFACE5_INFO 0x0b5c
1003 #define RADEON_SURFACE5_LOWER_BOUND 0x0b54
1004 #define RADEON_SURFACE5_UPPER_BOUND 0x0b58
1005 #define RADEON_SURFACE6_INFO 0x0b6c
1006 #define RADEON_SURFACE6_LOWER_BOUND 0x0b64
1007 #define RADEON_SURFACE6_UPPER_BOUND 0x0b68
1008 #define RADEON_SURFACE7_INFO 0x0b7c
1009 #define RADEON_SURFACE7_LOWER_BOUND 0x0b74
1010 #define RADEON_SURFACE7_UPPER_BOUND 0x0b78
1011 #define RADEON_SW_SEMAPHORE 0x013c
1012
1013 #define RADEON_WAIT_UNTIL 0x1720
1014 # define RADEON_WAIT_CRTC_PFLIP (1 << 0)
1015 # define RADEON_WAIT_2D_IDLE (1 << 14)
1016 # define RADEON_WAIT_3D_IDLE (1 << 15)
1017 # define RADEON_WAIT_2D_IDLECLEAN (1 << 16)
1018 # define RADEON_WAIT_3D_IDLECLEAN (1 << 17)
1019 # define RADEON_WAIT_HOST_IDLECLEAN (1 << 18)
1020
1021 #define RADEON_RB3D_ZMASKOFFSET 0x3234
1022 #define RADEON_RB3D_ZSTENCILCNTL 0x1c2c
1023 # define RADEON_DEPTH_FORMAT_16BIT_INT_Z (0 << 0)
1024 # define RADEON_DEPTH_FORMAT_24BIT_INT_Z (2 << 0)
1025
1026 /* CP registers */
1027 #define RADEON_CP_ME_RAM_ADDR 0x07d4
1028 #define RADEON_CP_ME_RAM_RADDR 0x07d8
1029 #define RADEON_CP_ME_RAM_DATAH 0x07dc
1030 #define RADEON_CP_ME_RAM_DATAL 0x07e0
1031
1032 #define RADEON_CP_RB_BASE 0x0700
1033 #define RADEON_CP_RB_CNTL 0x0704
1034 # define RADEON_BUF_SWAP_32BIT (2 << 16)
1035 # define RADEON_RB_NO_UPDATE (1 << 27)
1036 # define RADEON_RB_RPTR_WR_ENA (1 << 31)
1037 #define RADEON_CP_RB_RPTR_ADDR 0x070c
1038 #define RADEON_CP_RB_RPTR 0x0710
1039 #define RADEON_CP_RB_WPTR 0x0714
1040
1041 #define RADEON_CP_RB_WPTR_DELAY 0x0718
1042 # define RADEON_PRE_WRITE_TIMER_SHIFT 0
1043 # define RADEON_PRE_WRITE_LIMIT_SHIFT 23
1044
1045 #define RADEON_CP_IB_BASE 0x0738
1046
1047 #define RADEON_CP_CSQ_CNTL 0x0740
1048 # define RADEON_CSQ_CNT_PRIMARY_MASK (0xff << 0)
1049 # define RADEON_CSQ_PRIDIS_INDDIS (0 << 28)
1050 # define RADEON_CSQ_PRIPIO_INDDIS (1 << 28)
1051 # define RADEON_CSQ_PRIBM_INDDIS (2 << 28)
1052 # define RADEON_CSQ_PRIPIO_INDBM (3 << 28)
1053 # define RADEON_CSQ_PRIBM_INDBM (4 << 28)
1054 # define RADEON_CSQ_PRIPIO_INDPIO (15 << 28)
1055
1056 #define R300_CP_RESYNC_ADDR 0x0778
1057 #define R300_CP_RESYNC_DATA 0x077c
1058
1059 #define RADEON_AIC_CNTL 0x01d0
1060 # define RADEON_PCIGART_TRANSLATE_EN (1 << 0)
1061 # define RS400_MSI_REARM (1 << 3)
1062 #define RADEON_AIC_STAT 0x01d4
1063 #define RADEON_AIC_PT_BASE 0x01d8
1064 #define RADEON_AIC_LO_ADDR 0x01dc
1065 #define RADEON_AIC_HI_ADDR 0x01e0
1066 #define RADEON_AIC_TLB_ADDR 0x01e4
1067 #define RADEON_AIC_TLB_DATA 0x01e8
1068
1069 /* CP command packets */
1070 #define RADEON_CP_PACKET0 0x00000000
1071 # define RADEON_ONE_REG_WR (1 << 15)
1072 #define RADEON_CP_PACKET1 0x40000000
1073 #define RADEON_CP_PACKET2 0x80000000
1074 #define RADEON_CP_PACKET3 0xC0000000
1075 # define RADEON_CP_NOP 0x00001000
1076 # define RADEON_CP_NEXT_CHAR 0x00001900
1077 # define RADEON_CP_PLY_NEXTSCAN 0x00001D00
1078 # define RADEON_CP_SET_SCISSORS 0x00001E00
1079 /* GEN_INDX_PRIM is unsupported starting with R300 */
1080 # define RADEON_3D_RNDR_GEN_INDX_PRIM 0x00002300
1081 # define RADEON_WAIT_FOR_IDLE 0x00002600
1082 # define RADEON_3D_DRAW_VBUF 0x00002800
1083 # define RADEON_3D_DRAW_IMMD 0x00002900
1084 # define RADEON_3D_DRAW_INDX 0x00002A00
1085 # define RADEON_CP_LOAD_PALETTE 0x00002C00
1086 # define RADEON_3D_LOAD_VBPNTR 0x00002F00
1087 # define RADEON_MPEG_IDCT_MACROBLOCK 0x00003000
1088 # define RADEON_MPEG_IDCT_MACROBLOCK_REV 0x00003100
1089 # define RADEON_3D_CLEAR_ZMASK 0x00003200
1090 # define RADEON_CP_INDX_BUFFER 0x00003300
1091 # define RADEON_CP_3D_DRAW_VBUF_2 0x00003400
1092 # define RADEON_CP_3D_DRAW_IMMD_2 0x00003500
1093 # define RADEON_CP_3D_DRAW_INDX_2 0x00003600
1094 # define RADEON_3D_CLEAR_HIZ 0x00003700
1095 # define RADEON_CP_3D_CLEAR_CMASK 0x00003802
1096 # define RADEON_CNTL_HOSTDATA_BLT 0x00009400
1097 # define RADEON_CNTL_PAINT_MULTI 0x00009A00
1098 # define RADEON_CNTL_BITBLT_MULTI 0x00009B00
1099 # define RADEON_CNTL_SET_SCISSORS 0xC0001E00
1100
1101 # define R600_IT_INDIRECT_BUFFER_END 0x00001700
1102 # define R600_IT_SET_PREDICATION 0x00002000
1103 # define R600_IT_REG_RMW 0x00002100
1104 # define R600_IT_COND_EXEC 0x00002200
1105 # define R600_IT_PRED_EXEC 0x00002300
1106 # define R600_IT_START_3D_CMDBUF 0x00002400
1107 # define R600_IT_DRAW_INDEX_2 0x00002700
1108 # define R600_IT_CONTEXT_CONTROL 0x00002800
1109 # define R600_IT_DRAW_INDEX_IMMD_BE 0x00002900
1110 # define R600_IT_INDEX_TYPE 0x00002A00
1111 # define R600_IT_DRAW_INDEX 0x00002B00
1112 # define R600_IT_DRAW_INDEX_AUTO 0x00002D00
1113 # define R600_IT_DRAW_INDEX_IMMD 0x00002E00
1114 # define R600_IT_NUM_INSTANCES 0x00002F00
1115 # define R600_IT_STRMOUT_BUFFER_UPDATE 0x00003400
1116 # define R600_IT_INDIRECT_BUFFER_MP 0x00003800
1117 # define R600_IT_MEM_SEMAPHORE 0x00003900
1118 # define R600_IT_MPEG_INDEX 0x00003A00
1119 # define R600_IT_WAIT_REG_MEM 0x00003C00
1120 # define R600_IT_MEM_WRITE 0x00003D00
1121 # define R600_IT_INDIRECT_BUFFER 0x00003200
1122 # define R600_IT_SURFACE_SYNC 0x00004300
1123 # define R600_CB0_DEST_BASE_ENA (1 << 6)
1124 # define R600_TC_ACTION_ENA (1 << 23)
1125 # define R600_VC_ACTION_ENA (1 << 24)
1126 # define R600_CB_ACTION_ENA (1 << 25)
1127 # define R600_DB_ACTION_ENA (1 << 26)
1128 # define R600_SH_ACTION_ENA (1 << 27)
1129 # define R600_SMX_ACTION_ENA (1 << 28)
1130 # define R600_IT_ME_INITIALIZE 0x00004400
1131 # define R600_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16)
1132 # define R600_IT_COND_WRITE 0x00004500
1133 # define R600_IT_EVENT_WRITE 0x00004600
1134 # define R600_IT_EVENT_WRITE_EOP 0x00004700
1135 # define R600_IT_ONE_REG_WRITE 0x00005700
1136 # define R600_IT_SET_CONFIG_REG 0x00006800
1137 # define R600_SET_CONFIG_REG_OFFSET 0x00008000
1138 # define R600_SET_CONFIG_REG_END 0x0000ac00
1139 # define R600_IT_SET_CONTEXT_REG 0x00006900
1140 # define R600_SET_CONTEXT_REG_OFFSET 0x00028000
1141 # define R600_SET_CONTEXT_REG_END 0x00029000
1142 # define R600_IT_SET_ALU_CONST 0x00006A00
1143 # define R600_SET_ALU_CONST_OFFSET 0x00030000
1144 # define R600_SET_ALU_CONST_END 0x00032000
1145 # define R600_IT_SET_BOOL_CONST 0x00006B00
1146 # define R600_SET_BOOL_CONST_OFFSET 0x0003e380
1147 # define R600_SET_BOOL_CONST_END 0x00040000
1148 # define R600_IT_SET_LOOP_CONST 0x00006C00
1149 # define R600_SET_LOOP_CONST_OFFSET 0x0003e200
1150 # define R600_SET_LOOP_CONST_END 0x0003e380
1151 # define R600_IT_SET_RESOURCE 0x00006D00
1152 # define R600_SET_RESOURCE_OFFSET 0x00038000
1153 # define R600_SET_RESOURCE_END 0x0003c000
1154 # define R600_SQ_TEX_VTX_INVALID_TEXTURE 0x0
1155 # define R600_SQ_TEX_VTX_INVALID_BUFFER 0x1
1156 # define R600_SQ_TEX_VTX_VALID_TEXTURE 0x2
1157 # define R600_SQ_TEX_VTX_VALID_BUFFER 0x3
1158 # define R600_IT_SET_SAMPLER 0x00006E00
1159 # define R600_SET_SAMPLER_OFFSET 0x0003c000
1160 # define R600_SET_SAMPLER_END 0x0003cff0
1161 # define R600_IT_SET_CTL_CONST 0x00006F00
1162 # define R600_SET_CTL_CONST_OFFSET 0x0003cff0
1163 # define R600_SET_CTL_CONST_END 0x0003e200
1164 # define R600_IT_SURFACE_BASE_UPDATE 0x00007300
1165
1166 #define RADEON_CP_PACKET_MASK 0xC0000000
1167 #define RADEON_CP_PACKET_COUNT_MASK 0x3fff0000
1168 #define RADEON_CP_PACKET0_REG_MASK 0x000007ff
1169 #define RADEON_CP_PACKET1_REG0_MASK 0x000007ff
1170 #define RADEON_CP_PACKET1_REG1_MASK 0x003ff800
1171
1172 #define RADEON_VTX_Z_PRESENT (1 << 31)
1173 #define RADEON_VTX_PKCOLOR_PRESENT (1 << 3)
1174
1175 #define RADEON_PRIM_TYPE_NONE (0 << 0)
1176 #define RADEON_PRIM_TYPE_POINT (1 << 0)
1177 #define RADEON_PRIM_TYPE_LINE (2 << 0)
1178 #define RADEON_PRIM_TYPE_LINE_STRIP (3 << 0)
1179 #define RADEON_PRIM_TYPE_TRI_LIST (4 << 0)
1180 #define RADEON_PRIM_TYPE_TRI_FAN (5 << 0)
1181 #define RADEON_PRIM_TYPE_TRI_STRIP (6 << 0)
1182 #define RADEON_PRIM_TYPE_TRI_TYPE2 (7 << 0)
1183 #define RADEON_PRIM_TYPE_RECT_LIST (8 << 0)
1184 #define RADEON_PRIM_TYPE_3VRT_POINT_LIST (9 << 0)
1185 #define RADEON_PRIM_TYPE_3VRT_LINE_LIST (10 << 0)
1186 #define RADEON_PRIM_TYPE_MASK 0xf
1187 #define RADEON_PRIM_WALK_IND (1 << 4)
1188 #define RADEON_PRIM_WALK_LIST (2 << 4)
1189 #define RADEON_PRIM_WALK_RING (3 << 4)
1190 #define RADEON_COLOR_ORDER_BGRA (0 << 6)
1191 #define RADEON_COLOR_ORDER_RGBA (1 << 6)
1192 #define RADEON_MAOS_ENABLE (1 << 7)
1193 #define RADEON_VTX_FMT_R128_MODE (0 << 8)
1194 #define RADEON_VTX_FMT_RADEON_MODE (1 << 8)
1195 #define RADEON_NUM_VERTICES_SHIFT 16
1196
1197 #define RADEON_COLOR_FORMAT_CI8 2
1198 #define RADEON_COLOR_FORMAT_ARGB1555 3
1199 #define RADEON_COLOR_FORMAT_RGB565 4
1200 #define RADEON_COLOR_FORMAT_ARGB8888 6
1201 #define RADEON_COLOR_FORMAT_RGB332 7
1202 #define RADEON_COLOR_FORMAT_RGB8 9
1203 #define RADEON_COLOR_FORMAT_ARGB4444 15
1204
1205 #define RADEON_TXFORMAT_I8 0
1206 #define RADEON_TXFORMAT_AI88 1
1207 #define RADEON_TXFORMAT_RGB332 2
1208 #define RADEON_TXFORMAT_ARGB1555 3
1209 #define RADEON_TXFORMAT_RGB565 4
1210 #define RADEON_TXFORMAT_ARGB4444 5
1211 #define RADEON_TXFORMAT_ARGB8888 6
1212 #define RADEON_TXFORMAT_RGBA8888 7
1213 #define RADEON_TXFORMAT_Y8 8
1214 #define RADEON_TXFORMAT_VYUY422 10
1215 #define RADEON_TXFORMAT_YVYU422 11
1216 #define RADEON_TXFORMAT_DXT1 12
1217 #define RADEON_TXFORMAT_DXT23 14
1218 #define RADEON_TXFORMAT_DXT45 15
1219
1220 #define R200_PP_TXCBLEND_0 0x2f00
1221 #define R200_PP_TXCBLEND_1 0x2f10
1222 #define R200_PP_TXCBLEND_2 0x2f20
1223 #define R200_PP_TXCBLEND_3 0x2f30
1224 #define R200_PP_TXCBLEND_4 0x2f40
1225 #define R200_PP_TXCBLEND_5 0x2f50
1226 #define R200_PP_TXCBLEND_6 0x2f60
1227 #define R200_PP_TXCBLEND_7 0x2f70
1228 #define R200_SE_TCL_LIGHT_MODEL_CTL_0 0x2268
1229 #define R200_PP_TFACTOR_0 0x2ee0
1230 #define R200_SE_VTX_FMT_0 0x2088
1231 #define R200_SE_VAP_CNTL 0x2080
1232 #define R200_SE_TCL_MATRIX_SEL_0 0x2230
1233 #define R200_SE_TCL_TEX_PROC_CTL_2 0x22a8
1234 #define R200_SE_TCL_UCP_VERT_BLEND_CTL 0x22c0
1235 #define R200_PP_TXFILTER_5 0x2ca0
1236 #define R200_PP_TXFILTER_4 0x2c80
1237 #define R200_PP_TXFILTER_3 0x2c60
1238 #define R200_PP_TXFILTER_2 0x2c40
1239 #define R200_PP_TXFILTER_1 0x2c20
1240 #define R200_PP_TXFILTER_0 0x2c00
1241 #define R200_PP_TXOFFSET_5 0x2d78
1242 #define R200_PP_TXOFFSET_4 0x2d60
1243 #define R200_PP_TXOFFSET_3 0x2d48
1244 #define R200_PP_TXOFFSET_2 0x2d30
1245 #define R200_PP_TXOFFSET_1 0x2d18
1246 #define R200_PP_TXOFFSET_0 0x2d00
1247
1248 #define R200_PP_CUBIC_FACES_0 0x2c18
1249 #define R200_PP_CUBIC_FACES_1 0x2c38
1250 #define R200_PP_CUBIC_FACES_2 0x2c58
1251 #define R200_PP_CUBIC_FACES_3 0x2c78
1252 #define R200_PP_CUBIC_FACES_4 0x2c98
1253 #define R200_PP_CUBIC_FACES_5 0x2cb8
1254 #define R200_PP_CUBIC_OFFSET_F1_0 0x2d04
1255 #define R200_PP_CUBIC_OFFSET_F2_0 0x2d08
1256 #define R200_PP_CUBIC_OFFSET_F3_0 0x2d0c
1257 #define R200_PP_CUBIC_OFFSET_F4_0 0x2d10
1258 #define R200_PP_CUBIC_OFFSET_F5_0 0x2d14
1259 #define R200_PP_CUBIC_OFFSET_F1_1 0x2d1c
1260 #define R200_PP_CUBIC_OFFSET_F2_1 0x2d20
1261 #define R200_PP_CUBIC_OFFSET_F3_1 0x2d24
1262 #define R200_PP_CUBIC_OFFSET_F4_1 0x2d28
1263 #define R200_PP_CUBIC_OFFSET_F5_1 0x2d2c
1264 #define R200_PP_CUBIC_OFFSET_F1_2 0x2d34
1265 #define R200_PP_CUBIC_OFFSET_F2_2 0x2d38
1266 #define R200_PP_CUBIC_OFFSET_F3_2 0x2d3c
1267 #define R200_PP_CUBIC_OFFSET_F4_2 0x2d40
1268 #define R200_PP_CUBIC_OFFSET_F5_2 0x2d44
1269 #define R200_PP_CUBIC_OFFSET_F1_3 0x2d4c
1270 #define R200_PP_CUBIC_OFFSET_F2_3 0x2d50
1271 #define R200_PP_CUBIC_OFFSET_F3_3 0x2d54
1272 #define R200_PP_CUBIC_OFFSET_F4_3 0x2d58
1273 #define R200_PP_CUBIC_OFFSET_F5_3 0x2d5c
1274 #define R200_PP_CUBIC_OFFSET_F1_4 0x2d64
1275 #define R200_PP_CUBIC_OFFSET_F2_4 0x2d68
1276 #define R200_PP_CUBIC_OFFSET_F3_4 0x2d6c
1277 #define R200_PP_CUBIC_OFFSET_F4_4 0x2d70
1278 #define R200_PP_CUBIC_OFFSET_F5_4 0x2d74
1279 #define R200_PP_CUBIC_OFFSET_F1_5 0x2d7c
1280 #define R200_PP_CUBIC_OFFSET_F2_5 0x2d80
1281 #define R200_PP_CUBIC_OFFSET_F3_5 0x2d84
1282 #define R200_PP_CUBIC_OFFSET_F4_5 0x2d88
1283 #define R200_PP_CUBIC_OFFSET_F5_5 0x2d8c
1284
1285 #define R200_RE_AUX_SCISSOR_CNTL 0x26f0
1286 #define R200_SE_VTE_CNTL 0x20b0
1287 #define R200_SE_TCL_OUTPUT_VTX_COMP_SEL 0x2250
1288 #define R200_PP_TAM_DEBUG3 0x2d9c
1289 #define R200_PP_CNTL_X 0x2cc4
1290 #define R200_SE_VAP_CNTL_STATUS 0x2140
1291 #define R200_RE_SCISSOR_TL_0 0x1cd8
1292 #define R200_RE_SCISSOR_TL_1 0x1ce0
1293 #define R200_RE_SCISSOR_TL_2 0x1ce8
1294 #define R200_RB3D_DEPTHXY_OFFSET 0x1d60
1295 #define R200_RE_AUX_SCISSOR_CNTL 0x26f0
1296 #define R200_SE_VTX_STATE_CNTL 0x2180
1297 #define R200_RE_POINTSIZE 0x2648
1298 #define R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0 0x2254
1299
1300 #define RADEON_PP_TEX_SIZE_0 0x1d04 /* NPOT */
1301 #define RADEON_PP_TEX_SIZE_1 0x1d0c
1302 #define RADEON_PP_TEX_SIZE_2 0x1d14
1303
1304 #define RADEON_PP_CUBIC_FACES_0 0x1d24
1305 #define RADEON_PP_CUBIC_FACES_1 0x1d28
1306 #define RADEON_PP_CUBIC_FACES_2 0x1d2c
1307 #define RADEON_PP_CUBIC_OFFSET_T0_0 0x1dd0 /* bits [31:5] */
1308 #define RADEON_PP_CUBIC_OFFSET_T1_0 0x1e00
1309 #define RADEON_PP_CUBIC_OFFSET_T2_0 0x1e14
1310
1311 #define RADEON_SE_TCL_STATE_FLUSH 0x2284
1312
1313 #define SE_VAP_CNTL__TCL_ENA_MASK 0x00000001
1314 #define SE_VAP_CNTL__FORCE_W_TO_ONE_MASK 0x00010000
1315 #define SE_VAP_CNTL__VF_MAX_VTX_NUM__SHIFT 0x00000012
1316 #define SE_VTE_CNTL__VTX_XY_FMT_MASK 0x00000100
1317 #define SE_VTE_CNTL__VTX_Z_FMT_MASK 0x00000200
1318 #define SE_VTX_FMT_0__VTX_Z0_PRESENT_MASK 0x00000001
1319 #define SE_VTX_FMT_0__VTX_W0_PRESENT_MASK 0x00000002
1320 #define SE_VTX_FMT_0__VTX_COLOR_0_FMT__SHIFT 0x0000000b
1321 #define R200_3D_DRAW_IMMD_2 0xC0003500
1322 #define R200_SE_VTX_FMT_1 0x208c
1323 #define R200_RE_CNTL 0x1c50
1324
1325 #define R200_RB3D_BLENDCOLOR 0x3218
1326
1327 #define R200_SE_TCL_POINT_SPRITE_CNTL 0x22c4
1328
1329 #define R200_PP_TRI_PERF 0x2cf8
1330
1331 #define R200_PP_AFS_0 0x2f80
1332 #define R200_PP_AFS_1 0x2f00 /* same as txcblend_0 */
1333
1334 #define R200_VAP_PVS_CNTL_1 0x22D0
1335
1336 #define RADEON_CRTC_CRNT_FRAME 0x0214
1337 #define RADEON_CRTC2_CRNT_FRAME 0x0314
1338
1339 #define R500_D1CRTC_STATUS 0x609c
1340 #define R500_D2CRTC_STATUS 0x689c
1341 #define R500_CRTC_V_BLANK (1<<0)
1342
1343 #define R500_D1CRTC_FRAME_COUNT 0x60a4
1344 #define R500_D2CRTC_FRAME_COUNT 0x68a4
1345
1346 #define R500_D1MODE_V_COUNTER 0x6530
1347 #define R500_D2MODE_V_COUNTER 0x6d30
1348
1349 #define R500_D1MODE_VBLANK_STATUS 0x6534
1350 #define R500_D2MODE_VBLANK_STATUS 0x6d34
1351 #define R500_VBLANK_OCCURED (1<<0)
1352 #define R500_VBLANK_ACK (1<<4)
1353 #define R500_VBLANK_STAT (1<<12)
1354 #define R500_VBLANK_INT (1<<16)
1355
1356 #define R500_DxMODE_INT_MASK 0x6540
1357 #define R500_D1MODE_INT_MASK (1<<0)
1358 #define R500_D2MODE_INT_MASK (1<<8)
1359
1360 #define R500_DISP_INTERRUPT_STATUS 0x7edc
1361 #define R500_D1_VBLANK_INTERRUPT (1 << 4)
1362 #define R500_D2_VBLANK_INTERRUPT (1 << 5)
1363
1364 /* R6xx/R7xx registers */
1365 #define R600_MC_VM_FB_LOCATION 0x2180
1366 #define R600_MC_VM_AGP_TOP 0x2184
1367 #define R600_MC_VM_AGP_BOT 0x2188
1368 #define R600_MC_VM_AGP_BASE 0x218c
1369 #define R600_MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2190
1370 #define R600_MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2194
1371 #define R600_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x2198
1372
1373 #define R700_MC_VM_FB_LOCATION 0x2024
1374 #define R700_MC_VM_AGP_TOP 0x2028
1375 #define R700_MC_VM_AGP_BOT 0x202c
1376 #define R700_MC_VM_AGP_BASE 0x2030
1377 #define R700_MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034
1378 #define R700_MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038
1379 #define R700_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203c
1380
1381 #define R600_MCD_RD_A_CNTL 0x219c
1382 #define R600_MCD_RD_B_CNTL 0x21a0
1383
1384 #define R600_MCD_WR_A_CNTL 0x21a4
1385 #define R600_MCD_WR_B_CNTL 0x21a8
1386
1387 #define R600_MCD_RD_SYS_CNTL 0x2200
1388 #define R600_MCD_WR_SYS_CNTL 0x2214
1389
1390 #define R600_MCD_RD_GFX_CNTL 0x21fc
1391 #define R600_MCD_RD_HDP_CNTL 0x2204
1392 #define R600_MCD_RD_PDMA_CNTL 0x2208
1393 #define R600_MCD_RD_SEM_CNTL 0x220c
1394 #define R600_MCD_WR_GFX_CNTL 0x2210
1395 #define R600_MCD_WR_HDP_CNTL 0x2218
1396 #define R600_MCD_WR_PDMA_CNTL 0x221c
1397 #define R600_MCD_WR_SEM_CNTL 0x2220
1398
1399 # define R600_MCD_L1_TLB (1 << 0)
1400 # define R600_MCD_L1_FRAG_PROC (1 << 1)
1401 # define R600_MCD_L1_STRICT_ORDERING (1 << 2)
1402
1403 # define R600_MCD_SYSTEM_ACCESS_MODE_MASK (3 << 6)
1404 # define R600_MCD_SYSTEM_ACCESS_MODE_PA_ONLY (0 << 6)
1405 # define R600_MCD_SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 6)
1406 # define R600_MCD_SYSTEM_ACCESS_MODE_IN_SYS (2 << 6)
1407 # define R600_MCD_SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 6)
1408
1409 # define R600_MCD_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 8)
1410 # define R600_MCD_SYSTEM_APERTURE_UNMAPPED_ACCESS_DEFAULT_PAGE (1 << 8)
1411
1412 # define R600_MCD_SEMAPHORE_MODE (1 << 10)
1413 # define R600_MCD_WAIT_L2_QUERY (1 << 11)
1414 # define R600_MCD_EFFECTIVE_L1_TLB_SIZE(x) ((x) << 12)
1415 # define R600_MCD_EFFECTIVE_L1_QUEUE_SIZE(x) ((x) << 15)
1416
1417 #define R700_MC_VM_MD_L1_TLB0_CNTL 0x2654
1418 #define R700_MC_VM_MD_L1_TLB1_CNTL 0x2658
1419 #define R700_MC_VM_MD_L1_TLB2_CNTL 0x265c
1420
1421 #define R700_MC_VM_MB_L1_TLB0_CNTL 0x2234
1422 #define R700_MC_VM_MB_L1_TLB1_CNTL 0x2238
1423 #define R700_MC_VM_MB_L1_TLB2_CNTL 0x223c
1424 #define R700_MC_VM_MB_L1_TLB3_CNTL 0x2240
1425
1426 # define R700_ENABLE_L1_TLB (1 << 0)
1427 # define R700_ENABLE_L1_FRAGMENT_PROCESSING (1 << 1)
1428 # define R700_SYSTEM_ACCESS_MODE_IN_SYS (2 << 3)
1429 # define R700_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5)
1430 # define R700_EFFECTIVE_L1_TLB_SIZE(x) ((x) << 15)
1431 # define R700_EFFECTIVE_L1_QUEUE_SIZE(x) ((x) << 18)
1432
1433 #define R700_MC_ARB_RAMCFG 0x2760
1434 # define R700_NOOFBANK_SHIFT 0
1435 # define R700_NOOFBANK_MASK 0x3
1436 # define R700_NOOFRANK_SHIFT 2
1437 # define R700_NOOFRANK_MASK 0x1
1438 # define R700_NOOFROWS_SHIFT 3
1439 # define R700_NOOFROWS_MASK 0x7
1440 # define R700_NOOFCOLS_SHIFT 6
1441 # define R700_NOOFCOLS_MASK 0x3
1442 # define R700_CHANSIZE_SHIFT 8
1443 # define R700_CHANSIZE_MASK 0x1
1444 # define R700_BURSTLENGTH_SHIFT 9
1445 # define R700_BURSTLENGTH_MASK 0x1
1446 #define R600_RAMCFG 0x2408
1447 # define R600_NOOFBANK_SHIFT 0
1448 # define R600_NOOFBANK_MASK 0x1
1449 # define R600_NOOFRANK_SHIFT 1
1450 # define R600_NOOFRANK_MASK 0x1
1451 # define R600_NOOFROWS_SHIFT 2
1452 # define R600_NOOFROWS_MASK 0x7
1453 # define R600_NOOFCOLS_SHIFT 5
1454 # define R600_NOOFCOLS_MASK 0x3
1455 # define R600_CHANSIZE_SHIFT 7
1456 # define R600_CHANSIZE_MASK 0x1
1457 # define R600_BURSTLENGTH_SHIFT 8
1458 # define R600_BURSTLENGTH_MASK 0x1
1459
1460 #define R600_VM_L2_CNTL 0x1400
1461 # define R600_VM_L2_CACHE_EN (1 << 0)
1462 # define R600_VM_L2_FRAG_PROC (1 << 1)
1463 # define R600_VM_ENABLE_PTE_CACHE_LRU_W (1 << 9)
1464 # define R600_VM_L2_CNTL_QUEUE_SIZE(x) ((x) << 13)
1465 # define R700_VM_L2_CNTL_QUEUE_SIZE(x) ((x) << 14)
1466
1467 #define R600_VM_L2_CNTL2 0x1404
1468 # define R600_VM_L2_CNTL2_INVALIDATE_ALL_L1_TLBS (1 << 0)
1469 # define R600_VM_L2_CNTL2_INVALIDATE_L2_CACHE (1 << 1)
1470 #define R600_VM_L2_CNTL3 0x1408
1471 # define R600_VM_L2_CNTL3_BANK_SELECT_0(x) ((x) << 0)
1472 # define R600_VM_L2_CNTL3_BANK_SELECT_1(x) ((x) << 5)
1473 # define R600_VM_L2_CNTL3_CACHE_UPDATE_MODE(x) ((x) << 10)
1474 # define R700_VM_L2_CNTL3_BANK_SELECT(x) ((x) << 0)
1475 # define R700_VM_L2_CNTL3_CACHE_UPDATE_MODE(x) ((x) << 6)
1476
1477 #define R600_VM_L2_STATUS 0x140c
1478
1479 #define R600_VM_CONTEXT0_CNTL 0x1410
1480 # define R600_VM_ENABLE_CONTEXT (1 << 0)
1481 # define R600_VM_PAGE_TABLE_DEPTH_FLAT (0 << 1)
1482
1483 #define R600_VM_CONTEXT0_CNTL2 0x1430
1484 #define R600_VM_CONTEXT0_REQUEST_RESPONSE 0x1470
1485 #define R600_VM_CONTEXT0_INVALIDATION_LOW_ADDR 0x1490
1486 #define R600_VM_CONTEXT0_INVALIDATION_HIGH_ADDR 0x14b0
1487 #define R600_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x1574
1488 #define R600_VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x1594
1489 #define R600_VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x15b4
1490
1491 #define R700_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153c
1492 #define R700_VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155c
1493 #define R700_VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157c
1494
1495 #define R600_HDP_HOST_PATH_CNTL 0x2c00
1496
1497 #define R600_GRBM_CNTL 0x8000
1498 # define R600_GRBM_READ_TIMEOUT(x) ((x) << 0)
1499
1500 #define R600_GRBM_STATUS 0x8010
1501 # define R600_CMDFIFO_AVAIL_MASK 0x1f
1502 # define R700_CMDFIFO_AVAIL_MASK 0xf
1503 # define R600_GUI_ACTIVE (1 << 31)
1504 #define R600_GRBM_STATUS2 0x8014
1505 #define R600_GRBM_SOFT_RESET 0x8020
1506 # define R600_SOFT_RESET_CP (1 << 0)
1507 #define R600_WAIT_UNTIL 0x8040
1508
1509 #define R600_CP_SEM_WAIT_TIMER 0x85bc
1510 #define R600_CP_ME_CNTL 0x86d8
1511 # define R600_CP_ME_HALT (1 << 28)
1512 #define R600_CP_QUEUE_THRESHOLDS 0x8760
1513 # define R600_ROQ_IB1_START(x) ((x) << 0)
1514 # define R600_ROQ_IB2_START(x) ((x) << 8)
1515 #define R600_CP_MEQ_THRESHOLDS 0x8764
1516 # define R700_STQ_SPLIT(x) ((x) << 0)
1517 # define R600_MEQ_END(x) ((x) << 16)
1518 # define R600_ROQ_END(x) ((x) << 24)
1519 #define R600_CP_PERFMON_CNTL 0x87fc
1520 #define R600_CP_RB_BASE 0xc100
1521 #define R600_CP_RB_CNTL 0xc104
1522 # define R600_RB_BUFSZ(x) ((x) << 0)
1523 # define R600_RB_BLKSZ(x) ((x) << 8)
1524 # define R600_BUF_SWAP_32BIT (2 << 16)
1525 # define R600_RB_NO_UPDATE (1 << 27)
1526 # define R600_RB_RPTR_WR_ENA (1 << 31)
1527 #define R600_CP_RB_RPTR_WR 0xc108
1528 #define R600_CP_RB_RPTR_ADDR 0xc10c
1529 #define R600_CP_RB_RPTR_ADDR_HI 0xc110
1530 #define R600_CP_RB_WPTR 0xc114
1531 #define R600_CP_RB_WPTR_ADDR 0xc118
1532 #define R600_CP_RB_WPTR_ADDR_HI 0xc11c
1533 #define R600_CP_RB_RPTR 0x8700
1534 #define R600_CP_RB_WPTR_DELAY 0x8704
1535 #define R600_CP_PFP_UCODE_ADDR 0xc150
1536 #define R600_CP_PFP_UCODE_DATA 0xc154
1537 #define R600_CP_ME_RAM_RADDR 0xc158
1538 #define R600_CP_ME_RAM_WADDR 0xc15c
1539 #define R600_CP_ME_RAM_DATA 0xc160
1540 #define R600_CP_DEBUG 0xc1fc
1541
1542 #define R600_PA_CL_ENHANCE 0x8a14
1543 # define R600_CLIP_VTX_REORDER_ENA (1 << 0)
1544 # define R600_NUM_CLIP_SEQ(x) ((x) << 1)
1545 #define R600_PA_SC_LINE_STIPPLE_STATE 0x8b10
1546 #define R600_PA_SC_MULTI_CHIP_CNTL 0x8b20
1547 #define R700_PA_SC_FORCE_EOV_MAX_CNTS 0x8b24
1548 # define R700_FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0)
1549 # define R700_FORCE_EOV_MAX_REZ_CNT(x) ((x) << 16)
1550 #define R600_PA_SC_AA_SAMPLE_LOCS_2S 0x8b40
1551 #define R600_PA_SC_AA_SAMPLE_LOCS_4S 0x8b44
1552 #define R600_PA_SC_AA_SAMPLE_LOCS_8S_WD0 0x8b48
1553 #define R600_PA_SC_AA_SAMPLE_LOCS_8S_WD1 0x8b4c
1554 # define R600_S0_X(x) ((x) << 0)
1555 # define R600_S0_Y(x) ((x) << 4)
1556 # define R600_S1_X(x) ((x) << 8)
1557 # define R600_S1_Y(x) ((x) << 12)
1558 # define R600_S2_X(x) ((x) << 16)
1559 # define R600_S2_Y(x) ((x) << 20)
1560 # define R600_S3_X(x) ((x) << 24)
1561 # define R600_S3_Y(x) ((x) << 28)
1562 # define R600_S4_X(x) ((x) << 0)
1563 # define R600_S4_Y(x) ((x) << 4)
1564 # define R600_S5_X(x) ((x) << 8)
1565 # define R600_S5_Y(x) ((x) << 12)
1566 # define R600_S6_X(x) ((x) << 16)
1567 # define R600_S6_Y(x) ((x) << 20)
1568 # define R600_S7_X(x) ((x) << 24)
1569 # define R600_S7_Y(x) ((x) << 28)
1570 #define R600_PA_SC_FIFO_SIZE 0x8bd0
1571 # define R600_SC_PRIM_FIFO_SIZE(x) ((x) << 0)
1572 # define R600_SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 8)
1573 # define R600_SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 16)
1574 #define R700_PA_SC_FIFO_SIZE_R7XX 0x8bcc
1575 # define R700_SC_PRIM_FIFO_SIZE(x) ((x) << 0)
1576 # define R700_SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 12)
1577 # define R700_SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 20)
1578 #define R600_PA_SC_ENHANCE 0x8bf0
1579 # define R600_FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0)
1580 # define R600_FORCE_EOV_MAX_TILE_CNT(x) ((x) << 12)
1581 #define R600_PA_SC_CLIPRECT_RULE 0x2820c
1582 #define R700_PA_SC_EDGERULE 0x28230
1583 #define R600_PA_SC_LINE_STIPPLE 0x28a0c
1584 #define R600_PA_SC_MODE_CNTL 0x28a4c
1585 #define R600_PA_SC_AA_CONFIG 0x28c04
1586
1587 #define R600_SX_EXPORT_BUFFER_SIZES 0x900c
1588 # define R600_COLOR_BUFFER_SIZE(x) ((x) << 0)
1589 # define R600_POSITION_BUFFER_SIZE(x) ((x) << 8)
1590 # define R600_SMX_BUFFER_SIZE(x) ((x) << 16)
1591 #define R600_SX_DEBUG_1 0x9054
1592 # define R600_SMX_EVENT_RELEASE (1 << 0)
1593 # define R600_ENABLE_NEW_SMX_ADDRESS (1 << 16)
1594 #define R700_SX_DEBUG_1 0x9058
1595 # define R700_ENABLE_NEW_SMX_ADDRESS (1 << 16)
1596 #define R600_SX_MISC 0x28350
1597
1598 #define R600_DB_DEBUG 0x9830
1599 # define R600_PREZ_MUST_WAIT_FOR_POSTZ_DONE (1 << 31)
1600 #define R600_DB_WATERMARKS 0x9838
1601 # define R600_DEPTH_FREE(x) ((x) << 0)
1602 # define R600_DEPTH_FLUSH(x) ((x) << 5)
1603 # define R600_DEPTH_PENDING_FREE(x) ((x) << 15)
1604 # define R600_DEPTH_CACHELINE_FREE(x) ((x) << 20)
1605 #define R700_DB_DEBUG3 0x98b0
1606 # define R700_DB_CLK_OFF_DELAY(x) ((x) << 11)
1607 #define RV700_DB_DEBUG4 0x9b8c
1608 # define RV700_DISABLE_TILE_COVERED_FOR_PS_ITER (1 << 6)
1609
1610 #define R600_VGT_CACHE_INVALIDATION 0x88c4
1611 # define R600_CACHE_INVALIDATION(x) ((x) << 0)
1612 # define R600_VC_ONLY 0
1613 # define R600_TC_ONLY 1
1614 # define R600_VC_AND_TC 2
1615 # define R700_AUTO_INVLD_EN(x) ((x) << 6)
1616 # define R700_NO_AUTO 0
1617 # define R700_ES_AUTO 1
1618 # define R700_GS_AUTO 2
1619 # define R700_ES_AND_GS_AUTO 3
1620 #define R600_VGT_GS_PER_ES 0x88c8
1621 #define R600_VGT_ES_PER_GS 0x88cc
1622 #define R600_VGT_GS_PER_VS 0x88e8
1623 #define R600_VGT_GS_VERTEX_REUSE 0x88d4
1624 #define R600_VGT_NUM_INSTANCES 0x8974
1625 #define R600_VGT_STRMOUT_EN 0x28ab0
1626 #define R600_VGT_EVENT_INITIATOR 0x28a90
1627 # define R600_CACHE_FLUSH_AND_INV_EVENT (0x16 << 0)
1628 #define R600_VGT_VERTEX_REUSE_BLOCK_CNTL 0x28c58
1629 # define R600_VTX_REUSE_DEPTH_MASK 0xff
1630 #define R600_VGT_OUT_DEALLOC_CNTL 0x28c5c
1631 # define R600_DEALLOC_DIST_MASK 0x7f
1632
1633 #define R600_CB_COLOR0_BASE 0x28040
1634 #define R600_CB_COLOR1_BASE 0x28044
1635 #define R600_CB_COLOR2_BASE 0x28048
1636 #define R600_CB_COLOR3_BASE 0x2804c
1637 #define R600_CB_COLOR4_BASE 0x28050
1638 #define R600_CB_COLOR5_BASE 0x28054
1639 #define R600_CB_COLOR6_BASE 0x28058
1640 #define R600_CB_COLOR7_BASE 0x2805c
1641 #define R600_CB_COLOR7_FRAG 0x280fc
1642
1643 #define R600_CB_COLOR0_SIZE 0x28060
1644 #define R600_CB_COLOR0_VIEW 0x28080
1645 #define R600_CB_COLOR0_INFO 0x280a0
1646 #define R600_CB_COLOR0_TILE 0x280c0
1647 #define R600_CB_COLOR0_FRAG 0x280e0
1648 #define R600_CB_COLOR0_MASK 0x28100
1649
1650 #define AVIVO_D1MODE_VLINE_START_END 0x6538
1651 #define AVIVO_D2MODE_VLINE_START_END 0x6d38
1652 #define R600_CP_COHER_BASE 0x85f8
1653 #define R600_DB_DEPTH_BASE 0x2800c
1654 #define R600_SQ_PGM_START_FS 0x28894
1655 #define R600_SQ_PGM_START_ES 0x28880
1656 #define R600_SQ_PGM_START_VS 0x28858
1657 #define R600_SQ_PGM_RESOURCES_VS 0x28868
1658 #define R600_SQ_PGM_CF_OFFSET_VS 0x288d0
1659 #define R600_SQ_PGM_START_GS 0x2886c
1660 #define R600_SQ_PGM_START_PS 0x28840
1661 #define R600_SQ_PGM_RESOURCES_PS 0x28850
1662 #define R600_SQ_PGM_EXPORTS_PS 0x28854
1663 #define R600_SQ_PGM_CF_OFFSET_PS 0x288cc
1664 #define R600_VGT_DMA_BASE 0x287e8
1665 #define R600_VGT_DMA_BASE_HI 0x287e4
1666 #define R600_VGT_STRMOUT_BASE_OFFSET_0 0x28b10
1667 #define R600_VGT_STRMOUT_BASE_OFFSET_1 0x28b14
1668 #define R600_VGT_STRMOUT_BASE_OFFSET_2 0x28b18
1669 #define R600_VGT_STRMOUT_BASE_OFFSET_3 0x28b1c
1670 #define R600_VGT_STRMOUT_BASE_OFFSET_HI_0 0x28b44
1671 #define R600_VGT_STRMOUT_BASE_OFFSET_HI_1 0x28b48
1672 #define R600_VGT_STRMOUT_BASE_OFFSET_HI_2 0x28b4c
1673 #define R600_VGT_STRMOUT_BASE_OFFSET_HI_3 0x28b50
1674 #define R600_VGT_STRMOUT_BUFFER_BASE_0 0x28ad8
1675 #define R600_VGT_STRMOUT_BUFFER_BASE_1 0x28ae8
1676 #define R600_VGT_STRMOUT_BUFFER_BASE_2 0x28af8
1677 #define R600_VGT_STRMOUT_BUFFER_BASE_3 0x28b08
1678 #define R600_VGT_STRMOUT_BUFFER_OFFSET_0 0x28adc
1679 #define R600_VGT_STRMOUT_BUFFER_OFFSET_1 0x28aec
1680 #define R600_VGT_STRMOUT_BUFFER_OFFSET_2 0x28afc
1681 #define R600_VGT_STRMOUT_BUFFER_OFFSET_3 0x28b0c
1682
1683 #define R600_VGT_PRIMITIVE_TYPE 0x8958
1684
1685 #define R600_PA_SC_SCREEN_SCISSOR_TL 0x28030
1686 #define R600_PA_SC_GENERIC_SCISSOR_TL 0x28240
1687 #define R600_PA_SC_WINDOW_SCISSOR_TL 0x28204
1688
1689 #define R600_TC_CNTL 0x9608
1690 # define R600_TC_L2_SIZE(x) ((x) << 5)
1691 # define R600_L2_DISABLE_LATE_HIT (1 << 9)
1692
1693 #define R600_ARB_POP 0x2418
1694 # define R600_ENABLE_TC128 (1 << 30)
1695 #define R600_ARB_GDEC_RD_CNTL 0x246c
1696
1697 #define R600_TA_CNTL_AUX 0x9508
1698 # define R600_DISABLE_CUBE_WRAP (1 << 0)
1699 # define R600_DISABLE_CUBE_ANISO (1 << 1)
1700 # define R700_GETLOD_SELECT(x) ((x) << 2)
1701 # define R600_SYNC_GRADIENT (1 << 24)
1702 # define R600_SYNC_WALKER (1 << 25)
1703 # define R600_SYNC_ALIGNER (1 << 26)
1704 # define R600_BILINEAR_PRECISION_6_BIT (0 << 31)
1705 # define R600_BILINEAR_PRECISION_8_BIT (1 << 31)
1706
1707 #define R700_TCP_CNTL 0x9610
1708
1709 #define R600_SMX_DC_CTL0 0xa020
1710 # define R700_USE_HASH_FUNCTION (1 << 0)
1711 # define R700_CACHE_DEPTH(x) ((x) << 1)
1712 # define R700_FLUSH_ALL_ON_EVENT (1 << 10)
1713 # define R700_STALL_ON_EVENT (1 << 11)
1714 #define R700_SMX_EVENT_CTL 0xa02c
1715 # define R700_ES_FLUSH_CTL(x) ((x) << 0)
1716 # define R700_GS_FLUSH_CTL(x) ((x) << 3)
1717 # define R700_ACK_FLUSH_CTL(x) ((x) << 6)
1718 # define R700_SYNC_FLUSH_CTL (1 << 8)
1719
1720 #define R600_SQ_CONFIG 0x8c00
1721 # define R600_VC_ENABLE (1 << 0)
1722 # define R600_EXPORT_SRC_C (1 << 1)
1723 # define R600_DX9_CONSTS (1 << 2)
1724 # define R600_ALU_INST_PREFER_VECTOR (1 << 3)
1725 # define R600_DX10_CLAMP (1 << 4)
1726 # define R600_CLAUSE_SEQ_PRIO(x) ((x) << 8)
1727 # define R600_PS_PRIO(x) ((x) << 24)
1728 # define R600_VS_PRIO(x) ((x) << 26)
1729 # define R600_GS_PRIO(x) ((x) << 28)
1730 # define R600_ES_PRIO(x) ((x) << 30)
1731 #define R600_SQ_GPR_RESOURCE_MGMT_1 0x8c04
1732 # define R600_NUM_PS_GPRS(x) ((x) << 0)
1733 # define R600_NUM_VS_GPRS(x) ((x) << 16)
1734 # define R700_DYN_GPR_ENABLE (1 << 27)
1735 # define R600_NUM_CLAUSE_TEMP_GPRS(x) ((x) << 28)
1736 #define R600_SQ_GPR_RESOURCE_MGMT_2 0x8c08
1737 # define R600_NUM_GS_GPRS(x) ((x) << 0)
1738 # define R600_NUM_ES_GPRS(x) ((x) << 16)
1739 #define R600_SQ_THREAD_RESOURCE_MGMT 0x8c0c
1740 # define R600_NUM_PS_THREADS(x) ((x) << 0)
1741 # define R600_NUM_VS_THREADS(x) ((x) << 8)
1742 # define R600_NUM_GS_THREADS(x) ((x) << 16)
1743 # define R600_NUM_ES_THREADS(x) ((x) << 24)
1744 #define R600_SQ_STACK_RESOURCE_MGMT_1 0x8c10
1745 # define R600_NUM_PS_STACK_ENTRIES(x) ((x) << 0)
1746 # define R600_NUM_VS_STACK_ENTRIES(x) ((x) << 16)
1747 #define R600_SQ_STACK_RESOURCE_MGMT_2 0x8c14
1748 # define R600_NUM_GS_STACK_ENTRIES(x) ((x) << 0)
1749 # define R600_NUM_ES_STACK_ENTRIES(x) ((x) << 16)
1750 #define R600_SQ_MS_FIFO_SIZES 0x8cf0
1751 # define R600_CACHE_FIFO_SIZE(x) ((x) << 0)
1752 # define R600_FETCH_FIFO_HIWATER(x) ((x) << 8)
1753 # define R600_DONE_FIFO_HIWATER(x) ((x) << 16)
1754 # define R600_ALU_UPDATE_FIFO_HIWATER(x) ((x) << 24)
1755 #define R700_SQ_DYN_GPR_SIZE_SIMD_AB_0 0x8db0
1756 # define R700_SIMDA_RING0(x) ((x) << 0)
1757 # define R700_SIMDA_RING1(x) ((x) << 8)
1758 # define R700_SIMDB_RING0(x) ((x) << 16)
1759 # define R700_SIMDB_RING1(x) ((x) << 24)
1760 #define R700_SQ_DYN_GPR_SIZE_SIMD_AB_1 0x8db4
1761 #define R700_SQ_DYN_GPR_SIZE_SIMD_AB_2 0x8db8
1762 #define R700_SQ_DYN_GPR_SIZE_SIMD_AB_3 0x8dbc
1763 #define R700_SQ_DYN_GPR_SIZE_SIMD_AB_4 0x8dc0
1764 #define R700_SQ_DYN_GPR_SIZE_SIMD_AB_5 0x8dc4
1765 #define R700_SQ_DYN_GPR_SIZE_SIMD_AB_6 0x8dc8
1766 #define R700_SQ_DYN_GPR_SIZE_SIMD_AB_7 0x8dcc
1767
1768 #define R600_SPI_PS_IN_CONTROL_0 0x286cc
1769 # define R600_NUM_INTERP(x) ((x) << 0)
1770 # define R600_POSITION_ENA (1 << 8)
1771 # define R600_POSITION_CENTROID (1 << 9)
1772 # define R600_POSITION_ADDR(x) ((x) << 10)
1773 # define R600_PARAM_GEN(x) ((x) << 15)
1774 # define R600_PARAM_GEN_ADDR(x) ((x) << 19)
1775 # define R600_BARYC_SAMPLE_CNTL(x) ((x) << 26)
1776 # define R600_PERSP_GRADIENT_ENA (1 << 28)
1777 # define R600_LINEAR_GRADIENT_ENA (1 << 29)
1778 # define R600_POSITION_SAMPLE (1 << 30)
1779 # define R600_BARYC_AT_SAMPLE_ENA (1 << 31)
1780 #define R600_SPI_PS_IN_CONTROL_1 0x286d0
1781 # define R600_GEN_INDEX_PIX (1 << 0)
1782 # define R600_GEN_INDEX_PIX_ADDR(x) ((x) << 1)
1783 # define R600_FRONT_FACE_ENA (1 << 8)
1784 # define R600_FRONT_FACE_CHAN(x) ((x) << 9)
1785 # define R600_FRONT_FACE_ALL_BITS (1 << 11)
1786 # define R600_FRONT_FACE_ADDR(x) ((x) << 12)
1787 # define R600_FOG_ADDR(x) ((x) << 17)
1788 # define R600_FIXED_PT_POSITION_ENA (1 << 24)
1789 # define R600_FIXED_PT_POSITION_ADDR(x) ((x) << 25)
1790 # define R700_POSITION_ULC (1 << 30)
1791 #define R600_SPI_INPUT_Z 0x286d8
1792
1793 #define R600_SPI_CONFIG_CNTL 0x9100
1794 # define R600_GPR_WRITE_PRIORITY(x) ((x) << 0)
1795 # define R600_DISABLE_INTERP_1 (1 << 5)
1796 #define R600_SPI_CONFIG_CNTL_1 0x913c
1797 # define R600_VTX_DONE_DELAY(x) ((x) << 0)
1798 # define R600_INTERP_ONE_PRIM_PER_ROW (1 << 4)
1799
1800 #define R600_GB_TILING_CONFIG 0x98f0
1801 # define R600_PIPE_TILING(x) ((x) << 1)
1802 # define R600_BANK_TILING(x) ((x) << 4)
1803 # define R600_GROUP_SIZE(x) ((x) << 6)
1804 # define R600_ROW_TILING(x) ((x) << 8)
1805 # define R600_BANK_SWAPS(x) ((x) << 11)
1806 # define R600_SAMPLE_SPLIT(x) ((x) << 14)
1807 # define R600_BACKEND_MAP(x) ((x) << 16)
1808 #define R600_DCP_TILING_CONFIG 0x6ca0
1809 #define R600_HDP_TILING_CONFIG 0x2f3c
1810
1811 #define R600_CC_RB_BACKEND_DISABLE 0x98f4
1812 #define R700_CC_SYS_RB_BACKEND_DISABLE 0x3f88
1813 # define R600_BACKEND_DISABLE(x) ((x) << 16)
1814
1815 #define R600_CC_GC_SHADER_PIPE_CONFIG 0x8950
1816 #define R600_GC_USER_SHADER_PIPE_CONFIG 0x8954
1817 # define R600_INACTIVE_QD_PIPES(x) ((x) << 8)
1818 # define R600_INACTIVE_QD_PIPES_MASK (0xff << 8)
1819 # define R600_INACTIVE_SIMDS(x) ((x) << 16)
1820 # define R600_INACTIVE_SIMDS_MASK (0xff << 16)
1821
1822 #define R700_CGTS_SYS_TCC_DISABLE 0x3f90
1823 #define R700_CGTS_USER_SYS_TCC_DISABLE 0x3f94
1824 #define R700_CGTS_TCC_DISABLE 0x9148
1825 #define R700_CGTS_USER_TCC_DISABLE 0x914c
1826
1827 /* Constants */
1828 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
1829
1830 #define RADEON_LAST_FRAME_REG RADEON_SCRATCH_REG0
1831 #define RADEON_LAST_DISPATCH_REG RADEON_SCRATCH_REG1
1832 #define RADEON_LAST_CLEAR_REG RADEON_SCRATCH_REG2
1833 #define RADEON_LAST_SWI_REG RADEON_SCRATCH_REG3
1834 #define RADEON_LAST_DISPATCH 1
1835
1836 #define R600_LAST_FRAME_REG R600_SCRATCH_REG0
1837 #define R600_LAST_DISPATCH_REG R600_SCRATCH_REG1
1838 #define R600_LAST_CLEAR_REG R600_SCRATCH_REG2
1839 #define R600_LAST_SWI_REG R600_SCRATCH_REG3
1840
1841 #define RADEON_MAX_VB_AGE 0x7fffffff
1842 #define RADEON_MAX_VB_VERTS (0xffff)
1843
1844 #define RADEON_RING_HIGH_MARK 128
1845
1846 #define RADEON_PCIGART_TABLE_SIZE (32*1024)
1847
1848 #define RADEON_READ(reg) DRM_READ32( dev_priv->mmio, (reg) )
1849 #define RADEON_WRITE(reg, val) \
1850 do { \
1851 if (reg < 0x10000) { \
1852 DRM_WRITE32(dev_priv->mmio, (reg), (val)); \
1853 } else { \
1854 DRM_WRITE32(dev_priv->mmio, RADEON_MM_INDEX, (reg)); \
1855 DRM_WRITE32(dev_priv->mmio, RADEON_MM_DATA, (val)); \
1856 } \
1857 } while (0)
1858 #define RADEON_READ8(reg) DRM_READ8( dev_priv->mmio, (reg) )
1859 #define RADEON_WRITE8(reg,val) DRM_WRITE8( dev_priv->mmio, (reg), (val) )
1860
1861 #define RADEON_WRITE_PLL(addr, val) \
1862 do { \
1863 RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, \
1864 ((addr) & 0x1f) | RADEON_PLL_WR_EN ); \
1865 RADEON_WRITE(RADEON_CLOCK_CNTL_DATA, (val)); \
1866 } while (0)
1867
1868 #define RADEON_WRITE_PCIE(addr, val) \
1869 do { \
1870 RADEON_WRITE8(RADEON_PCIE_INDEX, \
1871 ((addr) & 0xff)); \
1872 RADEON_WRITE(RADEON_PCIE_DATA, (val)); \
1873 } while (0)
1874
1875 #define R500_WRITE_MCIND(addr, val) \
1876 do { \
1877 RADEON_WRITE(R520_MC_IND_INDEX, 0xff0000 | ((addr) & 0xff)); \
1878 RADEON_WRITE(R520_MC_IND_DATA, (val)); \
1879 RADEON_WRITE(R520_MC_IND_INDEX, 0); \
1880 } while (0)
1881
1882 #define RS480_WRITE_MCIND(addr, val) \
1883 do { \
1884 RADEON_WRITE(RS480_NB_MC_INDEX, \
1885 ((addr) & 0xff) | RS480_NB_MC_IND_WR_EN); \
1886 RADEON_WRITE(RS480_NB_MC_DATA, (val)); \
1887 RADEON_WRITE(RS480_NB_MC_INDEX, 0xff); \
1888 } while (0)
1889
1890 #define RS690_WRITE_MCIND(addr, val) \
1891 do { \
1892 RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_WR_EN | ((addr) & RS690_MC_INDEX_MASK)); \
1893 RADEON_WRITE(RS690_MC_DATA, val); \
1894 RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_WR_ACK); \
1895 } while (0)
1896
1897 #define RS600_WRITE_MCIND(addr, val) \
1898 do { \
1899 RADEON_WRITE(RS600_MC_INDEX, RS600_MC_IND_WR_EN | RS600_MC_IND_CITF_ARB0 | ((addr) & RS600_MC_ADDR_MASK)); \
1900 RADEON_WRITE(RS600_MC_DATA, val); \
1901 } while (0)
1902
1903 #define IGP_WRITE_MCIND(addr, val) \
1904 do { \
1905 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) || \
1906 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) \
1907 RS690_WRITE_MCIND(addr, val); \
1908 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) \
1909 RS600_WRITE_MCIND(addr, val); \
1910 else \
1911 RS480_WRITE_MCIND(addr, val); \
1912 } while (0)
1913
1914 #define CP_PACKET0( reg, n ) \
1915 (RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2))
1916 #define CP_PACKET0_TABLE( reg, n ) \
1917 (RADEON_CP_PACKET0 | RADEON_ONE_REG_WR | ((n) << 16) | ((reg) >> 2))
1918 #define CP_PACKET1( reg0, reg1 ) \
1919 (RADEON_CP_PACKET1 | (((reg1) >> 2) << 15) | ((reg0) >> 2))
1920 #define CP_PACKET2() \
1921 (RADEON_CP_PACKET2)
1922 #define CP_PACKET3( pkt, n ) \
1923 (RADEON_CP_PACKET3 | (pkt) | ((n) << 16))
1924
1925 /* ================================================================
1926 * Engine control helper macros
1927 */
1928
1929 #define RADEON_WAIT_UNTIL_2D_IDLE() do { \
1930 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1931 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \
1932 RADEON_WAIT_HOST_IDLECLEAN) ); \
1933 } while (0)
1934
1935 #define RADEON_WAIT_UNTIL_3D_IDLE() do { \
1936 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1937 OUT_RING( (RADEON_WAIT_3D_IDLECLEAN | \
1938 RADEON_WAIT_HOST_IDLECLEAN) ); \
1939 } while (0)
1940
1941 #define RADEON_WAIT_UNTIL_IDLE() do { \
1942 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1943 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \
1944 RADEON_WAIT_3D_IDLECLEAN | \
1945 RADEON_WAIT_HOST_IDLECLEAN) ); \
1946 } while (0)
1947
1948 #define RADEON_WAIT_UNTIL_PAGE_FLIPPED() do { \
1949 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1950 OUT_RING( RADEON_WAIT_CRTC_PFLIP ); \
1951 } while (0)
1952
1953 #define RADEON_FLUSH_CACHE() do { \
1954 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \
1955 OUT_RING(CP_PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); \
1956 OUT_RING(RADEON_RB3D_DC_FLUSH); \
1957 } else { \
1958 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); \
1959 OUT_RING(R300_RB3D_DC_FLUSH); \
1960 } \
1961 } while (0)
1962
1963 #define RADEON_PURGE_CACHE() do { \
1964 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \
1965 OUT_RING(CP_PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); \
1966 OUT_RING(RADEON_RB3D_DC_FLUSH | RADEON_RB3D_DC_FREE); \
1967 } else { \
1968 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); \
1969 OUT_RING(R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE); \
1970 } \
1971 } while (0)
1972
1973 #define RADEON_FLUSH_ZCACHE() do { \
1974 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \
1975 OUT_RING(CP_PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); \
1976 OUT_RING(RADEON_RB3D_ZC_FLUSH); \
1977 } else { \
1978 OUT_RING(CP_PACKET0(R300_ZB_ZCACHE_CTLSTAT, 0)); \
1979 OUT_RING(R300_ZC_FLUSH); \
1980 } \
1981 } while (0)
1982
1983 #define RADEON_PURGE_ZCACHE() do { \
1984 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \
1985 OUT_RING(CP_PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); \
1986 OUT_RING(RADEON_RB3D_ZC_FLUSH | RADEON_RB3D_ZC_FREE); \
1987 } else { \
1988 OUT_RING(CP_PACKET0(R300_ZB_ZCACHE_CTLSTAT, 0)); \
1989 OUT_RING(R300_ZC_FLUSH | R300_ZC_FREE); \
1990 } \
1991 } while (0)
1992
1993 /* ================================================================
1994 * Misc helper macros
1995 */
1996
1997 /* Perfbox functionality only.
1998 */
1999 #define RING_SPACE_TEST_WITH_RETURN( dev_priv ) \
2000 do { \
2001 if (!(dev_priv->stats.boxes & RADEON_BOX_DMA_IDLE)) { \
2002 u32 head = GET_RING_HEAD( dev_priv ); \
2003 if (head == dev_priv->ring.tail) \
2004 dev_priv->stats.boxes |= RADEON_BOX_DMA_IDLE; \
2005 } \
2006 } while (0)
2007
2008 #define VB_AGE_TEST_WITH_RETURN( dev_priv ) \
2009 do { \
2010 struct drm_radeon_master_private *master_priv = file_priv->master->driver_priv; \
2011 drm_radeon_sarea_t *sarea_priv = master_priv->sarea_priv; \
2012 if ( sarea_priv->last_dispatch >= RADEON_MAX_VB_AGE ) { \
2013 int __ret; \
2014 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) \
2015 __ret = r600_do_cp_idle(dev_priv); \
2016 else \
2017 __ret = radeon_do_cp_idle(dev_priv); \
2018 if ( __ret ) return __ret; \
2019 sarea_priv->last_dispatch = 0; \
2020 radeon_freelist_reset( dev ); \
2021 } \
2022 } while (0)
2023
2024 #define RADEON_DISPATCH_AGE( age ) do { \
2025 OUT_RING( CP_PACKET0( RADEON_LAST_DISPATCH_REG, 0 ) ); \
2026 OUT_RING( age ); \
2027 } while (0)
2028
2029 #define RADEON_FRAME_AGE( age ) do { \
2030 OUT_RING( CP_PACKET0( RADEON_LAST_FRAME_REG, 0 ) ); \
2031 OUT_RING( age ); \
2032 } while (0)
2033
2034 #define RADEON_CLEAR_AGE( age ) do { \
2035 OUT_RING( CP_PACKET0( RADEON_LAST_CLEAR_REG, 0 ) ); \
2036 OUT_RING( age ); \
2037 } while (0)
2038
2039 #define R600_DISPATCH_AGE(age) do { \
2040 OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); \
2041 OUT_RING((R600_LAST_DISPATCH_REG - R600_SET_CONFIG_REG_OFFSET) >> 2); \
2042 OUT_RING(age); \
2043 } while (0)
2044
2045 #define R600_FRAME_AGE(age) do { \
2046 OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); \
2047 OUT_RING((R600_LAST_FRAME_REG - R600_SET_CONFIG_REG_OFFSET) >> 2); \
2048 OUT_RING(age); \
2049 } while (0)
2050
2051 #define R600_CLEAR_AGE(age) do { \
2052 OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); \
2053 OUT_RING((R600_LAST_CLEAR_REG - R600_SET_CONFIG_REG_OFFSET) >> 2); \
2054 OUT_RING(age); \
2055 } while (0)
2056
2057 /* ================================================================
2058 * Ring control
2059 */
2060
2061 #define RADEON_VERBOSE 0
2062
2063 #define RING_LOCALS int write, _nr, _align_nr; unsigned int mask; u32 *ring;
2064
2065 #define RADEON_RING_ALIGN 16
2066
2067 #define BEGIN_RING( n ) do { \
2068 if ( RADEON_VERBOSE ) { \
2069 DRM_INFO( "BEGIN_RING( %d )\n", (n)); \
2070 } \
2071 _align_nr = RADEON_RING_ALIGN - ((dev_priv->ring.tail + n) & (RADEON_RING_ALIGN-1)); \
2072 _align_nr += n; \
2073 if (dev_priv->ring.space <= (_align_nr * sizeof(u32))) { \
2074 COMMIT_RING(); \
2075 radeon_wait_ring( dev_priv, _align_nr * sizeof(u32)); \
2076 } \
2077 _nr = n; dev_priv->ring.space -= (n) * sizeof(u32); \
2078 ring = dev_priv->ring.start; \
2079 write = dev_priv->ring.tail; \
2080 mask = dev_priv->ring.tail_mask; \
2081 } while (0)
2082
2083 #define ADVANCE_RING() do { \
2084 if ( RADEON_VERBOSE ) { \
2085 DRM_INFO( "ADVANCE_RING() wr=0x%06x tail=0x%06x\n", \
2086 write, dev_priv->ring.tail ); \
2087 } \
2088 if (((dev_priv->ring.tail + _nr) & mask) != write) { \
2089 DRM_ERROR( \
2090 "ADVANCE_RING(): mismatch: nr: %x write: %x line: %d\n", \
2091 ((dev_priv->ring.tail + _nr) & mask), \
2092 write, __LINE__); \
2093 } else \
2094 dev_priv->ring.tail = write; \
2095 } while (0)
2096
2097 extern void radeon_commit_ring(drm_radeon_private_t *dev_priv);
2098
2099 #define COMMIT_RING() do { \
2100 radeon_commit_ring(dev_priv); \
2101 } while(0)
2102
2103 #define OUT_RING( x ) do { \
2104 if ( RADEON_VERBOSE ) { \
2105 DRM_INFO( " OUT_RING( 0x%08x ) at 0x%x\n", \
2106 (unsigned int)(x), write ); \
2107 } \
2108 ring[write++] = (x); \
2109 write &= mask; \
2110 } while (0)
2111
2112 #define OUT_RING_REG( reg, val ) do { \
2113 OUT_RING( CP_PACKET0( reg, 0 ) ); \
2114 OUT_RING( val ); \
2115 } while (0)
2116
2117 #define OUT_RING_TABLE( tab, sz ) do { \
2118 int _size = (sz); \
2119 int *_tab = (int *)(tab); \
2120 \
2121 if (write + _size > mask) { \
2122 int _i = (mask+1) - write; \
2123 _size -= _i; \
2124 while (_i > 0 ) { \
2125 *(int *)(ring + write) = *_tab++; \
2126 write++; \
2127 _i--; \
2128 } \
2129 write = 0; \
2130 _tab += _i; \
2131 } \
2132 while (_size > 0) { \
2133 *(ring + write) = *_tab++; \
2134 write++; \
2135 _size--; \
2136 } \
2137 write &= mask; \
2138 } while (0)
2139
2140 /**
2141 * Copy given number of dwords from drm buffer to the ring buffer.
2142 */
2143 #define OUT_RING_DRM_BUFFER(buf, sz) do { \
2144 int _size = (sz) * 4; \
2145 struct drm_buffer *_buf = (buf); \
2146 int _part_size; \
2147 while (_size > 0) { \
2148 _part_size = _size; \
2149 \
2150 if (write + _part_size/4 > mask) \
2151 _part_size = ((mask + 1) - write)*4; \
2152 \
2153 if (drm_buffer_index(_buf) + _part_size > PAGE_SIZE) \
2154 _part_size = PAGE_SIZE - drm_buffer_index(_buf);\
2155 \
2156 \
2157 \
2158 memcpy(ring + write, &_buf->data[drm_buffer_page(_buf)] \
2159 [drm_buffer_index(_buf)], _part_size); \
2160 \
2161 _size -= _part_size; \
2162 write = (write + _part_size/4) & mask; \
2163 drm_buffer_advance(_buf, _part_size); \
2164 } \
2165 } while (0)
2166
2167
2168 #endif /* CONFIG_DRM_RADEON_UMS */
2169
2170 #endif /* __RADEON_DRV_H__ */
Linux kernel - Deliverables
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