drivers/gpu/drm/radeon/radeon_encoders.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include "drmP.h"
  27 #include "drm_crtc_helper.h"
  28 #include "radeon_drm.h"
  29 #include "radeon.h"
  30 #include "atom.h"
  31
  32 extern int atom_debug;
  33
  34 /* evil but including atombios.h is much worse */
  35 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
  36                                 struct drm_display_mode *mode);
  37
  38 static uint32_t radeon_encoder_clones(struct drm_encoder *encoder)
  39 {
  40         struct drm_device *dev = encoder->dev;
  41         struct radeon_device *rdev = dev->dev_private;
  42         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  43         struct drm_encoder *clone_encoder;
  44         uint32_t index_mask = 0;
  45         int count;
  46
  47         /* DIG routing gets problematic */
  48         if (rdev->family >= CHIP_R600)
  49                 return index_mask;
  50         /* LVDS/TV are too wacky */
  51         if (radeon_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
  52                 return index_mask;
  53         /* DVO requires 2x ppll clocks depending on tmds chip */
  54         if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT)
  55                 return index_mask;
  56
  57         count = -1;
  58         list_for_each_entry(clone_encoder, &dev->mode_config.encoder_list, head) {
  59                 struct radeon_encoder *radeon_clone = to_radeon_encoder(clone_encoder);
  60                 count++;
  61
  62                 if (clone_encoder == encoder)
  63                         continue;
  64                 if (radeon_clone->devices & (ATOM_DEVICE_LCD_SUPPORT))
  65                         continue;
  66                 if (radeon_clone->devices & ATOM_DEVICE_DFP2_SUPPORT)
  67                         continue;
  68                 else
  69                         index_mask |= (1 << count);
  70         }
  71         return index_mask;
  72 }
  73
  74 void radeon_setup_encoder_clones(struct drm_device *dev)
  75 {
  76         struct drm_encoder *encoder;
  77
  78         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
  79                 encoder->possible_clones = radeon_encoder_clones(encoder);
  80         }
  81 }
  82
  83 uint32_t
  84 radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device, uint8_t dac)
  85 {
  86         struct radeon_device *rdev = dev->dev_private;
  87         uint32_t ret = 0;
  88
  89         switch (supported_device) {
  90         case ATOM_DEVICE_CRT1_SUPPORT:
  91         case ATOM_DEVICE_TV1_SUPPORT:
  92         case ATOM_DEVICE_TV2_SUPPORT:
  93         case ATOM_DEVICE_CRT2_SUPPORT:
  94         case ATOM_DEVICE_CV_SUPPORT:
  95                 switch (dac) {
  96                 case 1: /* dac a */
  97                         if ((rdev->family == CHIP_RS300) ||
  98                             (rdev->family == CHIP_RS400) ||
  99                             (rdev->family == CHIP_RS480))
 100                                 ret = ENCODER_OBJECT_ID_INTERNAL_DAC2;
 101                         else if (ASIC_IS_AVIVO(rdev))
 102                                 ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1;
 103                         else
 104                                 ret = ENCODER_OBJECT_ID_INTERNAL_DAC1;
 105                         break;
 106                 case 2: /* dac b */
 107                         if (ASIC_IS_AVIVO(rdev))
 108                                 ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2;
 109                         else {
 110                                 /*if (rdev->family == CHIP_R200)
 111                                   ret = ENCODER_OBJECT_ID_INTERNAL_DVO1;
 112                                   else*/
 113                                 ret = ENCODER_OBJECT_ID_INTERNAL_DAC2;
 114                         }
 115                         break;
 116                 case 3: /* external dac */
 117                         if (ASIC_IS_AVIVO(rdev))
 118                                 ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1;
 119                         else
 120                                 ret = ENCODER_OBJECT_ID_INTERNAL_DVO1;
 121                         break;
 122                 }
 123                 break;
 124         case ATOM_DEVICE_LCD1_SUPPORT:
 125                 if (ASIC_IS_AVIVO(rdev))
 126                         ret = ENCODER_OBJECT_ID_INTERNAL_LVTM1;
 127                 else
 128                         ret = ENCODER_OBJECT_ID_INTERNAL_LVDS;
 129                 break;
 130         case ATOM_DEVICE_DFP1_SUPPORT:
 131                 if ((rdev->family == CHIP_RS300) ||
 132                     (rdev->family == CHIP_RS400) ||
 133                     (rdev->family == CHIP_RS480))
 134                         ret = ENCODER_OBJECT_ID_INTERNAL_DVO1;
 135                 else if (ASIC_IS_AVIVO(rdev))
 136                         ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1;
 137                 else
 138                         ret = ENCODER_OBJECT_ID_INTERNAL_TMDS1;
 139                 break;
 140         case ATOM_DEVICE_LCD2_SUPPORT:
 141         case ATOM_DEVICE_DFP2_SUPPORT:
 142                 if ((rdev->family == CHIP_RS600) ||
 143                     (rdev->family == CHIP_RS690) ||
 144                     (rdev->family == CHIP_RS740))
 145                         ret = ENCODER_OBJECT_ID_INTERNAL_DDI;
 146                 else if (ASIC_IS_AVIVO(rdev))
 147                         ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1;
 148                 else
 149                         ret = ENCODER_OBJECT_ID_INTERNAL_DVO1;
 150                 break;
 151         case ATOM_DEVICE_DFP3_SUPPORT:
 152                 ret = ENCODER_OBJECT_ID_INTERNAL_LVTM1;
 153                 break;
 154         }
 155
 156         return ret;
 157 }
 158
 159 static inline bool radeon_encoder_is_digital(struct drm_encoder *encoder)
 160 {
 161         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 162         switch (radeon_encoder->encoder_id) {
 163         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
 164         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
 165         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
 166         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
 167         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
 168         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
 169         case ENCODER_OBJECT_ID_INTERNAL_DDI:
 170         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 171         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
 172         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
 173         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
 174                 return true;
 175         default:
 176                 return false;
 177         }
 178 }
 179 void
 180 radeon_link_encoder_connector(struct drm_device *dev)
 181 {
 182         struct drm_connector *connector;
 183         struct radeon_connector *radeon_connector;
 184         struct drm_encoder *encoder;
 185         struct radeon_encoder *radeon_encoder;
 186
 187         /* walk the list and link encoders to connectors */
 188         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 189                 radeon_connector = to_radeon_connector(connector);
 190                 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 191                         radeon_encoder = to_radeon_encoder(encoder);
 192                         if (radeon_encoder->devices & radeon_connector->devices)
 193                                 drm_mode_connector_attach_encoder(connector, encoder);
 194                 }
 195         }
 196 }
 197
 198 void radeon_encoder_set_active_device(struct drm_encoder *encoder)
 199 {
 200         struct drm_device *dev = encoder->dev;
 201         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 202         struct drm_connector *connector;
 203
 204         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 205                 if (connector->encoder == encoder) {
 206                         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 207                         radeon_encoder->active_device = radeon_encoder->devices & radeon_connector->devices;
 208                         DRM_DEBUG("setting active device to %08x from %08x %08x for encoder %d\n",
 209                                   radeon_encoder->active_device, radeon_encoder->devices,
 210                                   radeon_connector->devices, encoder->encoder_type);
 211                 }
 212         }
 213 }
 214
 215 static struct drm_connector *
 216 radeon_get_connector_for_encoder(struct drm_encoder *encoder)
 217 {
 218         struct drm_device *dev = encoder->dev;
 219         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 220         struct drm_connector *connector;
 221         struct radeon_connector *radeon_connector;
 222
 223         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 224                 radeon_connector = to_radeon_connector(connector);
 225                 if (radeon_encoder->active_device & radeon_connector->devices)
 226                         return connector;
 227         }
 228         return NULL;
 229 }
 230
 231 static struct radeon_connector_atom_dig *
 232 radeon_get_atom_connector_priv_from_encoder(struct drm_encoder *encoder)
 233 {
 234         struct drm_device *dev = encoder->dev;
 235         struct radeon_device *rdev = dev->dev_private;
 236         struct drm_connector *connector;
 237         struct radeon_connector *radeon_connector;
 238         struct radeon_connector_atom_dig *dig_connector;
 239
 240         if (!rdev->is_atom_bios)
 241                 return NULL;
 242
 243         connector = radeon_get_connector_for_encoder(encoder);
 244         if (!connector)
 245                 return NULL;
 246
 247         radeon_connector = to_radeon_connector(connector);
 248
 249         if (!radeon_connector->con_priv)
 250                 return NULL;
 251
 252         dig_connector = radeon_connector->con_priv;
 253
 254         return dig_connector;
 255 }
 256
 257 static bool radeon_atom_mode_fixup(struct drm_encoder *encoder,
 258                                    struct drm_display_mode *mode,
 259                                    struct drm_display_mode *adjusted_mode)
 260 {
 261         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 262         struct drm_device *dev = encoder->dev;
 263         struct radeon_device *rdev = dev->dev_private;
 264
 265         /* adjust pm to upcoming mode change */
 266         radeon_pm_compute_clocks(rdev);
 267
 268         /* set the active encoder to connector routing */
 269         radeon_encoder_set_active_device(encoder);
 270         drm_mode_set_crtcinfo(adjusted_mode, 0);
 271
 272         /* hw bug */
 273         if ((mode->flags & DRM_MODE_FLAG_INTERLACE)
 274             && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2)))
 275                 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2;
 276
 277         /* get the native mode for LVDS */
 278         if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT)) {
 279                 struct drm_display_mode *native_mode = &radeon_encoder->native_mode;
 280                 int mode_id = adjusted_mode->base.id;
 281                 *adjusted_mode = *native_mode;
 282                 if (!ASIC_IS_AVIVO(rdev)) {
 283                         adjusted_mode->hdisplay = mode->hdisplay;
 284                         adjusted_mode->vdisplay = mode->vdisplay;
 285                         adjusted_mode->crtc_hdisplay = mode->hdisplay;
 286                         adjusted_mode->crtc_vdisplay = mode->vdisplay;
 287                 }
 288                 adjusted_mode->base.id = mode_id;
 289         }
 290
 291         /* get the native mode for TV */
 292         if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) {
 293                 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
 294                 if (tv_dac) {
 295                         if (tv_dac->tv_std == TV_STD_NTSC ||
 296                             tv_dac->tv_std == TV_STD_NTSC_J ||
 297                             tv_dac->tv_std == TV_STD_PAL_M)
 298                                 radeon_atom_get_tv_timings(rdev, 0, adjusted_mode);
 299                         else
 300                                 radeon_atom_get_tv_timings(rdev, 1, adjusted_mode);
 301                 }
 302         }
 303
 304         if (ASIC_IS_DCE3(rdev) &&
 305             (radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT))) {
 306                 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
 307                 radeon_dp_set_link_config(connector, mode);
 308         }
 309
 310         return true;
 311 }
 312
 313 static void
 314 atombios_dac_setup(struct drm_encoder *encoder, int action)
 315 {
 316         struct drm_device *dev = encoder->dev;
 317         struct radeon_device *rdev = dev->dev_private;
 318         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 319         DAC_ENCODER_CONTROL_PS_ALLOCATION args;
 320         int index = 0, num = 0;
 321         struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
 322         enum radeon_tv_std tv_std = TV_STD_NTSC;
 323
 324         if (dac_info->tv_std)
 325                 tv_std = dac_info->tv_std;
 326
 327         memset(&args, 0, sizeof(args));
 328
 329         switch (radeon_encoder->encoder_id) {
 330         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
 331         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
 332                 index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl);
 333                 num = 1;
 334                 break;
 335         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
 336         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
 337                 index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl);
 338                 num = 2;
 339                 break;
 340         }
 341
 342         args.ucAction = action;
 343
 344         if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT))
 345                 args.ucDacStandard = ATOM_DAC1_PS2;
 346         else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
 347                 args.ucDacStandard = ATOM_DAC1_CV;
 348         else {
 349                 switch (tv_std) {
 350                 case TV_STD_PAL:
 351                 case TV_STD_PAL_M:
 352                 case TV_STD_SCART_PAL:
 353                 case TV_STD_SECAM:
 354                 case TV_STD_PAL_CN:
 355                         args.ucDacStandard = ATOM_DAC1_PAL;
 356                         break;
 357                 case TV_STD_NTSC:
 358                 case TV_STD_NTSC_J:
 359                 case TV_STD_PAL_60:
 360                 default:
 361                         args.ucDacStandard = ATOM_DAC1_NTSC;
 362                         break;
 363                 }
 364         }
 365         args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 366
 367         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 368
 369 }
 370
 371 static void
 372 atombios_tv_setup(struct drm_encoder *encoder, int action)
 373 {
 374         struct drm_device *dev = encoder->dev;
 375         struct radeon_device *rdev = dev->dev_private;
 376         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 377         TV_ENCODER_CONTROL_PS_ALLOCATION args;
 378         int index = 0;
 379         struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
 380         enum radeon_tv_std tv_std = TV_STD_NTSC;
 381
 382         if (dac_info->tv_std)
 383                 tv_std = dac_info->tv_std;
 384
 385         memset(&args, 0, sizeof(args));
 386
 387         index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl);
 388
 389         args.sTVEncoder.ucAction = action;
 390
 391         if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
 392                 args.sTVEncoder.ucTvStandard = ATOM_TV_CV;
 393         else {
 394                 switch (tv_std) {
 395                 case TV_STD_NTSC:
 396                         args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
 397                         break;
 398                 case TV_STD_PAL:
 399                         args.sTVEncoder.ucTvStandard = ATOM_TV_PAL;
 400                         break;
 401                 case TV_STD_PAL_M:
 402                         args.sTVEncoder.ucTvStandard = ATOM_TV_PALM;
 403                         break;
 404                 case TV_STD_PAL_60:
 405                         args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60;
 406                         break;
 407                 case TV_STD_NTSC_J:
 408                         args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ;
 409                         break;
 410                 case TV_STD_SCART_PAL:
 411                         args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */
 412                         break;
 413                 case TV_STD_SECAM:
 414                         args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM;
 415                         break;
 416                 case TV_STD_PAL_CN:
 417                         args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN;
 418                         break;
 419                 default:
 420                         args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
 421                         break;
 422                 }
 423         }
 424
 425         args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 426
 427         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 428
 429 }
 430
 431 void
 432 atombios_external_tmds_setup(struct drm_encoder *encoder, int action)
 433 {
 434         struct drm_device *dev = encoder->dev;
 435         struct radeon_device *rdev = dev->dev_private;
 436         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 437         ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION args;
 438         int index = 0;
 439
 440         memset(&args, 0, sizeof(args));
 441
 442         index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
 443
 444         args.sXTmdsEncoder.ucEnable = action;
 445
 446         if (radeon_encoder->pixel_clock > 165000)
 447                 args.sXTmdsEncoder.ucMisc = PANEL_ENCODER_MISC_DUAL;
 448
 449         /*if (pScrn->rgbBits == 8)*/
 450         args.sXTmdsEncoder.ucMisc |= (1 << 1);
 451
 452         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 453
 454 }
 455
 456 static void
 457 atombios_ddia_setup(struct drm_encoder *encoder, int action)
 458 {
 459         struct drm_device *dev = encoder->dev;
 460         struct radeon_device *rdev = dev->dev_private;
 461         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 462         DVO_ENCODER_CONTROL_PS_ALLOCATION args;
 463         int index = 0;
 464
 465         memset(&args, 0, sizeof(args));
 466
 467         index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
 468
 469         args.sDVOEncoder.ucAction = action;
 470         args.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 471
 472         if (radeon_encoder->pixel_clock > 165000)
 473                 args.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute = PANEL_ENCODER_MISC_DUAL;
 474
 475         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 476
 477 }
 478
 479 union lvds_encoder_control {
 480         LVDS_ENCODER_CONTROL_PS_ALLOCATION    v1;
 481         LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2;
 482 };
 483
 484 void
 485 atombios_digital_setup(struct drm_encoder *encoder, int action)
 486 {
 487         struct drm_device *dev = encoder->dev;
 488         struct radeon_device *rdev = dev->dev_private;
 489         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 490         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 491         struct radeon_connector_atom_dig *dig_connector =
 492                 radeon_get_atom_connector_priv_from_encoder(encoder);
 493         union lvds_encoder_control args;
 494         int index = 0;
 495         int hdmi_detected = 0;
 496         uint8_t frev, crev;
 497
 498         if (!dig || !dig_connector)
 499                 return;
 500
 501         if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
 502                 hdmi_detected = 1;
 503
 504         memset(&args, 0, sizeof(args));
 505
 506         switch (radeon_encoder->encoder_id) {
 507         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
 508                 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
 509                 break;
 510         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
 511         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
 512                 index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl);
 513                 break;
 514         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
 515                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
 516                         index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
 517                 else
 518                         index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl);
 519                 break;
 520         }
 521
 522         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
 523                 return;
 524
 525         switch (frev) {
 526         case 1:
 527         case 2:
 528                 switch (crev) {
 529                 case 1:
 530                         args.v1.ucMisc = 0;
 531                         args.v1.ucAction = action;
 532                         if (hdmi_detected)
 533                                 args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
 534                         args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 535                         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
 536                                 if (dig->lvds_misc & ATOM_PANEL_MISC_DUAL)
 537                                         args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 538                                 if (dig->lvds_misc & ATOM_PANEL_MISC_888RGB)
 539                                         args.v1.ucMisc |= (1 << 1);
 540                         } else {
 541                                 if (dig_connector->linkb)
 542                                         args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
 543                                 if (radeon_encoder->pixel_clock > 165000)
 544                                         args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 545                                 /*if (pScrn->rgbBits == 8) */
 546                                 args.v1.ucMisc |= (1 << 1);
 547                         }
 548                         break;
 549                 case 2:
 550                 case 3:
 551                         args.v2.ucMisc = 0;
 552                         args.v2.ucAction = action;
 553                         if (crev == 3) {
 554                                 if (dig->coherent_mode)
 555                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT;
 556                         }
 557                         if (hdmi_detected)
 558                                 args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
 559                         args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 560                         args.v2.ucTruncate = 0;
 561                         args.v2.ucSpatial = 0;
 562                         args.v2.ucTemporal = 0;
 563                         args.v2.ucFRC = 0;
 564                         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
 565                                 if (dig->lvds_misc & ATOM_PANEL_MISC_DUAL)
 566                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 567                                 if (dig->lvds_misc & ATOM_PANEL_MISC_SPATIAL) {
 568                                         args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN;
 569                                         if (dig->lvds_misc & ATOM_PANEL_MISC_888RGB)
 570                                                 args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH;
 571                                 }
 572                                 if (dig->lvds_misc & ATOM_PANEL_MISC_TEMPORAL) {
 573                                         args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN;
 574                                         if (dig->lvds_misc & ATOM_PANEL_MISC_888RGB)
 575                                                 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH;
 576                                         if (((dig->lvds_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2)
 577                                                 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4;
 578                                 }
 579                         } else {
 580                                 if (dig_connector->linkb)
 581                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
 582                                 if (radeon_encoder->pixel_clock > 165000)
 583                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 584                         }
 585                         break;
 586                 default:
 587                         DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 588                         break;
 589                 }
 590                 break;
 591         default:
 592                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 593                 break;
 594         }
 595
 596         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 597 }
 598
 599 int
 600 atombios_get_encoder_mode(struct drm_encoder *encoder)
 601 {
 602         struct drm_connector *connector;
 603         struct radeon_connector *radeon_connector;
 604         struct radeon_connector_atom_dig *dig_connector;
 605
 606         connector = radeon_get_connector_for_encoder(encoder);
 607         if (!connector)
 608                 return 0;
 609
 610         radeon_connector = to_radeon_connector(connector);
 611
 612         switch (connector->connector_type) {
 613         case DRM_MODE_CONNECTOR_DVII:
 614         case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */
 615                 if (drm_detect_hdmi_monitor(radeon_connector->edid))
 616                         return ATOM_ENCODER_MODE_HDMI;
 617                 else if (radeon_connector->use_digital)
 618                         return ATOM_ENCODER_MODE_DVI;
 619                 else
 620                         return ATOM_ENCODER_MODE_CRT;
 621                 break;
 622         case DRM_MODE_CONNECTOR_DVID:
 623         case DRM_MODE_CONNECTOR_HDMIA:
 624         default:
 625                 if (drm_detect_hdmi_monitor(radeon_connector->edid))
 626                         return ATOM_ENCODER_MODE_HDMI;
 627                 else
 628                         return ATOM_ENCODER_MODE_DVI;
 629                 break;
 630         case DRM_MODE_CONNECTOR_LVDS:
 631                 return ATOM_ENCODER_MODE_LVDS;
 632                 break;
 633         case DRM_MODE_CONNECTOR_DisplayPort:
 634         case DRM_MODE_CONNECTOR_eDP:
 635                 dig_connector = radeon_connector->con_priv;
 636                 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
 637                     (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP))
 638                         return ATOM_ENCODER_MODE_DP;
 639                 else if (drm_detect_hdmi_monitor(radeon_connector->edid))
 640                         return ATOM_ENCODER_MODE_HDMI;
 641                 else
 642                         return ATOM_ENCODER_MODE_DVI;
 643                 break;
 644         case DRM_MODE_CONNECTOR_DVIA:
 645         case DRM_MODE_CONNECTOR_VGA:
 646                 return ATOM_ENCODER_MODE_CRT;
 647                 break;
 648         case DRM_MODE_CONNECTOR_Composite:
 649         case DRM_MODE_CONNECTOR_SVIDEO:
 650         case DRM_MODE_CONNECTOR_9PinDIN:
 651                 /* fix me */
 652                 return ATOM_ENCODER_MODE_TV;
 653                 /*return ATOM_ENCODER_MODE_CV;*/
 654                 break;
 655         }
 656 }
 657
 658 /*
 659  * DIG Encoder/Transmitter Setup
 660  *
 661  * DCE 3.0/3.1
 662  * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA.
 663  * Supports up to 3 digital outputs
 664  * - 2 DIG encoder blocks.
 665  * DIG1 can drive UNIPHY link A or link B
 666  * DIG2 can drive UNIPHY link B or LVTMA
 667  *
 668  * DCE 3.2
 669  * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B).
 670  * Supports up to 5 digital outputs
 671  * - 2 DIG encoder blocks.
 672  * DIG1/2 can drive UNIPHY0/1/2 link A or link B
 673  *
 674  * DCE 4.0
 675  * - 3 DIG transmitter blocks UNPHY0/1/2 (links A and B).
 676  * Supports up to 6 digital outputs
 677  * - 6 DIG encoder blocks.
 678  * - DIG to PHY mapping is hardcoded
 679  * DIG1 drives UNIPHY0 link A, A+B
 680  * DIG2 drives UNIPHY0 link B
 681  * DIG3 drives UNIPHY1 link A, A+B
 682  * DIG4 drives UNIPHY1 link B
 683  * DIG5 drives UNIPHY2 link A, A+B
 684  * DIG6 drives UNIPHY2 link B
 685  *
 686  * Routing
 687  * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links)
 688  * Examples:
 689  * crtc0 -> dig2 -> LVTMA   links A+B -> TMDS/HDMI
 690  * crtc1 -> dig1 -> UNIPHY0 link  B   -> DP
 691  * crtc0 -> dig1 -> UNIPHY2 link  A   -> LVDS
 692  * crtc1 -> dig2 -> UNIPHY1 link  B+A -> TMDS/HDMI
 693  */
 694
 695 union dig_encoder_control {
 696         DIG_ENCODER_CONTROL_PS_ALLOCATION v1;
 697         DIG_ENCODER_CONTROL_PARAMETERS_V2 v2;
 698         DIG_ENCODER_CONTROL_PARAMETERS_V3 v3;
 699 };
 700
 701 void
 702 atombios_dig_encoder_setup(struct drm_encoder *encoder, int action)
 703 {
 704         struct drm_device *dev = encoder->dev;
 705         struct radeon_device *rdev = dev->dev_private;
 706         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 707         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 708         struct radeon_connector_atom_dig *dig_connector =
 709                 radeon_get_atom_connector_priv_from_encoder(encoder);
 710         union dig_encoder_control args;
 711         int index = 0;
 712         uint8_t frev, crev;
 713
 714         if (!dig || !dig_connector)
 715                 return;
 716
 717         memset(&args, 0, sizeof(args));
 718
 719         if (ASIC_IS_DCE4(rdev))
 720                 index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl);
 721         else {
 722                 if (dig->dig_encoder)
 723                         index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
 724                 else
 725                         index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
 726         }
 727
 728         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
 729                 return;
 730
 731         args.v1.ucAction = action;
 732         args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 733         args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder);
 734
 735         if (args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) {
 736                 if (dig_connector->dp_clock == 270000)
 737                         args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
 738                 args.v1.ucLaneNum = dig_connector->dp_lane_count;
 739         } else if (radeon_encoder->pixel_clock > 165000)
 740                 args.v1.ucLaneNum = 8;
 741         else
 742                 args.v1.ucLaneNum = 4;
 743
 744         if (ASIC_IS_DCE4(rdev)) {
 745                 args.v3.acConfig.ucDigSel = dig->dig_encoder;
 746                 args.v3.ucBitPerColor = PANEL_8BIT_PER_COLOR;
 747         } else {
 748                 switch (radeon_encoder->encoder_id) {
 749                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 750                         args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1;
 751                         break;
 752                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
 753                 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
 754                         args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2;
 755                         break;
 756                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
 757                         args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3;
 758                         break;
 759                 }
 760                 if (dig_connector->linkb)
 761                         args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB;
 762                 else
 763                         args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA;
 764         }
 765
 766         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 767
 768 }
 769
 770 union dig_transmitter_control {
 771         DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1;
 772         DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2;
 773         DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3;
 774 };
 775
 776 void
 777 atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set)
 778 {
 779         struct drm_device *dev = encoder->dev;
 780         struct radeon_device *rdev = dev->dev_private;
 781         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 782         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 783         struct radeon_connector_atom_dig *dig_connector =
 784                 radeon_get_atom_connector_priv_from_encoder(encoder);
 785         struct drm_connector *connector;
 786         struct radeon_connector *radeon_connector;
 787         union dig_transmitter_control args;
 788         int index = 0;
 789         uint8_t frev, crev;
 790         bool is_dp = false;
 791         int pll_id = 0;
 792
 793         if (!dig || !dig_connector)
 794                 return;
 795
 796         connector = radeon_get_connector_for_encoder(encoder);
 797         radeon_connector = to_radeon_connector(connector);
 798
 799         if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP)
 800                 is_dp = true;
 801
 802         memset(&args, 0, sizeof(args));
 803
 804         if (ASIC_IS_DCE32(rdev) || ASIC_IS_DCE4(rdev))
 805                 index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
 806         else {
 807                 switch (radeon_encoder->encoder_id) {
 808                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 809                         index = GetIndexIntoMasterTable(COMMAND, DIG1TransmitterControl);
 810                         break;
 811                 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
 812                         index = GetIndexIntoMasterTable(COMMAND, DIG2TransmitterControl);
 813                         break;
 814                 }
 815         }
 816
 817         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
 818                 return;
 819
 820         args.v1.ucAction = action;
 821         if (action == ATOM_TRANSMITTER_ACTION_INIT) {
 822                 args.v1.usInitInfo = radeon_connector->connector_object_id;
 823         } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
 824                 args.v1.asMode.ucLaneSel = lane_num;
 825                 args.v1.asMode.ucLaneSet = lane_set;
 826         } else {
 827                 if (is_dp)
 828                         args.v1.usPixelClock =
 829                                 cpu_to_le16(dig_connector->dp_clock / 10);
 830                 else if (radeon_encoder->pixel_clock > 165000)
 831                         args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
 832                 else
 833                         args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 834         }
 835         if (ASIC_IS_DCE4(rdev)) {
 836                 if (is_dp)
 837                         args.v3.ucLaneNum = dig_connector->dp_lane_count;
 838                 else if (radeon_encoder->pixel_clock > 165000)
 839                         args.v3.ucLaneNum = 8;
 840                 else
 841                         args.v3.ucLaneNum = 4;
 842
 843                 if (dig_connector->linkb) {
 844                         args.v3.acConfig.ucLinkSel = 1;
 845                         args.v3.acConfig.ucEncoderSel = 1;
 846                 }
 847
 848                 /* Select the PLL for the PHY
 849                  * DP PHY should be clocked from external src if there is
 850                  * one.
 851                  */
 852                 if (encoder->crtc) {
 853                         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
 854                         pll_id = radeon_crtc->pll_id;
 855                 }
 856                 if (is_dp && rdev->clock.dp_extclk)
 857                         args.v3.acConfig.ucRefClkSource = 2; /* external src */
 858                 else
 859                         args.v3.acConfig.ucRefClkSource = pll_id;
 860
 861                 switch (radeon_encoder->encoder_id) {
 862                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 863                         args.v3.acConfig.ucTransmitterSel = 0;
 864                         break;
 865                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
 866                         args.v3.acConfig.ucTransmitterSel = 1;
 867                         break;
 868                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
 869                         args.v3.acConfig.ucTransmitterSel = 2;
 870                         break;
 871                 }
 872
 873                 if (is_dp)
 874                         args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */
 875                 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
 876                         if (dig->coherent_mode)
 877                                 args.v3.acConfig.fCoherentMode = 1;
 878                 }
 879         } else if (ASIC_IS_DCE32(rdev)) {
 880                 args.v2.acConfig.ucEncoderSel = dig->dig_encoder;
 881                 if (dig_connector->linkb)
 882                         args.v2.acConfig.ucLinkSel = 1;
 883
 884                 switch (radeon_encoder->encoder_id) {
 885                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 886                         args.v2.acConfig.ucTransmitterSel = 0;
 887                         break;
 888                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
 889                         args.v2.acConfig.ucTransmitterSel = 1;
 890                         break;
 891                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
 892                         args.v2.acConfig.ucTransmitterSel = 2;
 893                         break;
 894                 }
 895
 896                 if (is_dp)
 897                         args.v2.acConfig.fCoherentMode = 1;
 898                 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
 899                         if (dig->coherent_mode)
 900                                 args.v2.acConfig.fCoherentMode = 1;
 901                 }
 902         } else {
 903                 args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
 904
 905                 if (dig->dig_encoder)
 906                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
 907                 else
 908                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
 909
 910                 if ((rdev->flags & RADEON_IS_IGP) &&
 911                     (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) {
 912                         if (is_dp || (radeon_encoder->pixel_clock <= 165000)) {
 913                                 if (dig_connector->igp_lane_info & 0x1)
 914                                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3;
 915                                 else if (dig_connector->igp_lane_info & 0x2)
 916                                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7;
 917                                 else if (dig_connector->igp_lane_info & 0x4)
 918                                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11;
 919                                 else if (dig_connector->igp_lane_info & 0x8)
 920                                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15;
 921                         } else {
 922                                 if (dig_connector->igp_lane_info & 0x3)
 923                                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7;
 924                                 else if (dig_connector->igp_lane_info & 0xc)
 925                                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15;
 926                         }
 927                 }
 928
 929                 if (dig_connector->linkb)
 930                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB;
 931                 else
 932                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA;
 933
 934                 if (is_dp)
 935                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
 936                 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
 937                         if (dig->coherent_mode)
 938                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
 939                         if (radeon_encoder->pixel_clock > 165000)
 940                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK;
 941                 }
 942         }
 943
 944         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 945 }
 946
 947 static void
 948 atombios_yuv_setup(struct drm_encoder *encoder, bool enable)
 949 {
 950         struct drm_device *dev = encoder->dev;
 951         struct radeon_device *rdev = dev->dev_private;
 952         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 953         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
 954         ENABLE_YUV_PS_ALLOCATION args;
 955         int index = GetIndexIntoMasterTable(COMMAND, EnableYUV);
 956         uint32_t temp, reg;
 957
 958         memset(&args, 0, sizeof(args));
 959
 960         if (rdev->family >= CHIP_R600)
 961                 reg = R600_BIOS_3_SCRATCH;
 962         else
 963                 reg = RADEON_BIOS_3_SCRATCH;
 964
 965         /* XXX: fix up scratch reg handling */
 966         temp = RREG32(reg);
 967         if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
 968                 WREG32(reg, (ATOM_S3_TV1_ACTIVE |
 969                              (radeon_crtc->crtc_id << 18)));
 970         else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
 971                 WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24)));
 972         else
 973                 WREG32(reg, 0);
 974
 975         if (enable)
 976                 args.ucEnable = ATOM_ENABLE;
 977         args.ucCRTC = radeon_crtc->crtc_id;
 978
 979         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 980
 981         WREG32(reg, temp);
 982 }
 983
 984 static void
 985 radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
 986 {
 987         struct drm_device *dev = encoder->dev;
 988         struct radeon_device *rdev = dev->dev_private;
 989         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 990         DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
 991         int index = 0;
 992         bool is_dig = false;
 993
 994         memset(&args, 0, sizeof(args));
 995
 996         DRM_DEBUG("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n",
 997                   radeon_encoder->encoder_id, mode, radeon_encoder->devices,
 998                   radeon_encoder->active_device);
 999         switch (radeon_encoder->encoder_id) {
1000         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1001         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1002                 index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl);
1003                 break;
1004         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1005         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1006         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1007         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1008                 is_dig = true;
1009                 break;
1010         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1011         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1012         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1013                 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1014                 break;
1015         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1016                 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1017                 break;
1018         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1019                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1020                         index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1021                 else
1022                         index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl);
1023                 break;
1024         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1025         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1026                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1027                         index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1028                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1029                         index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1030                 else
1031                         index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl);
1032                 break;
1033         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1034         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1035                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1036                         index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1037                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1038                         index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1039                 else
1040                         index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl);
1041                 break;
1042         }
1043
1044         if (is_dig) {
1045                 switch (mode) {
1046                 case DRM_MODE_DPMS_ON:
1047                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0);
1048                         {
1049                                 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1050                                 dp_link_train(encoder, connector);
1051                         }
1052                         break;
1053                 case DRM_MODE_DPMS_STANDBY:
1054                 case DRM_MODE_DPMS_SUSPEND:
1055                 case DRM_MODE_DPMS_OFF:
1056                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0);
1057                         break;
1058                 }
1059         } else {
1060                 switch (mode) {
1061                 case DRM_MODE_DPMS_ON:
1062                         args.ucAction = ATOM_ENABLE;
1063                         break;
1064                 case DRM_MODE_DPMS_STANDBY:
1065                 case DRM_MODE_DPMS_SUSPEND:
1066                 case DRM_MODE_DPMS_OFF:
1067                         args.ucAction = ATOM_DISABLE;
1068                         break;
1069                 }
1070                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1071         }
1072         radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1073
1074         /* adjust pm to dpms change */
1075         radeon_pm_compute_clocks(rdev);
1076 }
1077
1078 union crtc_source_param {
1079         SELECT_CRTC_SOURCE_PS_ALLOCATION v1;
1080         SELECT_CRTC_SOURCE_PARAMETERS_V2 v2;
1081 };
1082
1083 static void
1084 atombios_set_encoder_crtc_source(struct drm_encoder *encoder)
1085 {
1086         struct drm_device *dev = encoder->dev;
1087         struct radeon_device *rdev = dev->dev_private;
1088         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1089         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1090         union crtc_source_param args;
1091         int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
1092         uint8_t frev, crev;
1093         struct radeon_encoder_atom_dig *dig;
1094
1095         memset(&args, 0, sizeof(args));
1096
1097         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1098                 return;
1099
1100         switch (frev) {
1101         case 1:
1102                 switch (crev) {
1103                 case 1:
1104                 default:
1105                         if (ASIC_IS_AVIVO(rdev))
1106                                 args.v1.ucCRTC = radeon_crtc->crtc_id;
1107                         else {
1108                                 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) {
1109                                         args.v1.ucCRTC = radeon_crtc->crtc_id;
1110                                 } else {
1111                                         args.v1.ucCRTC = radeon_crtc->crtc_id << 2;
1112                                 }
1113                         }
1114                         switch (radeon_encoder->encoder_id) {
1115                         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1116                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1117                                 args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX;
1118                                 break;
1119                         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1120                         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1121                                 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT)
1122                                         args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX;
1123                                 else
1124                                         args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX;
1125                                 break;
1126                         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1127                         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1128                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1129                                 args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX;
1130                                 break;
1131                         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1132                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1133                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1134                                         args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1135                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1136                                         args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1137                                 else
1138                                         args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX;
1139                                 break;
1140                         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1141                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1142                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1143                                         args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1144                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1145                                         args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1146                                 else
1147                                         args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX;
1148                                 break;
1149                         }
1150                         break;
1151                 case 2:
1152                         args.v2.ucCRTC = radeon_crtc->crtc_id;
1153                         args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1154                         switch (radeon_encoder->encoder_id) {
1155                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1156                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1157                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1158                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1159                                 dig = radeon_encoder->enc_priv;
1160                                 switch (dig->dig_encoder) {
1161                                 case 0:
1162                                         args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
1163                                         break;
1164                                 case 1:
1165                                         args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
1166                                         break;
1167                                 case 2:
1168                                         args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID;
1169                                         break;
1170                                 case 3:
1171                                         args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID;
1172                                         break;
1173                                 case 4:
1174                                         args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID;
1175                                         break;
1176                                 case 5:
1177                                         args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID;
1178                                         break;
1179                                 }
1180                                 break;
1181                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1182                                 args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID;
1183                                 break;
1184                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1185                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1186                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1187                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1188                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1189                                 else
1190                                         args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID;
1191                                 break;
1192                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1193                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1194                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1195                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1196                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1197                                 else
1198                                         args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID;
1199                                 break;
1200                         }
1201                         break;
1202                 }
1203                 break;
1204         default:
1205                 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1206                 break;
1207         }
1208
1209         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1210
1211         /* update scratch regs with new routing */
1212         radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1213 }
1214
1215 static void
1216 atombios_apply_encoder_quirks(struct drm_encoder *encoder,
1217                               struct drm_display_mode *mode)
1218 {
1219         struct drm_device *dev = encoder->dev;
1220         struct radeon_device *rdev = dev->dev_private;
1221         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1222         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1223
1224         /* Funky macbooks */
1225         if ((dev->pdev->device == 0x71C5) &&
1226             (dev->pdev->subsystem_vendor == 0x106b) &&
1227             (dev->pdev->subsystem_device == 0x0080)) {
1228                 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
1229                         uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL);
1230
1231                         lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN;
1232                         lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN;
1233
1234                         WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control);
1235                 }
1236         }
1237
1238         /* set scaler clears this on some chips */
1239         /* XXX check DCE4 */
1240         if (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))) {
1241                 if (ASIC_IS_AVIVO(rdev) && (mode->flags & DRM_MODE_FLAG_INTERLACE))
1242                         WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
1243                                AVIVO_D1MODE_INTERLEAVE_EN);
1244         }
1245 }
1246
1247 static int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder)
1248 {
1249         struct drm_device *dev = encoder->dev;
1250         struct radeon_device *rdev = dev->dev_private;
1251         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1252         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1253         struct drm_encoder *test_encoder;
1254         struct radeon_encoder_atom_dig *dig;
1255         uint32_t dig_enc_in_use = 0;
1256
1257         if (ASIC_IS_DCE4(rdev)) {
1258                 struct radeon_connector_atom_dig *dig_connector =
1259                         radeon_get_atom_connector_priv_from_encoder(encoder);
1260
1261                 switch (radeon_encoder->encoder_id) {
1262                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1263                         if (dig_connector->linkb)
1264                                 return 1;
1265                         else
1266                                 return 0;
1267                         break;
1268                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1269                         if (dig_connector->linkb)
1270                                 return 3;
1271                         else
1272                                 return 2;
1273                         break;
1274                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1275                         if (dig_connector->linkb)
1276                                 return 5;
1277                         else
1278                                 return 4;
1279                         break;
1280                 }
1281         }
1282
1283         /* on DCE32 and encoder can driver any block so just crtc id */
1284         if (ASIC_IS_DCE32(rdev)) {
1285                 return radeon_crtc->crtc_id;
1286         }
1287
1288         /* on DCE3 - LVTMA can only be driven by DIGB */
1289         list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
1290                 struct radeon_encoder *radeon_test_encoder;
1291
1292                 if (encoder == test_encoder)
1293                         continue;
1294
1295                 if (!radeon_encoder_is_digital(test_encoder))
1296                         continue;
1297
1298                 radeon_test_encoder = to_radeon_encoder(test_encoder);
1299                 dig = radeon_test_encoder->enc_priv;
1300
1301                 if (dig->dig_encoder >= 0)
1302                         dig_enc_in_use |= (1 << dig->dig_encoder);
1303         }
1304
1305         if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA) {
1306                 if (dig_enc_in_use & 0x2)
1307                         DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n");
1308                 return 1;
1309         }
1310         if (!(dig_enc_in_use & 1))
1311                 return 0;
1312         return 1;
1313 }
1314
1315 static void
1316 radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
1317                              struct drm_display_mode *mode,
1318                              struct drm_display_mode *adjusted_mode)
1319 {
1320         struct drm_device *dev = encoder->dev;
1321         struct radeon_device *rdev = dev->dev_private;
1322         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1323
1324         radeon_encoder->pixel_clock = adjusted_mode->clock;
1325
1326         if (ASIC_IS_AVIVO(rdev)) {
1327                 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT))
1328                         atombios_yuv_setup(encoder, true);
1329                 else
1330                         atombios_yuv_setup(encoder, false);
1331         }
1332
1333         switch (radeon_encoder->encoder_id) {
1334         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1335         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1336         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1337         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1338                 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
1339                 break;
1340         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1341         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1342         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1343         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1344                 if (ASIC_IS_DCE4(rdev)) {
1345                         /* disable the transmitter */
1346                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1347                         /* setup and enable the encoder */
1348                         atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP);
1349
1350                         /* init and enable the transmitter */
1351                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
1352                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1353                 } else {
1354                         /* disable the encoder and transmitter */
1355                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1356                         atombios_dig_encoder_setup(encoder, ATOM_DISABLE);
1357
1358                         /* setup and enable the encoder and transmitter */
1359                         atombios_dig_encoder_setup(encoder, ATOM_ENABLE);
1360                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
1361                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0);
1362                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1363                 }
1364                 break;
1365         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1366                 atombios_ddia_setup(encoder, ATOM_ENABLE);
1367                 break;
1368         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1369         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1370                 atombios_external_tmds_setup(encoder, ATOM_ENABLE);
1371                 break;
1372         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1373         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1374         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1375         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1376                 atombios_dac_setup(encoder, ATOM_ENABLE);
1377                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
1378                         atombios_tv_setup(encoder, ATOM_ENABLE);
1379                 break;
1380         }
1381         atombios_apply_encoder_quirks(encoder, adjusted_mode);
1382
1383         if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
1384                 r600_hdmi_enable(encoder);
1385                 r600_hdmi_setmode(encoder, adjusted_mode);
1386         }
1387 }
1388
1389 static bool
1390 atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1391 {
1392         struct drm_device *dev = encoder->dev;
1393         struct radeon_device *rdev = dev->dev_private;
1394         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1395         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1396
1397         if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT |
1398                                        ATOM_DEVICE_CV_SUPPORT |
1399                                        ATOM_DEVICE_CRT_SUPPORT)) {
1400                 DAC_LOAD_DETECTION_PS_ALLOCATION args;
1401                 int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection);
1402                 uint8_t frev, crev;
1403
1404                 memset(&args, 0, sizeof(args));
1405
1406                 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1407                         return false;
1408
1409                 args.sDacload.ucMisc = 0;
1410
1411                 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) ||
1412                     (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1))
1413                         args.sDacload.ucDacType = ATOM_DAC_A;
1414                 else
1415                         args.sDacload.ucDacType = ATOM_DAC_B;
1416
1417                 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)
1418                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT);
1419                 else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)
1420                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT);
1421                 else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
1422                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT);
1423                         if (crev >= 3)
1424                                 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
1425                 } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
1426                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT);
1427                         if (crev >= 3)
1428                                 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
1429                 }
1430
1431                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1432
1433                 return true;
1434         } else
1435                 return false;
1436 }
1437
1438 static enum drm_connector_status
1439 radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1440 {
1441         struct drm_device *dev = encoder->dev;
1442         struct radeon_device *rdev = dev->dev_private;
1443         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1444         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1445         uint32_t bios_0_scratch;
1446
1447         if (!atombios_dac_load_detect(encoder, connector)) {
1448                 DRM_DEBUG("detect returned false \n");
1449                 return connector_status_unknown;
1450         }
1451
1452         if (rdev->family >= CHIP_R600)
1453                 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
1454         else
1455                 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
1456
1457         DRM_DEBUG("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
1458         if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
1459                 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
1460                         return connector_status_connected;
1461         }
1462         if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
1463                 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
1464                         return connector_status_connected;
1465         }
1466         if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
1467                 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
1468                         return connector_status_connected;
1469         }
1470         if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
1471                 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
1472                         return connector_status_connected; /* CTV */
1473                 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
1474                         return connector_status_connected; /* STV */
1475         }
1476         return connector_status_disconnected;
1477 }
1478
1479 static void radeon_atom_encoder_prepare(struct drm_encoder *encoder)
1480 {
1481         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1482
1483         if (radeon_encoder->active_device &
1484             (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) {
1485                 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
1486                 if (dig)
1487                         dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder);
1488         }
1489
1490         radeon_atom_output_lock(encoder, true);
1491         radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
1492
1493         /* this is needed for the pll/ss setup to work correctly in some cases */
1494         atombios_set_encoder_crtc_source(encoder);
1495 }
1496
1497 static void radeon_atom_encoder_commit(struct drm_encoder *encoder)
1498 {
1499         radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
1500         radeon_atom_output_lock(encoder, false);
1501 }
1502
1503 static void radeon_atom_encoder_disable(struct drm_encoder *encoder)
1504 {
1505         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1506         struct radeon_encoder_atom_dig *dig;
1507         radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
1508
1509         if (radeon_encoder_is_digital(encoder)) {
1510                 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
1511                         r600_hdmi_disable(encoder);
1512                 dig = radeon_encoder->enc_priv;
1513                 dig->dig_encoder = -1;
1514         }
1515         radeon_encoder->active_device = 0;
1516 }
1517
1518 static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = {
1519         .dpms = radeon_atom_encoder_dpms,
1520         .mode_fixup = radeon_atom_mode_fixup,
1521         .prepare = radeon_atom_encoder_prepare,
1522         .mode_set = radeon_atom_encoder_mode_set,
1523         .commit = radeon_atom_encoder_commit,
1524         .disable = radeon_atom_encoder_disable,
1525         /* no detect for TMDS/LVDS yet */
1526 };
1527
1528 static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = {
1529         .dpms = radeon_atom_encoder_dpms,
1530         .mode_fixup = radeon_atom_mode_fixup,
1531         .prepare = radeon_atom_encoder_prepare,
1532         .mode_set = radeon_atom_encoder_mode_set,
1533         .commit = radeon_atom_encoder_commit,
1534         .detect = radeon_atom_dac_detect,
1535 };
1536
1537 void radeon_enc_destroy(struct drm_encoder *encoder)
1538 {
1539         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1540         kfree(radeon_encoder->enc_priv);
1541         drm_encoder_cleanup(encoder);
1542         kfree(radeon_encoder);
1543 }
1544
1545 static const struct drm_encoder_funcs radeon_atom_enc_funcs = {
1546         .destroy = radeon_enc_destroy,
1547 };
1548
1549 struct radeon_encoder_atom_dac *
1550 radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder)
1551 {
1552         struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL);
1553
1554         if (!dac)
1555                 return NULL;
1556
1557         dac->tv_std = TV_STD_NTSC;
1558         return dac;
1559 }
1560
1561 struct radeon_encoder_atom_dig *
1562 radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder)
1563 {
1564         struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
1565
1566         if (!dig)
1567                 return NULL;
1568
1569         /* coherent mode by default */
1570         dig->coherent_mode = true;
1571         dig->dig_encoder = -1;
1572
1573         return dig;
1574 }
1575
1576 void
1577 radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_id, uint32_t supported_device)
1578 {
1579         struct radeon_device *rdev = dev->dev_private;
1580         struct drm_encoder *encoder;
1581         struct radeon_encoder *radeon_encoder;
1582
1583         /* see if we already added it */
1584         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1585                 radeon_encoder = to_radeon_encoder(encoder);
1586                 if (radeon_encoder->encoder_id == encoder_id) {
1587                         radeon_encoder->devices |= supported_device;
1588                         return;
1589                 }
1590
1591         }
1592
1593         /* add a new one */
1594         radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
1595         if (!radeon_encoder)
1596                 return;
1597
1598         encoder = &radeon_encoder->base;
1599         switch (rdev->num_crtc) {
1600         case 1:
1601                 encoder->possible_crtcs = 0x1;
1602                 break;
1603         case 2:
1604         default:
1605                 encoder->possible_crtcs = 0x3;
1606                 break;
1607         case 6:
1608                 encoder->possible_crtcs = 0x3f;
1609                 break;
1610         }
1611
1612         radeon_encoder->enc_priv = NULL;
1613
1614         radeon_encoder->encoder_id = encoder_id;
1615         radeon_encoder->devices = supported_device;
1616         radeon_encoder->rmx_type = RMX_OFF;
1617
1618         switch (radeon_encoder->encoder_id) {
1619         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1620         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1621         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1622         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1623                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1624                         radeon_encoder->rmx_type = RMX_FULL;
1625                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
1626                         radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
1627                 } else {
1628                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
1629                         radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
1630                 }
1631                 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
1632                 break;
1633         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1634                 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
1635                 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
1636                 break;
1637         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1638         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1639         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1640                 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC);
1641                 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
1642                 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
1643                 break;
1644         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1645         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1646         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1647         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1648         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1649         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1650         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1651                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1652                         radeon_encoder->rmx_type = RMX_FULL;
1653                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
1654                         radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
1655                 } else {
1656                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
1657                         radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
1658                 }
1659                 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
1660                 break;
1661         }
1662 }