2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
26 #include <linux/export.h>
29 #include "radeon_drm.h"
33 extern int radeon_atom_hw_i2c_xfer(struct i2c_adapter
*i2c_adap
,
34 struct i2c_msg
*msgs
, int num
);
35 extern u32
radeon_atom_hw_i2c_func(struct i2c_adapter
*adap
);
41 bool radeon_ddc_probe(struct radeon_connector
*radeon_connector
)
46 struct i2c_msg msgs
[] = {
61 /* on hw with routers, select right port */
62 if (radeon_connector
->router
.ddc_valid
)
63 radeon_router_select_ddc_port(radeon_connector
);
65 ret
= i2c_transfer(&radeon_connector
->ddc_bus
->adapter
, msgs
, 2);
67 /* Couldn't find an accessible DDC on this connector */
69 /* Probe also for valid EDID header
70 * EDID header starts with:
71 * 0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00.
72 * Only the first 6 bytes must be valid as
73 * drm_edid_block_valid() can fix the last 2 bytes */
74 if (drm_edid_header_is_valid(buf
) < 6) {
75 /* Couldn't find an accessible EDID on this
84 static int pre_xfer(struct i2c_adapter
*i2c_adap
)
86 struct radeon_i2c_chan
*i2c
= i2c_get_adapdata(i2c_adap
);
87 struct radeon_device
*rdev
= i2c
->dev
->dev_private
;
88 struct radeon_i2c_bus_rec
*rec
= &i2c
->rec
;
91 /* RV410 appears to have a bug where the hw i2c in reset
92 * holds the i2c port in a bad state - switch hw i2c away before
93 * doing DDC - do this for all r200s/r300s/r400s for safety sake
95 if (rec
->hw_capable
) {
96 if ((rdev
->family
>= CHIP_R200
) && !ASIC_IS_AVIVO(rdev
)) {
99 if (rdev
->family
>= CHIP_RV350
)
100 reg
= RADEON_GPIO_MONID
;
101 else if ((rdev
->family
== CHIP_R300
) ||
102 (rdev
->family
== CHIP_R350
))
103 reg
= RADEON_GPIO_DVI_DDC
;
105 reg
= RADEON_GPIO_CRT2_DDC
;
107 mutex_lock(&rdev
->dc_hw_i2c_mutex
);
108 if (rec
->a_clk_reg
== reg
) {
109 WREG32(RADEON_DVI_I2C_CNTL_0
, (RADEON_I2C_SOFT_RST
|
110 R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1
)));
112 WREG32(RADEON_DVI_I2C_CNTL_0
, (RADEON_I2C_SOFT_RST
|
113 R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3
)));
115 mutex_unlock(&rdev
->dc_hw_i2c_mutex
);
119 /* switch the pads to ddc mode */
120 if (ASIC_IS_DCE3(rdev
) && rec
->hw_capable
) {
121 temp
= RREG32(rec
->mask_clk_reg
);
123 WREG32(rec
->mask_clk_reg
, temp
);
126 /* clear the output pin values */
127 temp
= RREG32(rec
->a_clk_reg
) & ~rec
->a_clk_mask
;
128 WREG32(rec
->a_clk_reg
, temp
);
130 temp
= RREG32(rec
->a_data_reg
) & ~rec
->a_data_mask
;
131 WREG32(rec
->a_data_reg
, temp
);
133 /* set the pins to input */
134 temp
= RREG32(rec
->en_clk_reg
) & ~rec
->en_clk_mask
;
135 WREG32(rec
->en_clk_reg
, temp
);
137 temp
= RREG32(rec
->en_data_reg
) & ~rec
->en_data_mask
;
138 WREG32(rec
->en_data_reg
, temp
);
140 /* mask the gpio pins for software use */
141 temp
= RREG32(rec
->mask_clk_reg
) | rec
->mask_clk_mask
;
142 WREG32(rec
->mask_clk_reg
, temp
);
143 temp
= RREG32(rec
->mask_clk_reg
);
145 temp
= RREG32(rec
->mask_data_reg
) | rec
->mask_data_mask
;
146 WREG32(rec
->mask_data_reg
, temp
);
147 temp
= RREG32(rec
->mask_data_reg
);
152 static void post_xfer(struct i2c_adapter
*i2c_adap
)
154 struct radeon_i2c_chan
*i2c
= i2c_get_adapdata(i2c_adap
);
155 struct radeon_device
*rdev
= i2c
->dev
->dev_private
;
156 struct radeon_i2c_bus_rec
*rec
= &i2c
->rec
;
159 /* unmask the gpio pins for software use */
160 temp
= RREG32(rec
->mask_clk_reg
) & ~rec
->mask_clk_mask
;
161 WREG32(rec
->mask_clk_reg
, temp
);
162 temp
= RREG32(rec
->mask_clk_reg
);
164 temp
= RREG32(rec
->mask_data_reg
) & ~rec
->mask_data_mask
;
165 WREG32(rec
->mask_data_reg
, temp
);
166 temp
= RREG32(rec
->mask_data_reg
);
169 static int get_clock(void *i2c_priv
)
171 struct radeon_i2c_chan
*i2c
= i2c_priv
;
172 struct radeon_device
*rdev
= i2c
->dev
->dev_private
;
173 struct radeon_i2c_bus_rec
*rec
= &i2c
->rec
;
176 /* read the value off the pin */
177 val
= RREG32(rec
->y_clk_reg
);
178 val
&= rec
->y_clk_mask
;
184 static int get_data(void *i2c_priv
)
186 struct radeon_i2c_chan
*i2c
= i2c_priv
;
187 struct radeon_device
*rdev
= i2c
->dev
->dev_private
;
188 struct radeon_i2c_bus_rec
*rec
= &i2c
->rec
;
191 /* read the value off the pin */
192 val
= RREG32(rec
->y_data_reg
);
193 val
&= rec
->y_data_mask
;
198 static void set_clock(void *i2c_priv
, int clock
)
200 struct radeon_i2c_chan
*i2c
= i2c_priv
;
201 struct radeon_device
*rdev
= i2c
->dev
->dev_private
;
202 struct radeon_i2c_bus_rec
*rec
= &i2c
->rec
;
205 /* set pin direction */
206 val
= RREG32(rec
->en_clk_reg
) & ~rec
->en_clk_mask
;
207 val
|= clock
? 0 : rec
->en_clk_mask
;
208 WREG32(rec
->en_clk_reg
, val
);
211 static void set_data(void *i2c_priv
, int data
)
213 struct radeon_i2c_chan
*i2c
= i2c_priv
;
214 struct radeon_device
*rdev
= i2c
->dev
->dev_private
;
215 struct radeon_i2c_bus_rec
*rec
= &i2c
->rec
;
218 /* set pin direction */
219 val
= RREG32(rec
->en_data_reg
) & ~rec
->en_data_mask
;
220 val
|= data
? 0 : rec
->en_data_mask
;
221 WREG32(rec
->en_data_reg
, val
);
226 static u32
radeon_get_i2c_prescale(struct radeon_device
*rdev
)
228 u32 sclk
= rdev
->pm
.current_sclk
;
234 switch (rdev
->family
) {
248 nm
= (sclk
* 10) / (i2c_clock
* 4);
249 for (loop
= 1; loop
< 255; loop
++) {
250 if ((nm
/ loop
) < loop
)
255 prescale
= m
| (n
<< 8);
263 prescale
= (((sclk
* 10)/(4 * 128 * 100) + 1) << 8) + 128;
277 if (rdev
->family
== CHIP_R520
)
278 prescale
= (127 << 8) + ((sclk
* 10) / (4 * 127 * i2c_clock
));
280 prescale
= (((sclk
* 10)/(4 * 128 * 100) + 1) << 8) + 128;
306 DRM_ERROR("i2c: unhandled radeon chip\n");
313 /* hw i2c engine for r1xx-4xx hardware
314 * hw can buffer up to 15 bytes
316 static int r100_hw_i2c_xfer(struct i2c_adapter
*i2c_adap
,
317 struct i2c_msg
*msgs
, int num
)
319 struct radeon_i2c_chan
*i2c
= i2c_get_adapdata(i2c_adap
);
320 struct radeon_device
*rdev
= i2c
->dev
->dev_private
;
321 struct radeon_i2c_bus_rec
*rec
= &i2c
->rec
;
323 int i
, j
, k
, ret
= num
;
325 u32 i2c_cntl_0
, i2c_cntl_1
, i2c_data
;
328 mutex_lock(&rdev
->dc_hw_i2c_mutex
);
329 /* take the pm lock since we need a constant sclk */
330 mutex_lock(&rdev
->pm
.mutex
);
332 prescale
= radeon_get_i2c_prescale(rdev
);
334 reg
= ((prescale
<< RADEON_I2C_PRESCALE_SHIFT
) |
335 RADEON_I2C_DRIVE_EN
|
340 if (rdev
->is_atom_bios
) {
341 tmp
= RREG32(RADEON_BIOS_6_SCRATCH
);
342 WREG32(RADEON_BIOS_6_SCRATCH
, tmp
| ATOM_S6_HW_I2C_BUSY_STATE
);
346 i2c_cntl_0
= RADEON_I2C_CNTL_0
;
347 i2c_cntl_1
= RADEON_I2C_CNTL_1
;
348 i2c_data
= RADEON_I2C_DATA
;
350 i2c_cntl_0
= RADEON_DVI_I2C_CNTL_0
;
351 i2c_cntl_1
= RADEON_DVI_I2C_CNTL_1
;
352 i2c_data
= RADEON_DVI_I2C_DATA
;
354 switch (rdev
->family
) {
361 switch (rec
->mask_clk_reg
) {
362 case RADEON_GPIO_DVI_DDC
:
363 /* no gpio select bit */
366 DRM_ERROR("gpio not supported with hw i2c\n");
372 /* only bit 4 on r200 */
373 switch (rec
->mask_clk_reg
) {
374 case RADEON_GPIO_DVI_DDC
:
375 reg
|= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1
);
377 case RADEON_GPIO_MONID
:
378 reg
|= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3
);
381 DRM_ERROR("gpio not supported with hw i2c\n");
389 switch (rec
->mask_clk_reg
) {
390 case RADEON_GPIO_DVI_DDC
:
391 reg
|= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1
);
393 case RADEON_GPIO_VGA_DDC
:
394 reg
|= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC2
);
396 case RADEON_GPIO_CRT2_DDC
:
397 reg
|= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3
);
400 DRM_ERROR("gpio not supported with hw i2c\n");
407 /* only bit 4 on r300/r350 */
408 switch (rec
->mask_clk_reg
) {
409 case RADEON_GPIO_VGA_DDC
:
410 reg
|= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1
);
412 case RADEON_GPIO_DVI_DDC
:
413 reg
|= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3
);
416 DRM_ERROR("gpio not supported with hw i2c\n");
429 switch (rec
->mask_clk_reg
) {
430 case RADEON_GPIO_VGA_DDC
:
431 reg
|= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1
);
433 case RADEON_GPIO_DVI_DDC
:
434 reg
|= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC2
);
436 case RADEON_GPIO_MONID
:
437 reg
|= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3
);
440 DRM_ERROR("gpio not supported with hw i2c\n");
446 DRM_ERROR("unsupported asic\n");
453 /* check for bus probe */
455 if ((num
== 1) && (p
->len
== 0)) {
456 WREG32(i2c_cntl_0
, (RADEON_I2C_DONE
|
459 RADEON_I2C_SOFT_RST
));
460 WREG32(i2c_data
, (p
->addr
<< 1) & 0xff);
462 WREG32(i2c_cntl_1
, ((1 << RADEON_I2C_DATA_COUNT_SHIFT
) |
463 (1 << RADEON_I2C_ADDR_COUNT_SHIFT
) |
465 (48 << RADEON_I2C_TIME_LIMIT_SHIFT
)));
466 WREG32(i2c_cntl_0
, reg
);
467 for (k
= 0; k
< 32; k
++) {
469 tmp
= RREG32(i2c_cntl_0
);
470 if (tmp
& RADEON_I2C_GO
)
472 tmp
= RREG32(i2c_cntl_0
);
473 if (tmp
& RADEON_I2C_DONE
)
476 DRM_DEBUG("i2c write error 0x%08x\n", tmp
);
477 WREG32(i2c_cntl_0
, tmp
| RADEON_I2C_ABORT
);
485 for (i
= 0; i
< num
; i
++) {
487 for (j
= 0; j
< p
->len
; j
++) {
488 if (p
->flags
& I2C_M_RD
) {
489 WREG32(i2c_cntl_0
, (RADEON_I2C_DONE
|
492 RADEON_I2C_SOFT_RST
));
493 WREG32(i2c_data
, ((p
->addr
<< 1) & 0xff) | 0x1);
494 WREG32(i2c_cntl_1
, ((1 << RADEON_I2C_DATA_COUNT_SHIFT
) |
495 (1 << RADEON_I2C_ADDR_COUNT_SHIFT
) |
497 (48 << RADEON_I2C_TIME_LIMIT_SHIFT
)));
498 WREG32(i2c_cntl_0
, reg
| RADEON_I2C_RECEIVE
);
499 for (k
= 0; k
< 32; k
++) {
501 tmp
= RREG32(i2c_cntl_0
);
502 if (tmp
& RADEON_I2C_GO
)
504 tmp
= RREG32(i2c_cntl_0
);
505 if (tmp
& RADEON_I2C_DONE
)
508 DRM_DEBUG("i2c read error 0x%08x\n", tmp
);
509 WREG32(i2c_cntl_0
, tmp
| RADEON_I2C_ABORT
);
514 p
->buf
[j
] = RREG32(i2c_data
) & 0xff;
516 WREG32(i2c_cntl_0
, (RADEON_I2C_DONE
|
519 RADEON_I2C_SOFT_RST
));
520 WREG32(i2c_data
, (p
->addr
<< 1) & 0xff);
521 WREG32(i2c_data
, p
->buf
[j
]);
522 WREG32(i2c_cntl_1
, ((1 << RADEON_I2C_DATA_COUNT_SHIFT
) |
523 (1 << RADEON_I2C_ADDR_COUNT_SHIFT
) |
525 (48 << RADEON_I2C_TIME_LIMIT_SHIFT
)));
526 WREG32(i2c_cntl_0
, reg
);
527 for (k
= 0; k
< 32; k
++) {
529 tmp
= RREG32(i2c_cntl_0
);
530 if (tmp
& RADEON_I2C_GO
)
532 tmp
= RREG32(i2c_cntl_0
);
533 if (tmp
& RADEON_I2C_DONE
)
536 DRM_DEBUG("i2c write error 0x%08x\n", tmp
);
537 WREG32(i2c_cntl_0
, tmp
| RADEON_I2C_ABORT
);
547 WREG32(i2c_cntl_0
, 0);
548 WREG32(i2c_cntl_1
, 0);
549 WREG32(i2c_cntl_0
, (RADEON_I2C_DONE
|
552 RADEON_I2C_SOFT_RST
));
554 if (rdev
->is_atom_bios
) {
555 tmp
= RREG32(RADEON_BIOS_6_SCRATCH
);
556 tmp
&= ~ATOM_S6_HW_I2C_BUSY_STATE
;
557 WREG32(RADEON_BIOS_6_SCRATCH
, tmp
);
560 mutex_unlock(&rdev
->pm
.mutex
);
561 mutex_unlock(&rdev
->dc_hw_i2c_mutex
);
566 /* hw i2c engine for r5xx hardware
567 * hw can buffer up to 15 bytes
569 static int r500_hw_i2c_xfer(struct i2c_adapter
*i2c_adap
,
570 struct i2c_msg
*msgs
, int num
)
572 struct radeon_i2c_chan
*i2c
= i2c_get_adapdata(i2c_adap
);
573 struct radeon_device
*rdev
= i2c
->dev
->dev_private
;
574 struct radeon_i2c_bus_rec
*rec
= &i2c
->rec
;
576 int i
, j
, remaining
, current_count
, buffer_offset
, ret
= num
;
581 mutex_lock(&rdev
->dc_hw_i2c_mutex
);
582 /* take the pm lock since we need a constant sclk */
583 mutex_lock(&rdev
->pm
.mutex
);
585 prescale
= radeon_get_i2c_prescale(rdev
);
587 /* clear gpio mask bits */
588 tmp
= RREG32(rec
->mask_clk_reg
);
589 tmp
&= ~rec
->mask_clk_mask
;
590 WREG32(rec
->mask_clk_reg
, tmp
);
591 tmp
= RREG32(rec
->mask_clk_reg
);
593 tmp
= RREG32(rec
->mask_data_reg
);
594 tmp
&= ~rec
->mask_data_mask
;
595 WREG32(rec
->mask_data_reg
, tmp
);
596 tmp
= RREG32(rec
->mask_data_reg
);
598 /* clear pin values */
599 tmp
= RREG32(rec
->a_clk_reg
);
600 tmp
&= ~rec
->a_clk_mask
;
601 WREG32(rec
->a_clk_reg
, tmp
);
602 tmp
= RREG32(rec
->a_clk_reg
);
604 tmp
= RREG32(rec
->a_data_reg
);
605 tmp
&= ~rec
->a_data_mask
;
606 WREG32(rec
->a_data_reg
, tmp
);
607 tmp
= RREG32(rec
->a_data_reg
);
609 /* set the pins to input */
610 tmp
= RREG32(rec
->en_clk_reg
);
611 tmp
&= ~rec
->en_clk_mask
;
612 WREG32(rec
->en_clk_reg
, tmp
);
613 tmp
= RREG32(rec
->en_clk_reg
);
615 tmp
= RREG32(rec
->en_data_reg
);
616 tmp
&= ~rec
->en_data_mask
;
617 WREG32(rec
->en_data_reg
, tmp
);
618 tmp
= RREG32(rec
->en_data_reg
);
621 tmp
= RREG32(RADEON_BIOS_6_SCRATCH
);
622 WREG32(RADEON_BIOS_6_SCRATCH
, tmp
| ATOM_S6_HW_I2C_BUSY_STATE
);
623 saved1
= RREG32(AVIVO_DC_I2C_CONTROL1
);
624 saved2
= RREG32(0x494);
625 WREG32(0x494, saved2
| 0x1);
627 WREG32(AVIVO_DC_I2C_ARBITRATION
, AVIVO_DC_I2C_SW_WANTS_TO_USE_I2C
);
628 for (i
= 0; i
< 50; i
++) {
630 if (RREG32(AVIVO_DC_I2C_ARBITRATION
) & AVIVO_DC_I2C_SW_CAN_USE_I2C
)
634 DRM_ERROR("failed to get i2c bus\n");
639 reg
= AVIVO_DC_I2C_START
| AVIVO_DC_I2C_STOP
| AVIVO_DC_I2C_EN
;
640 switch (rec
->mask_clk_reg
) {
641 case AVIVO_DC_GPIO_DDC1_MASK
:
642 reg
|= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC1
);
644 case AVIVO_DC_GPIO_DDC2_MASK
:
645 reg
|= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC2
);
647 case AVIVO_DC_GPIO_DDC3_MASK
:
648 reg
|= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC3
);
651 DRM_ERROR("gpio not supported with hw i2c\n");
656 /* check for bus probe */
658 if ((num
== 1) && (p
->len
== 0)) {
659 WREG32(AVIVO_DC_I2C_STATUS1
, (AVIVO_DC_I2C_DONE
|
662 WREG32(AVIVO_DC_I2C_RESET
, AVIVO_DC_I2C_SOFT_RESET
);
664 WREG32(AVIVO_DC_I2C_RESET
, 0);
666 WREG32(AVIVO_DC_I2C_DATA
, (p
->addr
<< 1) & 0xff);
667 WREG32(AVIVO_DC_I2C_DATA
, 0);
669 WREG32(AVIVO_DC_I2C_CONTROL3
, AVIVO_DC_I2C_TIME_LIMIT(48));
670 WREG32(AVIVO_DC_I2C_CONTROL2
, (AVIVO_DC_I2C_ADDR_COUNT(1) |
671 AVIVO_DC_I2C_DATA_COUNT(1) |
673 WREG32(AVIVO_DC_I2C_CONTROL1
, reg
);
674 WREG32(AVIVO_DC_I2C_STATUS1
, AVIVO_DC_I2C_GO
);
675 for (j
= 0; j
< 200; j
++) {
677 tmp
= RREG32(AVIVO_DC_I2C_STATUS1
);
678 if (tmp
& AVIVO_DC_I2C_GO
)
680 tmp
= RREG32(AVIVO_DC_I2C_STATUS1
);
681 if (tmp
& AVIVO_DC_I2C_DONE
)
684 DRM_DEBUG("i2c write error 0x%08x\n", tmp
);
685 WREG32(AVIVO_DC_I2C_RESET
, AVIVO_DC_I2C_ABORT
);
693 for (i
= 0; i
< num
; i
++) {
697 if (p
->flags
& I2C_M_RD
) {
702 current_count
= remaining
;
703 WREG32(AVIVO_DC_I2C_STATUS1
, (AVIVO_DC_I2C_DONE
|
706 WREG32(AVIVO_DC_I2C_RESET
, AVIVO_DC_I2C_SOFT_RESET
);
708 WREG32(AVIVO_DC_I2C_RESET
, 0);
710 WREG32(AVIVO_DC_I2C_DATA
, ((p
->addr
<< 1) & 0xff) | 0x1);
711 WREG32(AVIVO_DC_I2C_CONTROL3
, AVIVO_DC_I2C_TIME_LIMIT(48));
712 WREG32(AVIVO_DC_I2C_CONTROL2
, (AVIVO_DC_I2C_ADDR_COUNT(1) |
713 AVIVO_DC_I2C_DATA_COUNT(current_count
) |
715 WREG32(AVIVO_DC_I2C_CONTROL1
, reg
| AVIVO_DC_I2C_RECEIVE
);
716 WREG32(AVIVO_DC_I2C_STATUS1
, AVIVO_DC_I2C_GO
);
717 for (j
= 0; j
< 200; j
++) {
719 tmp
= RREG32(AVIVO_DC_I2C_STATUS1
);
720 if (tmp
& AVIVO_DC_I2C_GO
)
722 tmp
= RREG32(AVIVO_DC_I2C_STATUS1
);
723 if (tmp
& AVIVO_DC_I2C_DONE
)
726 DRM_DEBUG("i2c read error 0x%08x\n", tmp
);
727 WREG32(AVIVO_DC_I2C_RESET
, AVIVO_DC_I2C_ABORT
);
732 for (j
= 0; j
< current_count
; j
++)
733 p
->buf
[buffer_offset
+ j
] = RREG32(AVIVO_DC_I2C_DATA
) & 0xff;
734 remaining
-= current_count
;
735 buffer_offset
+= current_count
;
742 current_count
= remaining
;
743 WREG32(AVIVO_DC_I2C_STATUS1
, (AVIVO_DC_I2C_DONE
|
746 WREG32(AVIVO_DC_I2C_RESET
, AVIVO_DC_I2C_SOFT_RESET
);
748 WREG32(AVIVO_DC_I2C_RESET
, 0);
750 WREG32(AVIVO_DC_I2C_DATA
, (p
->addr
<< 1) & 0xff);
751 for (j
= 0; j
< current_count
; j
++)
752 WREG32(AVIVO_DC_I2C_DATA
, p
->buf
[buffer_offset
+ j
]);
754 WREG32(AVIVO_DC_I2C_CONTROL3
, AVIVO_DC_I2C_TIME_LIMIT(48));
755 WREG32(AVIVO_DC_I2C_CONTROL2
, (AVIVO_DC_I2C_ADDR_COUNT(1) |
756 AVIVO_DC_I2C_DATA_COUNT(current_count
) |
758 WREG32(AVIVO_DC_I2C_CONTROL1
, reg
);
759 WREG32(AVIVO_DC_I2C_STATUS1
, AVIVO_DC_I2C_GO
);
760 for (j
= 0; j
< 200; j
++) {
762 tmp
= RREG32(AVIVO_DC_I2C_STATUS1
);
763 if (tmp
& AVIVO_DC_I2C_GO
)
765 tmp
= RREG32(AVIVO_DC_I2C_STATUS1
);
766 if (tmp
& AVIVO_DC_I2C_DONE
)
769 DRM_DEBUG("i2c write error 0x%08x\n", tmp
);
770 WREG32(AVIVO_DC_I2C_RESET
, AVIVO_DC_I2C_ABORT
);
775 remaining
-= current_count
;
776 buffer_offset
+= current_count
;
782 WREG32(AVIVO_DC_I2C_STATUS1
, (AVIVO_DC_I2C_DONE
|
785 WREG32(AVIVO_DC_I2C_RESET
, AVIVO_DC_I2C_SOFT_RESET
);
787 WREG32(AVIVO_DC_I2C_RESET
, 0);
789 WREG32(AVIVO_DC_I2C_ARBITRATION
, AVIVO_DC_I2C_SW_DONE_USING_I2C
);
790 WREG32(AVIVO_DC_I2C_CONTROL1
, saved1
);
791 WREG32(0x494, saved2
);
792 tmp
= RREG32(RADEON_BIOS_6_SCRATCH
);
793 tmp
&= ~ATOM_S6_HW_I2C_BUSY_STATE
;
794 WREG32(RADEON_BIOS_6_SCRATCH
, tmp
);
796 mutex_unlock(&rdev
->pm
.mutex
);
797 mutex_unlock(&rdev
->dc_hw_i2c_mutex
);
802 static int radeon_hw_i2c_xfer(struct i2c_adapter
*i2c_adap
,
803 struct i2c_msg
*msgs
, int num
)
805 struct radeon_i2c_chan
*i2c
= i2c_get_adapdata(i2c_adap
);
806 struct radeon_device
*rdev
= i2c
->dev
->dev_private
;
807 struct radeon_i2c_bus_rec
*rec
= &i2c
->rec
;
810 switch (rdev
->family
) {
829 ret
= r100_hw_i2c_xfer(i2c_adap
, msgs
, num
);
834 /* XXX fill in hw i2c implementation */
843 ret
= r100_hw_i2c_xfer(i2c_adap
, msgs
, num
);
845 ret
= r500_hw_i2c_xfer(i2c_adap
, msgs
, num
);
851 /* XXX fill in hw i2c implementation */
861 /* XXX fill in hw i2c implementation */
868 /* XXX fill in hw i2c implementation */
871 DRM_ERROR("i2c: unhandled radeon chip\n");
879 static u32
radeon_hw_i2c_func(struct i2c_adapter
*adap
)
881 return I2C_FUNC_I2C
| I2C_FUNC_SMBUS_EMUL
;
884 static const struct i2c_algorithm radeon_i2c_algo
= {
885 .master_xfer
= radeon_hw_i2c_xfer
,
886 .functionality
= radeon_hw_i2c_func
,
889 static const struct i2c_algorithm radeon_atom_i2c_algo
= {
890 .master_xfer
= radeon_atom_hw_i2c_xfer
,
891 .functionality
= radeon_atom_hw_i2c_func
,
894 struct radeon_i2c_chan
*radeon_i2c_create(struct drm_device
*dev
,
895 struct radeon_i2c_bus_rec
*rec
,
898 struct radeon_device
*rdev
= dev
->dev_private
;
899 struct radeon_i2c_chan
*i2c
;
902 i2c
= kzalloc(sizeof(struct radeon_i2c_chan
), GFP_KERNEL
);
907 i2c
->adapter
.owner
= THIS_MODULE
;
908 i2c
->adapter
.class = I2C_CLASS_DDC
;
909 i2c
->adapter
.dev
.parent
= &dev
->pdev
->dev
;
911 i2c_set_adapdata(&i2c
->adapter
, i2c
);
915 ((rdev
->family
<= CHIP_RS480
) ||
916 ((rdev
->family
>= CHIP_RV515
) && (rdev
->family
<= CHIP_R580
))))) {
917 /* set the radeon hw i2c adapter */
918 snprintf(i2c
->adapter
.name
, sizeof(i2c
->adapter
.name
),
919 "Radeon i2c hw bus %s", name
);
920 i2c
->adapter
.algo
= &radeon_i2c_algo
;
921 ret
= i2c_add_adapter(&i2c
->adapter
);
923 DRM_ERROR("Failed to register hw i2c %s\n", name
);
926 } else if (rec
->hw_capable
&&
928 ASIC_IS_DCE3(rdev
)) {
929 /* hw i2c using atom */
930 snprintf(i2c
->adapter
.name
, sizeof(i2c
->adapter
.name
),
931 "Radeon i2c hw bus %s", name
);
932 i2c
->adapter
.algo
= &radeon_atom_i2c_algo
;
933 ret
= i2c_add_adapter(&i2c
->adapter
);
935 DRM_ERROR("Failed to register hw i2c %s\n", name
);
939 /* set the radeon bit adapter */
940 snprintf(i2c
->adapter
.name
, sizeof(i2c
->adapter
.name
),
941 "Radeon i2c bit bus %s", name
);
942 i2c
->adapter
.algo_data
= &i2c
->algo
.bit
;
943 i2c
->algo
.bit
.pre_xfer
= pre_xfer
;
944 i2c
->algo
.bit
.post_xfer
= post_xfer
;
945 i2c
->algo
.bit
.setsda
= set_data
;
946 i2c
->algo
.bit
.setscl
= set_clock
;
947 i2c
->algo
.bit
.getsda
= get_data
;
948 i2c
->algo
.bit
.getscl
= get_clock
;
949 i2c
->algo
.bit
.udelay
= 10;
950 i2c
->algo
.bit
.timeout
= usecs_to_jiffies(2200); /* from VESA */
951 i2c
->algo
.bit
.data
= i2c
;
952 ret
= i2c_bit_add_bus(&i2c
->adapter
);
954 DRM_ERROR("Failed to register bit i2c %s\n", name
);
966 struct radeon_i2c_chan
*radeon_i2c_create_dp(struct drm_device
*dev
,
967 struct radeon_i2c_bus_rec
*rec
,
970 struct radeon_i2c_chan
*i2c
;
973 i2c
= kzalloc(sizeof(struct radeon_i2c_chan
), GFP_KERNEL
);
978 i2c
->adapter
.owner
= THIS_MODULE
;
979 i2c
->adapter
.class = I2C_CLASS_DDC
;
980 i2c
->adapter
.dev
.parent
= &dev
->pdev
->dev
;
982 snprintf(i2c
->adapter
.name
, sizeof(i2c
->adapter
.name
),
983 "Radeon aux bus %s", name
);
984 i2c_set_adapdata(&i2c
->adapter
, i2c
);
985 i2c
->adapter
.algo_data
= &i2c
->algo
.dp
;
986 i2c
->algo
.dp
.aux_ch
= radeon_dp_i2c_aux_ch
;
987 i2c
->algo
.dp
.address
= 0;
988 ret
= i2c_dp_aux_add_bus(&i2c
->adapter
);
990 DRM_INFO("Failed to register i2c %s\n", name
);
1001 void radeon_i2c_destroy(struct radeon_i2c_chan
*i2c
)
1005 i2c_del_adapter(&i2c
->adapter
);
1009 /* Add the default buses */
1010 void radeon_i2c_init(struct radeon_device
*rdev
)
1012 if (rdev
->is_atom_bios
)
1013 radeon_atombios_i2c_init(rdev
);
1015 radeon_combios_i2c_init(rdev
);
1018 /* remove all the buses */
1019 void radeon_i2c_fini(struct radeon_device
*rdev
)
1023 for (i
= 0; i
< RADEON_MAX_I2C_BUS
; i
++) {
1024 if (rdev
->i2c_bus
[i
]) {
1025 radeon_i2c_destroy(rdev
->i2c_bus
[i
]);
1026 rdev
->i2c_bus
[i
] = NULL
;
1031 /* Add additional buses */
1032 void radeon_i2c_add(struct radeon_device
*rdev
,
1033 struct radeon_i2c_bus_rec
*rec
,
1036 struct drm_device
*dev
= rdev
->ddev
;
1039 for (i
= 0; i
< RADEON_MAX_I2C_BUS
; i
++) {
1040 if (!rdev
->i2c_bus
[i
]) {
1041 rdev
->i2c_bus
[i
] = radeon_i2c_create(dev
, rec
, name
);
1047 /* looks up bus based on id */
1048 struct radeon_i2c_chan
*radeon_i2c_lookup(struct radeon_device
*rdev
,
1049 struct radeon_i2c_bus_rec
*i2c_bus
)
1053 for (i
= 0; i
< RADEON_MAX_I2C_BUS
; i
++) {
1054 if (rdev
->i2c_bus
[i
] &&
1055 (rdev
->i2c_bus
[i
]->rec
.i2c_id
== i2c_bus
->i2c_id
)) {
1056 return rdev
->i2c_bus
[i
];
1062 struct drm_encoder
*radeon_best_encoder(struct drm_connector
*connector
)
1067 void radeon_i2c_get_byte(struct radeon_i2c_chan
*i2c_bus
,
1074 struct i2c_msg msgs
[] = {
1092 if (i2c_transfer(&i2c_bus
->adapter
, msgs
, 2) == 2) {
1094 DRM_DEBUG("val = 0x%02x\n", *val
);
1096 DRM_DEBUG("i2c 0x%02x 0x%02x read failed\n",
1101 void radeon_i2c_put_byte(struct radeon_i2c_chan
*i2c_bus
,
1107 struct i2c_msg msg
= {
1117 if (i2c_transfer(&i2c_bus
->adapter
, &msg
, 1) != 1)
1118 DRM_DEBUG("i2c 0x%02x 0x%02x write failed\n",
1122 /* ddc router switching */
1123 void radeon_router_select_ddc_port(struct radeon_connector
*radeon_connector
)
1127 if (!radeon_connector
->router
.ddc_valid
)
1130 if (!radeon_connector
->router_bus
)
1133 radeon_i2c_get_byte(radeon_connector
->router_bus
,
1134 radeon_connector
->router
.i2c_addr
,
1136 val
&= ~radeon_connector
->router
.ddc_mux_control_pin
;
1137 radeon_i2c_put_byte(radeon_connector
->router_bus
,
1138 radeon_connector
->router
.i2c_addr
,
1140 radeon_i2c_get_byte(radeon_connector
->router_bus
,
1141 radeon_connector
->router
.i2c_addr
,
1143 val
&= ~radeon_connector
->router
.ddc_mux_control_pin
;
1144 val
|= radeon_connector
->router
.ddc_mux_state
;
1145 radeon_i2c_put_byte(radeon_connector
->router_bus
,
1146 radeon_connector
->router
.i2c_addr
,
1150 /* clock/data router switching */
1151 void radeon_router_select_cd_port(struct radeon_connector
*radeon_connector
)
1155 if (!radeon_connector
->router
.cd_valid
)
1158 if (!radeon_connector
->router_bus
)
1161 radeon_i2c_get_byte(radeon_connector
->router_bus
,
1162 radeon_connector
->router
.i2c_addr
,
1164 val
&= ~radeon_connector
->router
.cd_mux_control_pin
;
1165 radeon_i2c_put_byte(radeon_connector
->router_bus
,
1166 radeon_connector
->router
.i2c_addr
,
1168 radeon_i2c_get_byte(radeon_connector
->router_bus
,
1169 radeon_connector
->router
.i2c_addr
,
1171 val
&= ~radeon_connector
->router
.cd_mux_control_pin
;
1172 val
|= radeon_connector
->router
.cd_mux_state
;
1173 radeon_i2c_put_byte(radeon_connector
->router_bus
,
1174 radeon_connector
->router
.i2c_addr
,