2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
29 #include "drm_sarea.h"
31 #include "radeon_drm.h"
33 #include <linux/vga_switcheroo.h>
34 #include <linux/slab.h>
36 int radeon_driver_unload_kms(struct drm_device
*dev
)
38 struct radeon_device
*rdev
= dev
->dev_private
;
42 radeon_modeset_fini(rdev
);
43 radeon_device_fini(rdev
);
45 dev
->dev_private
= NULL
;
49 int radeon_driver_load_kms(struct drm_device
*dev
, unsigned long flags
)
51 struct radeon_device
*rdev
;
54 rdev
= kzalloc(sizeof(struct radeon_device
), GFP_KERNEL
);
58 dev
->dev_private
= (void *)rdev
;
61 if (drm_device_is_agp(dev
)) {
62 flags
|= RADEON_IS_AGP
;
63 } else if (drm_device_is_pcie(dev
)) {
64 flags
|= RADEON_IS_PCIE
;
66 flags
|= RADEON_IS_PCI
;
69 /* radeon_device_init should report only fatal error
70 * like memory allocation failure or iomapping failure,
71 * or memory manager initialization failure, it must
72 * properly initialize the GPU MC controller and permit
75 r
= radeon_device_init(rdev
, dev
, dev
->pdev
, flags
);
77 dev_err(&dev
->pdev
->dev
, "Fatal error during GPU init\n");
81 /* Call ACPI methods */
82 acpi_status
= radeon_acpi_init(rdev
);
84 dev_dbg(&dev
->pdev
->dev
, "Error during ACPI methods call\n");
86 /* Again modeset_init should fail only on fatal error
87 * otherwise it should provide enough functionalities
90 r
= radeon_modeset_init(rdev
);
92 dev_err(&dev
->pdev
->dev
, "Fatal error during modeset init\n");
95 radeon_driver_unload_kms(dev
);
101 * Userspace get informations ioctl
103 int radeon_info_ioctl(struct drm_device
*dev
, void *data
, struct drm_file
*filp
)
105 struct radeon_device
*rdev
= dev
->dev_private
;
106 struct drm_radeon_info
*info
;
107 struct radeon_mode_info
*minfo
= &rdev
->mode_info
;
110 struct drm_crtc
*crtc
;
114 value_ptr
= (uint32_t *)((unsigned long)info
->value
);
115 if (DRM_COPY_FROM_USER(&value
, value_ptr
, sizeof(value
)))
118 switch (info
->request
) {
119 case RADEON_INFO_DEVICE_ID
:
120 value
= dev
->pci_device
;
122 case RADEON_INFO_NUM_GB_PIPES
:
123 value
= rdev
->num_gb_pipes
;
125 case RADEON_INFO_NUM_Z_PIPES
:
126 value
= rdev
->num_z_pipes
;
128 case RADEON_INFO_ACCEL_WORKING
:
129 /* xf86-video-ati 6.13.0 relies on this being false for evergreen */
130 if ((rdev
->family
>= CHIP_CEDAR
) && (rdev
->family
<= CHIP_HEMLOCK
))
133 value
= rdev
->accel_working
;
135 case RADEON_INFO_CRTC_FROM_ID
:
136 for (i
= 0, found
= 0; i
< rdev
->num_crtc
; i
++) {
137 crtc
= (struct drm_crtc
*)minfo
->crtcs
[i
];
138 if (crtc
&& crtc
->base
.id
== value
) {
139 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(crtc
);
140 value
= radeon_crtc
->crtc_id
;
146 DRM_DEBUG_KMS("unknown crtc id %d\n", value
);
150 case RADEON_INFO_ACCEL_WORKING2
:
151 value
= rdev
->accel_working
;
153 case RADEON_INFO_TILING_CONFIG
:
154 if (rdev
->family
>= CHIP_CEDAR
)
155 value
= rdev
->config
.evergreen
.tile_config
;
156 else if (rdev
->family
>= CHIP_RV770
)
157 value
= rdev
->config
.rv770
.tile_config
;
158 else if (rdev
->family
>= CHIP_R600
)
159 value
= rdev
->config
.r600
.tile_config
;
161 DRM_DEBUG_KMS("tiling config is r6xx+ only!\n");
164 case RADEON_INFO_WANT_HYPERZ
:
165 /* The "value" here is both an input and output parameter.
166 * If the input value is 1, filp requests hyper-z access.
167 * If the input value is 0, filp revokes its hyper-z access.
169 * When returning, the value is 1 if filp owns hyper-z access,
172 DRM_DEBUG_KMS("WANT_HYPERZ: invalid value %d\n", value
);
175 mutex_lock(&dev
->struct_mutex
);
178 if (!rdev
->hyperz_filp
)
179 rdev
->hyperz_filp
= filp
;
180 } else if (value
== 0) {
181 /* revokes hyper-z */
182 if (rdev
->hyperz_filp
== filp
)
183 rdev
->hyperz_filp
= NULL
;
185 value
= rdev
->hyperz_filp
== filp
? 1 : 0;
186 mutex_unlock(&dev
->struct_mutex
);
189 DRM_DEBUG_KMS("Invalid request %d\n", info
->request
);
192 if (DRM_COPY_TO_USER(value_ptr
, &value
, sizeof(uint32_t))) {
193 DRM_ERROR("copy_to_user\n");
201 * Outdated mess for old drm with Xorg being in charge (void function now).
203 int radeon_driver_firstopen_kms(struct drm_device
*dev
)
209 void radeon_driver_lastclose_kms(struct drm_device
*dev
)
211 vga_switcheroo_process_delayed_switch();
214 int radeon_driver_open_kms(struct drm_device
*dev
, struct drm_file
*file_priv
)
219 void radeon_driver_postclose_kms(struct drm_device
*dev
,
220 struct drm_file
*file_priv
)
224 void radeon_driver_preclose_kms(struct drm_device
*dev
,
225 struct drm_file
*file_priv
)
227 struct radeon_device
*rdev
= dev
->dev_private
;
228 if (rdev
->hyperz_filp
== file_priv
)
229 rdev
->hyperz_filp
= NULL
;
233 * VBlank related functions.
235 u32
radeon_get_vblank_counter_kms(struct drm_device
*dev
, int crtc
)
237 struct radeon_device
*rdev
= dev
->dev_private
;
239 if (crtc
< 0 || crtc
>= rdev
->num_crtc
) {
240 DRM_ERROR("Invalid crtc %d\n", crtc
);
244 return radeon_get_vblank_counter(rdev
, crtc
);
247 int radeon_enable_vblank_kms(struct drm_device
*dev
, int crtc
)
249 struct radeon_device
*rdev
= dev
->dev_private
;
251 if (crtc
< 0 || crtc
>= rdev
->num_crtc
) {
252 DRM_ERROR("Invalid crtc %d\n", crtc
);
256 rdev
->irq
.crtc_vblank_int
[crtc
] = true;
258 return radeon_irq_set(rdev
);
261 void radeon_disable_vblank_kms(struct drm_device
*dev
, int crtc
)
263 struct radeon_device
*rdev
= dev
->dev_private
;
265 if (crtc
< 0 || crtc
>= rdev
->num_crtc
) {
266 DRM_ERROR("Invalid crtc %d\n", crtc
);
270 rdev
->irq
.crtc_vblank_int
[crtc
] = false;
272 radeon_irq_set(rdev
);
279 int radeon_dma_ioctl_kms(struct drm_device
*dev
, void *data
,
280 struct drm_file
*file_priv
)
282 /* Not valid in KMS. */
286 #define KMS_INVALID_IOCTL(name) \
287 int name(struct drm_device *dev, void *data, struct drm_file *file_priv)\
289 DRM_ERROR("invalid ioctl with kms %s\n", __func__); \
294 * All these ioctls are invalid in kms world.
296 KMS_INVALID_IOCTL(radeon_cp_init_kms
)
297 KMS_INVALID_IOCTL(radeon_cp_start_kms
)
298 KMS_INVALID_IOCTL(radeon_cp_stop_kms
)
299 KMS_INVALID_IOCTL(radeon_cp_reset_kms
)
300 KMS_INVALID_IOCTL(radeon_cp_idle_kms
)
301 KMS_INVALID_IOCTL(radeon_cp_resume_kms
)
302 KMS_INVALID_IOCTL(radeon_engine_reset_kms
)
303 KMS_INVALID_IOCTL(radeon_fullscreen_kms
)
304 KMS_INVALID_IOCTL(radeon_cp_swap_kms
)
305 KMS_INVALID_IOCTL(radeon_cp_clear_kms
)
306 KMS_INVALID_IOCTL(radeon_cp_vertex_kms
)
307 KMS_INVALID_IOCTL(radeon_cp_indices_kms
)
308 KMS_INVALID_IOCTL(radeon_cp_texture_kms
)
309 KMS_INVALID_IOCTL(radeon_cp_stipple_kms
)
310 KMS_INVALID_IOCTL(radeon_cp_indirect_kms
)
311 KMS_INVALID_IOCTL(radeon_cp_vertex2_kms
)
312 KMS_INVALID_IOCTL(radeon_cp_cmdbuf_kms
)
313 KMS_INVALID_IOCTL(radeon_cp_getparam_kms
)
314 KMS_INVALID_IOCTL(radeon_cp_flip_kms
)
315 KMS_INVALID_IOCTL(radeon_mem_alloc_kms
)
316 KMS_INVALID_IOCTL(radeon_mem_free_kms
)
317 KMS_INVALID_IOCTL(radeon_mem_init_heap_kms
)
318 KMS_INVALID_IOCTL(radeon_irq_emit_kms
)
319 KMS_INVALID_IOCTL(radeon_irq_wait_kms
)
320 KMS_INVALID_IOCTL(radeon_cp_setparam_kms
)
321 KMS_INVALID_IOCTL(radeon_surface_alloc_kms
)
322 KMS_INVALID_IOCTL(radeon_surface_free_kms
)
325 struct drm_ioctl_desc radeon_ioctls_kms
[] = {
326 DRM_IOCTL_DEF_DRV(RADEON_CP_INIT
, radeon_cp_init_kms
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
327 DRM_IOCTL_DEF_DRV(RADEON_CP_START
, radeon_cp_start_kms
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
328 DRM_IOCTL_DEF_DRV(RADEON_CP_STOP
, radeon_cp_stop_kms
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
329 DRM_IOCTL_DEF_DRV(RADEON_CP_RESET
, radeon_cp_reset_kms
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
330 DRM_IOCTL_DEF_DRV(RADEON_CP_IDLE
, radeon_cp_idle_kms
, DRM_AUTH
),
331 DRM_IOCTL_DEF_DRV(RADEON_CP_RESUME
, radeon_cp_resume_kms
, DRM_AUTH
),
332 DRM_IOCTL_DEF_DRV(RADEON_RESET
, radeon_engine_reset_kms
, DRM_AUTH
),
333 DRM_IOCTL_DEF_DRV(RADEON_FULLSCREEN
, radeon_fullscreen_kms
, DRM_AUTH
),
334 DRM_IOCTL_DEF_DRV(RADEON_SWAP
, radeon_cp_swap_kms
, DRM_AUTH
),
335 DRM_IOCTL_DEF_DRV(RADEON_CLEAR
, radeon_cp_clear_kms
, DRM_AUTH
),
336 DRM_IOCTL_DEF_DRV(RADEON_VERTEX
, radeon_cp_vertex_kms
, DRM_AUTH
),
337 DRM_IOCTL_DEF_DRV(RADEON_INDICES
, radeon_cp_indices_kms
, DRM_AUTH
),
338 DRM_IOCTL_DEF_DRV(RADEON_TEXTURE
, radeon_cp_texture_kms
, DRM_AUTH
),
339 DRM_IOCTL_DEF_DRV(RADEON_STIPPLE
, radeon_cp_stipple_kms
, DRM_AUTH
),
340 DRM_IOCTL_DEF_DRV(RADEON_INDIRECT
, radeon_cp_indirect_kms
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
341 DRM_IOCTL_DEF_DRV(RADEON_VERTEX2
, radeon_cp_vertex2_kms
, DRM_AUTH
),
342 DRM_IOCTL_DEF_DRV(RADEON_CMDBUF
, radeon_cp_cmdbuf_kms
, DRM_AUTH
),
343 DRM_IOCTL_DEF_DRV(RADEON_GETPARAM
, radeon_cp_getparam_kms
, DRM_AUTH
),
344 DRM_IOCTL_DEF_DRV(RADEON_FLIP
, radeon_cp_flip_kms
, DRM_AUTH
),
345 DRM_IOCTL_DEF_DRV(RADEON_ALLOC
, radeon_mem_alloc_kms
, DRM_AUTH
),
346 DRM_IOCTL_DEF_DRV(RADEON_FREE
, radeon_mem_free_kms
, DRM_AUTH
),
347 DRM_IOCTL_DEF_DRV(RADEON_INIT_HEAP
, radeon_mem_init_heap_kms
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
348 DRM_IOCTL_DEF_DRV(RADEON_IRQ_EMIT
, radeon_irq_emit_kms
, DRM_AUTH
),
349 DRM_IOCTL_DEF_DRV(RADEON_IRQ_WAIT
, radeon_irq_wait_kms
, DRM_AUTH
),
350 DRM_IOCTL_DEF_DRV(RADEON_SETPARAM
, radeon_cp_setparam_kms
, DRM_AUTH
),
351 DRM_IOCTL_DEF_DRV(RADEON_SURF_ALLOC
, radeon_surface_alloc_kms
, DRM_AUTH
),
352 DRM_IOCTL_DEF_DRV(RADEON_SURF_FREE
, radeon_surface_free_kms
, DRM_AUTH
),
354 DRM_IOCTL_DEF_DRV(RADEON_GEM_INFO
, radeon_gem_info_ioctl
, DRM_AUTH
|DRM_UNLOCKED
),
355 DRM_IOCTL_DEF_DRV(RADEON_GEM_CREATE
, radeon_gem_create_ioctl
, DRM_AUTH
|DRM_UNLOCKED
),
356 DRM_IOCTL_DEF_DRV(RADEON_GEM_MMAP
, radeon_gem_mmap_ioctl
, DRM_AUTH
|DRM_UNLOCKED
),
357 DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_DOMAIN
, radeon_gem_set_domain_ioctl
, DRM_AUTH
|DRM_UNLOCKED
),
358 DRM_IOCTL_DEF_DRV(RADEON_GEM_PREAD
, radeon_gem_pread_ioctl
, DRM_AUTH
|DRM_UNLOCKED
),
359 DRM_IOCTL_DEF_DRV(RADEON_GEM_PWRITE
, radeon_gem_pwrite_ioctl
, DRM_AUTH
|DRM_UNLOCKED
),
360 DRM_IOCTL_DEF_DRV(RADEON_GEM_WAIT_IDLE
, radeon_gem_wait_idle_ioctl
, DRM_AUTH
|DRM_UNLOCKED
),
361 DRM_IOCTL_DEF_DRV(RADEON_CS
, radeon_cs_ioctl
, DRM_AUTH
|DRM_UNLOCKED
),
362 DRM_IOCTL_DEF_DRV(RADEON_INFO
, radeon_info_ioctl
, DRM_AUTH
|DRM_UNLOCKED
),
363 DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_TILING
, radeon_gem_set_tiling_ioctl
, DRM_AUTH
|DRM_UNLOCKED
),
364 DRM_IOCTL_DEF_DRV(RADEON_GEM_GET_TILING
, radeon_gem_get_tiling_ioctl
, DRM_AUTH
|DRM_UNLOCKED
),
365 DRM_IOCTL_DEF_DRV(RADEON_GEM_BUSY
, radeon_gem_busy_ioctl
, DRM_AUTH
|DRM_UNLOCKED
),
367 int radeon_max_kms_ioctl
= DRM_ARRAY_SIZE(radeon_ioctls_kms
);