2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
30 #include <drm/radeon_drm.h>
31 #include "radeon_asic.h"
33 #include <linux/vga_switcheroo.h>
34 #include <linux/slab.h>
37 * radeon_driver_unload_kms - Main unload function for KMS.
39 * @dev: drm dev pointer
41 * This is the main unload function for KMS (all asics).
42 * It calls radeon_modeset_fini() to tear down the
43 * displays, and radeon_device_fini() to tear down
44 * the rest of the device (CP, writeback, etc.).
45 * Returns 0 on success.
47 int radeon_driver_unload_kms(struct drm_device
*dev
)
49 struct radeon_device
*rdev
= dev
->dev_private
;
53 radeon_acpi_fini(rdev
);
54 radeon_modeset_fini(rdev
);
55 radeon_device_fini(rdev
);
57 dev
->dev_private
= NULL
;
62 * radeon_driver_load_kms - Main load function for KMS.
64 * @dev: drm dev pointer
65 * @flags: device flags
67 * This is the main load function for KMS (all asics).
68 * It calls radeon_device_init() to set up the non-display
69 * parts of the chip (asic init, CP, writeback, etc.), and
70 * radeon_modeset_init() to set up the display parts
71 * (crtcs, encoders, hotplug detect, etc.).
72 * Returns 0 on success, error on failure.
74 int radeon_driver_load_kms(struct drm_device
*dev
, unsigned long flags
)
76 struct radeon_device
*rdev
;
79 rdev
= kzalloc(sizeof(struct radeon_device
), GFP_KERNEL
);
83 dev
->dev_private
= (void *)rdev
;
86 if (drm_pci_device_is_agp(dev
)) {
87 flags
|= RADEON_IS_AGP
;
88 } else if (pci_is_pcie(dev
->pdev
)) {
89 flags
|= RADEON_IS_PCIE
;
91 flags
|= RADEON_IS_PCI
;
94 /* radeon_device_init should report only fatal error
95 * like memory allocation failure or iomapping failure,
96 * or memory manager initialization failure, it must
97 * properly initialize the GPU MC controller and permit
100 r
= radeon_device_init(rdev
, dev
, dev
->pdev
, flags
);
102 dev_err(&dev
->pdev
->dev
, "Fatal error during GPU init\n");
106 /* Again modeset_init should fail only on fatal error
107 * otherwise it should provide enough functionalities
108 * for shadowfb to run
110 r
= radeon_modeset_init(rdev
);
112 dev_err(&dev
->pdev
->dev
, "Fatal error during modeset init\n");
114 /* Call ACPI methods: require modeset init
115 * but failure is not fatal
118 acpi_status
= radeon_acpi_init(rdev
);
120 dev_dbg(&dev
->pdev
->dev
,
121 "Error during ACPI methods call\n");
126 radeon_driver_unload_kms(dev
);
131 * radeon_set_filp_rights - Set filp right.
133 * @dev: drm dev pointer
138 * Sets the filp rights for the device (all asics).
140 static void radeon_set_filp_rights(struct drm_device
*dev
,
141 struct drm_file
**owner
,
142 struct drm_file
*applier
,
145 mutex_lock(&dev
->struct_mutex
);
150 } else if (*value
== 0) {
152 if (*owner
== applier
)
155 *value
= *owner
== applier
? 1 : 0;
156 mutex_unlock(&dev
->struct_mutex
);
160 * Userspace get information ioctl
163 * radeon_info_ioctl - answer a device specific request.
165 * @rdev: radeon device pointer
166 * @data: request object
169 * This function is used to pass device specific parameters to the userspace
170 * drivers. Examples include: pci device id, pipeline parms, tiling params,
172 * Returns 0 on success, -EINVAL on failure.
174 int radeon_info_ioctl(struct drm_device
*dev
, void *data
, struct drm_file
*filp
)
176 struct radeon_device
*rdev
= dev
->dev_private
;
177 struct drm_radeon_info
*info
= data
;
178 struct radeon_mode_info
*minfo
= &rdev
->mode_info
;
179 uint32_t value
, *value_ptr
;
180 uint64_t value64
, *value_ptr64
;
181 struct drm_crtc
*crtc
;
184 /* TIMESTAMP is a 64-bit value, needs special handling. */
185 if (info
->request
== RADEON_INFO_TIMESTAMP
) {
186 if (rdev
->family
>= CHIP_R600
) {
187 value_ptr64
= (uint64_t*)((unsigned long)info
->value
);
188 if (rdev
->family
>= CHIP_TAHITI
) {
189 value64
= si_get_gpu_clock(rdev
);
191 value64
= r600_get_gpu_clock(rdev
);
194 if (DRM_COPY_TO_USER(value_ptr64
, &value64
, sizeof(value64
))) {
195 DRM_ERROR("copy_to_user %s:%u\n", __func__
, __LINE__
);
200 DRM_DEBUG_KMS("timestamp is r6xx+ only!\n");
205 value_ptr
= (uint32_t *)((unsigned long)info
->value
);
206 if (DRM_COPY_FROM_USER(&value
, value_ptr
, sizeof(value
))) {
207 DRM_ERROR("copy_from_user %s:%u\n", __func__
, __LINE__
);
211 switch (info
->request
) {
212 case RADEON_INFO_DEVICE_ID
:
213 value
= dev
->pci_device
;
215 case RADEON_INFO_NUM_GB_PIPES
:
216 value
= rdev
->num_gb_pipes
;
218 case RADEON_INFO_NUM_Z_PIPES
:
219 value
= rdev
->num_z_pipes
;
221 case RADEON_INFO_ACCEL_WORKING
:
222 /* xf86-video-ati 6.13.0 relies on this being false for evergreen */
223 if ((rdev
->family
>= CHIP_CEDAR
) && (rdev
->family
<= CHIP_HEMLOCK
))
226 value
= rdev
->accel_working
;
228 case RADEON_INFO_CRTC_FROM_ID
:
229 for (i
= 0, found
= 0; i
< rdev
->num_crtc
; i
++) {
230 crtc
= (struct drm_crtc
*)minfo
->crtcs
[i
];
231 if (crtc
&& crtc
->base
.id
== value
) {
232 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(crtc
);
233 value
= radeon_crtc
->crtc_id
;
239 DRM_DEBUG_KMS("unknown crtc id %d\n", value
);
243 case RADEON_INFO_ACCEL_WORKING2
:
244 value
= rdev
->accel_working
;
246 case RADEON_INFO_TILING_CONFIG
:
247 if (rdev
->family
>= CHIP_TAHITI
)
248 value
= rdev
->config
.si
.tile_config
;
249 else if (rdev
->family
>= CHIP_CAYMAN
)
250 value
= rdev
->config
.cayman
.tile_config
;
251 else if (rdev
->family
>= CHIP_CEDAR
)
252 value
= rdev
->config
.evergreen
.tile_config
;
253 else if (rdev
->family
>= CHIP_RV770
)
254 value
= rdev
->config
.rv770
.tile_config
;
255 else if (rdev
->family
>= CHIP_R600
)
256 value
= rdev
->config
.r600
.tile_config
;
258 DRM_DEBUG_KMS("tiling config is r6xx+ only!\n");
262 case RADEON_INFO_WANT_HYPERZ
:
263 /* The "value" here is both an input and output parameter.
264 * If the input value is 1, filp requests hyper-z access.
265 * If the input value is 0, filp revokes its hyper-z access.
267 * When returning, the value is 1 if filp owns hyper-z access,
270 DRM_DEBUG_KMS("WANT_HYPERZ: invalid value %d\n", value
);
273 radeon_set_filp_rights(dev
, &rdev
->hyperz_filp
, filp
, &value
);
275 case RADEON_INFO_WANT_CMASK
:
276 /* The same logic as Hyper-Z. */
278 DRM_DEBUG_KMS("WANT_CMASK: invalid value %d\n", value
);
281 radeon_set_filp_rights(dev
, &rdev
->cmask_filp
, filp
, &value
);
283 case RADEON_INFO_CLOCK_CRYSTAL_FREQ
:
284 /* return clock value in KHz */
285 value
= rdev
->clock
.spll
.reference_freq
* 10;
287 case RADEON_INFO_NUM_BACKENDS
:
288 if (rdev
->family
>= CHIP_TAHITI
)
289 value
= rdev
->config
.si
.max_backends_per_se
*
290 rdev
->config
.si
.max_shader_engines
;
291 else if (rdev
->family
>= CHIP_CAYMAN
)
292 value
= rdev
->config
.cayman
.max_backends_per_se
*
293 rdev
->config
.cayman
.max_shader_engines
;
294 else if (rdev
->family
>= CHIP_CEDAR
)
295 value
= rdev
->config
.evergreen
.max_backends
;
296 else if (rdev
->family
>= CHIP_RV770
)
297 value
= rdev
->config
.rv770
.max_backends
;
298 else if (rdev
->family
>= CHIP_R600
)
299 value
= rdev
->config
.r600
.max_backends
;
304 case RADEON_INFO_NUM_TILE_PIPES
:
305 if (rdev
->family
>= CHIP_TAHITI
)
306 value
= rdev
->config
.si
.max_tile_pipes
;
307 else if (rdev
->family
>= CHIP_CAYMAN
)
308 value
= rdev
->config
.cayman
.max_tile_pipes
;
309 else if (rdev
->family
>= CHIP_CEDAR
)
310 value
= rdev
->config
.evergreen
.max_tile_pipes
;
311 else if (rdev
->family
>= CHIP_RV770
)
312 value
= rdev
->config
.rv770
.max_tile_pipes
;
313 else if (rdev
->family
>= CHIP_R600
)
314 value
= rdev
->config
.r600
.max_tile_pipes
;
319 case RADEON_INFO_FUSION_GART_WORKING
:
322 case RADEON_INFO_BACKEND_MAP
:
323 if (rdev
->family
>= CHIP_TAHITI
)
324 value
= rdev
->config
.si
.backend_map
;
325 else if (rdev
->family
>= CHIP_CAYMAN
)
326 value
= rdev
->config
.cayman
.backend_map
;
327 else if (rdev
->family
>= CHIP_CEDAR
)
328 value
= rdev
->config
.evergreen
.backend_map
;
329 else if (rdev
->family
>= CHIP_RV770
)
330 value
= rdev
->config
.rv770
.backend_map
;
331 else if (rdev
->family
>= CHIP_R600
)
332 value
= rdev
->config
.r600
.backend_map
;
337 case RADEON_INFO_VA_START
:
338 /* this is where we report if vm is supported or not */
339 if (rdev
->family
< CHIP_CAYMAN
)
341 value
= RADEON_VA_RESERVED_SIZE
;
343 case RADEON_INFO_IB_VM_MAX_SIZE
:
344 /* this is where we report if vm is supported or not */
345 if (rdev
->family
< CHIP_CAYMAN
)
347 value
= RADEON_IB_VM_MAX_SIZE
;
349 case RADEON_INFO_MAX_PIPES
:
350 if (rdev
->family
>= CHIP_TAHITI
)
351 value
= rdev
->config
.si
.max_cu_per_sh
;
352 else if (rdev
->family
>= CHIP_CAYMAN
)
353 value
= rdev
->config
.cayman
.max_pipes_per_simd
;
354 else if (rdev
->family
>= CHIP_CEDAR
)
355 value
= rdev
->config
.evergreen
.max_pipes
;
356 else if (rdev
->family
>= CHIP_RV770
)
357 value
= rdev
->config
.rv770
.max_pipes
;
358 else if (rdev
->family
>= CHIP_R600
)
359 value
= rdev
->config
.r600
.max_pipes
;
365 DRM_DEBUG_KMS("Invalid request %d\n", info
->request
);
368 if (DRM_COPY_TO_USER(value_ptr
, &value
, sizeof(uint32_t))) {
369 DRM_ERROR("copy_to_user %s:%u\n", __func__
, __LINE__
);
377 * Outdated mess for old drm with Xorg being in charge (void function now).
380 * radeon_driver_firstopen_kms - drm callback for first open
382 * @dev: drm dev pointer
384 * Nothing to be done for KMS (all asics).
385 * Returns 0 on success.
387 int radeon_driver_firstopen_kms(struct drm_device
*dev
)
393 * radeon_driver_firstopen_kms - drm callback for last close
395 * @dev: drm dev pointer
397 * Switch vga switcheroo state after last close (all asics).
399 void radeon_driver_lastclose_kms(struct drm_device
*dev
)
401 vga_switcheroo_process_delayed_switch();
405 * radeon_driver_open_kms - drm callback for open
407 * @dev: drm dev pointer
408 * @file_priv: drm file
410 * On device open, init vm on cayman+ (all asics).
411 * Returns 0 on success, error on failure.
413 int radeon_driver_open_kms(struct drm_device
*dev
, struct drm_file
*file_priv
)
415 struct radeon_device
*rdev
= dev
->dev_private
;
417 file_priv
->driver_priv
= NULL
;
419 /* new gpu have virtual address space support */
420 if (rdev
->family
>= CHIP_CAYMAN
) {
421 struct radeon_fpriv
*fpriv
;
422 struct radeon_bo_va
*bo_va
;
425 fpriv
= kzalloc(sizeof(*fpriv
), GFP_KERNEL
);
426 if (unlikely(!fpriv
)) {
430 radeon_vm_init(rdev
, &fpriv
->vm
);
432 /* map the ib pool buffer read only into
433 * virtual address space */
434 bo_va
= radeon_vm_bo_add(rdev
, &fpriv
->vm
,
435 rdev
->ring_tmp_bo
.bo
);
436 r
= radeon_vm_bo_set_addr(rdev
, bo_va
, RADEON_VA_IB_OFFSET
,
437 RADEON_VM_PAGE_READABLE
|
438 RADEON_VM_PAGE_SNOOPED
);
440 radeon_vm_fini(rdev
, &fpriv
->vm
);
445 file_priv
->driver_priv
= fpriv
;
451 * radeon_driver_postclose_kms - drm callback for post close
453 * @dev: drm dev pointer
454 * @file_priv: drm file
456 * On device post close, tear down vm on cayman+ (all asics).
458 void radeon_driver_postclose_kms(struct drm_device
*dev
,
459 struct drm_file
*file_priv
)
461 struct radeon_device
*rdev
= dev
->dev_private
;
463 /* new gpu have virtual address space support */
464 if (rdev
->family
>= CHIP_CAYMAN
&& file_priv
->driver_priv
) {
465 struct radeon_fpriv
*fpriv
= file_priv
->driver_priv
;
466 struct radeon_bo_va
*bo_va
;
469 r
= radeon_bo_reserve(rdev
->ring_tmp_bo
.bo
, false);
471 bo_va
= radeon_vm_bo_find(&fpriv
->vm
,
472 rdev
->ring_tmp_bo
.bo
);
474 radeon_vm_bo_rmv(rdev
, bo_va
);
475 radeon_bo_unreserve(rdev
->ring_tmp_bo
.bo
);
478 radeon_vm_fini(rdev
, &fpriv
->vm
);
480 file_priv
->driver_priv
= NULL
;
485 * radeon_driver_preclose_kms - drm callback for pre close
487 * @dev: drm dev pointer
488 * @file_priv: drm file
490 * On device pre close, tear down hyperz and cmask filps on r1xx-r5xx
493 void radeon_driver_preclose_kms(struct drm_device
*dev
,
494 struct drm_file
*file_priv
)
496 struct radeon_device
*rdev
= dev
->dev_private
;
497 if (rdev
->hyperz_filp
== file_priv
)
498 rdev
->hyperz_filp
= NULL
;
499 if (rdev
->cmask_filp
== file_priv
)
500 rdev
->cmask_filp
= NULL
;
504 * VBlank related functions.
507 * radeon_get_vblank_counter_kms - get frame count
509 * @dev: drm dev pointer
510 * @crtc: crtc to get the frame count from
512 * Gets the frame count on the requested crtc (all asics).
513 * Returns frame count on success, -EINVAL on failure.
515 u32
radeon_get_vblank_counter_kms(struct drm_device
*dev
, int crtc
)
517 struct radeon_device
*rdev
= dev
->dev_private
;
519 if (crtc
< 0 || crtc
>= rdev
->num_crtc
) {
520 DRM_ERROR("Invalid crtc %d\n", crtc
);
524 return radeon_get_vblank_counter(rdev
, crtc
);
528 * radeon_enable_vblank_kms - enable vblank interrupt
530 * @dev: drm dev pointer
531 * @crtc: crtc to enable vblank interrupt for
533 * Enable the interrupt on the requested crtc (all asics).
534 * Returns 0 on success, -EINVAL on failure.
536 int radeon_enable_vblank_kms(struct drm_device
*dev
, int crtc
)
538 struct radeon_device
*rdev
= dev
->dev_private
;
539 unsigned long irqflags
;
542 if (crtc
< 0 || crtc
>= rdev
->num_crtc
) {
543 DRM_ERROR("Invalid crtc %d\n", crtc
);
547 spin_lock_irqsave(&rdev
->irq
.lock
, irqflags
);
548 rdev
->irq
.crtc_vblank_int
[crtc
] = true;
549 r
= radeon_irq_set(rdev
);
550 spin_unlock_irqrestore(&rdev
->irq
.lock
, irqflags
);
555 * radeon_disable_vblank_kms - disable vblank interrupt
557 * @dev: drm dev pointer
558 * @crtc: crtc to disable vblank interrupt for
560 * Disable the interrupt on the requested crtc (all asics).
562 void radeon_disable_vblank_kms(struct drm_device
*dev
, int crtc
)
564 struct radeon_device
*rdev
= dev
->dev_private
;
565 unsigned long irqflags
;
567 if (crtc
< 0 || crtc
>= rdev
->num_crtc
) {
568 DRM_ERROR("Invalid crtc %d\n", crtc
);
572 spin_lock_irqsave(&rdev
->irq
.lock
, irqflags
);
573 rdev
->irq
.crtc_vblank_int
[crtc
] = false;
574 radeon_irq_set(rdev
);
575 spin_unlock_irqrestore(&rdev
->irq
.lock
, irqflags
);
579 * radeon_get_vblank_timestamp_kms - get vblank timestamp
581 * @dev: drm dev pointer
582 * @crtc: crtc to get the timestamp for
583 * @max_error: max error
584 * @vblank_time: time value
585 * @flags: flags passed to the driver
587 * Gets the timestamp on the requested crtc based on the
588 * scanout position. (all asics).
589 * Returns postive status flags on success, negative error on failure.
591 int radeon_get_vblank_timestamp_kms(struct drm_device
*dev
, int crtc
,
593 struct timeval
*vblank_time
,
596 struct drm_crtc
*drmcrtc
;
597 struct radeon_device
*rdev
= dev
->dev_private
;
599 if (crtc
< 0 || crtc
>= dev
->num_crtcs
) {
600 DRM_ERROR("Invalid crtc %d\n", crtc
);
604 /* Get associated drm_crtc: */
605 drmcrtc
= &rdev
->mode_info
.crtcs
[crtc
]->base
;
607 /* Helper routine in DRM core does all the work: */
608 return drm_calc_vbltimestamp_from_scanoutpos(dev
, crtc
, max_error
,
616 int radeon_dma_ioctl_kms(struct drm_device
*dev
, void *data
,
617 struct drm_file
*file_priv
)
619 /* Not valid in KMS. */
623 #define KMS_INVALID_IOCTL(name) \
624 int name(struct drm_device *dev, void *data, struct drm_file *file_priv)\
626 DRM_ERROR("invalid ioctl with kms %s\n", __func__); \
631 * All these ioctls are invalid in kms world.
633 KMS_INVALID_IOCTL(radeon_cp_init_kms
)
634 KMS_INVALID_IOCTL(radeon_cp_start_kms
)
635 KMS_INVALID_IOCTL(radeon_cp_stop_kms
)
636 KMS_INVALID_IOCTL(radeon_cp_reset_kms
)
637 KMS_INVALID_IOCTL(radeon_cp_idle_kms
)
638 KMS_INVALID_IOCTL(radeon_cp_resume_kms
)
639 KMS_INVALID_IOCTL(radeon_engine_reset_kms
)
640 KMS_INVALID_IOCTL(radeon_fullscreen_kms
)
641 KMS_INVALID_IOCTL(radeon_cp_swap_kms
)
642 KMS_INVALID_IOCTL(radeon_cp_clear_kms
)
643 KMS_INVALID_IOCTL(radeon_cp_vertex_kms
)
644 KMS_INVALID_IOCTL(radeon_cp_indices_kms
)
645 KMS_INVALID_IOCTL(radeon_cp_texture_kms
)
646 KMS_INVALID_IOCTL(radeon_cp_stipple_kms
)
647 KMS_INVALID_IOCTL(radeon_cp_indirect_kms
)
648 KMS_INVALID_IOCTL(radeon_cp_vertex2_kms
)
649 KMS_INVALID_IOCTL(radeon_cp_cmdbuf_kms
)
650 KMS_INVALID_IOCTL(radeon_cp_getparam_kms
)
651 KMS_INVALID_IOCTL(radeon_cp_flip_kms
)
652 KMS_INVALID_IOCTL(radeon_mem_alloc_kms
)
653 KMS_INVALID_IOCTL(radeon_mem_free_kms
)
654 KMS_INVALID_IOCTL(radeon_mem_init_heap_kms
)
655 KMS_INVALID_IOCTL(radeon_irq_emit_kms
)
656 KMS_INVALID_IOCTL(radeon_irq_wait_kms
)
657 KMS_INVALID_IOCTL(radeon_cp_setparam_kms
)
658 KMS_INVALID_IOCTL(radeon_surface_alloc_kms
)
659 KMS_INVALID_IOCTL(radeon_surface_free_kms
)
662 struct drm_ioctl_desc radeon_ioctls_kms
[] = {
663 DRM_IOCTL_DEF_DRV(RADEON_CP_INIT
, radeon_cp_init_kms
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
664 DRM_IOCTL_DEF_DRV(RADEON_CP_START
, radeon_cp_start_kms
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
665 DRM_IOCTL_DEF_DRV(RADEON_CP_STOP
, radeon_cp_stop_kms
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
666 DRM_IOCTL_DEF_DRV(RADEON_CP_RESET
, radeon_cp_reset_kms
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
667 DRM_IOCTL_DEF_DRV(RADEON_CP_IDLE
, radeon_cp_idle_kms
, DRM_AUTH
),
668 DRM_IOCTL_DEF_DRV(RADEON_CP_RESUME
, radeon_cp_resume_kms
, DRM_AUTH
),
669 DRM_IOCTL_DEF_DRV(RADEON_RESET
, radeon_engine_reset_kms
, DRM_AUTH
),
670 DRM_IOCTL_DEF_DRV(RADEON_FULLSCREEN
, radeon_fullscreen_kms
, DRM_AUTH
),
671 DRM_IOCTL_DEF_DRV(RADEON_SWAP
, radeon_cp_swap_kms
, DRM_AUTH
),
672 DRM_IOCTL_DEF_DRV(RADEON_CLEAR
, radeon_cp_clear_kms
, DRM_AUTH
),
673 DRM_IOCTL_DEF_DRV(RADEON_VERTEX
, radeon_cp_vertex_kms
, DRM_AUTH
),
674 DRM_IOCTL_DEF_DRV(RADEON_INDICES
, radeon_cp_indices_kms
, DRM_AUTH
),
675 DRM_IOCTL_DEF_DRV(RADEON_TEXTURE
, radeon_cp_texture_kms
, DRM_AUTH
),
676 DRM_IOCTL_DEF_DRV(RADEON_STIPPLE
, radeon_cp_stipple_kms
, DRM_AUTH
),
677 DRM_IOCTL_DEF_DRV(RADEON_INDIRECT
, radeon_cp_indirect_kms
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
678 DRM_IOCTL_DEF_DRV(RADEON_VERTEX2
, radeon_cp_vertex2_kms
, DRM_AUTH
),
679 DRM_IOCTL_DEF_DRV(RADEON_CMDBUF
, radeon_cp_cmdbuf_kms
, DRM_AUTH
),
680 DRM_IOCTL_DEF_DRV(RADEON_GETPARAM
, radeon_cp_getparam_kms
, DRM_AUTH
),
681 DRM_IOCTL_DEF_DRV(RADEON_FLIP
, radeon_cp_flip_kms
, DRM_AUTH
),
682 DRM_IOCTL_DEF_DRV(RADEON_ALLOC
, radeon_mem_alloc_kms
, DRM_AUTH
),
683 DRM_IOCTL_DEF_DRV(RADEON_FREE
, radeon_mem_free_kms
, DRM_AUTH
),
684 DRM_IOCTL_DEF_DRV(RADEON_INIT_HEAP
, radeon_mem_init_heap_kms
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
685 DRM_IOCTL_DEF_DRV(RADEON_IRQ_EMIT
, radeon_irq_emit_kms
, DRM_AUTH
),
686 DRM_IOCTL_DEF_DRV(RADEON_IRQ_WAIT
, radeon_irq_wait_kms
, DRM_AUTH
),
687 DRM_IOCTL_DEF_DRV(RADEON_SETPARAM
, radeon_cp_setparam_kms
, DRM_AUTH
),
688 DRM_IOCTL_DEF_DRV(RADEON_SURF_ALLOC
, radeon_surface_alloc_kms
, DRM_AUTH
),
689 DRM_IOCTL_DEF_DRV(RADEON_SURF_FREE
, radeon_surface_free_kms
, DRM_AUTH
),
691 DRM_IOCTL_DEF_DRV(RADEON_GEM_INFO
, radeon_gem_info_ioctl
, DRM_AUTH
|DRM_UNLOCKED
),
692 DRM_IOCTL_DEF_DRV(RADEON_GEM_CREATE
, radeon_gem_create_ioctl
, DRM_AUTH
|DRM_UNLOCKED
),
693 DRM_IOCTL_DEF_DRV(RADEON_GEM_MMAP
, radeon_gem_mmap_ioctl
, DRM_AUTH
|DRM_UNLOCKED
),
694 DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_DOMAIN
, radeon_gem_set_domain_ioctl
, DRM_AUTH
|DRM_UNLOCKED
),
695 DRM_IOCTL_DEF_DRV(RADEON_GEM_PREAD
, radeon_gem_pread_ioctl
, DRM_AUTH
|DRM_UNLOCKED
),
696 DRM_IOCTL_DEF_DRV(RADEON_GEM_PWRITE
, radeon_gem_pwrite_ioctl
, DRM_AUTH
|DRM_UNLOCKED
),
697 DRM_IOCTL_DEF_DRV(RADEON_GEM_WAIT_IDLE
, radeon_gem_wait_idle_ioctl
, DRM_AUTH
|DRM_UNLOCKED
),
698 DRM_IOCTL_DEF_DRV(RADEON_CS
, radeon_cs_ioctl
, DRM_AUTH
|DRM_UNLOCKED
),
699 DRM_IOCTL_DEF_DRV(RADEON_INFO
, radeon_info_ioctl
, DRM_AUTH
|DRM_UNLOCKED
),
700 DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_TILING
, radeon_gem_set_tiling_ioctl
, DRM_AUTH
|DRM_UNLOCKED
),
701 DRM_IOCTL_DEF_DRV(RADEON_GEM_GET_TILING
, radeon_gem_get_tiling_ioctl
, DRM_AUTH
|DRM_UNLOCKED
),
702 DRM_IOCTL_DEF_DRV(RADEON_GEM_BUSY
, radeon_gem_busy_ioctl
, DRM_AUTH
|DRM_UNLOCKED
),
703 DRM_IOCTL_DEF_DRV(RADEON_GEM_VA
, radeon_gem_va_ioctl
, DRM_AUTH
|DRM_UNLOCKED
),
705 int radeon_max_kms_ioctl
= DRM_ARRAY_SIZE(radeon_ioctls_kms
);