2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
30 #include <drm/radeon_drm.h>
31 #include "radeon_asic.h"
33 #include <linux/vga_switcheroo.h>
34 #include <linux/slab.h>
37 * radeon_driver_unload_kms - Main unload function for KMS.
39 * @dev: drm dev pointer
41 * This is the main unload function for KMS (all asics).
42 * It calls radeon_modeset_fini() to tear down the
43 * displays, and radeon_device_fini() to tear down
44 * the rest of the device (CP, writeback, etc.).
45 * Returns 0 on success.
47 int radeon_driver_unload_kms(struct drm_device
*dev
)
49 struct radeon_device
*rdev
= dev
->dev_private
;
53 if (rdev
->rmmio
== NULL
)
55 radeon_acpi_fini(rdev
);
56 radeon_modeset_fini(rdev
);
57 radeon_device_fini(rdev
);
61 dev
->dev_private
= NULL
;
66 * radeon_driver_load_kms - Main load function for KMS.
68 * @dev: drm dev pointer
69 * @flags: device flags
71 * This is the main load function for KMS (all asics).
72 * It calls radeon_device_init() to set up the non-display
73 * parts of the chip (asic init, CP, writeback, etc.), and
74 * radeon_modeset_init() to set up the display parts
75 * (crtcs, encoders, hotplug detect, etc.).
76 * Returns 0 on success, error on failure.
78 int radeon_driver_load_kms(struct drm_device
*dev
, unsigned long flags
)
80 struct radeon_device
*rdev
;
83 rdev
= kzalloc(sizeof(struct radeon_device
), GFP_KERNEL
);
87 dev
->dev_private
= (void *)rdev
;
90 if (drm_pci_device_is_agp(dev
)) {
91 flags
|= RADEON_IS_AGP
;
92 } else if (pci_is_pcie(dev
->pdev
)) {
93 flags
|= RADEON_IS_PCIE
;
95 flags
|= RADEON_IS_PCI
;
98 /* radeon_device_init should report only fatal error
99 * like memory allocation failure or iomapping failure,
100 * or memory manager initialization failure, it must
101 * properly initialize the GPU MC controller and permit
104 r
= radeon_device_init(rdev
, dev
, dev
->pdev
, flags
);
106 dev_err(&dev
->pdev
->dev
, "Fatal error during GPU init\n");
110 /* Again modeset_init should fail only on fatal error
111 * otherwise it should provide enough functionalities
112 * for shadowfb to run
114 r
= radeon_modeset_init(rdev
);
116 dev_err(&dev
->pdev
->dev
, "Fatal error during modeset init\n");
118 /* Call ACPI methods: require modeset init
119 * but failure is not fatal
122 acpi_status
= radeon_acpi_init(rdev
);
124 dev_dbg(&dev
->pdev
->dev
,
125 "Error during ACPI methods call\n");
130 radeon_driver_unload_kms(dev
);
135 * radeon_set_filp_rights - Set filp right.
137 * @dev: drm dev pointer
142 * Sets the filp rights for the device (all asics).
144 static void radeon_set_filp_rights(struct drm_device
*dev
,
145 struct drm_file
**owner
,
146 struct drm_file
*applier
,
149 mutex_lock(&dev
->struct_mutex
);
154 } else if (*value
== 0) {
156 if (*owner
== applier
)
159 *value
= *owner
== applier
? 1 : 0;
160 mutex_unlock(&dev
->struct_mutex
);
164 * Userspace get information ioctl
167 * radeon_info_ioctl - answer a device specific request.
169 * @rdev: radeon device pointer
170 * @data: request object
173 * This function is used to pass device specific parameters to the userspace
174 * drivers. Examples include: pci device id, pipeline parms, tiling params,
176 * Returns 0 on success, -EINVAL on failure.
178 int radeon_info_ioctl(struct drm_device
*dev
, void *data
, struct drm_file
*filp
)
180 struct radeon_device
*rdev
= dev
->dev_private
;
181 struct drm_radeon_info
*info
= data
;
182 struct radeon_mode_info
*minfo
= &rdev
->mode_info
;
183 uint32_t *value
, value_tmp
, *value_ptr
, value_size
;
185 struct drm_crtc
*crtc
;
188 value_ptr
= (uint32_t *)((unsigned long)info
->value
);
190 value_size
= sizeof(uint32_t);
192 switch (info
->request
) {
193 case RADEON_INFO_DEVICE_ID
:
194 *value
= dev
->pci_device
;
196 case RADEON_INFO_NUM_GB_PIPES
:
197 *value
= rdev
->num_gb_pipes
;
199 case RADEON_INFO_NUM_Z_PIPES
:
200 *value
= rdev
->num_z_pipes
;
202 case RADEON_INFO_ACCEL_WORKING
:
203 /* xf86-video-ati 6.13.0 relies on this being false for evergreen */
204 if ((rdev
->family
>= CHIP_CEDAR
) && (rdev
->family
<= CHIP_HEMLOCK
))
207 *value
= rdev
->accel_working
;
209 case RADEON_INFO_CRTC_FROM_ID
:
210 if (DRM_COPY_FROM_USER(value
, value_ptr
, sizeof(uint32_t))) {
211 DRM_ERROR("copy_from_user %s:%u\n", __func__
, __LINE__
);
214 for (i
= 0, found
= 0; i
< rdev
->num_crtc
; i
++) {
215 crtc
= (struct drm_crtc
*)minfo
->crtcs
[i
];
216 if (crtc
&& crtc
->base
.id
== *value
) {
217 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(crtc
);
218 *value
= radeon_crtc
->crtc_id
;
224 DRM_DEBUG_KMS("unknown crtc id %d\n", *value
);
228 case RADEON_INFO_ACCEL_WORKING2
:
229 *value
= rdev
->accel_working
;
231 case RADEON_INFO_TILING_CONFIG
:
232 if (rdev
->family
>= CHIP_TAHITI
)
233 *value
= rdev
->config
.si
.tile_config
;
234 else if (rdev
->family
>= CHIP_CAYMAN
)
235 *value
= rdev
->config
.cayman
.tile_config
;
236 else if (rdev
->family
>= CHIP_CEDAR
)
237 *value
= rdev
->config
.evergreen
.tile_config
;
238 else if (rdev
->family
>= CHIP_RV770
)
239 *value
= rdev
->config
.rv770
.tile_config
;
240 else if (rdev
->family
>= CHIP_R600
)
241 *value
= rdev
->config
.r600
.tile_config
;
243 DRM_DEBUG_KMS("tiling config is r6xx+ only!\n");
247 case RADEON_INFO_WANT_HYPERZ
:
248 /* The "value" here is both an input and output parameter.
249 * If the input value is 1, filp requests hyper-z access.
250 * If the input value is 0, filp revokes its hyper-z access.
252 * When returning, the value is 1 if filp owns hyper-z access,
254 if (DRM_COPY_FROM_USER(value
, value_ptr
, sizeof(uint32_t))) {
255 DRM_ERROR("copy_from_user %s:%u\n", __func__
, __LINE__
);
259 DRM_DEBUG_KMS("WANT_HYPERZ: invalid value %d\n", *value
);
262 radeon_set_filp_rights(dev
, &rdev
->hyperz_filp
, filp
, value
);
264 case RADEON_INFO_WANT_CMASK
:
265 /* The same logic as Hyper-Z. */
266 if (DRM_COPY_FROM_USER(value
, value_ptr
, sizeof(uint32_t))) {
267 DRM_ERROR("copy_from_user %s:%u\n", __func__
, __LINE__
);
271 DRM_DEBUG_KMS("WANT_CMASK: invalid value %d\n", *value
);
274 radeon_set_filp_rights(dev
, &rdev
->cmask_filp
, filp
, value
);
276 case RADEON_INFO_CLOCK_CRYSTAL_FREQ
:
277 /* return clock value in KHz */
278 if (rdev
->asic
->get_xclk
)
279 *value
= radeon_get_xclk(rdev
) * 10;
281 *value
= rdev
->clock
.spll
.reference_freq
* 10;
283 case RADEON_INFO_NUM_BACKENDS
:
284 if (rdev
->family
>= CHIP_TAHITI
)
285 *value
= rdev
->config
.si
.max_backends_per_se
*
286 rdev
->config
.si
.max_shader_engines
;
287 else if (rdev
->family
>= CHIP_CAYMAN
)
288 *value
= rdev
->config
.cayman
.max_backends_per_se
*
289 rdev
->config
.cayman
.max_shader_engines
;
290 else if (rdev
->family
>= CHIP_CEDAR
)
291 *value
= rdev
->config
.evergreen
.max_backends
;
292 else if (rdev
->family
>= CHIP_RV770
)
293 *value
= rdev
->config
.rv770
.max_backends
;
294 else if (rdev
->family
>= CHIP_R600
)
295 *value
= rdev
->config
.r600
.max_backends
;
300 case RADEON_INFO_NUM_TILE_PIPES
:
301 if (rdev
->family
>= CHIP_TAHITI
)
302 *value
= rdev
->config
.si
.max_tile_pipes
;
303 else if (rdev
->family
>= CHIP_CAYMAN
)
304 *value
= rdev
->config
.cayman
.max_tile_pipes
;
305 else if (rdev
->family
>= CHIP_CEDAR
)
306 *value
= rdev
->config
.evergreen
.max_tile_pipes
;
307 else if (rdev
->family
>= CHIP_RV770
)
308 *value
= rdev
->config
.rv770
.max_tile_pipes
;
309 else if (rdev
->family
>= CHIP_R600
)
310 *value
= rdev
->config
.r600
.max_tile_pipes
;
315 case RADEON_INFO_FUSION_GART_WORKING
:
318 case RADEON_INFO_BACKEND_MAP
:
319 if (rdev
->family
>= CHIP_TAHITI
)
320 *value
= rdev
->config
.si
.backend_map
;
321 else if (rdev
->family
>= CHIP_CAYMAN
)
322 *value
= rdev
->config
.cayman
.backend_map
;
323 else if (rdev
->family
>= CHIP_CEDAR
)
324 *value
= rdev
->config
.evergreen
.backend_map
;
325 else if (rdev
->family
>= CHIP_RV770
)
326 *value
= rdev
->config
.rv770
.backend_map
;
327 else if (rdev
->family
>= CHIP_R600
)
328 *value
= rdev
->config
.r600
.backend_map
;
333 case RADEON_INFO_VA_START
:
334 /* this is where we report if vm is supported or not */
335 if (rdev
->family
< CHIP_CAYMAN
)
337 *value
= RADEON_VA_RESERVED_SIZE
;
339 case RADEON_INFO_IB_VM_MAX_SIZE
:
340 /* this is where we report if vm is supported or not */
341 if (rdev
->family
< CHIP_CAYMAN
)
343 *value
= RADEON_IB_VM_MAX_SIZE
;
345 case RADEON_INFO_MAX_PIPES
:
346 if (rdev
->family
>= CHIP_TAHITI
)
347 *value
= rdev
->config
.si
.max_cu_per_sh
;
348 else if (rdev
->family
>= CHIP_CAYMAN
)
349 *value
= rdev
->config
.cayman
.max_pipes_per_simd
;
350 else if (rdev
->family
>= CHIP_CEDAR
)
351 *value
= rdev
->config
.evergreen
.max_pipes
;
352 else if (rdev
->family
>= CHIP_RV770
)
353 *value
= rdev
->config
.rv770
.max_pipes
;
354 else if (rdev
->family
>= CHIP_R600
)
355 *value
= rdev
->config
.r600
.max_pipes
;
360 case RADEON_INFO_TIMESTAMP
:
361 if (rdev
->family
< CHIP_R600
) {
362 DRM_DEBUG_KMS("timestamp is r6xx+ only!\n");
365 value
= (uint32_t*)&value64
;
366 value_size
= sizeof(uint64_t);
367 value64
= radeon_get_gpu_clock_counter(rdev
);
369 case RADEON_INFO_MAX_SE
:
370 if (rdev
->family
>= CHIP_TAHITI
)
371 *value
= rdev
->config
.si
.max_shader_engines
;
372 else if (rdev
->family
>= CHIP_CAYMAN
)
373 *value
= rdev
->config
.cayman
.max_shader_engines
;
374 else if (rdev
->family
>= CHIP_CEDAR
)
375 *value
= rdev
->config
.evergreen
.num_ses
;
379 case RADEON_INFO_MAX_SH_PER_SE
:
380 if (rdev
->family
>= CHIP_TAHITI
)
381 *value
= rdev
->config
.si
.max_sh_per_se
;
385 case RADEON_INFO_FASTFB_WORKING
:
386 *value
= rdev
->fastfb_working
;
388 case RADEON_INFO_RING_WORKING
:
389 if (DRM_COPY_FROM_USER(value
, value_ptr
, sizeof(uint32_t))) {
390 DRM_ERROR("copy_from_user %s:%u\n", __func__
, __LINE__
);
394 case RADEON_CS_RING_GFX
:
395 case RADEON_CS_RING_COMPUTE
:
396 *value
= rdev
->ring
[RADEON_RING_TYPE_GFX_INDEX
].ready
;
398 case RADEON_CS_RING_DMA
:
399 *value
= rdev
->ring
[R600_RING_TYPE_DMA_INDEX
].ready
;
400 *value
|= rdev
->ring
[CAYMAN_RING_TYPE_DMA1_INDEX
].ready
;
402 case RADEON_CS_RING_UVD
:
403 *value
= rdev
->ring
[R600_RING_TYPE_UVD_INDEX
].ready
;
409 case RADEON_INFO_SI_TILE_MODE_ARRAY
:
410 if (rdev
->family
< CHIP_TAHITI
) {
411 DRM_DEBUG_KMS("tile mode array is si only!\n");
414 value
= rdev
->config
.si
.tile_mode_array
;
415 value_size
= sizeof(uint32_t)*32;
418 DRM_DEBUG_KMS("Invalid request %d\n", info
->request
);
421 if (DRM_COPY_TO_USER(value_ptr
, (char*)value
, value_size
)) {
422 DRM_ERROR("copy_to_user %s:%u\n", __func__
, __LINE__
);
430 * Outdated mess for old drm with Xorg being in charge (void function now).
433 * radeon_driver_firstopen_kms - drm callback for first open
435 * @dev: drm dev pointer
437 * Nothing to be done for KMS (all asics).
438 * Returns 0 on success.
440 int radeon_driver_firstopen_kms(struct drm_device
*dev
)
446 * radeon_driver_firstopen_kms - drm callback for last close
448 * @dev: drm dev pointer
450 * Switch vga switcheroo state after last close (all asics).
452 void radeon_driver_lastclose_kms(struct drm_device
*dev
)
454 vga_switcheroo_process_delayed_switch();
458 * radeon_driver_open_kms - drm callback for open
460 * @dev: drm dev pointer
461 * @file_priv: drm file
463 * On device open, init vm on cayman+ (all asics).
464 * Returns 0 on success, error on failure.
466 int radeon_driver_open_kms(struct drm_device
*dev
, struct drm_file
*file_priv
)
468 struct radeon_device
*rdev
= dev
->dev_private
;
470 file_priv
->driver_priv
= NULL
;
472 /* new gpu have virtual address space support */
473 if (rdev
->family
>= CHIP_CAYMAN
) {
474 struct radeon_fpriv
*fpriv
;
475 struct radeon_bo_va
*bo_va
;
478 fpriv
= kzalloc(sizeof(*fpriv
), GFP_KERNEL
);
479 if (unlikely(!fpriv
)) {
483 radeon_vm_init(rdev
, &fpriv
->vm
);
485 /* map the ib pool buffer read only into
486 * virtual address space */
487 bo_va
= radeon_vm_bo_add(rdev
, &fpriv
->vm
,
488 rdev
->ring_tmp_bo
.bo
);
489 r
= radeon_vm_bo_set_addr(rdev
, bo_va
, RADEON_VA_IB_OFFSET
,
490 RADEON_VM_PAGE_READABLE
|
491 RADEON_VM_PAGE_SNOOPED
);
493 radeon_vm_fini(rdev
, &fpriv
->vm
);
498 file_priv
->driver_priv
= fpriv
;
504 * radeon_driver_postclose_kms - drm callback for post close
506 * @dev: drm dev pointer
507 * @file_priv: drm file
509 * On device post close, tear down vm on cayman+ (all asics).
511 void radeon_driver_postclose_kms(struct drm_device
*dev
,
512 struct drm_file
*file_priv
)
514 struct radeon_device
*rdev
= dev
->dev_private
;
516 /* new gpu have virtual address space support */
517 if (rdev
->family
>= CHIP_CAYMAN
&& file_priv
->driver_priv
) {
518 struct radeon_fpriv
*fpriv
= file_priv
->driver_priv
;
519 struct radeon_bo_va
*bo_va
;
522 r
= radeon_bo_reserve(rdev
->ring_tmp_bo
.bo
, false);
524 bo_va
= radeon_vm_bo_find(&fpriv
->vm
,
525 rdev
->ring_tmp_bo
.bo
);
527 radeon_vm_bo_rmv(rdev
, bo_va
);
528 radeon_bo_unreserve(rdev
->ring_tmp_bo
.bo
);
531 radeon_vm_fini(rdev
, &fpriv
->vm
);
533 file_priv
->driver_priv
= NULL
;
538 * radeon_driver_preclose_kms - drm callback for pre close
540 * @dev: drm dev pointer
541 * @file_priv: drm file
543 * On device pre close, tear down hyperz and cmask filps on r1xx-r5xx
546 void radeon_driver_preclose_kms(struct drm_device
*dev
,
547 struct drm_file
*file_priv
)
549 struct radeon_device
*rdev
= dev
->dev_private
;
550 if (rdev
->hyperz_filp
== file_priv
)
551 rdev
->hyperz_filp
= NULL
;
552 if (rdev
->cmask_filp
== file_priv
)
553 rdev
->cmask_filp
= NULL
;
554 radeon_uvd_free_handles(rdev
, file_priv
);
558 * VBlank related functions.
561 * radeon_get_vblank_counter_kms - get frame count
563 * @dev: drm dev pointer
564 * @crtc: crtc to get the frame count from
566 * Gets the frame count on the requested crtc (all asics).
567 * Returns frame count on success, -EINVAL on failure.
569 u32
radeon_get_vblank_counter_kms(struct drm_device
*dev
, int crtc
)
571 struct radeon_device
*rdev
= dev
->dev_private
;
573 if (crtc
< 0 || crtc
>= rdev
->num_crtc
) {
574 DRM_ERROR("Invalid crtc %d\n", crtc
);
578 return radeon_get_vblank_counter(rdev
, crtc
);
582 * radeon_enable_vblank_kms - enable vblank interrupt
584 * @dev: drm dev pointer
585 * @crtc: crtc to enable vblank interrupt for
587 * Enable the interrupt on the requested crtc (all asics).
588 * Returns 0 on success, -EINVAL on failure.
590 int radeon_enable_vblank_kms(struct drm_device
*dev
, int crtc
)
592 struct radeon_device
*rdev
= dev
->dev_private
;
593 unsigned long irqflags
;
596 if (crtc
< 0 || crtc
>= rdev
->num_crtc
) {
597 DRM_ERROR("Invalid crtc %d\n", crtc
);
601 spin_lock_irqsave(&rdev
->irq
.lock
, irqflags
);
602 rdev
->irq
.crtc_vblank_int
[crtc
] = true;
603 r
= radeon_irq_set(rdev
);
604 spin_unlock_irqrestore(&rdev
->irq
.lock
, irqflags
);
609 * radeon_disable_vblank_kms - disable vblank interrupt
611 * @dev: drm dev pointer
612 * @crtc: crtc to disable vblank interrupt for
614 * Disable the interrupt on the requested crtc (all asics).
616 void radeon_disable_vblank_kms(struct drm_device
*dev
, int crtc
)
618 struct radeon_device
*rdev
= dev
->dev_private
;
619 unsigned long irqflags
;
621 if (crtc
< 0 || crtc
>= rdev
->num_crtc
) {
622 DRM_ERROR("Invalid crtc %d\n", crtc
);
626 spin_lock_irqsave(&rdev
->irq
.lock
, irqflags
);
627 rdev
->irq
.crtc_vblank_int
[crtc
] = false;
628 radeon_irq_set(rdev
);
629 spin_unlock_irqrestore(&rdev
->irq
.lock
, irqflags
);
633 * radeon_get_vblank_timestamp_kms - get vblank timestamp
635 * @dev: drm dev pointer
636 * @crtc: crtc to get the timestamp for
637 * @max_error: max error
638 * @vblank_time: time value
639 * @flags: flags passed to the driver
641 * Gets the timestamp on the requested crtc based on the
642 * scanout position. (all asics).
643 * Returns postive status flags on success, negative error on failure.
645 int radeon_get_vblank_timestamp_kms(struct drm_device
*dev
, int crtc
,
647 struct timeval
*vblank_time
,
650 struct drm_crtc
*drmcrtc
;
651 struct radeon_device
*rdev
= dev
->dev_private
;
653 if (crtc
< 0 || crtc
>= dev
->num_crtcs
) {
654 DRM_ERROR("Invalid crtc %d\n", crtc
);
658 /* Get associated drm_crtc: */
659 drmcrtc
= &rdev
->mode_info
.crtcs
[crtc
]->base
;
661 /* Helper routine in DRM core does all the work: */
662 return drm_calc_vbltimestamp_from_scanoutpos(dev
, crtc
, max_error
,
670 int radeon_dma_ioctl_kms(struct drm_device
*dev
, void *data
,
671 struct drm_file
*file_priv
)
673 /* Not valid in KMS. */
677 #define KMS_INVALID_IOCTL(name) \
678 int name(struct drm_device *dev, void *data, struct drm_file *file_priv)\
680 DRM_ERROR("invalid ioctl with kms %s\n", __func__); \
685 * All these ioctls are invalid in kms world.
687 KMS_INVALID_IOCTL(radeon_cp_init_kms
)
688 KMS_INVALID_IOCTL(radeon_cp_start_kms
)
689 KMS_INVALID_IOCTL(radeon_cp_stop_kms
)
690 KMS_INVALID_IOCTL(radeon_cp_reset_kms
)
691 KMS_INVALID_IOCTL(radeon_cp_idle_kms
)
692 KMS_INVALID_IOCTL(radeon_cp_resume_kms
)
693 KMS_INVALID_IOCTL(radeon_engine_reset_kms
)
694 KMS_INVALID_IOCTL(radeon_fullscreen_kms
)
695 KMS_INVALID_IOCTL(radeon_cp_swap_kms
)
696 KMS_INVALID_IOCTL(radeon_cp_clear_kms
)
697 KMS_INVALID_IOCTL(radeon_cp_vertex_kms
)
698 KMS_INVALID_IOCTL(radeon_cp_indices_kms
)
699 KMS_INVALID_IOCTL(radeon_cp_texture_kms
)
700 KMS_INVALID_IOCTL(radeon_cp_stipple_kms
)
701 KMS_INVALID_IOCTL(radeon_cp_indirect_kms
)
702 KMS_INVALID_IOCTL(radeon_cp_vertex2_kms
)
703 KMS_INVALID_IOCTL(radeon_cp_cmdbuf_kms
)
704 KMS_INVALID_IOCTL(radeon_cp_getparam_kms
)
705 KMS_INVALID_IOCTL(radeon_cp_flip_kms
)
706 KMS_INVALID_IOCTL(radeon_mem_alloc_kms
)
707 KMS_INVALID_IOCTL(radeon_mem_free_kms
)
708 KMS_INVALID_IOCTL(radeon_mem_init_heap_kms
)
709 KMS_INVALID_IOCTL(radeon_irq_emit_kms
)
710 KMS_INVALID_IOCTL(radeon_irq_wait_kms
)
711 KMS_INVALID_IOCTL(radeon_cp_setparam_kms
)
712 KMS_INVALID_IOCTL(radeon_surface_alloc_kms
)
713 KMS_INVALID_IOCTL(radeon_surface_free_kms
)
716 struct drm_ioctl_desc radeon_ioctls_kms
[] = {
717 DRM_IOCTL_DEF_DRV(RADEON_CP_INIT
, radeon_cp_init_kms
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
718 DRM_IOCTL_DEF_DRV(RADEON_CP_START
, radeon_cp_start_kms
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
719 DRM_IOCTL_DEF_DRV(RADEON_CP_STOP
, radeon_cp_stop_kms
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
720 DRM_IOCTL_DEF_DRV(RADEON_CP_RESET
, radeon_cp_reset_kms
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
721 DRM_IOCTL_DEF_DRV(RADEON_CP_IDLE
, radeon_cp_idle_kms
, DRM_AUTH
),
722 DRM_IOCTL_DEF_DRV(RADEON_CP_RESUME
, radeon_cp_resume_kms
, DRM_AUTH
),
723 DRM_IOCTL_DEF_DRV(RADEON_RESET
, radeon_engine_reset_kms
, DRM_AUTH
),
724 DRM_IOCTL_DEF_DRV(RADEON_FULLSCREEN
, radeon_fullscreen_kms
, DRM_AUTH
),
725 DRM_IOCTL_DEF_DRV(RADEON_SWAP
, radeon_cp_swap_kms
, DRM_AUTH
),
726 DRM_IOCTL_DEF_DRV(RADEON_CLEAR
, radeon_cp_clear_kms
, DRM_AUTH
),
727 DRM_IOCTL_DEF_DRV(RADEON_VERTEX
, radeon_cp_vertex_kms
, DRM_AUTH
),
728 DRM_IOCTL_DEF_DRV(RADEON_INDICES
, radeon_cp_indices_kms
, DRM_AUTH
),
729 DRM_IOCTL_DEF_DRV(RADEON_TEXTURE
, radeon_cp_texture_kms
, DRM_AUTH
),
730 DRM_IOCTL_DEF_DRV(RADEON_STIPPLE
, radeon_cp_stipple_kms
, DRM_AUTH
),
731 DRM_IOCTL_DEF_DRV(RADEON_INDIRECT
, radeon_cp_indirect_kms
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
732 DRM_IOCTL_DEF_DRV(RADEON_VERTEX2
, radeon_cp_vertex2_kms
, DRM_AUTH
),
733 DRM_IOCTL_DEF_DRV(RADEON_CMDBUF
, radeon_cp_cmdbuf_kms
, DRM_AUTH
),
734 DRM_IOCTL_DEF_DRV(RADEON_GETPARAM
, radeon_cp_getparam_kms
, DRM_AUTH
),
735 DRM_IOCTL_DEF_DRV(RADEON_FLIP
, radeon_cp_flip_kms
, DRM_AUTH
),
736 DRM_IOCTL_DEF_DRV(RADEON_ALLOC
, radeon_mem_alloc_kms
, DRM_AUTH
),
737 DRM_IOCTL_DEF_DRV(RADEON_FREE
, radeon_mem_free_kms
, DRM_AUTH
),
738 DRM_IOCTL_DEF_DRV(RADEON_INIT_HEAP
, radeon_mem_init_heap_kms
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
739 DRM_IOCTL_DEF_DRV(RADEON_IRQ_EMIT
, radeon_irq_emit_kms
, DRM_AUTH
),
740 DRM_IOCTL_DEF_DRV(RADEON_IRQ_WAIT
, radeon_irq_wait_kms
, DRM_AUTH
),
741 DRM_IOCTL_DEF_DRV(RADEON_SETPARAM
, radeon_cp_setparam_kms
, DRM_AUTH
),
742 DRM_IOCTL_DEF_DRV(RADEON_SURF_ALLOC
, radeon_surface_alloc_kms
, DRM_AUTH
),
743 DRM_IOCTL_DEF_DRV(RADEON_SURF_FREE
, radeon_surface_free_kms
, DRM_AUTH
),
745 DRM_IOCTL_DEF_DRV(RADEON_GEM_INFO
, radeon_gem_info_ioctl
, DRM_AUTH
|DRM_UNLOCKED
),
746 DRM_IOCTL_DEF_DRV(RADEON_GEM_CREATE
, radeon_gem_create_ioctl
, DRM_AUTH
|DRM_UNLOCKED
),
747 DRM_IOCTL_DEF_DRV(RADEON_GEM_MMAP
, radeon_gem_mmap_ioctl
, DRM_AUTH
|DRM_UNLOCKED
),
748 DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_DOMAIN
, radeon_gem_set_domain_ioctl
, DRM_AUTH
|DRM_UNLOCKED
),
749 DRM_IOCTL_DEF_DRV(RADEON_GEM_PREAD
, radeon_gem_pread_ioctl
, DRM_AUTH
|DRM_UNLOCKED
),
750 DRM_IOCTL_DEF_DRV(RADEON_GEM_PWRITE
, radeon_gem_pwrite_ioctl
, DRM_AUTH
|DRM_UNLOCKED
),
751 DRM_IOCTL_DEF_DRV(RADEON_GEM_WAIT_IDLE
, radeon_gem_wait_idle_ioctl
, DRM_AUTH
|DRM_UNLOCKED
),
752 DRM_IOCTL_DEF_DRV(RADEON_CS
, radeon_cs_ioctl
, DRM_AUTH
|DRM_UNLOCKED
),
753 DRM_IOCTL_DEF_DRV(RADEON_INFO
, radeon_info_ioctl
, DRM_AUTH
|DRM_UNLOCKED
),
754 DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_TILING
, radeon_gem_set_tiling_ioctl
, DRM_AUTH
|DRM_UNLOCKED
),
755 DRM_IOCTL_DEF_DRV(RADEON_GEM_GET_TILING
, radeon_gem_get_tiling_ioctl
, DRM_AUTH
|DRM_UNLOCKED
),
756 DRM_IOCTL_DEF_DRV(RADEON_GEM_BUSY
, radeon_gem_busy_ioctl
, DRM_AUTH
|DRM_UNLOCKED
),
757 DRM_IOCTL_DEF_DRV(RADEON_GEM_VA
, radeon_gem_va_ioctl
, DRM_AUTH
|DRM_UNLOCKED
),
759 int radeon_max_kms_ioctl
= DRM_ARRAY_SIZE(radeon_ioctls_kms
);