drivers/gpu/drm/radeon/radeon_mode.h

   1 /*
   2  * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
   3  *                VA Linux Systems Inc., Fremont, California.
   4  * Copyright 2008 Red Hat Inc.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Original Authors:
  25  *   Kevin E. Martin, Rickard E. Faith, Alan Hourihane
  26  *
  27  * Kernel port Author: Dave Airlie
  28  */
  29
  30 #ifndef RADEON_MODE_H
  31 #define RADEON_MODE_H
  32
  33 #include <drm/drm_crtc.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drm_dp_helper.h>
  36 #include <drm/drm_fixed.h>
  37 #include <drm/drm_crtc_helper.h>
  38 #include <linux/i2c.h>
  39 #include <linux/i2c-algo-bit.h>
  40
  41 struct radeon_bo;
  42 struct radeon_device;
  43
  44 #define to_radeon_crtc(x) container_of(x, struct radeon_crtc, base)
  45 #define to_radeon_connector(x) container_of(x, struct radeon_connector, base)
  46 #define to_radeon_encoder(x) container_of(x, struct radeon_encoder, base)
  47 #define to_radeon_framebuffer(x) container_of(x, struct radeon_framebuffer, base)
  48
  49 enum radeon_rmx_type {
  50         RMX_OFF,
  51         RMX_FULL,
  52         RMX_CENTER,
  53         RMX_ASPECT
  54 };
  55
  56 enum radeon_tv_std {
  57         TV_STD_NTSC,
  58         TV_STD_PAL,
  59         TV_STD_PAL_M,
  60         TV_STD_PAL_60,
  61         TV_STD_NTSC_J,
  62         TV_STD_SCART_PAL,
  63         TV_STD_SECAM,
  64         TV_STD_PAL_CN,
  65         TV_STD_PAL_N,
  66 };
  67
  68 enum radeon_underscan_type {
  69         UNDERSCAN_OFF,
  70         UNDERSCAN_ON,
  71         UNDERSCAN_AUTO,
  72 };
  73
  74 enum radeon_hpd_id {
  75         RADEON_HPD_1 = 0,
  76         RADEON_HPD_2,
  77         RADEON_HPD_3,
  78         RADEON_HPD_4,
  79         RADEON_HPD_5,
  80         RADEON_HPD_6,
  81         RADEON_HPD_NONE = 0xff,
  82 };
  83
  84 #define RADEON_MAX_I2C_BUS 16
  85
  86 /* radeon gpio-based i2c
  87  * 1. "mask" reg and bits
  88  *    grabs the gpio pins for software use
  89  *    0=not held  1=held
  90  * 2. "a" reg and bits
  91  *    output pin value
  92  *    0=low 1=high
  93  * 3. "en" reg and bits
  94  *    sets the pin direction
  95  *    0=input 1=output
  96  * 4. "y" reg and bits
  97  *    input pin value
  98  *    0=low 1=high
  99  */
 100 struct radeon_i2c_bus_rec {
 101         bool valid;
 102         /* id used by atom */
 103         uint8_t i2c_id;
 104         /* id used by atom */
 105         enum radeon_hpd_id hpd;
 106         /* can be used with hw i2c engine */
 107         bool hw_capable;
 108         /* uses multi-media i2c engine */
 109         bool mm_i2c;
 110         /* regs and bits */
 111         uint32_t mask_clk_reg;
 112         uint32_t mask_data_reg;
 113         uint32_t a_clk_reg;
 114         uint32_t a_data_reg;
 115         uint32_t en_clk_reg;
 116         uint32_t en_data_reg;
 117         uint32_t y_clk_reg;
 118         uint32_t y_data_reg;
 119         uint32_t mask_clk_mask;
 120         uint32_t mask_data_mask;
 121         uint32_t a_clk_mask;
 122         uint32_t a_data_mask;
 123         uint32_t en_clk_mask;
 124         uint32_t en_data_mask;
 125         uint32_t y_clk_mask;
 126         uint32_t y_data_mask;
 127 };
 128
 129 struct radeon_tmds_pll {
 130     uint32_t freq;
 131     uint32_t value;
 132 };
 133
 134 #define RADEON_MAX_BIOS_CONNECTOR 16
 135
 136 /* pll flags */
 137 #define RADEON_PLL_USE_BIOS_DIVS        (1 << 0)
 138 #define RADEON_PLL_NO_ODD_POST_DIV      (1 << 1)
 139 #define RADEON_PLL_USE_REF_DIV          (1 << 2)
 140 #define RADEON_PLL_LEGACY               (1 << 3)
 141 #define RADEON_PLL_PREFER_LOW_REF_DIV   (1 << 4)
 142 #define RADEON_PLL_PREFER_HIGH_REF_DIV  (1 << 5)
 143 #define RADEON_PLL_PREFER_LOW_FB_DIV    (1 << 6)
 144 #define RADEON_PLL_PREFER_HIGH_FB_DIV   (1 << 7)
 145 #define RADEON_PLL_PREFER_LOW_POST_DIV  (1 << 8)
 146 #define RADEON_PLL_PREFER_HIGH_POST_DIV (1 << 9)
 147 #define RADEON_PLL_USE_FRAC_FB_DIV      (1 << 10)
 148 #define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 11)
 149 #define RADEON_PLL_USE_POST_DIV         (1 << 12)
 150 #define RADEON_PLL_IS_LCD               (1 << 13)
 151 #define RADEON_PLL_PREFER_MINM_OVER_MAXP (1 << 14)
 152
 153 struct radeon_pll {
 154         /* reference frequency */
 155         uint32_t reference_freq;
 156
 157         /* fixed dividers */
 158         uint32_t reference_div;
 159         uint32_t post_div;
 160
 161         /* pll in/out limits */
 162         uint32_t pll_in_min;
 163         uint32_t pll_in_max;
 164         uint32_t pll_out_min;
 165         uint32_t pll_out_max;
 166         uint32_t lcd_pll_out_min;
 167         uint32_t lcd_pll_out_max;
 168         uint32_t best_vco;
 169
 170         /* divider limits */
 171         uint32_t min_ref_div;
 172         uint32_t max_ref_div;
 173         uint32_t min_post_div;
 174         uint32_t max_post_div;
 175         uint32_t min_feedback_div;
 176         uint32_t max_feedback_div;
 177         uint32_t min_frac_feedback_div;
 178         uint32_t max_frac_feedback_div;
 179
 180         /* flags for the current clock */
 181         uint32_t flags;
 182
 183         /* pll id */
 184         uint32_t id;
 185 };
 186
 187 struct radeon_i2c_chan {
 188         struct i2c_adapter adapter;
 189         struct drm_device *dev;
 190         union {
 191                 struct i2c_algo_bit_data bit;
 192                 struct i2c_algo_dp_aux_data dp;
 193         } algo;
 194         struct radeon_i2c_bus_rec rec;
 195 };
 196
 197 /* mostly for macs, but really any system without connector tables */
 198 enum radeon_connector_table {
 199         CT_NONE = 0,
 200         CT_GENERIC,
 201         CT_IBOOK,
 202         CT_POWERBOOK_EXTERNAL,
 203         CT_POWERBOOK_INTERNAL,
 204         CT_POWERBOOK_VGA,
 205         CT_MINI_EXTERNAL,
 206         CT_MINI_INTERNAL,
 207         CT_IMAC_G5_ISIGHT,
 208         CT_EMAC,
 209         CT_RN50_POWER,
 210         CT_MAC_X800,
 211         CT_MAC_G5_9600,
 212         CT_SAM440EP,
 213         CT_MAC_G4_SILVER
 214 };
 215
 216 enum radeon_dvo_chip {
 217         DVO_SIL164,
 218         DVO_SIL1178,
 219 };
 220
 221 struct radeon_fbdev;
 222
 223 struct radeon_afmt {
 224         bool enabled;
 225         int offset;
 226         bool last_buffer_filled_status;
 227         int id;
 228 };
 229
 230 struct radeon_mode_info {
 231         struct atom_context *atom_context;
 232         struct card_info *atom_card_info;
 233         enum radeon_connector_table connector_table;
 234         bool mode_config_initialized;
 235         struct radeon_crtc *crtcs[6];
 236         struct radeon_afmt *afmt[6];
 237         /* DVI-I properties */
 238         struct drm_property *coherent_mode_property;
 239         /* DAC enable load detect */
 240         struct drm_property *load_detect_property;
 241         /* TV standard */
 242         struct drm_property *tv_std_property;
 243         /* legacy TMDS PLL detect */
 244         struct drm_property *tmds_pll_property;
 245         /* underscan */
 246         struct drm_property *underscan_property;
 247         struct drm_property *underscan_hborder_property;
 248         struct drm_property *underscan_vborder_property;
 249         /* hardcoded DFP edid from BIOS */
 250         struct edid *bios_hardcoded_edid;
 251         int bios_hardcoded_edid_size;
 252
 253         /* pointer to fbdev info structure */
 254         struct radeon_fbdev *rfbdev;
 255         /* firmware flags */
 256         u16 firmware_flags;
 257         /* pointer to backlight encoder */
 258         struct radeon_encoder *bl_encoder;
 259 };
 260
 261 #define RADEON_MAX_BL_LEVEL 0xFF
 262
 263 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
 264
 265 struct radeon_backlight_privdata {
 266         struct radeon_encoder *encoder;
 267         uint8_t negative;
 268 };
 269
 270 #endif
 271
 272 #define MAX_H_CODE_TIMING_LEN 32
 273 #define MAX_V_CODE_TIMING_LEN 32
 274
 275 /* need to store these as reading
 276    back code tables is excessive */
 277 struct radeon_tv_regs {
 278         uint32_t tv_uv_adr;
 279         uint32_t timing_cntl;
 280         uint32_t hrestart;
 281         uint32_t vrestart;
 282         uint32_t frestart;
 283         uint16_t h_code_timing[MAX_H_CODE_TIMING_LEN];
 284         uint16_t v_code_timing[MAX_V_CODE_TIMING_LEN];
 285 };
 286
 287 struct radeon_atom_ss {
 288         uint16_t percentage;
 289         uint8_t type;
 290         uint16_t step;
 291         uint8_t delay;
 292         uint8_t range;
 293         uint8_t refdiv;
 294         /* asic_ss */
 295         uint16_t rate;
 296         uint16_t amount;
 297 };
 298
 299 struct radeon_crtc {
 300         struct drm_crtc base;
 301         int crtc_id;
 302         u16 lut_r[256], lut_g[256], lut_b[256];
 303         bool enabled;
 304         bool can_tile;
 305         uint32_t crtc_offset;
 306         struct drm_gem_object *cursor_bo;
 307         uint64_t cursor_addr;
 308         int cursor_width;
 309         int cursor_height;
 310         int max_cursor_width;
 311         int max_cursor_height;
 312         uint32_t legacy_display_base_addr;
 313         uint32_t legacy_cursor_offset;
 314         enum radeon_rmx_type rmx_type;
 315         u8 h_border;
 316         u8 v_border;
 317         fixed20_12 vsc;
 318         fixed20_12 hsc;
 319         struct drm_display_mode native_mode;
 320         int pll_id;
 321         /* page flipping */
 322         struct radeon_unpin_work *unpin_work;
 323         int deferred_flip_completion;
 324         /* pll sharing */
 325         struct radeon_atom_ss ss;
 326         bool ss_enabled;
 327         u32 adjusted_clock;
 328         int bpc;
 329         u32 pll_reference_div;
 330         u32 pll_post_div;
 331         u32 pll_flags;
 332         struct drm_encoder *encoder;
 333         struct drm_connector *connector;
 334 };
 335
 336 struct radeon_encoder_primary_dac {
 337         /* legacy primary dac */
 338         uint32_t ps2_pdac_adj;
 339 };
 340
 341 struct radeon_encoder_lvds {
 342         /* legacy lvds */
 343         uint16_t panel_vcc_delay;
 344         uint8_t  panel_pwr_delay;
 345         uint8_t  panel_digon_delay;
 346         uint8_t  panel_blon_delay;
 347         uint16_t panel_ref_divider;
 348         uint8_t  panel_post_divider;
 349         uint16_t panel_fb_divider;
 350         bool     use_bios_dividers;
 351         uint32_t lvds_gen_cntl;
 352         /* panel mode */
 353         struct drm_display_mode native_mode;
 354         struct backlight_device *bl_dev;
 355         int      dpms_mode;
 356         uint8_t  backlight_level;
 357 };
 358
 359 struct radeon_encoder_tv_dac {
 360         /* legacy tv dac */
 361         uint32_t ps2_tvdac_adj;
 362         uint32_t ntsc_tvdac_adj;
 363         uint32_t pal_tvdac_adj;
 364
 365         int               h_pos;
 366         int               v_pos;
 367         int               h_size;
 368         int               supported_tv_stds;
 369         bool              tv_on;
 370         enum radeon_tv_std tv_std;
 371         struct radeon_tv_regs tv;
 372 };
 373
 374 struct radeon_encoder_int_tmds {
 375         /* legacy int tmds */
 376         struct radeon_tmds_pll tmds_pll[4];
 377 };
 378
 379 struct radeon_encoder_ext_tmds {
 380         /* tmds over dvo */
 381         struct radeon_i2c_chan *i2c_bus;
 382         uint8_t slave_addr;
 383         enum radeon_dvo_chip dvo_chip;
 384 };
 385
 386 /* spread spectrum */
 387 struct radeon_encoder_atom_dig {
 388         bool linkb;
 389         /* atom dig */
 390         bool coherent_mode;
 391         int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB, etc. */
 392         /* atom lvds/edp */
 393         uint32_t lcd_misc;
 394         uint16_t panel_pwr_delay;
 395         uint32_t lcd_ss_id;
 396         /* panel mode */
 397         struct drm_display_mode native_mode;
 398         struct backlight_device *bl_dev;
 399         int dpms_mode;
 400         uint8_t backlight_level;
 401         int panel_mode;
 402         struct radeon_afmt *afmt;
 403 };
 404
 405 struct radeon_encoder_atom_dac {
 406         enum radeon_tv_std tv_std;
 407 };
 408
 409 struct radeon_encoder {
 410         struct drm_encoder base;
 411         uint32_t encoder_enum;
 412         uint32_t encoder_id;
 413         uint32_t devices;
 414         uint32_t active_device;
 415         uint32_t flags;
 416         uint32_t pixel_clock;
 417         enum radeon_rmx_type rmx_type;
 418         enum radeon_underscan_type underscan_type;
 419         uint32_t underscan_hborder;
 420         uint32_t underscan_vborder;
 421         struct drm_display_mode native_mode;
 422         void *enc_priv;
 423         int audio_polling_active;
 424         bool is_ext_encoder;
 425         u16 caps;
 426 };
 427
 428 struct radeon_connector_atom_dig {
 429         uint32_t igp_lane_info;
 430         /* displayport */
 431         struct radeon_i2c_chan *dp_i2c_bus;
 432         u8 dpcd[DP_RECEIVER_CAP_SIZE];
 433         u8 dp_sink_type;
 434         int dp_clock;
 435         int dp_lane_count;
 436         bool edp_on;
 437 };
 438
 439 struct radeon_gpio_rec {
 440         bool valid;
 441         u8 id;
 442         u32 reg;
 443         u32 mask;
 444 };
 445
 446 struct radeon_hpd {
 447         enum radeon_hpd_id hpd;
 448         u8 plugged_state;
 449         struct radeon_gpio_rec gpio;
 450 };
 451
 452 struct radeon_router {
 453         u32 router_id;
 454         struct radeon_i2c_bus_rec i2c_info;
 455         u8 i2c_addr;
 456         /* i2c mux */
 457         bool ddc_valid;
 458         u8 ddc_mux_type;
 459         u8 ddc_mux_control_pin;
 460         u8 ddc_mux_state;
 461         /* clock/data mux */
 462         bool cd_valid;
 463         u8 cd_mux_type;
 464         u8 cd_mux_control_pin;
 465         u8 cd_mux_state;
 466 };
 467
 468 struct radeon_connector {
 469         struct drm_connector base;
 470         uint32_t connector_id;
 471         uint32_t devices;
 472         struct radeon_i2c_chan *ddc_bus;
 473         /* some systems have an hdmi and vga port with a shared ddc line */
 474         bool shared_ddc;
 475         bool use_digital;
 476         /* we need to mind the EDID between detect
 477            and get modes due to analog/digital/tvencoder */
 478         struct edid *edid;
 479         void *con_priv;
 480         bool dac_load_detect;
 481         bool detected_by_load; /* if the connection status was determined by load */
 482         uint16_t connector_object_id;
 483         struct radeon_hpd hpd;
 484         struct radeon_router router;
 485         struct radeon_i2c_chan *router_bus;
 486 };
 487
 488 struct radeon_framebuffer {
 489         struct drm_framebuffer base;
 490         struct drm_gem_object *obj;
 491 };
 492
 493 #define ENCODER_MODE_IS_DP(em) (((em) == ATOM_ENCODER_MODE_DP) || \
 494                                 ((em) == ATOM_ENCODER_MODE_DP_MST))
 495
 496 struct atom_clock_dividers {
 497         u32 post_div;
 498         union {
 499                 struct {
 500 #ifdef __BIG_ENDIAN
 501                         u32 reserved : 6;
 502                         u32 whole_fb_div : 12;
 503                         u32 frac_fb_div : 14;
 504 #else
 505                         u32 frac_fb_div : 14;
 506                         u32 whole_fb_div : 12;
 507                         u32 reserved : 6;
 508 #endif
 509                 };
 510                 u32 fb_div;
 511         };
 512         u32 ref_div;
 513         bool enable_post_div;
 514         bool enable_dithen;
 515         u32 vco_mode;
 516         u32 real_clock;
 517         /* added for CI */
 518         u32 post_divider;
 519         u32 flags;
 520 };
 521
 522 #define MEM_TYPE_GDDR5  0x50
 523 #define MEM_TYPE_GDDR4  0x40
 524 #define MEM_TYPE_GDDR3  0x30
 525 #define MEM_TYPE_DDR2   0x20
 526 #define MEM_TYPE_GDDR1  0x10
 527 #define MEM_TYPE_DDR3   0xb0
 528 #define MEM_TYPE_MASK   0xf0
 529
 530 struct atom_memory_info {
 531         u8 mem_vendor;
 532         u8 mem_type;
 533 };
 534
 535 #define MAX_AC_TIMING_ENTRIES 16
 536
 537 struct atom_memory_clock_range_table
 538 {
 539         u8 num_entries;
 540         u8 rsv[3];
 541         u32 mclk[MAX_AC_TIMING_ENTRIES];
 542 };
 543
 544 #define VBIOS_MC_REGISTER_ARRAY_SIZE 32
 545 #define VBIOS_MAX_AC_TIMING_ENTRIES 20
 546
 547 struct atom_mc_reg_entry {
 548         u32 mclk_max;
 549         u32 mc_data[VBIOS_MC_REGISTER_ARRAY_SIZE];
 550 };
 551
 552 struct atom_mc_register_address {
 553         u16 s1;
 554         u8 pre_reg_data;
 555 };
 556
 557 struct atom_mc_reg_table {
 558         u8 last;
 559         u8 num_entries;
 560         struct atom_mc_reg_entry mc_reg_table_entry[VBIOS_MAX_AC_TIMING_ENTRIES];
 561         struct atom_mc_register_address mc_reg_address[VBIOS_MC_REGISTER_ARRAY_SIZE];
 562 };
 563
 564 #define MAX_VOLTAGE_ENTRIES 32
 565
 566 struct atom_voltage_table_entry
 567 {
 568         u16 value;
 569         u32 smio_low;
 570 };
 571
 572 struct atom_voltage_table
 573 {
 574         u32 count;
 575         u32 mask_low;
 576         struct atom_voltage_table_entry entries[MAX_VOLTAGE_ENTRIES];
 577 };
 578
 579 extern enum radeon_tv_std
 580 radeon_combios_get_tv_info(struct radeon_device *rdev);
 581 extern enum radeon_tv_std
 582 radeon_atombios_get_tv_info(struct radeon_device *rdev);
 583
 584 extern struct drm_connector *
 585 radeon_get_connector_for_encoder(struct drm_encoder *encoder);
 586 extern struct drm_connector *
 587 radeon_get_connector_for_encoder_init(struct drm_encoder *encoder);
 588 extern bool radeon_dig_monitor_is_duallink(struct drm_encoder *encoder,
 589                                     u32 pixel_clock);
 590
 591 extern u16 radeon_encoder_get_dp_bridge_encoder_id(struct drm_encoder *encoder);
 592 extern u16 radeon_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector);
 593 extern bool radeon_connector_encoder_is_hbr2(struct drm_connector *connector);
 594 extern bool radeon_connector_is_dp12_capable(struct drm_connector *connector);
 595 extern int radeon_get_monitor_bpc(struct drm_connector *connector);
 596
 597 extern void radeon_connector_hotplug(struct drm_connector *connector);
 598 extern int radeon_dp_mode_valid_helper(struct drm_connector *connector,
 599                                        struct drm_display_mode *mode);
 600 extern void radeon_dp_set_link_config(struct drm_connector *connector,
 601                                       const struct drm_display_mode *mode);
 602 extern void radeon_dp_link_train(struct drm_encoder *encoder,
 603                                  struct drm_connector *connector);
 604 extern bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector);
 605 extern u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector);
 606 extern bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector);
 607 extern int radeon_dp_get_panel_mode(struct drm_encoder *encoder,
 608                                     struct drm_connector *connector);
 609 extern void atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode);
 610 extern void radeon_atom_encoder_init(struct radeon_device *rdev);
 611 extern void radeon_atom_disp_eng_pll_init(struct radeon_device *rdev);
 612 extern void atombios_dig_transmitter_setup(struct drm_encoder *encoder,
 613                                            int action, uint8_t lane_num,
 614                                            uint8_t lane_set);
 615 extern void radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder);
 616 extern struct drm_encoder *radeon_get_external_encoder(struct drm_encoder *encoder);
 617 extern int radeon_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
 618                                 u8 write_byte, u8 *read_byte);
 619
 620 extern void radeon_i2c_init(struct radeon_device *rdev);
 621 extern void radeon_i2c_fini(struct radeon_device *rdev);
 622 extern void radeon_combios_i2c_init(struct radeon_device *rdev);
 623 extern void radeon_atombios_i2c_init(struct radeon_device *rdev);
 624 extern void radeon_i2c_add(struct radeon_device *rdev,
 625                            struct radeon_i2c_bus_rec *rec,
 626                            const char *name);
 627 extern struct radeon_i2c_chan *radeon_i2c_lookup(struct radeon_device *rdev,
 628                                                  struct radeon_i2c_bus_rec *i2c_bus);
 629 extern struct radeon_i2c_chan *radeon_i2c_create_dp(struct drm_device *dev,
 630                                                     struct radeon_i2c_bus_rec *rec,
 631                                                     const char *name);
 632 extern struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev,
 633                                                  struct radeon_i2c_bus_rec *rec,
 634                                                  const char *name);
 635 extern void radeon_i2c_destroy(struct radeon_i2c_chan *i2c);
 636 extern void radeon_i2c_get_byte(struct radeon_i2c_chan *i2c_bus,
 637                                 u8 slave_addr,
 638                                 u8 addr,
 639                                 u8 *val);
 640 extern void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c,
 641                                 u8 slave_addr,
 642                                 u8 addr,
 643                                 u8 val);
 644 extern void radeon_router_select_ddc_port(struct radeon_connector *radeon_connector);
 645 extern void radeon_router_select_cd_port(struct radeon_connector *radeon_connector);
 646 extern bool radeon_ddc_probe(struct radeon_connector *radeon_connector, bool use_aux);
 647 extern int radeon_ddc_get_modes(struct radeon_connector *radeon_connector);
 648
 649 extern struct drm_encoder *radeon_best_encoder(struct drm_connector *connector);
 650
 651 extern bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev,
 652                                              struct radeon_atom_ss *ss,
 653                                              int id);
 654 extern bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev,
 655                                              struct radeon_atom_ss *ss,
 656                                              int id, u32 clock);
 657
 658 extern void radeon_compute_pll_legacy(struct radeon_pll *pll,
 659                                       uint64_t freq,
 660                                       uint32_t *dot_clock_p,
 661                                       uint32_t *fb_div_p,
 662                                       uint32_t *frac_fb_div_p,
 663                                       uint32_t *ref_div_p,
 664                                       uint32_t *post_div_p);
 665
 666 extern void radeon_compute_pll_avivo(struct radeon_pll *pll,
 667                                      u32 freq,
 668                                      u32 *dot_clock_p,
 669                                      u32 *fb_div_p,
 670                                      u32 *frac_fb_div_p,
 671                                      u32 *ref_div_p,
 672                                      u32 *post_div_p);
 673
 674 extern void radeon_setup_encoder_clones(struct drm_device *dev);
 675
 676 struct drm_encoder *radeon_encoder_legacy_lvds_add(struct drm_device *dev, int bios_index);
 677 struct drm_encoder *radeon_encoder_legacy_primary_dac_add(struct drm_device *dev, int bios_index, int with_tv);
 678 struct drm_encoder *radeon_encoder_legacy_tv_dac_add(struct drm_device *dev, int bios_index, int with_tv);
 679 struct drm_encoder *radeon_encoder_legacy_tmds_int_add(struct drm_device *dev, int bios_index);
 680 struct drm_encoder *radeon_encoder_legacy_tmds_ext_add(struct drm_device *dev, int bios_index);
 681 extern void atombios_dvo_setup(struct drm_encoder *encoder, int action);
 682 extern void atombios_digital_setup(struct drm_encoder *encoder, int action);
 683 extern int atombios_get_encoder_mode(struct drm_encoder *encoder);
 684 extern bool atombios_set_edp_panel_power(struct drm_connector *connector, int action);
 685 extern void radeon_encoder_set_active_device(struct drm_encoder *encoder);
 686
 687 extern void radeon_crtc_load_lut(struct drm_crtc *crtc);
 688 extern int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
 689                                    struct drm_framebuffer *old_fb);
 690 extern int atombios_crtc_set_base_atomic(struct drm_crtc *crtc,
 691                                          struct drm_framebuffer *fb,
 692                                          int x, int y,
 693                                          enum mode_set_atomic state);
 694 extern int atombios_crtc_mode_set(struct drm_crtc *crtc,
 695                                    struct drm_display_mode *mode,
 696                                    struct drm_display_mode *adjusted_mode,
 697                                    int x, int y,
 698                                    struct drm_framebuffer *old_fb);
 699 extern void atombios_crtc_dpms(struct drm_crtc *crtc, int mode);
 700
 701 extern int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
 702                                  struct drm_framebuffer *old_fb);
 703 extern int radeon_crtc_set_base_atomic(struct drm_crtc *crtc,
 704                                        struct drm_framebuffer *fb,
 705                                        int x, int y,
 706                                        enum mode_set_atomic state);
 707 extern int radeon_crtc_do_set_base(struct drm_crtc *crtc,
 708                                    struct drm_framebuffer *fb,
 709                                    int x, int y, int atomic);
 710 extern int radeon_crtc_cursor_set(struct drm_crtc *crtc,
 711                                   struct drm_file *file_priv,
 712                                   uint32_t handle,
 713                                   uint32_t width,
 714                                   uint32_t height);
 715 extern int radeon_crtc_cursor_move(struct drm_crtc *crtc,
 716                                    int x, int y);
 717
 718 extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc,
 719                                       int *vpos, int *hpos);
 720
 721 extern bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev);
 722 extern struct edid *
 723 radeon_bios_get_hardcoded_edid(struct radeon_device *rdev);
 724 extern bool radeon_atom_get_clock_info(struct drm_device *dev);
 725 extern bool radeon_combios_get_clock_info(struct drm_device *dev);
 726 extern struct radeon_encoder_atom_dig *
 727 radeon_atombios_get_lvds_info(struct radeon_encoder *encoder);
 728 extern bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
 729                                           struct radeon_encoder_int_tmds *tmds);
 730 extern bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder,
 731                                                      struct radeon_encoder_int_tmds *tmds);
 732 extern bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder,
 733                                                    struct radeon_encoder_int_tmds *tmds);
 734 extern bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder,
 735                                                          struct radeon_encoder_ext_tmds *tmds);
 736 extern bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder,
 737                                                        struct radeon_encoder_ext_tmds *tmds);
 738 extern struct radeon_encoder_primary_dac *
 739 radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder);
 740 extern struct radeon_encoder_tv_dac *
 741 radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder);
 742 extern struct radeon_encoder_lvds *
 743 radeon_combios_get_lvds_info(struct radeon_encoder *encoder);
 744 extern void radeon_combios_get_ext_tmds_info(struct radeon_encoder *encoder);
 745 extern struct radeon_encoder_tv_dac *
 746 radeon_combios_get_tv_dac_info(struct radeon_encoder *encoder);
 747 extern struct radeon_encoder_primary_dac *
 748 radeon_combios_get_primary_dac_info(struct radeon_encoder *encoder);
 749 extern bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder);
 750 extern void radeon_external_tmds_setup(struct drm_encoder *encoder);
 751 extern void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock);
 752 extern void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev);
 753 extern void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock);
 754 extern void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev);
 755 extern void radeon_save_bios_scratch_regs(struct radeon_device *rdev);
 756 extern void radeon_restore_bios_scratch_regs(struct radeon_device *rdev);
 757 extern void
 758 radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc);
 759 extern void
 760 radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on);
 761 extern void
 762 radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc);
 763 extern void
 764 radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on);
 765 extern void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
 766                                      u16 blue, int regno);
 767 extern void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
 768                                      u16 *blue, int regno);
 769 int radeon_framebuffer_init(struct drm_device *dev,
 770                              struct radeon_framebuffer *rfb,
 771                              struct drm_mode_fb_cmd2 *mode_cmd,
 772                              struct drm_gem_object *obj);
 773
 774 int radeonfb_remove(struct drm_device *dev, struct drm_framebuffer *fb);
 775 bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev);
 776 bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev);
 777 void radeon_atombios_init_crtc(struct drm_device *dev,
 778                                struct radeon_crtc *radeon_crtc);
 779 void radeon_legacy_init_crtc(struct drm_device *dev,
 780                              struct radeon_crtc *radeon_crtc);
 781
 782 void radeon_get_clock_info(struct drm_device *dev);
 783
 784 extern bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev);
 785 extern bool radeon_get_atom_connector_info_from_supported_devices_table(struct drm_device *dev);
 786
 787 void radeon_enc_destroy(struct drm_encoder *encoder);
 788 void radeon_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj);
 789 void radeon_combios_asic_init(struct drm_device *dev);
 790 bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
 791                                         const struct drm_display_mode *mode,
 792                                         struct drm_display_mode *adjusted_mode);
 793 void radeon_panel_mode_fixup(struct drm_encoder *encoder,
 794                              struct drm_display_mode *adjusted_mode);
 795 void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *radeon_crtc);
 796
 797 /* legacy tv */
 798 void radeon_legacy_tv_adjust_crtc_reg(struct drm_encoder *encoder,
 799                                       uint32_t *h_total_disp, uint32_t *h_sync_strt_wid,
 800                                       uint32_t *v_total_disp, uint32_t *v_sync_strt_wid);
 801 void radeon_legacy_tv_adjust_pll1(struct drm_encoder *encoder,
 802                                   uint32_t *htotal_cntl, uint32_t *ppll_ref_div,
 803                                   uint32_t *ppll_div_3, uint32_t *pixclks_cntl);
 804 void radeon_legacy_tv_adjust_pll2(struct drm_encoder *encoder,
 805                                   uint32_t *htotal2_cntl, uint32_t *p2pll_ref_div,
 806                                   uint32_t *p2pll_div_0, uint32_t *pixclks_cntl);
 807 void radeon_legacy_tv_mode_set(struct drm_encoder *encoder,
 808                                struct drm_display_mode *mode,
 809                                struct drm_display_mode *adjusted_mode);
 810
 811 /* fbdev layer */
 812 int radeon_fbdev_init(struct radeon_device *rdev);
 813 void radeon_fbdev_fini(struct radeon_device *rdev);
 814 void radeon_fbdev_set_suspend(struct radeon_device *rdev, int state);
 815 int radeon_fbdev_total_size(struct radeon_device *rdev);
 816 bool radeon_fbdev_robj_is_fb(struct radeon_device *rdev, struct radeon_bo *robj);
 817
 818 void radeon_fb_output_poll_changed(struct radeon_device *rdev);
 819
 820 void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id);
 821
 822 int radeon_align_pitch(struct radeon_device *rdev, int width, int bpp, bool tiled);
 823 #endif