drivers/gpu/drm/radeon/radeon_object.c

   1 /*
   2  * Copyright 2009 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26 /*
  27  * Authors:
  28  *    Jerome Glisse <glisse@freedesktop.org>
  29  *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
  30  *    Dave Airlie
  31  */
  32 #include <linux/list.h>
  33 #include <linux/slab.h>
  34 #include <drm/drmP.h>
  35 #include <drm/radeon_drm.h>
  36 #include "radeon.h"
  37 #include "radeon_trace.h"
  38
  39
  40 int radeon_ttm_init(struct radeon_device *rdev);
  41 void radeon_ttm_fini(struct radeon_device *rdev);
  42 static void radeon_bo_clear_surface_reg(struct radeon_bo *bo);
  43
  44 /*
  45  * To exclude mutual BO access we rely on bo_reserve exclusion, as all
  46  * function are calling it.
  47  */
  48
  49 static void radeon_bo_clear_va(struct radeon_bo *bo)
  50 {
  51         struct radeon_bo_va *bo_va, *tmp;
  52
  53         list_for_each_entry_safe(bo_va, tmp, &bo->va, bo_list) {
  54                 /* remove from all vm address space */
  55                 radeon_vm_bo_rmv(bo->rdev, bo_va);
  56         }
  57 }
  58
  59 static void radeon_update_memory_usage(struct radeon_bo *bo,
  60                                        unsigned mem_type, int sign)
  61 {
  62         struct radeon_device *rdev = bo->rdev;
  63         u64 size = (u64)bo->tbo.num_pages << PAGE_SHIFT;
  64
  65         switch (mem_type) {
  66         case TTM_PL_TT:
  67                 if (sign > 0)
  68                         atomic64_add(size, &rdev->gtt_usage);
  69                 else
  70                         atomic64_sub(size, &rdev->gtt_usage);
  71                 break;
  72         case TTM_PL_VRAM:
  73                 if (sign > 0)
  74                         atomic64_add(size, &rdev->vram_usage);
  75                 else
  76                         atomic64_sub(size, &rdev->vram_usage);
  77                 break;
  78         }
  79 }
  80
  81 static void radeon_ttm_bo_destroy(struct ttm_buffer_object *tbo)
  82 {
  83         struct radeon_bo *bo;
  84
  85         bo = container_of(tbo, struct radeon_bo, tbo);
  86
  87         radeon_update_memory_usage(bo, bo->tbo.mem.mem_type, -1);
  88
  89         mutex_lock(&bo->rdev->gem.mutex);
  90         list_del_init(&bo->list);
  91         mutex_unlock(&bo->rdev->gem.mutex);
  92         radeon_bo_clear_surface_reg(bo);
  93         radeon_bo_clear_va(bo);
  94         drm_gem_object_release(&bo->gem_base);
  95         kfree(bo);
  96 }
  97
  98 bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo)
  99 {
 100         if (bo->destroy == &radeon_ttm_bo_destroy)
 101                 return true;
 102         return false;
 103 }
 104
 105 void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain)
 106 {
 107         u32 c = 0, i;
 108
 109         rbo->placement.fpfn = 0;
 110         rbo->placement.lpfn = 0;
 111         rbo->placement.placement = rbo->placements;
 112         rbo->placement.busy_placement = rbo->placements;
 113         if (domain & RADEON_GEM_DOMAIN_VRAM)
 114                 rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED |
 115                                         TTM_PL_FLAG_VRAM;
 116         if (domain & RADEON_GEM_DOMAIN_GTT) {
 117                 if (rbo->flags & RADEON_GEM_GTT_UC) {
 118                         rbo->placements[c++] = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_TT;
 119                 } else if ((rbo->flags & RADEON_GEM_GTT_WC) ||
 120                            (rbo->rdev->flags & RADEON_IS_AGP)) {
 121                         rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED |
 122                                 TTM_PL_FLAG_TT;
 123                 } else {
 124                         rbo->placements[c++] = TTM_PL_FLAG_CACHED | TTM_PL_FLAG_TT;
 125                 }
 126         }
 127         if (domain & RADEON_GEM_DOMAIN_CPU) {
 128                 if (rbo->flags & RADEON_GEM_GTT_UC) {
 129                         rbo->placements[c++] = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_SYSTEM;
 130                 } else if ((rbo->flags & RADEON_GEM_GTT_WC) ||
 131                     rbo->rdev->flags & RADEON_IS_AGP) {
 132                         rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED |
 133                                 TTM_PL_FLAG_SYSTEM;
 134                 } else {
 135                         rbo->placements[c++] = TTM_PL_FLAG_CACHED | TTM_PL_FLAG_SYSTEM;
 136                 }
 137         }
 138         if (!c)
 139                 rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM;
 140         rbo->placement.num_placement = c;
 141         rbo->placement.num_busy_placement = c;
 142
 143         /*
 144          * Use two-ended allocation depending on the buffer size to
 145          * improve fragmentation quality.
 146          * 512kb was measured as the most optimal number.
 147          */
 148         if (rbo->tbo.mem.size > 512 * 1024) {
 149                 for (i = 0; i < c; i++) {
 150                         rbo->placements[i] |= TTM_PL_FLAG_TOPDOWN;
 151                 }
 152         }
 153 }
 154
 155 int radeon_bo_create(struct radeon_device *rdev,
 156                      unsigned long size, int byte_align, bool kernel, u32 domain,
 157                      u32 flags, struct sg_table *sg, struct radeon_bo **bo_ptr)
 158 {
 159         struct radeon_bo *bo;
 160         enum ttm_bo_type type;
 161         unsigned long page_align = roundup(byte_align, PAGE_SIZE) >> PAGE_SHIFT;
 162         size_t acc_size;
 163         int r;
 164
 165         size = ALIGN(size, PAGE_SIZE);
 166
 167         if (kernel) {
 168                 type = ttm_bo_type_kernel;
 169         } else if (sg) {
 170                 type = ttm_bo_type_sg;
 171         } else {
 172                 type = ttm_bo_type_device;
 173         }
 174         *bo_ptr = NULL;
 175
 176         acc_size = ttm_bo_dma_acc_size(&rdev->mman.bdev, size,
 177                                        sizeof(struct radeon_bo));
 178
 179         bo = kzalloc(sizeof(struct radeon_bo), GFP_KERNEL);
 180         if (bo == NULL)
 181                 return -ENOMEM;
 182         r = drm_gem_object_init(rdev->ddev, &bo->gem_base, size);
 183         if (unlikely(r)) {
 184                 kfree(bo);
 185                 return r;
 186         }
 187         bo->rdev = rdev;
 188         bo->surface_reg = -1;
 189         INIT_LIST_HEAD(&bo->list);
 190         INIT_LIST_HEAD(&bo->va);
 191         bo->initial_domain = domain & (RADEON_GEM_DOMAIN_VRAM |
 192                                        RADEON_GEM_DOMAIN_GTT |
 193                                        RADEON_GEM_DOMAIN_CPU);
 194
 195         bo->flags = flags;
 196         /* PCI GART is always snooped */
 197         if (!(rdev->flags & RADEON_IS_PCIE))
 198                 bo->flags &= ~(RADEON_GEM_GTT_WC | RADEON_GEM_GTT_UC);
 199
 200         radeon_ttm_placement_from_domain(bo, domain);
 201         /* Kernel allocation are uninterruptible */
 202         down_read(&rdev->pm.mclk_lock);
 203         r = ttm_bo_init(&rdev->mman.bdev, &bo->tbo, size, type,
 204                         &bo->placement, page_align, !kernel, NULL,
 205                         acc_size, sg, &radeon_ttm_bo_destroy);
 206         up_read(&rdev->pm.mclk_lock);
 207         if (unlikely(r != 0)) {
 208                 return r;
 209         }
 210         *bo_ptr = bo;
 211
 212         trace_radeon_bo_create(bo);
 213
 214         return 0;
 215 }
 216
 217 int radeon_bo_kmap(struct radeon_bo *bo, void **ptr)
 218 {
 219         bool is_iomem;
 220         int r;
 221
 222         if (bo->kptr) {
 223                 if (ptr) {
 224                         *ptr = bo->kptr;
 225                 }
 226                 return 0;
 227         }
 228         r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap);
 229         if (r) {
 230                 return r;
 231         }
 232         bo->kptr = ttm_kmap_obj_virtual(&bo->kmap, &is_iomem);
 233         if (ptr) {
 234                 *ptr = bo->kptr;
 235         }
 236         radeon_bo_check_tiling(bo, 0, 0);
 237         return 0;
 238 }
 239
 240 void radeon_bo_kunmap(struct radeon_bo *bo)
 241 {
 242         if (bo->kptr == NULL)
 243                 return;
 244         bo->kptr = NULL;
 245         radeon_bo_check_tiling(bo, 0, 0);
 246         ttm_bo_kunmap(&bo->kmap);
 247 }
 248
 249 void radeon_bo_unref(struct radeon_bo **bo)
 250 {
 251         struct ttm_buffer_object *tbo;
 252         struct radeon_device *rdev;
 253
 254         if ((*bo) == NULL)
 255                 return;
 256         rdev = (*bo)->rdev;
 257         tbo = &((*bo)->tbo);
 258         down_read(&rdev->pm.mclk_lock);
 259         ttm_bo_unref(&tbo);
 260         up_read(&rdev->pm.mclk_lock);
 261         if (tbo == NULL)
 262                 *bo = NULL;
 263 }
 264
 265 int radeon_bo_pin_restricted(struct radeon_bo *bo, u32 domain, u64 max_offset,
 266                              u64 *gpu_addr)
 267 {
 268         int r, i;
 269
 270         if (bo->pin_count) {
 271                 bo->pin_count++;
 272                 if (gpu_addr)
 273                         *gpu_addr = radeon_bo_gpu_offset(bo);
 274
 275                 if (max_offset != 0) {
 276                         u64 domain_start;
 277
 278                         if (domain == RADEON_GEM_DOMAIN_VRAM)
 279                                 domain_start = bo->rdev->mc.vram_start;
 280                         else
 281                                 domain_start = bo->rdev->mc.gtt_start;
 282                         WARN_ON_ONCE(max_offset <
 283                                      (radeon_bo_gpu_offset(bo) - domain_start));
 284                 }
 285
 286                 return 0;
 287         }
 288         radeon_ttm_placement_from_domain(bo, domain);
 289         if (domain == RADEON_GEM_DOMAIN_VRAM) {
 290                 /* force to pin into visible video ram */
 291                 bo->placement.lpfn = bo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
 292         }
 293         if (max_offset) {
 294                 u64 lpfn = max_offset >> PAGE_SHIFT;
 295
 296                 if (!bo->placement.lpfn)
 297                         bo->placement.lpfn = bo->rdev->mc.gtt_size >> PAGE_SHIFT;
 298
 299                 if (lpfn < bo->placement.lpfn)
 300                         bo->placement.lpfn = lpfn;
 301         }
 302         for (i = 0; i < bo->placement.num_placement; i++)
 303                 bo->placements[i] |= TTM_PL_FLAG_NO_EVICT;
 304         r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
 305         if (likely(r == 0)) {
 306                 bo->pin_count = 1;
 307                 if (gpu_addr != NULL)
 308                         *gpu_addr = radeon_bo_gpu_offset(bo);
 309         }
 310         if (unlikely(r != 0))
 311                 dev_err(bo->rdev->dev, "%p pin failed\n", bo);
 312         return r;
 313 }
 314
 315 int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr)
 316 {
 317         return radeon_bo_pin_restricted(bo, domain, 0, gpu_addr);
 318 }
 319
 320 int radeon_bo_unpin(struct radeon_bo *bo)
 321 {
 322         int r, i;
 323
 324         if (!bo->pin_count) {
 325                 dev_warn(bo->rdev->dev, "%p unpin not necessary\n", bo);
 326                 return 0;
 327         }
 328         bo->pin_count--;
 329         if (bo->pin_count)
 330                 return 0;
 331         for (i = 0; i < bo->placement.num_placement; i++)
 332                 bo->placements[i] &= ~TTM_PL_FLAG_NO_EVICT;
 333         r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
 334         if (unlikely(r != 0))
 335                 dev_err(bo->rdev->dev, "%p validate failed for unpin\n", bo);
 336         return r;
 337 }
 338
 339 int radeon_bo_evict_vram(struct radeon_device *rdev)
 340 {
 341         /* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */
 342         if (0 && (rdev->flags & RADEON_IS_IGP)) {
 343                 if (rdev->mc.igp_sideport_enabled == false)
 344                         /* Useless to evict on IGP chips */
 345                         return 0;
 346         }
 347         return ttm_bo_evict_mm(&rdev->mman.bdev, TTM_PL_VRAM);
 348 }
 349
 350 void radeon_bo_force_delete(struct radeon_device *rdev)
 351 {
 352         struct radeon_bo *bo, *n;
 353
 354         if (list_empty(&rdev->gem.objects)) {
 355                 return;
 356         }
 357         dev_err(rdev->dev, "Userspace still has active objects !\n");
 358         list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
 359                 mutex_lock(&rdev->ddev->struct_mutex);
 360                 dev_err(rdev->dev, "%p %p %lu %lu force free\n",
 361                         &bo->gem_base, bo, (unsigned long)bo->gem_base.size,
 362                         *((unsigned long *)&bo->gem_base.refcount));
 363                 mutex_lock(&bo->rdev->gem.mutex);
 364                 list_del_init(&bo->list);
 365                 mutex_unlock(&bo->rdev->gem.mutex);
 366                 /* this should unref the ttm bo */
 367                 drm_gem_object_unreference(&bo->gem_base);
 368                 mutex_unlock(&rdev->ddev->struct_mutex);
 369         }
 370 }
 371
 372 int radeon_bo_init(struct radeon_device *rdev)
 373 {
 374         /* Add an MTRR for the VRAM */
 375         if (!rdev->fastfb_working) {
 376                 rdev->mc.vram_mtrr = arch_phys_wc_add(rdev->mc.aper_base,
 377                                                       rdev->mc.aper_size);
 378         }
 379         DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n",
 380                 rdev->mc.mc_vram_size >> 20,
 381                 (unsigned long long)rdev->mc.aper_size >> 20);
 382         DRM_INFO("RAM width %dbits %cDR\n",
 383                         rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S');
 384         return radeon_ttm_init(rdev);
 385 }
 386
 387 void radeon_bo_fini(struct radeon_device *rdev)
 388 {
 389         radeon_ttm_fini(rdev);
 390         arch_phys_wc_del(rdev->mc.vram_mtrr);
 391 }
 392
 393 /* Returns how many bytes TTM can move per IB.
 394  */
 395 static u64 radeon_bo_get_threshold_for_moves(struct radeon_device *rdev)
 396 {
 397         u64 real_vram_size = rdev->mc.real_vram_size;
 398         u64 vram_usage = atomic64_read(&rdev->vram_usage);
 399
 400         /* This function is based on the current VRAM usage.
 401          *
 402          * - If all of VRAM is free, allow relocating the number of bytes that
 403          *   is equal to 1/4 of the size of VRAM for this IB.
 404
 405          * - If more than one half of VRAM is occupied, only allow relocating
 406          *   1 MB of data for this IB.
 407          *
 408          * - From 0 to one half of used VRAM, the threshold decreases
 409          *   linearly.
 410          *         __________________
 411          * 1/4 of -|\               |
 412          * VRAM    | \              |
 413          *         |  \             |
 414          *         |   \            |
 415          *         |    \           |
 416          *         |     \          |
 417          *         |      \         |
 418          *         |       \________|1 MB
 419          *         |----------------|
 420          *    VRAM 0 %             100 %
 421          *         used            used
 422          *
 423          * Note: It's a threshold, not a limit. The threshold must be crossed
 424          * for buffer relocations to stop, so any buffer of an arbitrary size
 425          * can be moved as long as the threshold isn't crossed before
 426          * the relocation takes place. We don't want to disable buffer
 427          * relocations completely.
 428          *
 429          * The idea is that buffers should be placed in VRAM at creation time
 430          * and TTM should only do a minimum number of relocations during
 431          * command submission. In practice, you need to submit at least
 432          * a dozen IBs to move all buffers to VRAM if they are in GTT.
 433          *
 434          * Also, things can get pretty crazy under memory pressure and actual
 435          * VRAM usage can change a lot, so playing safe even at 50% does
 436          * consistently increase performance.
 437          */
 438
 439         u64 half_vram = real_vram_size >> 1;
 440         u64 half_free_vram = vram_usage >= half_vram ? 0 : half_vram - vram_usage;
 441         u64 bytes_moved_threshold = half_free_vram >> 1;
 442         return max(bytes_moved_threshold, 1024*1024ull);
 443 }
 444
 445 int radeon_bo_list_validate(struct radeon_device *rdev,
 446                             struct ww_acquire_ctx *ticket,
 447                             struct list_head *head, int ring)
 448 {
 449         struct radeon_cs_reloc *lobj;
 450         struct radeon_bo *bo;
 451         int r;
 452         u64 bytes_moved = 0, initial_bytes_moved;
 453         u64 bytes_moved_threshold = radeon_bo_get_threshold_for_moves(rdev);
 454
 455         r = ttm_eu_reserve_buffers(ticket, head);
 456         if (unlikely(r != 0)) {
 457                 return r;
 458         }
 459
 460         list_for_each_entry(lobj, head, tv.head) {
 461                 bo = lobj->robj;
 462                 if (!bo->pin_count) {
 463                         u32 domain = lobj->prefered_domains;
 464                         u32 current_domain =
 465                                 radeon_mem_type_to_domain(bo->tbo.mem.mem_type);
 466
 467                         /* Check if this buffer will be moved and don't move it
 468                          * if we have moved too many buffers for this IB already.
 469                          *
 470                          * Note that this allows moving at least one buffer of
 471                          * any size, because it doesn't take the current "bo"
 472                          * into account. We don't want to disallow buffer moves
 473                          * completely.
 474                          */
 475                         if ((lobj->allowed_domains & current_domain) != 0 &&
 476                             (domain & current_domain) == 0 && /* will be moved */
 477                             bytes_moved > bytes_moved_threshold) {
 478                                 /* don't move it */
 479                                 domain = current_domain;
 480                         }
 481
 482                 retry:
 483                         radeon_ttm_placement_from_domain(bo, domain);
 484                         if (ring == R600_RING_TYPE_UVD_INDEX)
 485                                 radeon_uvd_force_into_uvd_segment(bo);
 486
 487                         initial_bytes_moved = atomic64_read(&rdev->num_bytes_moved);
 488                         r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
 489                         bytes_moved += atomic64_read(&rdev->num_bytes_moved) -
 490                                        initial_bytes_moved;
 491
 492                         if (unlikely(r)) {
 493                                 if (r != -ERESTARTSYS &&
 494                                     domain != lobj->allowed_domains) {
 495                                         domain = lobj->allowed_domains;
 496                                         goto retry;
 497                                 }
 498                                 ttm_eu_backoff_reservation(ticket, head);
 499                                 return r;
 500                         }
 501                 }
 502                 lobj->gpu_offset = radeon_bo_gpu_offset(bo);
 503                 lobj->tiling_flags = bo->tiling_flags;
 504         }
 505         return 0;
 506 }
 507
 508 int radeon_bo_fbdev_mmap(struct radeon_bo *bo,
 509                              struct vm_area_struct *vma)
 510 {
 511         return ttm_fbdev_mmap(vma, &bo->tbo);
 512 }
 513
 514 int radeon_bo_get_surface_reg(struct radeon_bo *bo)
 515 {
 516         struct radeon_device *rdev = bo->rdev;
 517         struct radeon_surface_reg *reg;
 518         struct radeon_bo *old_object;
 519         int steal;
 520         int i;
 521
 522         lockdep_assert_held(&bo->tbo.resv->lock.base);
 523
 524         if (!bo->tiling_flags)
 525                 return 0;
 526
 527         if (bo->surface_reg >= 0) {
 528                 reg = &rdev->surface_regs[bo->surface_reg];
 529                 i = bo->surface_reg;
 530                 goto out;
 531         }
 532
 533         steal = -1;
 534         for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {
 535
 536                 reg = &rdev->surface_regs[i];
 537                 if (!reg->bo)
 538                         break;
 539
 540                 old_object = reg->bo;
 541                 if (old_object->pin_count == 0)
 542                         steal = i;
 543         }
 544
 545         /* if we are all out */
 546         if (i == RADEON_GEM_MAX_SURFACES) {
 547                 if (steal == -1)
 548                         return -ENOMEM;
 549                 /* find someone with a surface reg and nuke their BO */
 550                 reg = &rdev->surface_regs[steal];
 551                 old_object = reg->bo;
 552                 /* blow away the mapping */
 553                 DRM_DEBUG("stealing surface reg %d from %p\n", steal, old_object);
 554                 ttm_bo_unmap_virtual(&old_object->tbo);
 555                 old_object->surface_reg = -1;
 556                 i = steal;
 557         }
 558
 559         bo->surface_reg = i;
 560         reg->bo = bo;
 561
 562 out:
 563         radeon_set_surface_reg(rdev, i, bo->tiling_flags, bo->pitch,
 564                                bo->tbo.mem.start << PAGE_SHIFT,
 565                                bo->tbo.num_pages << PAGE_SHIFT);
 566         return 0;
 567 }
 568
 569 static void radeon_bo_clear_surface_reg(struct radeon_bo *bo)
 570 {
 571         struct radeon_device *rdev = bo->rdev;
 572         struct radeon_surface_reg *reg;
 573
 574         if (bo->surface_reg == -1)
 575                 return;
 576
 577         reg = &rdev->surface_regs[bo->surface_reg];
 578         radeon_clear_surface_reg(rdev, bo->surface_reg);
 579
 580         reg->bo = NULL;
 581         bo->surface_reg = -1;
 582 }
 583
 584 int radeon_bo_set_tiling_flags(struct radeon_bo *bo,
 585                                 uint32_t tiling_flags, uint32_t pitch)
 586 {
 587         struct radeon_device *rdev = bo->rdev;
 588         int r;
 589
 590         if (rdev->family >= CHIP_CEDAR) {
 591                 unsigned bankw, bankh, mtaspect, tilesplit, stilesplit;
 592
 593                 bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK;
 594                 bankh = (tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK;
 595                 mtaspect = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK;
 596                 tilesplit = (tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MASK;
 597                 stilesplit = (tiling_flags >> RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK;
 598                 switch (bankw) {
 599                 case 0:
 600                 case 1:
 601                 case 2:
 602                 case 4:
 603                 case 8:
 604                         break;
 605                 default:
 606                         return -EINVAL;
 607                 }
 608                 switch (bankh) {
 609                 case 0:
 610                 case 1:
 611                 case 2:
 612                 case 4:
 613                 case 8:
 614                         break;
 615                 default:
 616                         return -EINVAL;
 617                 }
 618                 switch (mtaspect) {
 619                 case 0:
 620                 case 1:
 621                 case 2:
 622                 case 4:
 623                 case 8:
 624                         break;
 625                 default:
 626                         return -EINVAL;
 627                 }
 628                 if (tilesplit > 6) {
 629                         return -EINVAL;
 630                 }
 631                 if (stilesplit > 6) {
 632                         return -EINVAL;
 633                 }
 634         }
 635         r = radeon_bo_reserve(bo, false);
 636         if (unlikely(r != 0))
 637                 return r;
 638         bo->tiling_flags = tiling_flags;
 639         bo->pitch = pitch;
 640         radeon_bo_unreserve(bo);
 641         return 0;
 642 }
 643
 644 void radeon_bo_get_tiling_flags(struct radeon_bo *bo,
 645                                 uint32_t *tiling_flags,
 646                                 uint32_t *pitch)
 647 {
 648         lockdep_assert_held(&bo->tbo.resv->lock.base);
 649
 650         if (tiling_flags)
 651                 *tiling_flags = bo->tiling_flags;
 652         if (pitch)
 653                 *pitch = bo->pitch;
 654 }
 655
 656 int radeon_bo_check_tiling(struct radeon_bo *bo, bool has_moved,
 657                                 bool force_drop)
 658 {
 659         if (!force_drop)
 660                 lockdep_assert_held(&bo->tbo.resv->lock.base);
 661
 662         if (!(bo->tiling_flags & RADEON_TILING_SURFACE))
 663                 return 0;
 664
 665         if (force_drop) {
 666                 radeon_bo_clear_surface_reg(bo);
 667                 return 0;
 668         }
 669
 670         if (bo->tbo.mem.mem_type != TTM_PL_VRAM) {
 671                 if (!has_moved)
 672                         return 0;
 673
 674                 if (bo->surface_reg >= 0)
 675                         radeon_bo_clear_surface_reg(bo);
 676                 return 0;
 677         }
 678
 679         if ((bo->surface_reg >= 0) && !has_moved)
 680                 return 0;
 681
 682         return radeon_bo_get_surface_reg(bo);
 683 }
 684
 685 void radeon_bo_move_notify(struct ttm_buffer_object *bo,
 686                            struct ttm_mem_reg *new_mem)
 687 {
 688         struct radeon_bo *rbo;
 689
 690         if (!radeon_ttm_bo_is_radeon_bo(bo))
 691                 return;
 692
 693         rbo = container_of(bo, struct radeon_bo, tbo);
 694         radeon_bo_check_tiling(rbo, 0, 1);
 695         radeon_vm_bo_invalidate(rbo->rdev, rbo);
 696
 697         /* update statistics */
 698         if (!new_mem)
 699                 return;
 700
 701         radeon_update_memory_usage(rbo, bo->mem.mem_type, -1);
 702         radeon_update_memory_usage(rbo, new_mem->mem_type, 1);
 703 }
 704
 705 int radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
 706 {
 707         struct radeon_device *rdev;
 708         struct radeon_bo *rbo;
 709         unsigned long offset, size;
 710         int r;
 711
 712         if (!radeon_ttm_bo_is_radeon_bo(bo))
 713                 return 0;
 714         rbo = container_of(bo, struct radeon_bo, tbo);
 715         radeon_bo_check_tiling(rbo, 0, 0);
 716         rdev = rbo->rdev;
 717         if (bo->mem.mem_type != TTM_PL_VRAM)
 718                 return 0;
 719
 720         size = bo->mem.num_pages << PAGE_SHIFT;
 721         offset = bo->mem.start << PAGE_SHIFT;
 722         if ((offset + size) <= rdev->mc.visible_vram_size)
 723                 return 0;
 724
 725         /* hurrah the memory is not visible ! */
 726         radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_VRAM);
 727         rbo->placement.lpfn = rdev->mc.visible_vram_size >> PAGE_SHIFT;
 728         r = ttm_bo_validate(bo, &rbo->placement, false, false);
 729         if (unlikely(r == -ENOMEM)) {
 730                 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_GTT);
 731                 return ttm_bo_validate(bo, &rbo->placement, false, false);
 732         } else if (unlikely(r != 0)) {
 733                 return r;
 734         }
 735
 736         offset = bo->mem.start << PAGE_SHIFT;
 737         /* this should never happen */
 738         if ((offset + size) > rdev->mc.visible_vram_size)
 739                 return -EINVAL;
 740
 741         return 0;
 742 }
 743
 744 int radeon_bo_wait(struct radeon_bo *bo, u32 *mem_type, bool no_wait)
 745 {
 746         int r;
 747
 748         r = ttm_bo_reserve(&bo->tbo, true, no_wait, false, NULL);
 749         if (unlikely(r != 0))
 750                 return r;
 751         spin_lock(&bo->tbo.bdev->fence_lock);
 752         if (mem_type)
 753                 *mem_type = bo->tbo.mem.mem_type;
 754         if (bo->tbo.sync_obj)
 755                 r = ttm_bo_wait(&bo->tbo, true, true, no_wait);
 756         spin_unlock(&bo->tbo.bdev->fence_lock);
 757         ttm_bo_unreserve(&bo->tbo);
 758         return r;
 759 }