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drm/ttm: flip the switch, and convert to dma_fence
[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon_object.c
1 /*
2 * Copyright 2009 Jerome Glisse.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
20 *
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
23 * of the Software.
24 *
25 */
26 /*
27 * Authors:
28 * Jerome Glisse <glisse@freedesktop.org>
29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
30 * Dave Airlie
31 */
32 #include <linux/list.h>
33 #include <linux/slab.h>
34 #include <drm/drmP.h>
35 #include <drm/radeon_drm.h>
36 #include "radeon.h"
37 #include "radeon_trace.h"
38
39
40 int radeon_ttm_init(struct radeon_device *rdev);
41 void radeon_ttm_fini(struct radeon_device *rdev);
42 static void radeon_bo_clear_surface_reg(struct radeon_bo *bo);
43
44 /*
45 * To exclude mutual BO access we rely on bo_reserve exclusion, as all
46 * function are calling it.
47 */
48
49 static void radeon_update_memory_usage(struct radeon_bo *bo,
50 unsigned mem_type, int sign)
51 {
52 struct radeon_device *rdev = bo->rdev;
53 u64 size = (u64)bo->tbo.num_pages << PAGE_SHIFT;
54
55 switch (mem_type) {
56 case TTM_PL_TT:
57 if (sign > 0)
58 atomic64_add(size, &rdev->gtt_usage);
59 else
60 atomic64_sub(size, &rdev->gtt_usage);
61 break;
62 case TTM_PL_VRAM:
63 if (sign > 0)
64 atomic64_add(size, &rdev->vram_usage);
65 else
66 atomic64_sub(size, &rdev->vram_usage);
67 break;
68 }
69 }
70
71 static void radeon_ttm_bo_destroy(struct ttm_buffer_object *tbo)
72 {
73 struct radeon_bo *bo;
74
75 bo = container_of(tbo, struct radeon_bo, tbo);
76
77 radeon_update_memory_usage(bo, bo->tbo.mem.mem_type, -1);
78 radeon_mn_unregister(bo);
79
80 mutex_lock(&bo->rdev->gem.mutex);
81 list_del_init(&bo->list);
82 mutex_unlock(&bo->rdev->gem.mutex);
83 radeon_bo_clear_surface_reg(bo);
84 WARN_ON(!list_empty(&bo->va));
85 drm_gem_object_release(&bo->gem_base);
86 kfree(bo);
87 }
88
89 bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo)
90 {
91 if (bo->destroy == &radeon_ttm_bo_destroy)
92 return true;
93 return false;
94 }
95
96 void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain)
97 {
98 u32 c = 0, i;
99
100 rbo->placement.placement = rbo->placements;
101 rbo->placement.busy_placement = rbo->placements;
102 if (domain & RADEON_GEM_DOMAIN_VRAM)
103 rbo->placements[c++].flags = TTM_PL_FLAG_WC |
104 TTM_PL_FLAG_UNCACHED |
105 TTM_PL_FLAG_VRAM;
106
107 if (domain & RADEON_GEM_DOMAIN_GTT) {
108 if (rbo->flags & RADEON_GEM_GTT_UC) {
109 rbo->placements[c++].flags = TTM_PL_FLAG_UNCACHED |
110 TTM_PL_FLAG_TT;
111
112 } else if ((rbo->flags & RADEON_GEM_GTT_WC) ||
113 (rbo->rdev->flags & RADEON_IS_AGP)) {
114 rbo->placements[c++].flags = TTM_PL_FLAG_WC |
115 TTM_PL_FLAG_UNCACHED |
116 TTM_PL_FLAG_TT;
117 } else {
118 rbo->placements[c++].flags = TTM_PL_FLAG_CACHED |
119 TTM_PL_FLAG_TT;
120 }
121 }
122
123 if (domain & RADEON_GEM_DOMAIN_CPU) {
124 if (rbo->flags & RADEON_GEM_GTT_UC) {
125 rbo->placements[c++].flags = TTM_PL_FLAG_UNCACHED |
126 TTM_PL_FLAG_SYSTEM;
127
128 } else if ((rbo->flags & RADEON_GEM_GTT_WC) ||
129 rbo->rdev->flags & RADEON_IS_AGP) {
130 rbo->placements[c++].flags = TTM_PL_FLAG_WC |
131 TTM_PL_FLAG_UNCACHED |
132 TTM_PL_FLAG_SYSTEM;
133 } else {
134 rbo->placements[c++].flags = TTM_PL_FLAG_CACHED |
135 TTM_PL_FLAG_SYSTEM;
136 }
137 }
138 if (!c)
139 rbo->placements[c++].flags = TTM_PL_MASK_CACHING |
140 TTM_PL_FLAG_SYSTEM;
141
142 rbo->placement.num_placement = c;
143 rbo->placement.num_busy_placement = c;
144
145 for (i = 0; i < c; ++i) {
146 rbo->placements[i].fpfn = 0;
147 rbo->placements[i].lpfn = 0;
148 }
149
150 /*
151 * Use two-ended allocation depending on the buffer size to
152 * improve fragmentation quality.
153 * 512kb was measured as the most optimal number.
154 */
155 if (rbo->tbo.mem.size > 512 * 1024) {
156 for (i = 0; i < c; i++) {
157 rbo->placements[i].flags |= TTM_PL_FLAG_TOPDOWN;
158 }
159 }
160 }
161
162 int radeon_bo_create(struct radeon_device *rdev,
163 unsigned long size, int byte_align, bool kernel, u32 domain,
164 u32 flags, struct sg_table *sg, struct radeon_bo **bo_ptr)
165 {
166 struct radeon_bo *bo;
167 enum ttm_bo_type type;
168 unsigned long page_align = roundup(byte_align, PAGE_SIZE) >> PAGE_SHIFT;
169 size_t acc_size;
170 int r;
171
172 size = ALIGN(size, PAGE_SIZE);
173
174 if (kernel) {
175 type = ttm_bo_type_kernel;
176 } else if (sg) {
177 type = ttm_bo_type_sg;
178 } else {
179 type = ttm_bo_type_device;
180 }
181 *bo_ptr = NULL;
182
183 acc_size = ttm_bo_dma_acc_size(&rdev->mman.bdev, size,
184 sizeof(struct radeon_bo));
185
186 bo = kzalloc(sizeof(struct radeon_bo), GFP_KERNEL);
187 if (bo == NULL)
188 return -ENOMEM;
189 r = drm_gem_object_init(rdev->ddev, &bo->gem_base, size);
190 if (unlikely(r)) {
191 kfree(bo);
192 return r;
193 }
194 bo->rdev = rdev;
195 bo->surface_reg = -1;
196 INIT_LIST_HEAD(&bo->list);
197 INIT_LIST_HEAD(&bo->va);
198 bo->initial_domain = domain & (RADEON_GEM_DOMAIN_VRAM |
199 RADEON_GEM_DOMAIN_GTT |
200 RADEON_GEM_DOMAIN_CPU);
201
202 bo->flags = flags;
203 /* PCI GART is always snooped */
204 if (!(rdev->flags & RADEON_IS_PCIE))
205 bo->flags &= ~(RADEON_GEM_GTT_WC | RADEON_GEM_GTT_UC);
206
207 radeon_ttm_placement_from_domain(bo, domain);
208 /* Kernel allocation are uninterruptible */
209 down_read(&rdev->pm.mclk_lock);
210 r = ttm_bo_init(&rdev->mman.bdev, &bo->tbo, size, type,
211 &bo->placement, page_align, !kernel, NULL,
212 acc_size, sg, &radeon_ttm_bo_destroy);
213 up_read(&rdev->pm.mclk_lock);
214 if (unlikely(r != 0)) {
215 return r;
216 }
217 *bo_ptr = bo;
218
219 trace_radeon_bo_create(bo);
220
221 return 0;
222 }
223
224 int radeon_bo_kmap(struct radeon_bo *bo, void **ptr)
225 {
226 bool is_iomem;
227 int r;
228
229 if (bo->kptr) {
230 if (ptr) {
231 *ptr = bo->kptr;
232 }
233 return 0;
234 }
235 r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap);
236 if (r) {
237 return r;
238 }
239 bo->kptr = ttm_kmap_obj_virtual(&bo->kmap, &is_iomem);
240 if (ptr) {
241 *ptr = bo->kptr;
242 }
243 radeon_bo_check_tiling(bo, 0, 0);
244 return 0;
245 }
246
247 void radeon_bo_kunmap(struct radeon_bo *bo)
248 {
249 if (bo->kptr == NULL)
250 return;
251 bo->kptr = NULL;
252 radeon_bo_check_tiling(bo, 0, 0);
253 ttm_bo_kunmap(&bo->kmap);
254 }
255
256 struct radeon_bo *radeon_bo_ref(struct radeon_bo *bo)
257 {
258 if (bo == NULL)
259 return NULL;
260
261 ttm_bo_reference(&bo->tbo);
262 return bo;
263 }
264
265 void radeon_bo_unref(struct radeon_bo **bo)
266 {
267 struct ttm_buffer_object *tbo;
268 struct radeon_device *rdev;
269
270 if ((*bo) == NULL)
271 return;
272 rdev = (*bo)->rdev;
273 tbo = &((*bo)->tbo);
274 ttm_bo_unref(&tbo);
275 if (tbo == NULL)
276 *bo = NULL;
277 }
278
279 int radeon_bo_pin_restricted(struct radeon_bo *bo, u32 domain, u64 max_offset,
280 u64 *gpu_addr)
281 {
282 int r, i;
283
284 if (radeon_ttm_tt_has_userptr(bo->tbo.ttm))
285 return -EPERM;
286
287 if (bo->pin_count) {
288 bo->pin_count++;
289 if (gpu_addr)
290 *gpu_addr = radeon_bo_gpu_offset(bo);
291
292 if (max_offset != 0) {
293 u64 domain_start;
294
295 if (domain == RADEON_GEM_DOMAIN_VRAM)
296 domain_start = bo->rdev->mc.vram_start;
297 else
298 domain_start = bo->rdev->mc.gtt_start;
299 WARN_ON_ONCE(max_offset <
300 (radeon_bo_gpu_offset(bo) - domain_start));
301 }
302
303 return 0;
304 }
305 radeon_ttm_placement_from_domain(bo, domain);
306 for (i = 0; i < bo->placement.num_placement; i++) {
307 unsigned lpfn = 0;
308
309 /* force to pin into visible video ram */
310 if (bo->placements[i].flags & TTM_PL_FLAG_VRAM)
311 lpfn = bo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
312 else
313 lpfn = bo->rdev->mc.gtt_size >> PAGE_SHIFT; /* ??? */
314
315 if (max_offset)
316 lpfn = min (lpfn, (unsigned)(max_offset >> PAGE_SHIFT));
317
318 bo->placements[i].lpfn = lpfn;
319 bo->placements[i].flags |= TTM_PL_FLAG_NO_EVICT;
320 }
321
322 r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
323 if (likely(r == 0)) {
324 bo->pin_count = 1;
325 if (gpu_addr != NULL)
326 *gpu_addr = radeon_bo_gpu_offset(bo);
327 if (domain == RADEON_GEM_DOMAIN_VRAM)
328 bo->rdev->vram_pin_size += radeon_bo_size(bo);
329 else
330 bo->rdev->gart_pin_size += radeon_bo_size(bo);
331 } else {
332 dev_err(bo->rdev->dev, "%p pin failed\n", bo);
333 }
334 return r;
335 }
336
337 int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr)
338 {
339 return radeon_bo_pin_restricted(bo, domain, 0, gpu_addr);
340 }
341
342 int radeon_bo_unpin(struct radeon_bo *bo)
343 {
344 int r, i;
345
346 if (!bo->pin_count) {
347 dev_warn(bo->rdev->dev, "%p unpin not necessary\n", bo);
348 return 0;
349 }
350 bo->pin_count--;
351 if (bo->pin_count)
352 return 0;
353 for (i = 0; i < bo->placement.num_placement; i++) {
354 bo->placements[i].lpfn = 0;
355 bo->placements[i].flags &= ~TTM_PL_FLAG_NO_EVICT;
356 }
357 r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
358 if (likely(r == 0)) {
359 if (bo->tbo.mem.mem_type == TTM_PL_VRAM)
360 bo->rdev->vram_pin_size -= radeon_bo_size(bo);
361 else
362 bo->rdev->gart_pin_size -= radeon_bo_size(bo);
363 } else {
364 dev_err(bo->rdev->dev, "%p validate failed for unpin\n", bo);
365 }
366 return r;
367 }
368
369 int radeon_bo_evict_vram(struct radeon_device *rdev)
370 {
371 /* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */
372 if (0 && (rdev->flags & RADEON_IS_IGP)) {
373 if (rdev->mc.igp_sideport_enabled == false)
374 /* Useless to evict on IGP chips */
375 return 0;
376 }
377 return ttm_bo_evict_mm(&rdev->mman.bdev, TTM_PL_VRAM);
378 }
379
380 void radeon_bo_force_delete(struct radeon_device *rdev)
381 {
382 struct radeon_bo *bo, *n;
383
384 if (list_empty(&rdev->gem.objects)) {
385 return;
386 }
387 dev_err(rdev->dev, "Userspace still has active objects !\n");
388 list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
389 mutex_lock(&rdev->ddev->struct_mutex);
390 dev_err(rdev->dev, "%p %p %lu %lu force free\n",
391 &bo->gem_base, bo, (unsigned long)bo->gem_base.size,
392 *((unsigned long *)&bo->gem_base.refcount));
393 mutex_lock(&bo->rdev->gem.mutex);
394 list_del_init(&bo->list);
395 mutex_unlock(&bo->rdev->gem.mutex);
396 /* this should unref the ttm bo */
397 drm_gem_object_unreference(&bo->gem_base);
398 mutex_unlock(&rdev->ddev->struct_mutex);
399 }
400 }
401
402 int radeon_bo_init(struct radeon_device *rdev)
403 {
404 /* Add an MTRR for the VRAM */
405 if (!rdev->fastfb_working) {
406 rdev->mc.vram_mtrr = arch_phys_wc_add(rdev->mc.aper_base,
407 rdev->mc.aper_size);
408 }
409 DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n",
410 rdev->mc.mc_vram_size >> 20,
411 (unsigned long long)rdev->mc.aper_size >> 20);
412 DRM_INFO("RAM width %dbits %cDR\n",
413 rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S');
414 return radeon_ttm_init(rdev);
415 }
416
417 void radeon_bo_fini(struct radeon_device *rdev)
418 {
419 radeon_ttm_fini(rdev);
420 arch_phys_wc_del(rdev->mc.vram_mtrr);
421 }
422
423 /* Returns how many bytes TTM can move per IB.
424 */
425 static u64 radeon_bo_get_threshold_for_moves(struct radeon_device *rdev)
426 {
427 u64 real_vram_size = rdev->mc.real_vram_size;
428 u64 vram_usage = atomic64_read(&rdev->vram_usage);
429
430 /* This function is based on the current VRAM usage.
431 *
432 * - If all of VRAM is free, allow relocating the number of bytes that
433 * is equal to 1/4 of the size of VRAM for this IB.
434
435 * - If more than one half of VRAM is occupied, only allow relocating
436 * 1 MB of data for this IB.
437 *
438 * - From 0 to one half of used VRAM, the threshold decreases
439 * linearly.
440 * __________________
441 * 1/4 of -|\ |
442 * VRAM | \ |
443 * | \ |
444 * | \ |
445 * | \ |
446 * | \ |
447 * | \ |
448 * | \________|1 MB
449 * |----------------|
450 * VRAM 0 % 100 %
451 * used used
452 *
453 * Note: It's a threshold, not a limit. The threshold must be crossed
454 * for buffer relocations to stop, so any buffer of an arbitrary size
455 * can be moved as long as the threshold isn't crossed before
456 * the relocation takes place. We don't want to disable buffer
457 * relocations completely.
458 *
459 * The idea is that buffers should be placed in VRAM at creation time
460 * and TTM should only do a minimum number of relocations during
461 * command submission. In practice, you need to submit at least
462 * a dozen IBs to move all buffers to VRAM if they are in GTT.
463 *
464 * Also, things can get pretty crazy under memory pressure and actual
465 * VRAM usage can change a lot, so playing safe even at 50% does
466 * consistently increase performance.
467 */
468
469 u64 half_vram = real_vram_size >> 1;
470 u64 half_free_vram = vram_usage >= half_vram ? 0 : half_vram - vram_usage;
471 u64 bytes_moved_threshold = half_free_vram >> 1;
472 return max(bytes_moved_threshold, 1024*1024ull);
473 }
474
475 int radeon_bo_list_validate(struct radeon_device *rdev,
476 struct ww_acquire_ctx *ticket,
477 struct list_head *head, int ring)
478 {
479 struct radeon_cs_reloc *lobj;
480 struct radeon_bo *bo;
481 int r;
482 u64 bytes_moved = 0, initial_bytes_moved;
483 u64 bytes_moved_threshold = radeon_bo_get_threshold_for_moves(rdev);
484
485 r = ttm_eu_reserve_buffers(ticket, head, true);
486 if (unlikely(r != 0)) {
487 return r;
488 }
489
490 list_for_each_entry(lobj, head, tv.head) {
491 bo = lobj->robj;
492 if (!bo->pin_count) {
493 u32 domain = lobj->prefered_domains;
494 u32 allowed = lobj->allowed_domains;
495 u32 current_domain =
496 radeon_mem_type_to_domain(bo->tbo.mem.mem_type);
497
498 /* Check if this buffer will be moved and don't move it
499 * if we have moved too many buffers for this IB already.
500 *
501 * Note that this allows moving at least one buffer of
502 * any size, because it doesn't take the current "bo"
503 * into account. We don't want to disallow buffer moves
504 * completely.
505 */
506 if ((allowed & current_domain) != 0 &&
507 (domain & current_domain) == 0 && /* will be moved */
508 bytes_moved > bytes_moved_threshold) {
509 /* don't move it */
510 domain = current_domain;
511 }
512
513 retry:
514 radeon_ttm_placement_from_domain(bo, domain);
515 if (ring == R600_RING_TYPE_UVD_INDEX)
516 radeon_uvd_force_into_uvd_segment(bo, allowed);
517
518 initial_bytes_moved = atomic64_read(&rdev->num_bytes_moved);
519 r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
520 bytes_moved += atomic64_read(&rdev->num_bytes_moved) -
521 initial_bytes_moved;
522
523 if (unlikely(r)) {
524 if (r != -ERESTARTSYS &&
525 domain != lobj->allowed_domains) {
526 domain = lobj->allowed_domains;
527 goto retry;
528 }
529 ttm_eu_backoff_reservation(ticket, head);
530 return r;
531 }
532 }
533 lobj->gpu_offset = radeon_bo_gpu_offset(bo);
534 lobj->tiling_flags = bo->tiling_flags;
535 }
536 return 0;
537 }
538
539 int radeon_bo_fbdev_mmap(struct radeon_bo *bo,
540 struct vm_area_struct *vma)
541 {
542 return ttm_fbdev_mmap(vma, &bo->tbo);
543 }
544
545 int radeon_bo_get_surface_reg(struct radeon_bo *bo)
546 {
547 struct radeon_device *rdev = bo->rdev;
548 struct radeon_surface_reg *reg;
549 struct radeon_bo *old_object;
550 int steal;
551 int i;
552
553 lockdep_assert_held(&bo->tbo.resv->lock.base);
554
555 if (!bo->tiling_flags)
556 return 0;
557
558 if (bo->surface_reg >= 0) {
559 reg = &rdev->surface_regs[bo->surface_reg];
560 i = bo->surface_reg;
561 goto out;
562 }
563
564 steal = -1;
565 for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {
566
567 reg = &rdev->surface_regs[i];
568 if (!reg->bo)
569 break;
570
571 old_object = reg->bo;
572 if (old_object->pin_count == 0)
573 steal = i;
574 }
575
576 /* if we are all out */
577 if (i == RADEON_GEM_MAX_SURFACES) {
578 if (steal == -1)
579 return -ENOMEM;
580 /* find someone with a surface reg and nuke their BO */
581 reg = &rdev->surface_regs[steal];
582 old_object = reg->bo;
583 /* blow away the mapping */
584 DRM_DEBUG("stealing surface reg %d from %p\n", steal, old_object);
585 ttm_bo_unmap_virtual(&old_object->tbo);
586 old_object->surface_reg = -1;
587 i = steal;
588 }
589
590 bo->surface_reg = i;
591 reg->bo = bo;
592
593 out:
594 radeon_set_surface_reg(rdev, i, bo->tiling_flags, bo->pitch,
595 bo->tbo.mem.start << PAGE_SHIFT,
596 bo->tbo.num_pages << PAGE_SHIFT);
597 return 0;
598 }
599
600 static void radeon_bo_clear_surface_reg(struct radeon_bo *bo)
601 {
602 struct radeon_device *rdev = bo->rdev;
603 struct radeon_surface_reg *reg;
604
605 if (bo->surface_reg == -1)
606 return;
607
608 reg = &rdev->surface_regs[bo->surface_reg];
609 radeon_clear_surface_reg(rdev, bo->surface_reg);
610
611 reg->bo = NULL;
612 bo->surface_reg = -1;
613 }
614
615 int radeon_bo_set_tiling_flags(struct radeon_bo *bo,
616 uint32_t tiling_flags, uint32_t pitch)
617 {
618 struct radeon_device *rdev = bo->rdev;
619 int r;
620
621 if (rdev->family >= CHIP_CEDAR) {
622 unsigned bankw, bankh, mtaspect, tilesplit, stilesplit;
623
624 bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK;
625 bankh = (tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK;
626 mtaspect = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK;
627 tilesplit = (tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MASK;
628 stilesplit = (tiling_flags >> RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK;
629 switch (bankw) {
630 case 0:
631 case 1:
632 case 2:
633 case 4:
634 case 8:
635 break;
636 default:
637 return -EINVAL;
638 }
639 switch (bankh) {
640 case 0:
641 case 1:
642 case 2:
643 case 4:
644 case 8:
645 break;
646 default:
647 return -EINVAL;
648 }
649 switch (mtaspect) {
650 case 0:
651 case 1:
652 case 2:
653 case 4:
654 case 8:
655 break;
656 default:
657 return -EINVAL;
658 }
659 if (tilesplit > 6) {
660 return -EINVAL;
661 }
662 if (stilesplit > 6) {
663 return -EINVAL;
664 }
665 }
666 r = radeon_bo_reserve(bo, false);
667 if (unlikely(r != 0))
668 return r;
669 bo->tiling_flags = tiling_flags;
670 bo->pitch = pitch;
671 radeon_bo_unreserve(bo);
672 return 0;
673 }
674
675 void radeon_bo_get_tiling_flags(struct radeon_bo *bo,
676 uint32_t *tiling_flags,
677 uint32_t *pitch)
678 {
679 lockdep_assert_held(&bo->tbo.resv->lock.base);
680
681 if (tiling_flags)
682 *tiling_flags = bo->tiling_flags;
683 if (pitch)
684 *pitch = bo->pitch;
685 }
686
687 int radeon_bo_check_tiling(struct radeon_bo *bo, bool has_moved,
688 bool force_drop)
689 {
690 if (!force_drop)
691 lockdep_assert_held(&bo->tbo.resv->lock.base);
692
693 if (!(bo->tiling_flags & RADEON_TILING_SURFACE))
694 return 0;
695
696 if (force_drop) {
697 radeon_bo_clear_surface_reg(bo);
698 return 0;
699 }
700
701 if (bo->tbo.mem.mem_type != TTM_PL_VRAM) {
702 if (!has_moved)
703 return 0;
704
705 if (bo->surface_reg >= 0)
706 radeon_bo_clear_surface_reg(bo);
707 return 0;
708 }
709
710 if ((bo->surface_reg >= 0) && !has_moved)
711 return 0;
712
713 return radeon_bo_get_surface_reg(bo);
714 }
715
716 void radeon_bo_move_notify(struct ttm_buffer_object *bo,
717 struct ttm_mem_reg *new_mem)
718 {
719 struct radeon_bo *rbo;
720
721 if (!radeon_ttm_bo_is_radeon_bo(bo))
722 return;
723
724 rbo = container_of(bo, struct radeon_bo, tbo);
725 radeon_bo_check_tiling(rbo, 0, 1);
726 radeon_vm_bo_invalidate(rbo->rdev, rbo);
727
728 /* update statistics */
729 if (!new_mem)
730 return;
731
732 radeon_update_memory_usage(rbo, bo->mem.mem_type, -1);
733 radeon_update_memory_usage(rbo, new_mem->mem_type, 1);
734 }
735
736 int radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
737 {
738 struct radeon_device *rdev;
739 struct radeon_bo *rbo;
740 unsigned long offset, size;
741 int r;
742
743 if (!radeon_ttm_bo_is_radeon_bo(bo))
744 return 0;
745 rbo = container_of(bo, struct radeon_bo, tbo);
746 radeon_bo_check_tiling(rbo, 0, 0);
747 rdev = rbo->rdev;
748 if (bo->mem.mem_type != TTM_PL_VRAM)
749 return 0;
750
751 size = bo->mem.num_pages << PAGE_SHIFT;
752 offset = bo->mem.start << PAGE_SHIFT;
753 if ((offset + size) <= rdev->mc.visible_vram_size)
754 return 0;
755
756 /* hurrah the memory is not visible ! */
757 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_VRAM);
758 rbo->placements[0].lpfn = rdev->mc.visible_vram_size >> PAGE_SHIFT;
759 r = ttm_bo_validate(bo, &rbo->placement, false, false);
760 if (unlikely(r == -ENOMEM)) {
761 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_GTT);
762 return ttm_bo_validate(bo, &rbo->placement, false, false);
763 } else if (unlikely(r != 0)) {
764 return r;
765 }
766
767 offset = bo->mem.start << PAGE_SHIFT;
768 /* this should never happen */
769 if ((offset + size) > rdev->mc.visible_vram_size)
770 return -EINVAL;
771
772 return 0;
773 }
774
775 int radeon_bo_wait(struct radeon_bo *bo, u32 *mem_type, bool no_wait)
776 {
777 int r;
778
779 r = ttm_bo_reserve(&bo->tbo, true, no_wait, false, NULL);
780 if (unlikely(r != 0))
781 return r;
782 if (mem_type)
783 *mem_type = bo->tbo.mem.mem_type;
784
785 r = ttm_bo_wait(&bo->tbo, true, true, no_wait);
786 ttm_bo_unreserve(&bo->tbo);
787 return r;
788 }
Linux kernel - Deliverables
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