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[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon_object.c
1 /*
2 * Copyright 2009 Jerome Glisse.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
20 *
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
23 * of the Software.
24 *
25 */
26 /*
27 * Authors:
28 * Jerome Glisse <glisse@freedesktop.org>
29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
30 * Dave Airlie
31 */
32 #include <linux/list.h>
33 #include <linux/slab.h>
34 #include <drm/drmP.h>
35 #include <drm/radeon_drm.h>
36 #include "radeon.h"
37 #include "radeon_trace.h"
38
39
40 int radeon_ttm_init(struct radeon_device *rdev);
41 void radeon_ttm_fini(struct radeon_device *rdev);
42 static void radeon_bo_clear_surface_reg(struct radeon_bo *bo);
43
44 /*
45 * To exclude mutual BO access we rely on bo_reserve exclusion, as all
46 * function are calling it.
47 */
48
49 static void radeon_bo_clear_va(struct radeon_bo *bo)
50 {
51 struct radeon_bo_va *bo_va, *tmp;
52
53 list_for_each_entry_safe(bo_va, tmp, &bo->va, bo_list) {
54 /* remove from all vm address space */
55 radeon_vm_bo_rmv(bo->rdev, bo_va);
56 }
57 }
58
59 static void radeon_update_memory_usage(struct radeon_bo *bo,
60 unsigned mem_type, int sign)
61 {
62 struct radeon_device *rdev = bo->rdev;
63 u64 size = (u64)bo->tbo.num_pages << PAGE_SHIFT;
64
65 switch (mem_type) {
66 case TTM_PL_TT:
67 if (sign > 0)
68 atomic64_add(size, &rdev->gtt_usage);
69 else
70 atomic64_sub(size, &rdev->gtt_usage);
71 break;
72 case TTM_PL_VRAM:
73 if (sign > 0)
74 atomic64_add(size, &rdev->vram_usage);
75 else
76 atomic64_sub(size, &rdev->vram_usage);
77 break;
78 }
79 }
80
81 static void radeon_ttm_bo_destroy(struct ttm_buffer_object *tbo)
82 {
83 struct radeon_bo *bo;
84
85 bo = container_of(tbo, struct radeon_bo, tbo);
86
87 radeon_update_memory_usage(bo, bo->tbo.mem.mem_type, -1);
88
89 mutex_lock(&bo->rdev->gem.mutex);
90 list_del_init(&bo->list);
91 mutex_unlock(&bo->rdev->gem.mutex);
92 radeon_bo_clear_surface_reg(bo);
93 radeon_bo_clear_va(bo);
94 drm_gem_object_release(&bo->gem_base);
95 kfree(bo);
96 }
97
98 bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo)
99 {
100 if (bo->destroy == &radeon_ttm_bo_destroy)
101 return true;
102 return false;
103 }
104
105 void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain)
106 {
107 u32 c = 0;
108
109 rbo->placement.fpfn = 0;
110 rbo->placement.lpfn = 0;
111 rbo->placement.placement = rbo->placements;
112 rbo->placement.busy_placement = rbo->placements;
113 if (domain & RADEON_GEM_DOMAIN_VRAM)
114 rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED |
115 TTM_PL_FLAG_VRAM;
116 if (domain & RADEON_GEM_DOMAIN_GTT) {
117 if (rbo->rdev->flags & RADEON_IS_AGP) {
118 rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_TT;
119 } else {
120 rbo->placements[c++] = TTM_PL_FLAG_CACHED | TTM_PL_FLAG_TT;
121 }
122 }
123 if (domain & RADEON_GEM_DOMAIN_CPU) {
124 if (rbo->rdev->flags & RADEON_IS_AGP) {
125 rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_SYSTEM;
126 } else {
127 rbo->placements[c++] = TTM_PL_FLAG_CACHED | TTM_PL_FLAG_SYSTEM;
128 }
129 }
130 if (!c)
131 rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM;
132 rbo->placement.num_placement = c;
133 rbo->placement.num_busy_placement = c;
134 }
135
136 int radeon_bo_create(struct radeon_device *rdev,
137 unsigned long size, int byte_align, bool kernel, u32 domain,
138 struct sg_table *sg, struct radeon_bo **bo_ptr)
139 {
140 struct radeon_bo *bo;
141 enum ttm_bo_type type;
142 unsigned long page_align = roundup(byte_align, PAGE_SIZE) >> PAGE_SHIFT;
143 size_t acc_size;
144 int r;
145
146 size = ALIGN(size, PAGE_SIZE);
147
148 rdev->mman.bdev.dev_mapping = rdev->ddev->dev_mapping;
149 if (kernel) {
150 type = ttm_bo_type_kernel;
151 } else if (sg) {
152 type = ttm_bo_type_sg;
153 } else {
154 type = ttm_bo_type_device;
155 }
156 *bo_ptr = NULL;
157
158 acc_size = ttm_bo_dma_acc_size(&rdev->mman.bdev, size,
159 sizeof(struct radeon_bo));
160
161 bo = kzalloc(sizeof(struct radeon_bo), GFP_KERNEL);
162 if (bo == NULL)
163 return -ENOMEM;
164 r = drm_gem_object_init(rdev->ddev, &bo->gem_base, size);
165 if (unlikely(r)) {
166 kfree(bo);
167 return r;
168 }
169 bo->rdev = rdev;
170 bo->surface_reg = -1;
171 INIT_LIST_HEAD(&bo->list);
172 INIT_LIST_HEAD(&bo->va);
173 bo->initial_domain = domain & (RADEON_GEM_DOMAIN_VRAM |
174 RADEON_GEM_DOMAIN_GTT |
175 RADEON_GEM_DOMAIN_CPU);
176 radeon_ttm_placement_from_domain(bo, domain);
177 /* Kernel allocation are uninterruptible */
178 down_read(&rdev->pm.mclk_lock);
179 r = ttm_bo_init(&rdev->mman.bdev, &bo->tbo, size, type,
180 &bo->placement, page_align, !kernel, NULL,
181 acc_size, sg, &radeon_ttm_bo_destroy);
182 up_read(&rdev->pm.mclk_lock);
183 if (unlikely(r != 0)) {
184 return r;
185 }
186 *bo_ptr = bo;
187
188 trace_radeon_bo_create(bo);
189
190 return 0;
191 }
192
193 int radeon_bo_kmap(struct radeon_bo *bo, void **ptr)
194 {
195 bool is_iomem;
196 int r;
197
198 if (bo->kptr) {
199 if (ptr) {
200 *ptr = bo->kptr;
201 }
202 return 0;
203 }
204 r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap);
205 if (r) {
206 return r;
207 }
208 bo->kptr = ttm_kmap_obj_virtual(&bo->kmap, &is_iomem);
209 if (ptr) {
210 *ptr = bo->kptr;
211 }
212 radeon_bo_check_tiling(bo, 0, 0);
213 return 0;
214 }
215
216 void radeon_bo_kunmap(struct radeon_bo *bo)
217 {
218 if (bo->kptr == NULL)
219 return;
220 bo->kptr = NULL;
221 radeon_bo_check_tiling(bo, 0, 0);
222 ttm_bo_kunmap(&bo->kmap);
223 }
224
225 void radeon_bo_unref(struct radeon_bo **bo)
226 {
227 struct ttm_buffer_object *tbo;
228 struct radeon_device *rdev;
229
230 if ((*bo) == NULL)
231 return;
232 rdev = (*bo)->rdev;
233 tbo = &((*bo)->tbo);
234 down_read(&rdev->pm.mclk_lock);
235 ttm_bo_unref(&tbo);
236 up_read(&rdev->pm.mclk_lock);
237 if (tbo == NULL)
238 *bo = NULL;
239 }
240
241 int radeon_bo_pin_restricted(struct radeon_bo *bo, u32 domain, u64 max_offset,
242 u64 *gpu_addr)
243 {
244 int r, i;
245
246 if (bo->pin_count) {
247 bo->pin_count++;
248 if (gpu_addr)
249 *gpu_addr = radeon_bo_gpu_offset(bo);
250
251 if (max_offset != 0) {
252 u64 domain_start;
253
254 if (domain == RADEON_GEM_DOMAIN_VRAM)
255 domain_start = bo->rdev->mc.vram_start;
256 else
257 domain_start = bo->rdev->mc.gtt_start;
258 WARN_ON_ONCE(max_offset <
259 (radeon_bo_gpu_offset(bo) - domain_start));
260 }
261
262 return 0;
263 }
264 radeon_ttm_placement_from_domain(bo, domain);
265 if (domain == RADEON_GEM_DOMAIN_VRAM) {
266 /* force to pin into visible video ram */
267 bo->placement.lpfn = bo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
268 }
269 if (max_offset) {
270 u64 lpfn = max_offset >> PAGE_SHIFT;
271
272 if (!bo->placement.lpfn)
273 bo->placement.lpfn = bo->rdev->mc.gtt_size >> PAGE_SHIFT;
274
275 if (lpfn < bo->placement.lpfn)
276 bo->placement.lpfn = lpfn;
277 }
278 for (i = 0; i < bo->placement.num_placement; i++)
279 bo->placements[i] |= TTM_PL_FLAG_NO_EVICT;
280 r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
281 if (likely(r == 0)) {
282 bo->pin_count = 1;
283 if (gpu_addr != NULL)
284 *gpu_addr = radeon_bo_gpu_offset(bo);
285 }
286 if (unlikely(r != 0))
287 dev_err(bo->rdev->dev, "%p pin failed\n", bo);
288 return r;
289 }
290
291 int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr)
292 {
293 return radeon_bo_pin_restricted(bo, domain, 0, gpu_addr);
294 }
295
296 int radeon_bo_unpin(struct radeon_bo *bo)
297 {
298 int r, i;
299
300 if (!bo->pin_count) {
301 dev_warn(bo->rdev->dev, "%p unpin not necessary\n", bo);
302 return 0;
303 }
304 bo->pin_count--;
305 if (bo->pin_count)
306 return 0;
307 for (i = 0; i < bo->placement.num_placement; i++)
308 bo->placements[i] &= ~TTM_PL_FLAG_NO_EVICT;
309 r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
310 if (unlikely(r != 0))
311 dev_err(bo->rdev->dev, "%p validate failed for unpin\n", bo);
312 return r;
313 }
314
315 int radeon_bo_evict_vram(struct radeon_device *rdev)
316 {
317 /* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */
318 if (0 && (rdev->flags & RADEON_IS_IGP)) {
319 if (rdev->mc.igp_sideport_enabled == false)
320 /* Useless to evict on IGP chips */
321 return 0;
322 }
323 return ttm_bo_evict_mm(&rdev->mman.bdev, TTM_PL_VRAM);
324 }
325
326 void radeon_bo_force_delete(struct radeon_device *rdev)
327 {
328 struct radeon_bo *bo, *n;
329
330 if (list_empty(&rdev->gem.objects)) {
331 return;
332 }
333 dev_err(rdev->dev, "Userspace still has active objects !\n");
334 list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
335 mutex_lock(&rdev->ddev->struct_mutex);
336 dev_err(rdev->dev, "%p %p %lu %lu force free\n",
337 &bo->gem_base, bo, (unsigned long)bo->gem_base.size,
338 *((unsigned long *)&bo->gem_base.refcount));
339 mutex_lock(&bo->rdev->gem.mutex);
340 list_del_init(&bo->list);
341 mutex_unlock(&bo->rdev->gem.mutex);
342 /* this should unref the ttm bo */
343 drm_gem_object_unreference(&bo->gem_base);
344 mutex_unlock(&rdev->ddev->struct_mutex);
345 }
346 }
347
348 int radeon_bo_init(struct radeon_device *rdev)
349 {
350 /* Add an MTRR for the VRAM */
351 if (!rdev->fastfb_working) {
352 rdev->mc.vram_mtrr = arch_phys_wc_add(rdev->mc.aper_base,
353 rdev->mc.aper_size);
354 }
355 DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n",
356 rdev->mc.mc_vram_size >> 20,
357 (unsigned long long)rdev->mc.aper_size >> 20);
358 DRM_INFO("RAM width %dbits %cDR\n",
359 rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S');
360 return radeon_ttm_init(rdev);
361 }
362
363 void radeon_bo_fini(struct radeon_device *rdev)
364 {
365 radeon_ttm_fini(rdev);
366 arch_phys_wc_del(rdev->mc.vram_mtrr);
367 }
368
369 /* Returns how many bytes TTM can move per IB.
370 */
371 static u64 radeon_bo_get_threshold_for_moves(struct radeon_device *rdev)
372 {
373 u64 real_vram_size = rdev->mc.real_vram_size;
374 u64 vram_usage = atomic64_read(&rdev->vram_usage);
375
376 /* This function is based on the current VRAM usage.
377 *
378 * - If all of VRAM is free, allow relocating the number of bytes that
379 * is equal to 1/4 of the size of VRAM for this IB.
380
381 * - If more than one half of VRAM is occupied, only allow relocating
382 * 1 MB of data for this IB.
383 *
384 * - From 0 to one half of used VRAM, the threshold decreases
385 * linearly.
386 * __________________
387 * 1/4 of -|\ |
388 * VRAM | \ |
389 * | \ |
390 * | \ |
391 * | \ |
392 * | \ |
393 * | \ |
394 * | \________|1 MB
395 * |----------------|
396 * VRAM 0 % 100 %
397 * used used
398 *
399 * Note: It's a threshold, not a limit. The threshold must be crossed
400 * for buffer relocations to stop, so any buffer of an arbitrary size
401 * can be moved as long as the threshold isn't crossed before
402 * the relocation takes place. We don't want to disable buffer
403 * relocations completely.
404 *
405 * The idea is that buffers should be placed in VRAM at creation time
406 * and TTM should only do a minimum number of relocations during
407 * command submission. In practice, you need to submit at least
408 * a dozen IBs to move all buffers to VRAM if they are in GTT.
409 *
410 * Also, things can get pretty crazy under memory pressure and actual
411 * VRAM usage can change a lot, so playing safe even at 50% does
412 * consistently increase performance.
413 */
414
415 u64 half_vram = real_vram_size >> 1;
416 u64 half_free_vram = vram_usage >= half_vram ? 0 : half_vram - vram_usage;
417 u64 bytes_moved_threshold = half_free_vram >> 1;
418 return max(bytes_moved_threshold, 1024*1024ull);
419 }
420
421 int radeon_bo_list_validate(struct radeon_device *rdev,
422 struct ww_acquire_ctx *ticket,
423 struct list_head *head, int ring)
424 {
425 struct radeon_bo_list *lobj;
426 struct radeon_bo *bo;
427 int r;
428 u64 bytes_moved = 0, initial_bytes_moved;
429 u64 bytes_moved_threshold = radeon_bo_get_threshold_for_moves(rdev);
430
431 r = ttm_eu_reserve_buffers(ticket, head);
432 if (unlikely(r != 0)) {
433 return r;
434 }
435
436 list_for_each_entry(lobj, head, tv.head) {
437 bo = lobj->bo;
438 if (!bo->pin_count) {
439 u32 domain = lobj->domain;
440 u32 current_domain =
441 radeon_mem_type_to_domain(bo->tbo.mem.mem_type);
442
443 /* Check if this buffer will be moved and don't move it
444 * if we have moved too many buffers for this IB already.
445 *
446 * Note that this allows moving at least one buffer of
447 * any size, because it doesn't take the current "bo"
448 * into account. We don't want to disallow buffer moves
449 * completely.
450 */
451 if (current_domain != RADEON_GEM_DOMAIN_CPU &&
452 (domain & current_domain) == 0 && /* will be moved */
453 bytes_moved > bytes_moved_threshold) {
454 /* don't move it */
455 domain = current_domain;
456 }
457
458 retry:
459 radeon_ttm_placement_from_domain(bo, domain);
460 if (ring == R600_RING_TYPE_UVD_INDEX)
461 radeon_uvd_force_into_uvd_segment(bo);
462
463 initial_bytes_moved = atomic64_read(&rdev->num_bytes_moved);
464 r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
465 bytes_moved += atomic64_read(&rdev->num_bytes_moved) -
466 initial_bytes_moved;
467
468 if (unlikely(r)) {
469 if (r != -ERESTARTSYS && domain != lobj->alt_domain) {
470 domain = lobj->alt_domain;
471 goto retry;
472 }
473 ttm_eu_backoff_reservation(ticket, head);
474 return r;
475 }
476 }
477 lobj->gpu_offset = radeon_bo_gpu_offset(bo);
478 lobj->tiling_flags = bo->tiling_flags;
479 }
480 return 0;
481 }
482
483 int radeon_bo_fbdev_mmap(struct radeon_bo *bo,
484 struct vm_area_struct *vma)
485 {
486 return ttm_fbdev_mmap(vma, &bo->tbo);
487 }
488
489 int radeon_bo_get_surface_reg(struct radeon_bo *bo)
490 {
491 struct radeon_device *rdev = bo->rdev;
492 struct radeon_surface_reg *reg;
493 struct radeon_bo *old_object;
494 int steal;
495 int i;
496
497 lockdep_assert_held(&bo->tbo.resv->lock.base);
498
499 if (!bo->tiling_flags)
500 return 0;
501
502 if (bo->surface_reg >= 0) {
503 reg = &rdev->surface_regs[bo->surface_reg];
504 i = bo->surface_reg;
505 goto out;
506 }
507
508 steal = -1;
509 for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {
510
511 reg = &rdev->surface_regs[i];
512 if (!reg->bo)
513 break;
514
515 old_object = reg->bo;
516 if (old_object->pin_count == 0)
517 steal = i;
518 }
519
520 /* if we are all out */
521 if (i == RADEON_GEM_MAX_SURFACES) {
522 if (steal == -1)
523 return -ENOMEM;
524 /* find someone with a surface reg and nuke their BO */
525 reg = &rdev->surface_regs[steal];
526 old_object = reg->bo;
527 /* blow away the mapping */
528 DRM_DEBUG("stealing surface reg %d from %p\n", steal, old_object);
529 ttm_bo_unmap_virtual(&old_object->tbo);
530 old_object->surface_reg = -1;
531 i = steal;
532 }
533
534 bo->surface_reg = i;
535 reg->bo = bo;
536
537 out:
538 radeon_set_surface_reg(rdev, i, bo->tiling_flags, bo->pitch,
539 bo->tbo.mem.start << PAGE_SHIFT,
540 bo->tbo.num_pages << PAGE_SHIFT);
541 return 0;
542 }
543
544 static void radeon_bo_clear_surface_reg(struct radeon_bo *bo)
545 {
546 struct radeon_device *rdev = bo->rdev;
547 struct radeon_surface_reg *reg;
548
549 if (bo->surface_reg == -1)
550 return;
551
552 reg = &rdev->surface_regs[bo->surface_reg];
553 radeon_clear_surface_reg(rdev, bo->surface_reg);
554
555 reg->bo = NULL;
556 bo->surface_reg = -1;
557 }
558
559 int radeon_bo_set_tiling_flags(struct radeon_bo *bo,
560 uint32_t tiling_flags, uint32_t pitch)
561 {
562 struct radeon_device *rdev = bo->rdev;
563 int r;
564
565 if (rdev->family >= CHIP_CEDAR) {
566 unsigned bankw, bankh, mtaspect, tilesplit, stilesplit;
567
568 bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK;
569 bankh = (tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK;
570 mtaspect = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK;
571 tilesplit = (tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MASK;
572 stilesplit = (tiling_flags >> RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK;
573 switch (bankw) {
574 case 0:
575 case 1:
576 case 2:
577 case 4:
578 case 8:
579 break;
580 default:
581 return -EINVAL;
582 }
583 switch (bankh) {
584 case 0:
585 case 1:
586 case 2:
587 case 4:
588 case 8:
589 break;
590 default:
591 return -EINVAL;
592 }
593 switch (mtaspect) {
594 case 0:
595 case 1:
596 case 2:
597 case 4:
598 case 8:
599 break;
600 default:
601 return -EINVAL;
602 }
603 if (tilesplit > 6) {
604 return -EINVAL;
605 }
606 if (stilesplit > 6) {
607 return -EINVAL;
608 }
609 }
610 r = radeon_bo_reserve(bo, false);
611 if (unlikely(r != 0))
612 return r;
613 bo->tiling_flags = tiling_flags;
614 bo->pitch = pitch;
615 radeon_bo_unreserve(bo);
616 return 0;
617 }
618
619 void radeon_bo_get_tiling_flags(struct radeon_bo *bo,
620 uint32_t *tiling_flags,
621 uint32_t *pitch)
622 {
623 lockdep_assert_held(&bo->tbo.resv->lock.base);
624
625 if (tiling_flags)
626 *tiling_flags = bo->tiling_flags;
627 if (pitch)
628 *pitch = bo->pitch;
629 }
630
631 int radeon_bo_check_tiling(struct radeon_bo *bo, bool has_moved,
632 bool force_drop)
633 {
634 if (!force_drop)
635 lockdep_assert_held(&bo->tbo.resv->lock.base);
636
637 if (!(bo->tiling_flags & RADEON_TILING_SURFACE))
638 return 0;
639
640 if (force_drop) {
641 radeon_bo_clear_surface_reg(bo);
642 return 0;
643 }
644
645 if (bo->tbo.mem.mem_type != TTM_PL_VRAM) {
646 if (!has_moved)
647 return 0;
648
649 if (bo->surface_reg >= 0)
650 radeon_bo_clear_surface_reg(bo);
651 return 0;
652 }
653
654 if ((bo->surface_reg >= 0) && !has_moved)
655 return 0;
656
657 return radeon_bo_get_surface_reg(bo);
658 }
659
660 void radeon_bo_move_notify(struct ttm_buffer_object *bo,
661 struct ttm_mem_reg *new_mem)
662 {
663 struct radeon_bo *rbo;
664
665 if (!radeon_ttm_bo_is_radeon_bo(bo))
666 return;
667
668 rbo = container_of(bo, struct radeon_bo, tbo);
669 radeon_bo_check_tiling(rbo, 0, 1);
670 radeon_vm_bo_invalidate(rbo->rdev, rbo);
671
672 /* update statistics */
673 if (!new_mem)
674 return;
675
676 radeon_update_memory_usage(rbo, bo->mem.mem_type, -1);
677 radeon_update_memory_usage(rbo, new_mem->mem_type, 1);
678 }
679
680 int radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
681 {
682 struct radeon_device *rdev;
683 struct radeon_bo *rbo;
684 unsigned long offset, size;
685 int r;
686
687 if (!radeon_ttm_bo_is_radeon_bo(bo))
688 return 0;
689 rbo = container_of(bo, struct radeon_bo, tbo);
690 radeon_bo_check_tiling(rbo, 0, 0);
691 rdev = rbo->rdev;
692 if (bo->mem.mem_type == TTM_PL_VRAM) {
693 size = bo->mem.num_pages << PAGE_SHIFT;
694 offset = bo->mem.start << PAGE_SHIFT;
695 if ((offset + size) > rdev->mc.visible_vram_size) {
696 /* hurrah the memory is not visible ! */
697 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_VRAM);
698 rbo->placement.lpfn = rdev->mc.visible_vram_size >> PAGE_SHIFT;
699 r = ttm_bo_validate(bo, &rbo->placement, false, false);
700 if (unlikely(r != 0))
701 return r;
702 offset = bo->mem.start << PAGE_SHIFT;
703 /* this should not happen */
704 if ((offset + size) > rdev->mc.visible_vram_size)
705 return -EINVAL;
706 }
707 }
708 return 0;
709 }
710
711 int radeon_bo_wait(struct radeon_bo *bo, u32 *mem_type, bool no_wait)
712 {
713 int r;
714
715 r = ttm_bo_reserve(&bo->tbo, true, no_wait, false, 0);
716 if (unlikely(r != 0))
717 return r;
718 spin_lock(&bo->tbo.bdev->fence_lock);
719 if (mem_type)
720 *mem_type = bo->tbo.mem.mem_type;
721 if (bo->tbo.sync_obj)
722 r = ttm_bo_wait(&bo->tbo, true, true, no_wait);
723 spin_unlock(&bo->tbo.bdev->fence_lock);
724 ttm_bo_unreserve(&bo->tbo);
725 return r;
726 }
Linux kernel - Deliverables
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