2 * Copyright 2009 Jerome Glisse.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
28 * Jerome Glisse <glisse@freedesktop.org>
29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
32 #include <linux/list.h>
33 #include <linux/slab.h>
35 #include <drm/radeon_drm.h>
37 #include "radeon_trace.h"
40 int radeon_ttm_init(struct radeon_device
*rdev
);
41 void radeon_ttm_fini(struct radeon_device
*rdev
);
42 static void radeon_bo_clear_surface_reg(struct radeon_bo
*bo
);
45 * To exclude mutual BO access we rely on bo_reserve exclusion, as all
46 * function are calling it.
49 static void radeon_update_memory_usage(struct radeon_bo
*bo
,
50 unsigned mem_type
, int sign
)
52 struct radeon_device
*rdev
= bo
->rdev
;
53 u64 size
= (u64
)bo
->tbo
.num_pages
<< PAGE_SHIFT
;
58 atomic64_add(size
, &rdev
->gtt_usage
);
60 atomic64_sub(size
, &rdev
->gtt_usage
);
64 atomic64_add(size
, &rdev
->vram_usage
);
66 atomic64_sub(size
, &rdev
->vram_usage
);
71 static void radeon_ttm_bo_destroy(struct ttm_buffer_object
*tbo
)
75 bo
= container_of(tbo
, struct radeon_bo
, tbo
);
77 radeon_update_memory_usage(bo
, bo
->tbo
.mem
.mem_type
, -1);
78 radeon_mn_unregister(bo
);
80 mutex_lock(&bo
->rdev
->gem
.mutex
);
81 list_del_init(&bo
->list
);
82 mutex_unlock(&bo
->rdev
->gem
.mutex
);
83 radeon_bo_clear_surface_reg(bo
);
84 WARN_ON(!list_empty(&bo
->va
));
85 drm_gem_object_release(&bo
->gem_base
);
89 bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object
*bo
)
91 if (bo
->destroy
== &radeon_ttm_bo_destroy
)
96 void radeon_ttm_placement_from_domain(struct radeon_bo
*rbo
, u32 domain
)
100 rbo
->placement
.placement
= rbo
->placements
;
101 rbo
->placement
.busy_placement
= rbo
->placements
;
102 if (domain
& RADEON_GEM_DOMAIN_VRAM
) {
103 /* Try placing BOs which don't need CPU access outside of the
104 * CPU accessible part of VRAM
106 if ((rbo
->flags
& RADEON_GEM_NO_CPU_ACCESS
) &&
107 rbo
->rdev
->mc
.visible_vram_size
< rbo
->rdev
->mc
.real_vram_size
) {
108 rbo
->placements
[c
].fpfn
=
109 rbo
->rdev
->mc
.visible_vram_size
>> PAGE_SHIFT
;
110 rbo
->placements
[c
++].flags
= TTM_PL_FLAG_WC
|
111 TTM_PL_FLAG_UNCACHED
|
115 rbo
->placements
[c
].fpfn
= 0;
116 rbo
->placements
[c
++].flags
= TTM_PL_FLAG_WC
|
117 TTM_PL_FLAG_UNCACHED
|
121 if (domain
& RADEON_GEM_DOMAIN_GTT
) {
122 if (rbo
->flags
& RADEON_GEM_GTT_UC
) {
123 rbo
->placements
[c
].fpfn
= 0;
124 rbo
->placements
[c
++].flags
= TTM_PL_FLAG_UNCACHED
|
127 } else if ((rbo
->flags
& RADEON_GEM_GTT_WC
) ||
128 (rbo
->rdev
->flags
& RADEON_IS_AGP
)) {
129 rbo
->placements
[c
].fpfn
= 0;
130 rbo
->placements
[c
++].flags
= TTM_PL_FLAG_WC
|
131 TTM_PL_FLAG_UNCACHED
|
134 rbo
->placements
[c
].fpfn
= 0;
135 rbo
->placements
[c
++].flags
= TTM_PL_FLAG_CACHED
|
140 if (domain
& RADEON_GEM_DOMAIN_CPU
) {
141 if (rbo
->flags
& RADEON_GEM_GTT_UC
) {
142 rbo
->placements
[c
].fpfn
= 0;
143 rbo
->placements
[c
++].flags
= TTM_PL_FLAG_UNCACHED
|
146 } else if ((rbo
->flags
& RADEON_GEM_GTT_WC
) ||
147 rbo
->rdev
->flags
& RADEON_IS_AGP
) {
148 rbo
->placements
[c
].fpfn
= 0;
149 rbo
->placements
[c
++].flags
= TTM_PL_FLAG_WC
|
150 TTM_PL_FLAG_UNCACHED
|
153 rbo
->placements
[c
].fpfn
= 0;
154 rbo
->placements
[c
++].flags
= TTM_PL_FLAG_CACHED
|
159 rbo
->placements
[c
].fpfn
= 0;
160 rbo
->placements
[c
++].flags
= TTM_PL_MASK_CACHING
|
164 rbo
->placement
.num_placement
= c
;
165 rbo
->placement
.num_busy_placement
= c
;
167 for (i
= 0; i
< c
; ++i
) {
168 if ((rbo
->flags
& RADEON_GEM_CPU_ACCESS
) &&
169 (rbo
->placements
[i
].flags
& TTM_PL_FLAG_VRAM
) &&
170 !rbo
->placements
[i
].fpfn
)
171 rbo
->placements
[i
].lpfn
=
172 rbo
->rdev
->mc
.visible_vram_size
>> PAGE_SHIFT
;
174 rbo
->placements
[i
].lpfn
= 0;
178 int radeon_bo_create(struct radeon_device
*rdev
,
179 unsigned long size
, int byte_align
, bool kernel
,
180 u32 domain
, u32 flags
, struct sg_table
*sg
,
181 struct reservation_object
*resv
,
182 struct radeon_bo
**bo_ptr
)
184 struct radeon_bo
*bo
;
185 enum ttm_bo_type type
;
186 unsigned long page_align
= roundup(byte_align
, PAGE_SIZE
) >> PAGE_SHIFT
;
190 size
= ALIGN(size
, PAGE_SIZE
);
193 type
= ttm_bo_type_kernel
;
195 type
= ttm_bo_type_sg
;
197 type
= ttm_bo_type_device
;
201 acc_size
= ttm_bo_dma_acc_size(&rdev
->mman
.bdev
, size
,
202 sizeof(struct radeon_bo
));
204 bo
= kzalloc(sizeof(struct radeon_bo
), GFP_KERNEL
);
207 r
= drm_gem_object_init(rdev
->ddev
, &bo
->gem_base
, size
);
213 bo
->surface_reg
= -1;
214 INIT_LIST_HEAD(&bo
->list
);
215 INIT_LIST_HEAD(&bo
->va
);
216 bo
->initial_domain
= domain
& (RADEON_GEM_DOMAIN_VRAM
|
217 RADEON_GEM_DOMAIN_GTT
|
218 RADEON_GEM_DOMAIN_CPU
);
221 /* PCI GART is always snooped */
222 if (!(rdev
->flags
& RADEON_IS_PCIE
))
223 bo
->flags
&= ~(RADEON_GEM_GTT_WC
| RADEON_GEM_GTT_UC
);
226 /* XXX: Write-combined CPU mappings of GTT seem broken on 32-bit
227 * See https://bugs.freedesktop.org/show_bug.cgi?id=84627
229 bo
->flags
&= ~RADEON_GEM_GTT_WC
;
230 #elif defined(CONFIG_X86) && !defined(CONFIG_X86_PAT)
231 /* Don't try to enable write-combining when it can't work, or things
233 * See https://bugs.freedesktop.org/show_bug.cgi?id=88758
236 #warning Please enable CONFIG_MTRR and CONFIG_X86_PAT for better performance \
237 thanks to write-combining
239 DRM_INFO_ONCE("Please enable CONFIG_MTRR and CONFIG_X86_PAT for "
240 "better performance thanks to write-combining\n");
241 bo
->flags
&= ~RADEON_GEM_GTT_WC
;
244 radeon_ttm_placement_from_domain(bo
, domain
);
245 /* Kernel allocation are uninterruptible */
246 down_read(&rdev
->pm
.mclk_lock
);
247 r
= ttm_bo_init(&rdev
->mman
.bdev
, &bo
->tbo
, size
, type
,
248 &bo
->placement
, page_align
, !kernel
, NULL
,
249 acc_size
, sg
, resv
, &radeon_ttm_bo_destroy
);
250 up_read(&rdev
->pm
.mclk_lock
);
251 if (unlikely(r
!= 0)) {
256 trace_radeon_bo_create(bo
);
261 int radeon_bo_kmap(struct radeon_bo
*bo
, void **ptr
)
272 r
= ttm_bo_kmap(&bo
->tbo
, 0, bo
->tbo
.num_pages
, &bo
->kmap
);
276 bo
->kptr
= ttm_kmap_obj_virtual(&bo
->kmap
, &is_iomem
);
280 radeon_bo_check_tiling(bo
, 0, 0);
284 void radeon_bo_kunmap(struct radeon_bo
*bo
)
286 if (bo
->kptr
== NULL
)
289 radeon_bo_check_tiling(bo
, 0, 0);
290 ttm_bo_kunmap(&bo
->kmap
);
293 struct radeon_bo
*radeon_bo_ref(struct radeon_bo
*bo
)
298 ttm_bo_reference(&bo
->tbo
);
302 void radeon_bo_unref(struct radeon_bo
**bo
)
304 struct ttm_buffer_object
*tbo
;
305 struct radeon_device
*rdev
;
316 int radeon_bo_pin_restricted(struct radeon_bo
*bo
, u32 domain
, u64 max_offset
,
321 if (radeon_ttm_tt_has_userptr(bo
->tbo
.ttm
))
327 *gpu_addr
= radeon_bo_gpu_offset(bo
);
329 if (max_offset
!= 0) {
332 if (domain
== RADEON_GEM_DOMAIN_VRAM
)
333 domain_start
= bo
->rdev
->mc
.vram_start
;
335 domain_start
= bo
->rdev
->mc
.gtt_start
;
336 WARN_ON_ONCE(max_offset
<
337 (radeon_bo_gpu_offset(bo
) - domain_start
));
342 radeon_ttm_placement_from_domain(bo
, domain
);
343 for (i
= 0; i
< bo
->placement
.num_placement
; i
++) {
344 /* force to pin into visible video ram */
345 if ((bo
->placements
[i
].flags
& TTM_PL_FLAG_VRAM
) &&
346 !(bo
->flags
& RADEON_GEM_NO_CPU_ACCESS
) &&
347 (!max_offset
|| max_offset
> bo
->rdev
->mc
.visible_vram_size
))
348 bo
->placements
[i
].lpfn
=
349 bo
->rdev
->mc
.visible_vram_size
>> PAGE_SHIFT
;
351 bo
->placements
[i
].lpfn
= max_offset
>> PAGE_SHIFT
;
353 bo
->placements
[i
].flags
|= TTM_PL_FLAG_NO_EVICT
;
356 r
= ttm_bo_validate(&bo
->tbo
, &bo
->placement
, false, false);
357 if (likely(r
== 0)) {
359 if (gpu_addr
!= NULL
)
360 *gpu_addr
= radeon_bo_gpu_offset(bo
);
361 if (domain
== RADEON_GEM_DOMAIN_VRAM
)
362 bo
->rdev
->vram_pin_size
+= radeon_bo_size(bo
);
364 bo
->rdev
->gart_pin_size
+= radeon_bo_size(bo
);
366 dev_err(bo
->rdev
->dev
, "%p pin failed\n", bo
);
371 int radeon_bo_pin(struct radeon_bo
*bo
, u32 domain
, u64
*gpu_addr
)
373 return radeon_bo_pin_restricted(bo
, domain
, 0, gpu_addr
);
376 int radeon_bo_unpin(struct radeon_bo
*bo
)
380 if (!bo
->pin_count
) {
381 dev_warn(bo
->rdev
->dev
, "%p unpin not necessary\n", bo
);
387 for (i
= 0; i
< bo
->placement
.num_placement
; i
++) {
388 bo
->placements
[i
].lpfn
= 0;
389 bo
->placements
[i
].flags
&= ~TTM_PL_FLAG_NO_EVICT
;
391 r
= ttm_bo_validate(&bo
->tbo
, &bo
->placement
, false, false);
392 if (likely(r
== 0)) {
393 if (bo
->tbo
.mem
.mem_type
== TTM_PL_VRAM
)
394 bo
->rdev
->vram_pin_size
-= radeon_bo_size(bo
);
396 bo
->rdev
->gart_pin_size
-= radeon_bo_size(bo
);
398 dev_err(bo
->rdev
->dev
, "%p validate failed for unpin\n", bo
);
403 int radeon_bo_evict_vram(struct radeon_device
*rdev
)
405 /* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */
406 if (0 && (rdev
->flags
& RADEON_IS_IGP
)) {
407 if (rdev
->mc
.igp_sideport_enabled
== false)
408 /* Useless to evict on IGP chips */
411 return ttm_bo_evict_mm(&rdev
->mman
.bdev
, TTM_PL_VRAM
);
414 void radeon_bo_force_delete(struct radeon_device
*rdev
)
416 struct radeon_bo
*bo
, *n
;
418 if (list_empty(&rdev
->gem
.objects
)) {
421 dev_err(rdev
->dev
, "Userspace still has active objects !\n");
422 list_for_each_entry_safe(bo
, n
, &rdev
->gem
.objects
, list
) {
423 mutex_lock(&rdev
->ddev
->struct_mutex
);
424 dev_err(rdev
->dev
, "%p %p %lu %lu force free\n",
425 &bo
->gem_base
, bo
, (unsigned long)bo
->gem_base
.size
,
426 *((unsigned long *)&bo
->gem_base
.refcount
));
427 mutex_lock(&bo
->rdev
->gem
.mutex
);
428 list_del_init(&bo
->list
);
429 mutex_unlock(&bo
->rdev
->gem
.mutex
);
430 /* this should unref the ttm bo */
431 drm_gem_object_unreference(&bo
->gem_base
);
432 mutex_unlock(&rdev
->ddev
->struct_mutex
);
436 int radeon_bo_init(struct radeon_device
*rdev
)
438 /* Add an MTRR for the VRAM */
439 if (!rdev
->fastfb_working
) {
440 rdev
->mc
.vram_mtrr
= arch_phys_wc_add(rdev
->mc
.aper_base
,
443 DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n",
444 rdev
->mc
.mc_vram_size
>> 20,
445 (unsigned long long)rdev
->mc
.aper_size
>> 20);
446 DRM_INFO("RAM width %dbits %cDR\n",
447 rdev
->mc
.vram_width
, rdev
->mc
.vram_is_ddr
? 'D' : 'S');
448 return radeon_ttm_init(rdev
);
451 void radeon_bo_fini(struct radeon_device
*rdev
)
453 radeon_ttm_fini(rdev
);
454 arch_phys_wc_del(rdev
->mc
.vram_mtrr
);
457 /* Returns how many bytes TTM can move per IB.
459 static u64
radeon_bo_get_threshold_for_moves(struct radeon_device
*rdev
)
461 u64 real_vram_size
= rdev
->mc
.real_vram_size
;
462 u64 vram_usage
= atomic64_read(&rdev
->vram_usage
);
464 /* This function is based on the current VRAM usage.
466 * - If all of VRAM is free, allow relocating the number of bytes that
467 * is equal to 1/4 of the size of VRAM for this IB.
469 * - If more than one half of VRAM is occupied, only allow relocating
470 * 1 MB of data for this IB.
472 * - From 0 to one half of used VRAM, the threshold decreases
487 * Note: It's a threshold, not a limit. The threshold must be crossed
488 * for buffer relocations to stop, so any buffer of an arbitrary size
489 * can be moved as long as the threshold isn't crossed before
490 * the relocation takes place. We don't want to disable buffer
491 * relocations completely.
493 * The idea is that buffers should be placed in VRAM at creation time
494 * and TTM should only do a minimum number of relocations during
495 * command submission. In practice, you need to submit at least
496 * a dozen IBs to move all buffers to VRAM if they are in GTT.
498 * Also, things can get pretty crazy under memory pressure and actual
499 * VRAM usage can change a lot, so playing safe even at 50% does
500 * consistently increase performance.
503 u64 half_vram
= real_vram_size
>> 1;
504 u64 half_free_vram
= vram_usage
>= half_vram
? 0 : half_vram
- vram_usage
;
505 u64 bytes_moved_threshold
= half_free_vram
>> 1;
506 return max(bytes_moved_threshold
, 1024*1024ull);
509 int radeon_bo_list_validate(struct radeon_device
*rdev
,
510 struct ww_acquire_ctx
*ticket
,
511 struct list_head
*head
, int ring
)
513 struct radeon_bo_list
*lobj
;
514 struct list_head duplicates
;
516 u64 bytes_moved
= 0, initial_bytes_moved
;
517 u64 bytes_moved_threshold
= radeon_bo_get_threshold_for_moves(rdev
);
519 INIT_LIST_HEAD(&duplicates
);
520 r
= ttm_eu_reserve_buffers(ticket
, head
, true, &duplicates
);
521 if (unlikely(r
!= 0)) {
525 list_for_each_entry(lobj
, head
, tv
.head
) {
526 struct radeon_bo
*bo
= lobj
->robj
;
527 if (!bo
->pin_count
) {
528 u32 domain
= lobj
->prefered_domains
;
529 u32 allowed
= lobj
->allowed_domains
;
531 radeon_mem_type_to_domain(bo
->tbo
.mem
.mem_type
);
533 /* Check if this buffer will be moved and don't move it
534 * if we have moved too many buffers for this IB already.
536 * Note that this allows moving at least one buffer of
537 * any size, because it doesn't take the current "bo"
538 * into account. We don't want to disallow buffer moves
541 if ((allowed
& current_domain
) != 0 &&
542 (domain
& current_domain
) == 0 && /* will be moved */
543 bytes_moved
> bytes_moved_threshold
) {
545 domain
= current_domain
;
549 radeon_ttm_placement_from_domain(bo
, domain
);
550 if (ring
== R600_RING_TYPE_UVD_INDEX
)
551 radeon_uvd_force_into_uvd_segment(bo
, allowed
);
553 initial_bytes_moved
= atomic64_read(&rdev
->num_bytes_moved
);
554 r
= ttm_bo_validate(&bo
->tbo
, &bo
->placement
, true, false);
555 bytes_moved
+= atomic64_read(&rdev
->num_bytes_moved
) -
559 if (r
!= -ERESTARTSYS
&&
560 domain
!= lobj
->allowed_domains
) {
561 domain
= lobj
->allowed_domains
;
564 ttm_eu_backoff_reservation(ticket
, head
);
568 lobj
->gpu_offset
= radeon_bo_gpu_offset(bo
);
569 lobj
->tiling_flags
= bo
->tiling_flags
;
572 list_for_each_entry(lobj
, &duplicates
, tv
.head
) {
573 lobj
->gpu_offset
= radeon_bo_gpu_offset(lobj
->robj
);
574 lobj
->tiling_flags
= lobj
->robj
->tiling_flags
;
580 int radeon_bo_get_surface_reg(struct radeon_bo
*bo
)
582 struct radeon_device
*rdev
= bo
->rdev
;
583 struct radeon_surface_reg
*reg
;
584 struct radeon_bo
*old_object
;
588 lockdep_assert_held(&bo
->tbo
.resv
->lock
.base
);
590 if (!bo
->tiling_flags
)
593 if (bo
->surface_reg
>= 0) {
594 reg
= &rdev
->surface_regs
[bo
->surface_reg
];
600 for (i
= 0; i
< RADEON_GEM_MAX_SURFACES
; i
++) {
602 reg
= &rdev
->surface_regs
[i
];
606 old_object
= reg
->bo
;
607 if (old_object
->pin_count
== 0)
611 /* if we are all out */
612 if (i
== RADEON_GEM_MAX_SURFACES
) {
615 /* find someone with a surface reg and nuke their BO */
616 reg
= &rdev
->surface_regs
[steal
];
617 old_object
= reg
->bo
;
618 /* blow away the mapping */
619 DRM_DEBUG("stealing surface reg %d from %p\n", steal
, old_object
);
620 ttm_bo_unmap_virtual(&old_object
->tbo
);
621 old_object
->surface_reg
= -1;
629 radeon_set_surface_reg(rdev
, i
, bo
->tiling_flags
, bo
->pitch
,
630 bo
->tbo
.mem
.start
<< PAGE_SHIFT
,
631 bo
->tbo
.num_pages
<< PAGE_SHIFT
);
635 static void radeon_bo_clear_surface_reg(struct radeon_bo
*bo
)
637 struct radeon_device
*rdev
= bo
->rdev
;
638 struct radeon_surface_reg
*reg
;
640 if (bo
->surface_reg
== -1)
643 reg
= &rdev
->surface_regs
[bo
->surface_reg
];
644 radeon_clear_surface_reg(rdev
, bo
->surface_reg
);
647 bo
->surface_reg
= -1;
650 int radeon_bo_set_tiling_flags(struct radeon_bo
*bo
,
651 uint32_t tiling_flags
, uint32_t pitch
)
653 struct radeon_device
*rdev
= bo
->rdev
;
656 if (rdev
->family
>= CHIP_CEDAR
) {
657 unsigned bankw
, bankh
, mtaspect
, tilesplit
, stilesplit
;
659 bankw
= (tiling_flags
>> RADEON_TILING_EG_BANKW_SHIFT
) & RADEON_TILING_EG_BANKW_MASK
;
660 bankh
= (tiling_flags
>> RADEON_TILING_EG_BANKH_SHIFT
) & RADEON_TILING_EG_BANKH_MASK
;
661 mtaspect
= (tiling_flags
>> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT
) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK
;
662 tilesplit
= (tiling_flags
>> RADEON_TILING_EG_TILE_SPLIT_SHIFT
) & RADEON_TILING_EG_TILE_SPLIT_MASK
;
663 stilesplit
= (tiling_flags
>> RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT
) & RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK
;
697 if (stilesplit
> 6) {
701 r
= radeon_bo_reserve(bo
, false);
702 if (unlikely(r
!= 0))
704 bo
->tiling_flags
= tiling_flags
;
706 radeon_bo_unreserve(bo
);
710 void radeon_bo_get_tiling_flags(struct radeon_bo
*bo
,
711 uint32_t *tiling_flags
,
714 lockdep_assert_held(&bo
->tbo
.resv
->lock
.base
);
717 *tiling_flags
= bo
->tiling_flags
;
722 int radeon_bo_check_tiling(struct radeon_bo
*bo
, bool has_moved
,
726 lockdep_assert_held(&bo
->tbo
.resv
->lock
.base
);
728 if (!(bo
->tiling_flags
& RADEON_TILING_SURFACE
))
732 radeon_bo_clear_surface_reg(bo
);
736 if (bo
->tbo
.mem
.mem_type
!= TTM_PL_VRAM
) {
740 if (bo
->surface_reg
>= 0)
741 radeon_bo_clear_surface_reg(bo
);
745 if ((bo
->surface_reg
>= 0) && !has_moved
)
748 return radeon_bo_get_surface_reg(bo
);
751 void radeon_bo_move_notify(struct ttm_buffer_object
*bo
,
752 struct ttm_mem_reg
*new_mem
)
754 struct radeon_bo
*rbo
;
756 if (!radeon_ttm_bo_is_radeon_bo(bo
))
759 rbo
= container_of(bo
, struct radeon_bo
, tbo
);
760 radeon_bo_check_tiling(rbo
, 0, 1);
761 radeon_vm_bo_invalidate(rbo
->rdev
, rbo
);
763 /* update statistics */
767 radeon_update_memory_usage(rbo
, bo
->mem
.mem_type
, -1);
768 radeon_update_memory_usage(rbo
, new_mem
->mem_type
, 1);
771 int radeon_bo_fault_reserve_notify(struct ttm_buffer_object
*bo
)
773 struct radeon_device
*rdev
;
774 struct radeon_bo
*rbo
;
775 unsigned long offset
, size
, lpfn
;
778 if (!radeon_ttm_bo_is_radeon_bo(bo
))
780 rbo
= container_of(bo
, struct radeon_bo
, tbo
);
781 radeon_bo_check_tiling(rbo
, 0, 0);
783 if (bo
->mem
.mem_type
!= TTM_PL_VRAM
)
786 size
= bo
->mem
.num_pages
<< PAGE_SHIFT
;
787 offset
= bo
->mem
.start
<< PAGE_SHIFT
;
788 if ((offset
+ size
) <= rdev
->mc
.visible_vram_size
)
791 /* hurrah the memory is not visible ! */
792 radeon_ttm_placement_from_domain(rbo
, RADEON_GEM_DOMAIN_VRAM
);
793 lpfn
= rdev
->mc
.visible_vram_size
>> PAGE_SHIFT
;
794 for (i
= 0; i
< rbo
->placement
.num_placement
; i
++) {
795 /* Force into visible VRAM */
796 if ((rbo
->placements
[i
].flags
& TTM_PL_FLAG_VRAM
) &&
797 (!rbo
->placements
[i
].lpfn
|| rbo
->placements
[i
].lpfn
> lpfn
))
798 rbo
->placements
[i
].lpfn
= lpfn
;
800 r
= ttm_bo_validate(bo
, &rbo
->placement
, false, false);
801 if (unlikely(r
== -ENOMEM
)) {
802 radeon_ttm_placement_from_domain(rbo
, RADEON_GEM_DOMAIN_GTT
);
803 return ttm_bo_validate(bo
, &rbo
->placement
, false, false);
804 } else if (unlikely(r
!= 0)) {
808 offset
= bo
->mem
.start
<< PAGE_SHIFT
;
809 /* this should never happen */
810 if ((offset
+ size
) > rdev
->mc
.visible_vram_size
)
816 int radeon_bo_wait(struct radeon_bo
*bo
, u32
*mem_type
, bool no_wait
)
820 r
= ttm_bo_reserve(&bo
->tbo
, true, no_wait
, false, NULL
);
821 if (unlikely(r
!= 0))
824 *mem_type
= bo
->tbo
.mem
.mem_type
;
826 r
= ttm_bo_wait(&bo
->tbo
, true, true, no_wait
);
827 ttm_bo_unreserve(&bo
->tbo
);
832 * radeon_bo_fence - add fence to buffer object
834 * @bo: buffer object in question
835 * @fence: fence to add
836 * @shared: true if fence should be added shared
839 void radeon_bo_fence(struct radeon_bo
*bo
, struct radeon_fence
*fence
,
842 struct reservation_object
*resv
= bo
->tbo
.resv
;
845 reservation_object_add_shared_fence(resv
, &fence
->base
);
847 reservation_object_add_excl_fence(resv
, &fence
->base
);