2 * Permission is hereby granted, free of charge, to any person obtaining a
3 * copy of this software and associated documentation files (the "Software"),
4 * to deal in the Software without restriction, including without limitation
5 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
6 * and/or sell copies of the Software, and to permit persons to whom the
7 * Software is furnished to do so, subject to the following conditions:
9 * The above copyright notice and this permission notice shall be included in
10 * all copies or substantial portions of the Software.
12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
13 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
14 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
15 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
16 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
17 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
18 * OTHER DEALINGS IN THE SOFTWARE.
20 * Authors: Rafał Miłecki <zajec5@gmail.com>
21 * Alex Deucher <alexdeucher@gmail.com>
28 #include <linux/acpi.h>
30 #include <linux/power_supply.h>
31 #include <linux/hwmon.h>
32 #include <linux/hwmon-sysfs.h>
34 #define RADEON_IDLE_LOOP_MS 100
35 #define RADEON_RECLOCK_DELAY_MS 200
36 #define RADEON_WAIT_VBLANK_TIMEOUT 200
37 #define RADEON_WAIT_IDLE_TIMEOUT 200
39 static const char *radeon_pm_state_type_name
[5] = {
47 static void radeon_dynpm_idle_work_handler(struct work_struct
*work
);
48 static int radeon_debugfs_pm_init(struct radeon_device
*rdev
);
49 static bool radeon_pm_in_vbl(struct radeon_device
*rdev
);
50 static bool radeon_pm_debug_check_in_vbl(struct radeon_device
*rdev
, bool finish
);
51 static void radeon_pm_update_profile(struct radeon_device
*rdev
);
52 static void radeon_pm_set_clocks(struct radeon_device
*rdev
);
54 #define ACPI_AC_CLASS "ac_adapter"
56 int radeon_pm_get_type_index(struct radeon_device
*rdev
,
57 enum radeon_pm_state_type ps_type
,
61 int found_instance
= -1;
63 for (i
= 0; i
< rdev
->pm
.num_power_states
; i
++) {
64 if (rdev
->pm
.power_state
[i
].type
== ps_type
) {
66 if (found_instance
== instance
)
70 /* return default if no match */
71 return rdev
->pm
.default_power_state_index
;
75 static int radeon_acpi_event(struct notifier_block
*nb
,
79 struct radeon_device
*rdev
= container_of(nb
, struct radeon_device
, acpi_nb
);
80 struct acpi_bus_event
*entry
= (struct acpi_bus_event
*)data
;
82 if (strcmp(entry
->device_class
, ACPI_AC_CLASS
) == 0) {
83 if (power_supply_is_system_supplied() > 0)
84 DRM_DEBUG_DRIVER("pm: AC\n");
86 DRM_DEBUG_DRIVER("pm: DC\n");
88 if (rdev
->pm
.pm_method
== PM_METHOD_PROFILE
) {
89 if (rdev
->pm
.profile
== PM_PROFILE_AUTO
) {
90 mutex_lock(&rdev
->pm
.mutex
);
91 radeon_pm_update_profile(rdev
);
92 radeon_pm_set_clocks(rdev
);
93 mutex_unlock(&rdev
->pm
.mutex
);
102 static void radeon_pm_update_profile(struct radeon_device
*rdev
)
104 switch (rdev
->pm
.profile
) {
105 case PM_PROFILE_DEFAULT
:
106 rdev
->pm
.profile_index
= PM_PROFILE_DEFAULT_IDX
;
108 case PM_PROFILE_AUTO
:
109 if (power_supply_is_system_supplied() > 0) {
110 if (rdev
->pm
.active_crtc_count
> 1)
111 rdev
->pm
.profile_index
= PM_PROFILE_HIGH_MH_IDX
;
113 rdev
->pm
.profile_index
= PM_PROFILE_HIGH_SH_IDX
;
115 if (rdev
->pm
.active_crtc_count
> 1)
116 rdev
->pm
.profile_index
= PM_PROFILE_MID_MH_IDX
;
118 rdev
->pm
.profile_index
= PM_PROFILE_MID_SH_IDX
;
122 if (rdev
->pm
.active_crtc_count
> 1)
123 rdev
->pm
.profile_index
= PM_PROFILE_LOW_MH_IDX
;
125 rdev
->pm
.profile_index
= PM_PROFILE_LOW_SH_IDX
;
128 if (rdev
->pm
.active_crtc_count
> 1)
129 rdev
->pm
.profile_index
= PM_PROFILE_MID_MH_IDX
;
131 rdev
->pm
.profile_index
= PM_PROFILE_MID_SH_IDX
;
133 case PM_PROFILE_HIGH
:
134 if (rdev
->pm
.active_crtc_count
> 1)
135 rdev
->pm
.profile_index
= PM_PROFILE_HIGH_MH_IDX
;
137 rdev
->pm
.profile_index
= PM_PROFILE_HIGH_SH_IDX
;
141 if (rdev
->pm
.active_crtc_count
== 0) {
142 rdev
->pm
.requested_power_state_index
=
143 rdev
->pm
.profiles
[rdev
->pm
.profile_index
].dpms_off_ps_idx
;
144 rdev
->pm
.requested_clock_mode_index
=
145 rdev
->pm
.profiles
[rdev
->pm
.profile_index
].dpms_off_cm_idx
;
147 rdev
->pm
.requested_power_state_index
=
148 rdev
->pm
.profiles
[rdev
->pm
.profile_index
].dpms_on_ps_idx
;
149 rdev
->pm
.requested_clock_mode_index
=
150 rdev
->pm
.profiles
[rdev
->pm
.profile_index
].dpms_on_cm_idx
;
154 static void radeon_unmap_vram_bos(struct radeon_device
*rdev
)
156 struct radeon_bo
*bo
, *n
;
158 if (list_empty(&rdev
->gem
.objects
))
161 list_for_each_entry_safe(bo
, n
, &rdev
->gem
.objects
, list
) {
162 if (bo
->tbo
.mem
.mem_type
== TTM_PL_VRAM
)
163 ttm_bo_unmap_virtual(&bo
->tbo
);
167 static void radeon_sync_with_vblank(struct radeon_device
*rdev
)
169 if (rdev
->pm
.active_crtcs
) {
170 rdev
->pm
.vblank_sync
= false;
172 rdev
->irq
.vblank_queue
, rdev
->pm
.vblank_sync
,
173 msecs_to_jiffies(RADEON_WAIT_VBLANK_TIMEOUT
));
177 static void radeon_set_power_state(struct radeon_device
*rdev
)
180 bool misc_after
= false;
182 if ((rdev
->pm
.requested_clock_mode_index
== rdev
->pm
.current_clock_mode_index
) &&
183 (rdev
->pm
.requested_power_state_index
== rdev
->pm
.current_power_state_index
))
186 if (radeon_gui_idle(rdev
)) {
187 sclk
= rdev
->pm
.power_state
[rdev
->pm
.requested_power_state_index
].
188 clock_info
[rdev
->pm
.requested_clock_mode_index
].sclk
;
189 if (sclk
> rdev
->pm
.default_sclk
)
190 sclk
= rdev
->pm
.default_sclk
;
192 mclk
= rdev
->pm
.power_state
[rdev
->pm
.requested_power_state_index
].
193 clock_info
[rdev
->pm
.requested_clock_mode_index
].mclk
;
194 if (mclk
> rdev
->pm
.default_mclk
)
195 mclk
= rdev
->pm
.default_mclk
;
197 /* upvolt before raising clocks, downvolt after lowering clocks */
198 if (sclk
< rdev
->pm
.current_sclk
)
201 radeon_sync_with_vblank(rdev
);
203 if (rdev
->pm
.pm_method
== PM_METHOD_DYNPM
) {
204 if (!radeon_pm_in_vbl(rdev
))
208 radeon_pm_prepare(rdev
);
211 /* voltage, pcie lanes, etc.*/
212 radeon_pm_misc(rdev
);
214 /* set engine clock */
215 if (sclk
!= rdev
->pm
.current_sclk
) {
216 radeon_pm_debug_check_in_vbl(rdev
, false);
217 radeon_set_engine_clock(rdev
, sclk
);
218 radeon_pm_debug_check_in_vbl(rdev
, true);
219 rdev
->pm
.current_sclk
= sclk
;
220 DRM_DEBUG_DRIVER("Setting: e: %d\n", sclk
);
223 /* set memory clock */
224 if (rdev
->asic
->pm
.set_memory_clock
&& (mclk
!= rdev
->pm
.current_mclk
)) {
225 radeon_pm_debug_check_in_vbl(rdev
, false);
226 radeon_set_memory_clock(rdev
, mclk
);
227 radeon_pm_debug_check_in_vbl(rdev
, true);
228 rdev
->pm
.current_mclk
= mclk
;
229 DRM_DEBUG_DRIVER("Setting: m: %d\n", mclk
);
233 /* voltage, pcie lanes, etc.*/
234 radeon_pm_misc(rdev
);
236 radeon_pm_finish(rdev
);
238 rdev
->pm
.current_power_state_index
= rdev
->pm
.requested_power_state_index
;
239 rdev
->pm
.current_clock_mode_index
= rdev
->pm
.requested_clock_mode_index
;
241 DRM_DEBUG_DRIVER("pm: GUI not idle!!!\n");
244 static void radeon_pm_set_clocks(struct radeon_device
*rdev
)
248 /* no need to take locks, etc. if nothing's going to change */
249 if ((rdev
->pm
.requested_clock_mode_index
== rdev
->pm
.current_clock_mode_index
) &&
250 (rdev
->pm
.requested_power_state_index
== rdev
->pm
.current_power_state_index
))
253 mutex_lock(&rdev
->ddev
->struct_mutex
);
254 mutex_lock(&rdev
->vram_mutex
);
255 mutex_lock(&rdev
->ring_lock
);
257 /* gui idle int has issues on older chips it seems */
258 if (rdev
->family
>= CHIP_R600
) {
259 if (rdev
->irq
.installed
) {
260 /* wait for GPU idle */
261 rdev
->pm
.gui_idle
= false;
262 rdev
->irq
.gui_idle
= true;
263 radeon_irq_set(rdev
);
264 wait_event_interruptible_timeout(
265 rdev
->irq
.idle_queue
, rdev
->pm
.gui_idle
,
266 msecs_to_jiffies(RADEON_WAIT_IDLE_TIMEOUT
));
267 rdev
->irq
.gui_idle
= false;
268 radeon_irq_set(rdev
);
271 struct radeon_ring
*ring
= &rdev
->ring
[RADEON_RING_TYPE_GFX_INDEX
];
273 radeon_fence_wait_empty_locked(rdev
, RADEON_RING_TYPE_GFX_INDEX
);
276 radeon_unmap_vram_bos(rdev
);
278 if (rdev
->irq
.installed
) {
279 for (i
= 0; i
< rdev
->num_crtc
; i
++) {
280 if (rdev
->pm
.active_crtcs
& (1 << i
)) {
281 rdev
->pm
.req_vblank
|= (1 << i
);
282 drm_vblank_get(rdev
->ddev
, i
);
287 radeon_set_power_state(rdev
);
289 if (rdev
->irq
.installed
) {
290 for (i
= 0; i
< rdev
->num_crtc
; i
++) {
291 if (rdev
->pm
.req_vblank
& (1 << i
)) {
292 rdev
->pm
.req_vblank
&= ~(1 << i
);
293 drm_vblank_put(rdev
->ddev
, i
);
298 /* update display watermarks based on new power state */
299 radeon_update_bandwidth_info(rdev
);
300 if (rdev
->pm
.active_crtc_count
)
301 radeon_bandwidth_update(rdev
);
303 rdev
->pm
.dynpm_planned_action
= DYNPM_ACTION_NONE
;
305 mutex_unlock(&rdev
->ring_lock
);
306 mutex_unlock(&rdev
->vram_mutex
);
307 mutex_unlock(&rdev
->ddev
->struct_mutex
);
310 static void radeon_pm_print_states(struct radeon_device
*rdev
)
313 struct radeon_power_state
*power_state
;
314 struct radeon_pm_clock_info
*clock_info
;
316 DRM_DEBUG_DRIVER("%d Power State(s)\n", rdev
->pm
.num_power_states
);
317 for (i
= 0; i
< rdev
->pm
.num_power_states
; i
++) {
318 power_state
= &rdev
->pm
.power_state
[i
];
319 DRM_DEBUG_DRIVER("State %d: %s\n", i
,
320 radeon_pm_state_type_name
[power_state
->type
]);
321 if (i
== rdev
->pm
.default_power_state_index
)
322 DRM_DEBUG_DRIVER("\tDefault");
323 if ((rdev
->flags
& RADEON_IS_PCIE
) && !(rdev
->flags
& RADEON_IS_IGP
))
324 DRM_DEBUG_DRIVER("\t%d PCIE Lanes\n", power_state
->pcie_lanes
);
325 if (power_state
->flags
& RADEON_PM_STATE_SINGLE_DISPLAY_ONLY
)
326 DRM_DEBUG_DRIVER("\tSingle display only\n");
327 DRM_DEBUG_DRIVER("\t%d Clock Mode(s)\n", power_state
->num_clock_modes
);
328 for (j
= 0; j
< power_state
->num_clock_modes
; j
++) {
329 clock_info
= &(power_state
->clock_info
[j
]);
330 if (rdev
->flags
& RADEON_IS_IGP
)
331 DRM_DEBUG_DRIVER("\t\t%d e: %d%s\n",
333 clock_info
->sclk
* 10,
334 clock_info
->flags
& RADEON_PM_MODE_NO_DISPLAY
? "\tNo display only" : "");
336 DRM_DEBUG_DRIVER("\t\t%d e: %d\tm: %d\tv: %d%s\n",
338 clock_info
->sclk
* 10,
339 clock_info
->mclk
* 10,
340 clock_info
->voltage
.voltage
,
341 clock_info
->flags
& RADEON_PM_MODE_NO_DISPLAY
? "\tNo display only" : "");
346 static ssize_t
radeon_get_pm_profile(struct device
*dev
,
347 struct device_attribute
*attr
,
350 struct drm_device
*ddev
= pci_get_drvdata(to_pci_dev(dev
));
351 struct radeon_device
*rdev
= ddev
->dev_private
;
352 int cp
= rdev
->pm
.profile
;
354 return snprintf(buf
, PAGE_SIZE
, "%s\n",
355 (cp
== PM_PROFILE_AUTO
) ? "auto" :
356 (cp
== PM_PROFILE_LOW
) ? "low" :
357 (cp
== PM_PROFILE_MID
) ? "mid" :
358 (cp
== PM_PROFILE_HIGH
) ? "high" : "default");
361 static ssize_t
radeon_set_pm_profile(struct device
*dev
,
362 struct device_attribute
*attr
,
366 struct drm_device
*ddev
= pci_get_drvdata(to_pci_dev(dev
));
367 struct radeon_device
*rdev
= ddev
->dev_private
;
369 mutex_lock(&rdev
->pm
.mutex
);
370 if (rdev
->pm
.pm_method
== PM_METHOD_PROFILE
) {
371 if (strncmp("default", buf
, strlen("default")) == 0)
372 rdev
->pm
.profile
= PM_PROFILE_DEFAULT
;
373 else if (strncmp("auto", buf
, strlen("auto")) == 0)
374 rdev
->pm
.profile
= PM_PROFILE_AUTO
;
375 else if (strncmp("low", buf
, strlen("low")) == 0)
376 rdev
->pm
.profile
= PM_PROFILE_LOW
;
377 else if (strncmp("mid", buf
, strlen("mid")) == 0)
378 rdev
->pm
.profile
= PM_PROFILE_MID
;
379 else if (strncmp("high", buf
, strlen("high")) == 0)
380 rdev
->pm
.profile
= PM_PROFILE_HIGH
;
385 radeon_pm_update_profile(rdev
);
386 radeon_pm_set_clocks(rdev
);
391 mutex_unlock(&rdev
->pm
.mutex
);
396 static ssize_t
radeon_get_pm_method(struct device
*dev
,
397 struct device_attribute
*attr
,
400 struct drm_device
*ddev
= pci_get_drvdata(to_pci_dev(dev
));
401 struct radeon_device
*rdev
= ddev
->dev_private
;
402 int pm
= rdev
->pm
.pm_method
;
404 return snprintf(buf
, PAGE_SIZE
, "%s\n",
405 (pm
== PM_METHOD_DYNPM
) ? "dynpm" : "profile");
408 static ssize_t
radeon_set_pm_method(struct device
*dev
,
409 struct device_attribute
*attr
,
413 struct drm_device
*ddev
= pci_get_drvdata(to_pci_dev(dev
));
414 struct radeon_device
*rdev
= ddev
->dev_private
;
417 if (strncmp("dynpm", buf
, strlen("dynpm")) == 0) {
418 mutex_lock(&rdev
->pm
.mutex
);
419 rdev
->pm
.pm_method
= PM_METHOD_DYNPM
;
420 rdev
->pm
.dynpm_state
= DYNPM_STATE_PAUSED
;
421 rdev
->pm
.dynpm_planned_action
= DYNPM_ACTION_DEFAULT
;
422 mutex_unlock(&rdev
->pm
.mutex
);
423 } else if (strncmp("profile", buf
, strlen("profile")) == 0) {
424 mutex_lock(&rdev
->pm
.mutex
);
426 rdev
->pm
.dynpm_state
= DYNPM_STATE_DISABLED
;
427 rdev
->pm
.dynpm_planned_action
= DYNPM_ACTION_NONE
;
428 rdev
->pm
.pm_method
= PM_METHOD_PROFILE
;
429 mutex_unlock(&rdev
->pm
.mutex
);
430 cancel_delayed_work_sync(&rdev
->pm
.dynpm_idle_work
);
435 radeon_pm_compute_clocks(rdev
);
440 static DEVICE_ATTR(power_profile
, S_IRUGO
| S_IWUSR
, radeon_get_pm_profile
, radeon_set_pm_profile
);
441 static DEVICE_ATTR(power_method
, S_IRUGO
| S_IWUSR
, radeon_get_pm_method
, radeon_set_pm_method
);
443 static ssize_t
radeon_hwmon_show_temp(struct device
*dev
,
444 struct device_attribute
*attr
,
447 struct drm_device
*ddev
= pci_get_drvdata(to_pci_dev(dev
));
448 struct radeon_device
*rdev
= ddev
->dev_private
;
451 switch (rdev
->pm
.int_thermal_type
) {
452 case THERMAL_TYPE_RV6XX
:
453 temp
= rv6xx_get_temp(rdev
);
455 case THERMAL_TYPE_RV770
:
456 temp
= rv770_get_temp(rdev
);
458 case THERMAL_TYPE_EVERGREEN
:
459 case THERMAL_TYPE_NI
:
460 temp
= evergreen_get_temp(rdev
);
462 case THERMAL_TYPE_SUMO
:
463 temp
= sumo_get_temp(rdev
);
465 case THERMAL_TYPE_SI
:
466 temp
= si_get_temp(rdev
);
473 return snprintf(buf
, PAGE_SIZE
, "%d\n", temp
);
476 static ssize_t
radeon_hwmon_show_name(struct device
*dev
,
477 struct device_attribute
*attr
,
480 return sprintf(buf
, "radeon\n");
483 static SENSOR_DEVICE_ATTR(temp1_input
, S_IRUGO
, radeon_hwmon_show_temp
, NULL
, 0);
484 static SENSOR_DEVICE_ATTR(name
, S_IRUGO
, radeon_hwmon_show_name
, NULL
, 0);
486 static struct attribute
*hwmon_attributes
[] = {
487 &sensor_dev_attr_temp1_input
.dev_attr
.attr
,
488 &sensor_dev_attr_name
.dev_attr
.attr
,
492 static const struct attribute_group hwmon_attrgroup
= {
493 .attrs
= hwmon_attributes
,
496 static int radeon_hwmon_init(struct radeon_device
*rdev
)
500 rdev
->pm
.int_hwmon_dev
= NULL
;
502 switch (rdev
->pm
.int_thermal_type
) {
503 case THERMAL_TYPE_RV6XX
:
504 case THERMAL_TYPE_RV770
:
505 case THERMAL_TYPE_EVERGREEN
:
506 case THERMAL_TYPE_NI
:
507 case THERMAL_TYPE_SUMO
:
508 case THERMAL_TYPE_SI
:
509 /* No support for TN yet */
510 if (rdev
->family
== CHIP_ARUBA
)
512 rdev
->pm
.int_hwmon_dev
= hwmon_device_register(rdev
->dev
);
513 if (IS_ERR(rdev
->pm
.int_hwmon_dev
)) {
514 err
= PTR_ERR(rdev
->pm
.int_hwmon_dev
);
516 "Unable to register hwmon device: %d\n", err
);
519 dev_set_drvdata(rdev
->pm
.int_hwmon_dev
, rdev
->ddev
);
520 err
= sysfs_create_group(&rdev
->pm
.int_hwmon_dev
->kobj
,
524 "Unable to create hwmon sysfs file: %d\n", err
);
525 hwmon_device_unregister(rdev
->dev
);
535 static void radeon_hwmon_fini(struct radeon_device
*rdev
)
537 if (rdev
->pm
.int_hwmon_dev
) {
538 sysfs_remove_group(&rdev
->pm
.int_hwmon_dev
->kobj
, &hwmon_attrgroup
);
539 hwmon_device_unregister(rdev
->pm
.int_hwmon_dev
);
543 void radeon_pm_suspend(struct radeon_device
*rdev
)
545 mutex_lock(&rdev
->pm
.mutex
);
546 if (rdev
->pm
.pm_method
== PM_METHOD_DYNPM
) {
547 if (rdev
->pm
.dynpm_state
== DYNPM_STATE_ACTIVE
)
548 rdev
->pm
.dynpm_state
= DYNPM_STATE_SUSPENDED
;
550 mutex_unlock(&rdev
->pm
.mutex
);
552 cancel_delayed_work_sync(&rdev
->pm
.dynpm_idle_work
);
555 void radeon_pm_resume(struct radeon_device
*rdev
)
557 /* set up the default clocks if the MC ucode is loaded */
558 if (ASIC_IS_DCE5(rdev
) && rdev
->mc_fw
) {
559 if (rdev
->pm
.default_vddc
)
560 radeon_atom_set_voltage(rdev
, rdev
->pm
.default_vddc
,
561 SET_VOLTAGE_TYPE_ASIC_VDDC
);
562 if (rdev
->pm
.default_vddci
)
563 radeon_atom_set_voltage(rdev
, rdev
->pm
.default_vddci
,
564 SET_VOLTAGE_TYPE_ASIC_VDDCI
);
565 if (rdev
->pm
.default_sclk
)
566 radeon_set_engine_clock(rdev
, rdev
->pm
.default_sclk
);
567 if (rdev
->pm
.default_mclk
)
568 radeon_set_memory_clock(rdev
, rdev
->pm
.default_mclk
);
570 /* asic init will reset the default power state */
571 mutex_lock(&rdev
->pm
.mutex
);
572 rdev
->pm
.current_power_state_index
= rdev
->pm
.default_power_state_index
;
573 rdev
->pm
.current_clock_mode_index
= 0;
574 rdev
->pm
.current_sclk
= rdev
->pm
.default_sclk
;
575 rdev
->pm
.current_mclk
= rdev
->pm
.default_mclk
;
576 rdev
->pm
.current_vddc
= rdev
->pm
.power_state
[rdev
->pm
.default_power_state_index
].clock_info
[0].voltage
.voltage
;
577 rdev
->pm
.current_vddci
= rdev
->pm
.power_state
[rdev
->pm
.default_power_state_index
].clock_info
[0].voltage
.vddci
;
578 if (rdev
->pm
.pm_method
== PM_METHOD_DYNPM
579 && rdev
->pm
.dynpm_state
== DYNPM_STATE_SUSPENDED
) {
580 rdev
->pm
.dynpm_state
= DYNPM_STATE_ACTIVE
;
581 schedule_delayed_work(&rdev
->pm
.dynpm_idle_work
,
582 msecs_to_jiffies(RADEON_IDLE_LOOP_MS
));
584 mutex_unlock(&rdev
->pm
.mutex
);
585 radeon_pm_compute_clocks(rdev
);
588 int radeon_pm_init(struct radeon_device
*rdev
)
592 /* default to profile method */
593 rdev
->pm
.pm_method
= PM_METHOD_PROFILE
;
594 rdev
->pm
.profile
= PM_PROFILE_DEFAULT
;
595 rdev
->pm
.dynpm_state
= DYNPM_STATE_DISABLED
;
596 rdev
->pm
.dynpm_planned_action
= DYNPM_ACTION_NONE
;
597 rdev
->pm
.dynpm_can_upclock
= true;
598 rdev
->pm
.dynpm_can_downclock
= true;
599 rdev
->pm
.default_sclk
= rdev
->clock
.default_sclk
;
600 rdev
->pm
.default_mclk
= rdev
->clock
.default_mclk
;
601 rdev
->pm
.current_sclk
= rdev
->clock
.default_sclk
;
602 rdev
->pm
.current_mclk
= rdev
->clock
.default_mclk
;
603 rdev
->pm
.int_thermal_type
= THERMAL_TYPE_NONE
;
606 if (rdev
->is_atom_bios
)
607 radeon_atombios_get_power_modes(rdev
);
609 radeon_combios_get_power_modes(rdev
);
610 radeon_pm_print_states(rdev
);
611 radeon_pm_init_profile(rdev
);
612 /* set up the default clocks if the MC ucode is loaded */
613 if (ASIC_IS_DCE5(rdev
) && rdev
->mc_fw
) {
614 if (rdev
->pm
.default_vddc
)
615 radeon_atom_set_voltage(rdev
, rdev
->pm
.default_vddc
,
616 SET_VOLTAGE_TYPE_ASIC_VDDC
);
617 if (rdev
->pm
.default_vddci
)
618 radeon_atom_set_voltage(rdev
, rdev
->pm
.default_vddci
,
619 SET_VOLTAGE_TYPE_ASIC_VDDCI
);
620 if (rdev
->pm
.default_sclk
)
621 radeon_set_engine_clock(rdev
, rdev
->pm
.default_sclk
);
622 if (rdev
->pm
.default_mclk
)
623 radeon_set_memory_clock(rdev
, rdev
->pm
.default_mclk
);
627 /* set up the internal thermal sensor if applicable */
628 ret
= radeon_hwmon_init(rdev
);
632 INIT_DELAYED_WORK(&rdev
->pm
.dynpm_idle_work
, radeon_dynpm_idle_work_handler
);
634 if (rdev
->pm
.num_power_states
> 1) {
635 /* where's the best place to put these? */
636 ret
= device_create_file(rdev
->dev
, &dev_attr_power_profile
);
638 DRM_ERROR("failed to create device file for power profile\n");
639 ret
= device_create_file(rdev
->dev
, &dev_attr_power_method
);
641 DRM_ERROR("failed to create device file for power method\n");
644 rdev
->acpi_nb
.notifier_call
= radeon_acpi_event
;
645 register_acpi_notifier(&rdev
->acpi_nb
);
647 if (radeon_debugfs_pm_init(rdev
)) {
648 DRM_ERROR("Failed to register debugfs file for PM!\n");
651 DRM_INFO("radeon: power management initialized\n");
657 void radeon_pm_fini(struct radeon_device
*rdev
)
659 if (rdev
->pm
.num_power_states
> 1) {
660 mutex_lock(&rdev
->pm
.mutex
);
661 if (rdev
->pm
.pm_method
== PM_METHOD_PROFILE
) {
662 rdev
->pm
.profile
= PM_PROFILE_DEFAULT
;
663 radeon_pm_update_profile(rdev
);
664 radeon_pm_set_clocks(rdev
);
665 } else if (rdev
->pm
.pm_method
== PM_METHOD_DYNPM
) {
666 /* reset default clocks */
667 rdev
->pm
.dynpm_state
= DYNPM_STATE_DISABLED
;
668 rdev
->pm
.dynpm_planned_action
= DYNPM_ACTION_DEFAULT
;
669 radeon_pm_set_clocks(rdev
);
671 mutex_unlock(&rdev
->pm
.mutex
);
673 cancel_delayed_work_sync(&rdev
->pm
.dynpm_idle_work
);
675 device_remove_file(rdev
->dev
, &dev_attr_power_profile
);
676 device_remove_file(rdev
->dev
, &dev_attr_power_method
);
678 unregister_acpi_notifier(&rdev
->acpi_nb
);
682 if (rdev
->pm
.power_state
)
683 kfree(rdev
->pm
.power_state
);
685 radeon_hwmon_fini(rdev
);
688 void radeon_pm_compute_clocks(struct radeon_device
*rdev
)
690 struct drm_device
*ddev
= rdev
->ddev
;
691 struct drm_crtc
*crtc
;
692 struct radeon_crtc
*radeon_crtc
;
694 if (rdev
->pm
.num_power_states
< 2)
697 mutex_lock(&rdev
->pm
.mutex
);
699 rdev
->pm
.active_crtcs
= 0;
700 rdev
->pm
.active_crtc_count
= 0;
701 list_for_each_entry(crtc
,
702 &ddev
->mode_config
.crtc_list
, head
) {
703 radeon_crtc
= to_radeon_crtc(crtc
);
704 if (radeon_crtc
->enabled
) {
705 rdev
->pm
.active_crtcs
|= (1 << radeon_crtc
->crtc_id
);
706 rdev
->pm
.active_crtc_count
++;
710 if (rdev
->pm
.pm_method
== PM_METHOD_PROFILE
) {
711 radeon_pm_update_profile(rdev
);
712 radeon_pm_set_clocks(rdev
);
713 } else if (rdev
->pm
.pm_method
== PM_METHOD_DYNPM
) {
714 if (rdev
->pm
.dynpm_state
!= DYNPM_STATE_DISABLED
) {
715 if (rdev
->pm
.active_crtc_count
> 1) {
716 if (rdev
->pm
.dynpm_state
== DYNPM_STATE_ACTIVE
) {
717 cancel_delayed_work(&rdev
->pm
.dynpm_idle_work
);
719 rdev
->pm
.dynpm_state
= DYNPM_STATE_PAUSED
;
720 rdev
->pm
.dynpm_planned_action
= DYNPM_ACTION_DEFAULT
;
721 radeon_pm_get_dynpm_state(rdev
);
722 radeon_pm_set_clocks(rdev
);
724 DRM_DEBUG_DRIVER("radeon: dynamic power management deactivated\n");
726 } else if (rdev
->pm
.active_crtc_count
== 1) {
727 /* TODO: Increase clocks if needed for current mode */
729 if (rdev
->pm
.dynpm_state
== DYNPM_STATE_MINIMUM
) {
730 rdev
->pm
.dynpm_state
= DYNPM_STATE_ACTIVE
;
731 rdev
->pm
.dynpm_planned_action
= DYNPM_ACTION_UPCLOCK
;
732 radeon_pm_get_dynpm_state(rdev
);
733 radeon_pm_set_clocks(rdev
);
735 schedule_delayed_work(&rdev
->pm
.dynpm_idle_work
,
736 msecs_to_jiffies(RADEON_IDLE_LOOP_MS
));
737 } else if (rdev
->pm
.dynpm_state
== DYNPM_STATE_PAUSED
) {
738 rdev
->pm
.dynpm_state
= DYNPM_STATE_ACTIVE
;
739 schedule_delayed_work(&rdev
->pm
.dynpm_idle_work
,
740 msecs_to_jiffies(RADEON_IDLE_LOOP_MS
));
741 DRM_DEBUG_DRIVER("radeon: dynamic power management activated\n");
743 } else { /* count == 0 */
744 if (rdev
->pm
.dynpm_state
!= DYNPM_STATE_MINIMUM
) {
745 cancel_delayed_work(&rdev
->pm
.dynpm_idle_work
);
747 rdev
->pm
.dynpm_state
= DYNPM_STATE_MINIMUM
;
748 rdev
->pm
.dynpm_planned_action
= DYNPM_ACTION_MINIMUM
;
749 radeon_pm_get_dynpm_state(rdev
);
750 radeon_pm_set_clocks(rdev
);
756 mutex_unlock(&rdev
->pm
.mutex
);
759 static bool radeon_pm_in_vbl(struct radeon_device
*rdev
)
761 int crtc
, vpos
, hpos
, vbl_status
;
764 /* Iterate over all active crtc's. All crtc's must be in vblank,
765 * otherwise return in_vbl == false.
767 for (crtc
= 0; (crtc
< rdev
->num_crtc
) && in_vbl
; crtc
++) {
768 if (rdev
->pm
.active_crtcs
& (1 << crtc
)) {
769 vbl_status
= radeon_get_crtc_scanoutpos(rdev
->ddev
, crtc
, &vpos
, &hpos
);
770 if ((vbl_status
& DRM_SCANOUTPOS_VALID
) &&
771 !(vbl_status
& DRM_SCANOUTPOS_INVBL
))
779 static bool radeon_pm_debug_check_in_vbl(struct radeon_device
*rdev
, bool finish
)
782 bool in_vbl
= radeon_pm_in_vbl(rdev
);
785 DRM_DEBUG_DRIVER("not in vbl for pm change %08x at %s\n", stat_crtc
,
786 finish
? "exit" : "entry");
790 static void radeon_dynpm_idle_work_handler(struct work_struct
*work
)
792 struct radeon_device
*rdev
;
794 rdev
= container_of(work
, struct radeon_device
,
795 pm
.dynpm_idle_work
.work
);
797 resched
= ttm_bo_lock_delayed_workqueue(&rdev
->mman
.bdev
);
798 mutex_lock(&rdev
->pm
.mutex
);
799 if (rdev
->pm
.dynpm_state
== DYNPM_STATE_ACTIVE
) {
800 int not_processed
= 0;
803 for (i
= 0; i
< RADEON_NUM_RINGS
; ++i
) {
804 not_processed
+= radeon_fence_count_emitted(rdev
, i
);
805 if (not_processed
>= 3)
809 if (not_processed
>= 3) { /* should upclock */
810 if (rdev
->pm
.dynpm_planned_action
== DYNPM_ACTION_DOWNCLOCK
) {
811 rdev
->pm
.dynpm_planned_action
= DYNPM_ACTION_NONE
;
812 } else if (rdev
->pm
.dynpm_planned_action
== DYNPM_ACTION_NONE
&&
813 rdev
->pm
.dynpm_can_upclock
) {
814 rdev
->pm
.dynpm_planned_action
=
815 DYNPM_ACTION_UPCLOCK
;
816 rdev
->pm
.dynpm_action_timeout
= jiffies
+
817 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS
);
819 } else if (not_processed
== 0) { /* should downclock */
820 if (rdev
->pm
.dynpm_planned_action
== DYNPM_ACTION_UPCLOCK
) {
821 rdev
->pm
.dynpm_planned_action
= DYNPM_ACTION_NONE
;
822 } else if (rdev
->pm
.dynpm_planned_action
== DYNPM_ACTION_NONE
&&
823 rdev
->pm
.dynpm_can_downclock
) {
824 rdev
->pm
.dynpm_planned_action
=
825 DYNPM_ACTION_DOWNCLOCK
;
826 rdev
->pm
.dynpm_action_timeout
= jiffies
+
827 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS
);
831 /* Note, radeon_pm_set_clocks is called with static_switch set
832 * to false since we want to wait for vbl to avoid flicker.
834 if (rdev
->pm
.dynpm_planned_action
!= DYNPM_ACTION_NONE
&&
835 jiffies
> rdev
->pm
.dynpm_action_timeout
) {
836 radeon_pm_get_dynpm_state(rdev
);
837 radeon_pm_set_clocks(rdev
);
840 schedule_delayed_work(&rdev
->pm
.dynpm_idle_work
,
841 msecs_to_jiffies(RADEON_IDLE_LOOP_MS
));
843 mutex_unlock(&rdev
->pm
.mutex
);
844 ttm_bo_unlock_delayed_workqueue(&rdev
->mman
.bdev
, resched
);
850 #if defined(CONFIG_DEBUG_FS)
852 static int radeon_debugfs_pm_info(struct seq_file
*m
, void *data
)
854 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
855 struct drm_device
*dev
= node
->minor
->dev
;
856 struct radeon_device
*rdev
= dev
->dev_private
;
858 seq_printf(m
, "default engine clock: %u0 kHz\n", rdev
->pm
.default_sclk
);
859 seq_printf(m
, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev
));
860 seq_printf(m
, "default memory clock: %u0 kHz\n", rdev
->pm
.default_mclk
);
861 if (rdev
->asic
->pm
.get_memory_clock
)
862 seq_printf(m
, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev
));
863 if (rdev
->pm
.current_vddc
)
864 seq_printf(m
, "voltage: %u mV\n", rdev
->pm
.current_vddc
);
865 if (rdev
->asic
->pm
.get_pcie_lanes
)
866 seq_printf(m
, "PCIE lanes: %d\n", radeon_get_pcie_lanes(rdev
));
871 static struct drm_info_list radeon_pm_info_list
[] = {
872 {"radeon_pm_info", radeon_debugfs_pm_info
, 0, NULL
},
876 static int radeon_debugfs_pm_init(struct radeon_device
*rdev
)
878 #if defined(CONFIG_DEBUG_FS)
879 return radeon_debugfs_add_files(rdev
, radeon_pm_info_list
, ARRAY_SIZE(radeon_pm_info_list
));