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ASoC: cs4265: Convert to params_width()
[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon_pm.c
1 /*
2 * Permission is hereby granted, free of charge, to any person obtaining a
3 * copy of this software and associated documentation files (the "Software"),
4 * to deal in the Software without restriction, including without limitation
5 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
6 * and/or sell copies of the Software, and to permit persons to whom the
7 * Software is furnished to do so, subject to the following conditions:
8 *
9 * The above copyright notice and this permission notice shall be included in
10 * all copies or substantial portions of the Software.
11 *
12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
13 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
14 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
15 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
16 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
17 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
18 * OTHER DEALINGS IN THE SOFTWARE.
19 *
20 * Authors: Rafał Miłecki <zajec5@gmail.com>
21 * Alex Deucher <alexdeucher@gmail.com>
22 */
23 #include <drm/drmP.h>
24 #include "radeon.h"
25 #include "avivod.h"
26 #include "atom.h"
27 #include <linux/power_supply.h>
28 #include <linux/hwmon.h>
29 #include <linux/hwmon-sysfs.h>
30
31 #define RADEON_IDLE_LOOP_MS 100
32 #define RADEON_RECLOCK_DELAY_MS 200
33 #define RADEON_WAIT_VBLANK_TIMEOUT 200
34
35 static const char *radeon_pm_state_type_name[5] = {
36 "",
37 "Powersave",
38 "Battery",
39 "Balanced",
40 "Performance",
41 };
42
43 static void radeon_dynpm_idle_work_handler(struct work_struct *work);
44 static int radeon_debugfs_pm_init(struct radeon_device *rdev);
45 static bool radeon_pm_in_vbl(struct radeon_device *rdev);
46 static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish);
47 static void radeon_pm_update_profile(struct radeon_device *rdev);
48 static void radeon_pm_set_clocks(struct radeon_device *rdev);
49
50 int radeon_pm_get_type_index(struct radeon_device *rdev,
51 enum radeon_pm_state_type ps_type,
52 int instance)
53 {
54 int i;
55 int found_instance = -1;
56
57 for (i = 0; i < rdev->pm.num_power_states; i++) {
58 if (rdev->pm.power_state[i].type == ps_type) {
59 found_instance++;
60 if (found_instance == instance)
61 return i;
62 }
63 }
64 /* return default if no match */
65 return rdev->pm.default_power_state_index;
66 }
67
68 void radeon_pm_acpi_event_handler(struct radeon_device *rdev)
69 {
70 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
71 mutex_lock(&rdev->pm.mutex);
72 if (power_supply_is_system_supplied() > 0)
73 rdev->pm.dpm.ac_power = true;
74 else
75 rdev->pm.dpm.ac_power = false;
76 if (rdev->asic->dpm.enable_bapm)
77 radeon_dpm_enable_bapm(rdev, rdev->pm.dpm.ac_power);
78 mutex_unlock(&rdev->pm.mutex);
79 } else if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
80 if (rdev->pm.profile == PM_PROFILE_AUTO) {
81 mutex_lock(&rdev->pm.mutex);
82 radeon_pm_update_profile(rdev);
83 radeon_pm_set_clocks(rdev);
84 mutex_unlock(&rdev->pm.mutex);
85 }
86 }
87 }
88
89 static void radeon_pm_update_profile(struct radeon_device *rdev)
90 {
91 switch (rdev->pm.profile) {
92 case PM_PROFILE_DEFAULT:
93 rdev->pm.profile_index = PM_PROFILE_DEFAULT_IDX;
94 break;
95 case PM_PROFILE_AUTO:
96 if (power_supply_is_system_supplied() > 0) {
97 if (rdev->pm.active_crtc_count > 1)
98 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
99 else
100 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
101 } else {
102 if (rdev->pm.active_crtc_count > 1)
103 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
104 else
105 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
106 }
107 break;
108 case PM_PROFILE_LOW:
109 if (rdev->pm.active_crtc_count > 1)
110 rdev->pm.profile_index = PM_PROFILE_LOW_MH_IDX;
111 else
112 rdev->pm.profile_index = PM_PROFILE_LOW_SH_IDX;
113 break;
114 case PM_PROFILE_MID:
115 if (rdev->pm.active_crtc_count > 1)
116 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
117 else
118 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
119 break;
120 case PM_PROFILE_HIGH:
121 if (rdev->pm.active_crtc_count > 1)
122 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
123 else
124 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
125 break;
126 }
127
128 if (rdev->pm.active_crtc_count == 0) {
129 rdev->pm.requested_power_state_index =
130 rdev->pm.profiles[rdev->pm.profile_index].dpms_off_ps_idx;
131 rdev->pm.requested_clock_mode_index =
132 rdev->pm.profiles[rdev->pm.profile_index].dpms_off_cm_idx;
133 } else {
134 rdev->pm.requested_power_state_index =
135 rdev->pm.profiles[rdev->pm.profile_index].dpms_on_ps_idx;
136 rdev->pm.requested_clock_mode_index =
137 rdev->pm.profiles[rdev->pm.profile_index].dpms_on_cm_idx;
138 }
139 }
140
141 static void radeon_unmap_vram_bos(struct radeon_device *rdev)
142 {
143 struct radeon_bo *bo, *n;
144
145 if (list_empty(&rdev->gem.objects))
146 return;
147
148 list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
149 if (bo->tbo.mem.mem_type == TTM_PL_VRAM)
150 ttm_bo_unmap_virtual(&bo->tbo);
151 }
152 }
153
154 static void radeon_sync_with_vblank(struct radeon_device *rdev)
155 {
156 if (rdev->pm.active_crtcs) {
157 rdev->pm.vblank_sync = false;
158 wait_event_timeout(
159 rdev->irq.vblank_queue, rdev->pm.vblank_sync,
160 msecs_to_jiffies(RADEON_WAIT_VBLANK_TIMEOUT));
161 }
162 }
163
164 static void radeon_set_power_state(struct radeon_device *rdev)
165 {
166 u32 sclk, mclk;
167 bool misc_after = false;
168
169 if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
170 (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
171 return;
172
173 if (radeon_gui_idle(rdev)) {
174 sclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
175 clock_info[rdev->pm.requested_clock_mode_index].sclk;
176 if (sclk > rdev->pm.default_sclk)
177 sclk = rdev->pm.default_sclk;
178
179 /* starting with BTC, there is one state that is used for both
180 * MH and SH. Difference is that we always use the high clock index for
181 * mclk and vddci.
182 */
183 if ((rdev->pm.pm_method == PM_METHOD_PROFILE) &&
184 (rdev->family >= CHIP_BARTS) &&
185 rdev->pm.active_crtc_count &&
186 ((rdev->pm.profile_index == PM_PROFILE_MID_MH_IDX) ||
187 (rdev->pm.profile_index == PM_PROFILE_LOW_MH_IDX)))
188 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
189 clock_info[rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx].mclk;
190 else
191 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
192 clock_info[rdev->pm.requested_clock_mode_index].mclk;
193
194 if (mclk > rdev->pm.default_mclk)
195 mclk = rdev->pm.default_mclk;
196
197 /* upvolt before raising clocks, downvolt after lowering clocks */
198 if (sclk < rdev->pm.current_sclk)
199 misc_after = true;
200
201 radeon_sync_with_vblank(rdev);
202
203 if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
204 if (!radeon_pm_in_vbl(rdev))
205 return;
206 }
207
208 radeon_pm_prepare(rdev);
209
210 if (!misc_after)
211 /* voltage, pcie lanes, etc.*/
212 radeon_pm_misc(rdev);
213
214 /* set engine clock */
215 if (sclk != rdev->pm.current_sclk) {
216 radeon_pm_debug_check_in_vbl(rdev, false);
217 radeon_set_engine_clock(rdev, sclk);
218 radeon_pm_debug_check_in_vbl(rdev, true);
219 rdev->pm.current_sclk = sclk;
220 DRM_DEBUG_DRIVER("Setting: e: %d\n", sclk);
221 }
222
223 /* set memory clock */
224 if (rdev->asic->pm.set_memory_clock && (mclk != rdev->pm.current_mclk)) {
225 radeon_pm_debug_check_in_vbl(rdev, false);
226 radeon_set_memory_clock(rdev, mclk);
227 radeon_pm_debug_check_in_vbl(rdev, true);
228 rdev->pm.current_mclk = mclk;
229 DRM_DEBUG_DRIVER("Setting: m: %d\n", mclk);
230 }
231
232 if (misc_after)
233 /* voltage, pcie lanes, etc.*/
234 radeon_pm_misc(rdev);
235
236 radeon_pm_finish(rdev);
237
238 rdev->pm.current_power_state_index = rdev->pm.requested_power_state_index;
239 rdev->pm.current_clock_mode_index = rdev->pm.requested_clock_mode_index;
240 } else
241 DRM_DEBUG_DRIVER("pm: GUI not idle!!!\n");
242 }
243
244 static void radeon_pm_set_clocks(struct radeon_device *rdev)
245 {
246 int i, r;
247
248 /* no need to take locks, etc. if nothing's going to change */
249 if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
250 (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
251 return;
252
253 mutex_lock(&rdev->ddev->struct_mutex);
254 down_write(&rdev->pm.mclk_lock);
255 mutex_lock(&rdev->ring_lock);
256
257 /* wait for the rings to drain */
258 for (i = 0; i < RADEON_NUM_RINGS; i++) {
259 struct radeon_ring *ring = &rdev->ring[i];
260 if (!ring->ready) {
261 continue;
262 }
263 r = radeon_fence_wait_empty(rdev, i);
264 if (r) {
265 /* needs a GPU reset dont reset here */
266 mutex_unlock(&rdev->ring_lock);
267 up_write(&rdev->pm.mclk_lock);
268 mutex_unlock(&rdev->ddev->struct_mutex);
269 return;
270 }
271 }
272
273 radeon_unmap_vram_bos(rdev);
274
275 if (rdev->irq.installed) {
276 for (i = 0; i < rdev->num_crtc; i++) {
277 if (rdev->pm.active_crtcs & (1 << i)) {
278 rdev->pm.req_vblank |= (1 << i);
279 drm_vblank_get(rdev->ddev, i);
280 }
281 }
282 }
283
284 radeon_set_power_state(rdev);
285
286 if (rdev->irq.installed) {
287 for (i = 0; i < rdev->num_crtc; i++) {
288 if (rdev->pm.req_vblank & (1 << i)) {
289 rdev->pm.req_vblank &= ~(1 << i);
290 drm_vblank_put(rdev->ddev, i);
291 }
292 }
293 }
294
295 /* update display watermarks based on new power state */
296 radeon_update_bandwidth_info(rdev);
297 if (rdev->pm.active_crtc_count)
298 radeon_bandwidth_update(rdev);
299
300 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
301
302 mutex_unlock(&rdev->ring_lock);
303 up_write(&rdev->pm.mclk_lock);
304 mutex_unlock(&rdev->ddev->struct_mutex);
305 }
306
307 static void radeon_pm_print_states(struct radeon_device *rdev)
308 {
309 int i, j;
310 struct radeon_power_state *power_state;
311 struct radeon_pm_clock_info *clock_info;
312
313 DRM_DEBUG_DRIVER("%d Power State(s)\n", rdev->pm.num_power_states);
314 for (i = 0; i < rdev->pm.num_power_states; i++) {
315 power_state = &rdev->pm.power_state[i];
316 DRM_DEBUG_DRIVER("State %d: %s\n", i,
317 radeon_pm_state_type_name[power_state->type]);
318 if (i == rdev->pm.default_power_state_index)
319 DRM_DEBUG_DRIVER("\tDefault");
320 if ((rdev->flags & RADEON_IS_PCIE) && !(rdev->flags & RADEON_IS_IGP))
321 DRM_DEBUG_DRIVER("\t%d PCIE Lanes\n", power_state->pcie_lanes);
322 if (power_state->flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
323 DRM_DEBUG_DRIVER("\tSingle display only\n");
324 DRM_DEBUG_DRIVER("\t%d Clock Mode(s)\n", power_state->num_clock_modes);
325 for (j = 0; j < power_state->num_clock_modes; j++) {
326 clock_info = &(power_state->clock_info[j]);
327 if (rdev->flags & RADEON_IS_IGP)
328 DRM_DEBUG_DRIVER("\t\t%d e: %d\n",
329 j,
330 clock_info->sclk * 10);
331 else
332 DRM_DEBUG_DRIVER("\t\t%d e: %d\tm: %d\tv: %d\n",
333 j,
334 clock_info->sclk * 10,
335 clock_info->mclk * 10,
336 clock_info->voltage.voltage);
337 }
338 }
339 }
340
341 static ssize_t radeon_get_pm_profile(struct device *dev,
342 struct device_attribute *attr,
343 char *buf)
344 {
345 struct drm_device *ddev = dev_get_drvdata(dev);
346 struct radeon_device *rdev = ddev->dev_private;
347 int cp = rdev->pm.profile;
348
349 return snprintf(buf, PAGE_SIZE, "%s\n",
350 (cp == PM_PROFILE_AUTO) ? "auto" :
351 (cp == PM_PROFILE_LOW) ? "low" :
352 (cp == PM_PROFILE_MID) ? "mid" :
353 (cp == PM_PROFILE_HIGH) ? "high" : "default");
354 }
355
356 static ssize_t radeon_set_pm_profile(struct device *dev,
357 struct device_attribute *attr,
358 const char *buf,
359 size_t count)
360 {
361 struct drm_device *ddev = dev_get_drvdata(dev);
362 struct radeon_device *rdev = ddev->dev_private;
363
364 /* Can't set profile when the card is off */
365 if ((rdev->flags & RADEON_IS_PX) &&
366 (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
367 return -EINVAL;
368
369 mutex_lock(&rdev->pm.mutex);
370 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
371 if (strncmp("default", buf, strlen("default")) == 0)
372 rdev->pm.profile = PM_PROFILE_DEFAULT;
373 else if (strncmp("auto", buf, strlen("auto")) == 0)
374 rdev->pm.profile = PM_PROFILE_AUTO;
375 else if (strncmp("low", buf, strlen("low")) == 0)
376 rdev->pm.profile = PM_PROFILE_LOW;
377 else if (strncmp("mid", buf, strlen("mid")) == 0)
378 rdev->pm.profile = PM_PROFILE_MID;
379 else if (strncmp("high", buf, strlen("high")) == 0)
380 rdev->pm.profile = PM_PROFILE_HIGH;
381 else {
382 count = -EINVAL;
383 goto fail;
384 }
385 radeon_pm_update_profile(rdev);
386 radeon_pm_set_clocks(rdev);
387 } else
388 count = -EINVAL;
389
390 fail:
391 mutex_unlock(&rdev->pm.mutex);
392
393 return count;
394 }
395
396 static ssize_t radeon_get_pm_method(struct device *dev,
397 struct device_attribute *attr,
398 char *buf)
399 {
400 struct drm_device *ddev = dev_get_drvdata(dev);
401 struct radeon_device *rdev = ddev->dev_private;
402 int pm = rdev->pm.pm_method;
403
404 return snprintf(buf, PAGE_SIZE, "%s\n",
405 (pm == PM_METHOD_DYNPM) ? "dynpm" :
406 (pm == PM_METHOD_PROFILE) ? "profile" : "dpm");
407 }
408
409 static ssize_t radeon_set_pm_method(struct device *dev,
410 struct device_attribute *attr,
411 const char *buf,
412 size_t count)
413 {
414 struct drm_device *ddev = dev_get_drvdata(dev);
415 struct radeon_device *rdev = ddev->dev_private;
416
417 /* Can't set method when the card is off */
418 if ((rdev->flags & RADEON_IS_PX) &&
419 (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) {
420 count = -EINVAL;
421 goto fail;
422 }
423
424 /* we don't support the legacy modes with dpm */
425 if (rdev->pm.pm_method == PM_METHOD_DPM) {
426 count = -EINVAL;
427 goto fail;
428 }
429
430 if (strncmp("dynpm", buf, strlen("dynpm")) == 0) {
431 mutex_lock(&rdev->pm.mutex);
432 rdev->pm.pm_method = PM_METHOD_DYNPM;
433 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
434 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
435 mutex_unlock(&rdev->pm.mutex);
436 } else if (strncmp("profile", buf, strlen("profile")) == 0) {
437 mutex_lock(&rdev->pm.mutex);
438 /* disable dynpm */
439 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
440 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
441 rdev->pm.pm_method = PM_METHOD_PROFILE;
442 mutex_unlock(&rdev->pm.mutex);
443 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
444 } else {
445 count = -EINVAL;
446 goto fail;
447 }
448 radeon_pm_compute_clocks(rdev);
449 fail:
450 return count;
451 }
452
453 static ssize_t radeon_get_dpm_state(struct device *dev,
454 struct device_attribute *attr,
455 char *buf)
456 {
457 struct drm_device *ddev = dev_get_drvdata(dev);
458 struct radeon_device *rdev = ddev->dev_private;
459 enum radeon_pm_state_type pm = rdev->pm.dpm.user_state;
460
461 if ((rdev->flags & RADEON_IS_PX) &&
462 (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
463 return snprintf(buf, PAGE_SIZE, "off\n");
464
465 return snprintf(buf, PAGE_SIZE, "%s\n",
466 (pm == POWER_STATE_TYPE_BATTERY) ? "battery" :
467 (pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance");
468 }
469
470 static ssize_t radeon_set_dpm_state(struct device *dev,
471 struct device_attribute *attr,
472 const char *buf,
473 size_t count)
474 {
475 struct drm_device *ddev = dev_get_drvdata(dev);
476 struct radeon_device *rdev = ddev->dev_private;
477
478 /* Can't set dpm state when the card is off */
479 if ((rdev->flags & RADEON_IS_PX) &&
480 (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
481 return -EINVAL;
482
483 mutex_lock(&rdev->pm.mutex);
484 if (strncmp("battery", buf, strlen("battery")) == 0)
485 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BATTERY;
486 else if (strncmp("balanced", buf, strlen("balanced")) == 0)
487 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
488 else if (strncmp("performance", buf, strlen("performance")) == 0)
489 rdev->pm.dpm.user_state = POWER_STATE_TYPE_PERFORMANCE;
490 else {
491 mutex_unlock(&rdev->pm.mutex);
492 count = -EINVAL;
493 goto fail;
494 }
495 mutex_unlock(&rdev->pm.mutex);
496 radeon_pm_compute_clocks(rdev);
497 fail:
498 return count;
499 }
500
501 static ssize_t radeon_get_dpm_forced_performance_level(struct device *dev,
502 struct device_attribute *attr,
503 char *buf)
504 {
505 struct drm_device *ddev = dev_get_drvdata(dev);
506 struct radeon_device *rdev = ddev->dev_private;
507 enum radeon_dpm_forced_level level = rdev->pm.dpm.forced_level;
508
509 if ((rdev->flags & RADEON_IS_PX) &&
510 (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
511 return snprintf(buf, PAGE_SIZE, "off\n");
512
513 return snprintf(buf, PAGE_SIZE, "%s\n",
514 (level == RADEON_DPM_FORCED_LEVEL_AUTO) ? "auto" :
515 (level == RADEON_DPM_FORCED_LEVEL_LOW) ? "low" : "high");
516 }
517
518 static ssize_t radeon_set_dpm_forced_performance_level(struct device *dev,
519 struct device_attribute *attr,
520 const char *buf,
521 size_t count)
522 {
523 struct drm_device *ddev = dev_get_drvdata(dev);
524 struct radeon_device *rdev = ddev->dev_private;
525 enum radeon_dpm_forced_level level;
526 int ret = 0;
527
528 /* Can't force performance level when the card is off */
529 if ((rdev->flags & RADEON_IS_PX) &&
530 (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
531 return -EINVAL;
532
533 mutex_lock(&rdev->pm.mutex);
534 if (strncmp("low", buf, strlen("low")) == 0) {
535 level = RADEON_DPM_FORCED_LEVEL_LOW;
536 } else if (strncmp("high", buf, strlen("high")) == 0) {
537 level = RADEON_DPM_FORCED_LEVEL_HIGH;
538 } else if (strncmp("auto", buf, strlen("auto")) == 0) {
539 level = RADEON_DPM_FORCED_LEVEL_AUTO;
540 } else {
541 count = -EINVAL;
542 goto fail;
543 }
544 if (rdev->asic->dpm.force_performance_level) {
545 if (rdev->pm.dpm.thermal_active) {
546 count = -EINVAL;
547 goto fail;
548 }
549 ret = radeon_dpm_force_performance_level(rdev, level);
550 if (ret)
551 count = -EINVAL;
552 }
553 fail:
554 mutex_unlock(&rdev->pm.mutex);
555
556 return count;
557 }
558
559 static DEVICE_ATTR(power_profile, S_IRUGO | S_IWUSR, radeon_get_pm_profile, radeon_set_pm_profile);
560 static DEVICE_ATTR(power_method, S_IRUGO | S_IWUSR, radeon_get_pm_method, radeon_set_pm_method);
561 static DEVICE_ATTR(power_dpm_state, S_IRUGO | S_IWUSR, radeon_get_dpm_state, radeon_set_dpm_state);
562 static DEVICE_ATTR(power_dpm_force_performance_level, S_IRUGO | S_IWUSR,
563 radeon_get_dpm_forced_performance_level,
564 radeon_set_dpm_forced_performance_level);
565
566 static ssize_t radeon_hwmon_show_temp(struct device *dev,
567 struct device_attribute *attr,
568 char *buf)
569 {
570 struct radeon_device *rdev = dev_get_drvdata(dev);
571 struct drm_device *ddev = rdev->ddev;
572 int temp;
573
574 /* Can't get temperature when the card is off */
575 if ((rdev->flags & RADEON_IS_PX) &&
576 (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
577 return -EINVAL;
578
579 if (rdev->asic->pm.get_temperature)
580 temp = radeon_get_temperature(rdev);
581 else
582 temp = 0;
583
584 return snprintf(buf, PAGE_SIZE, "%d\n", temp);
585 }
586
587 static ssize_t radeon_hwmon_show_temp_thresh(struct device *dev,
588 struct device_attribute *attr,
589 char *buf)
590 {
591 struct radeon_device *rdev = dev_get_drvdata(dev);
592 int hyst = to_sensor_dev_attr(attr)->index;
593 int temp;
594
595 if (hyst)
596 temp = rdev->pm.dpm.thermal.min_temp;
597 else
598 temp = rdev->pm.dpm.thermal.max_temp;
599
600 return snprintf(buf, PAGE_SIZE, "%d\n", temp);
601 }
602
603 static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, radeon_hwmon_show_temp, NULL, 0);
604 static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, radeon_hwmon_show_temp_thresh, NULL, 0);
605 static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, radeon_hwmon_show_temp_thresh, NULL, 1);
606
607 static struct attribute *hwmon_attributes[] = {
608 &sensor_dev_attr_temp1_input.dev_attr.attr,
609 &sensor_dev_attr_temp1_crit.dev_attr.attr,
610 &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr,
611 NULL
612 };
613
614 static umode_t hwmon_attributes_visible(struct kobject *kobj,
615 struct attribute *attr, int index)
616 {
617 struct device *dev = container_of(kobj, struct device, kobj);
618 struct radeon_device *rdev = dev_get_drvdata(dev);
619
620 /* Skip limit attributes if DPM is not enabled */
621 if (rdev->pm.pm_method != PM_METHOD_DPM &&
622 (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr ||
623 attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr))
624 return 0;
625
626 return attr->mode;
627 }
628
629 static const struct attribute_group hwmon_attrgroup = {
630 .attrs = hwmon_attributes,
631 .is_visible = hwmon_attributes_visible,
632 };
633
634 static const struct attribute_group *hwmon_groups[] = {
635 &hwmon_attrgroup,
636 NULL
637 };
638
639 static int radeon_hwmon_init(struct radeon_device *rdev)
640 {
641 int err = 0;
642
643 switch (rdev->pm.int_thermal_type) {
644 case THERMAL_TYPE_RV6XX:
645 case THERMAL_TYPE_RV770:
646 case THERMAL_TYPE_EVERGREEN:
647 case THERMAL_TYPE_NI:
648 case THERMAL_TYPE_SUMO:
649 case THERMAL_TYPE_SI:
650 case THERMAL_TYPE_CI:
651 case THERMAL_TYPE_KV:
652 if (rdev->asic->pm.get_temperature == NULL)
653 return err;
654 rdev->pm.int_hwmon_dev = hwmon_device_register_with_groups(rdev->dev,
655 "radeon", rdev,
656 hwmon_groups);
657 if (IS_ERR(rdev->pm.int_hwmon_dev)) {
658 err = PTR_ERR(rdev->pm.int_hwmon_dev);
659 dev_err(rdev->dev,
660 "Unable to register hwmon device: %d\n", err);
661 }
662 break;
663 default:
664 break;
665 }
666
667 return err;
668 }
669
670 static void radeon_hwmon_fini(struct radeon_device *rdev)
671 {
672 if (rdev->pm.int_hwmon_dev)
673 hwmon_device_unregister(rdev->pm.int_hwmon_dev);
674 }
675
676 static void radeon_dpm_thermal_work_handler(struct work_struct *work)
677 {
678 struct radeon_device *rdev =
679 container_of(work, struct radeon_device,
680 pm.dpm.thermal.work);
681 /* switch to the thermal state */
682 enum radeon_pm_state_type dpm_state = POWER_STATE_TYPE_INTERNAL_THERMAL;
683
684 if (!rdev->pm.dpm_enabled)
685 return;
686
687 if (rdev->asic->pm.get_temperature) {
688 int temp = radeon_get_temperature(rdev);
689
690 if (temp < rdev->pm.dpm.thermal.min_temp)
691 /* switch back the user state */
692 dpm_state = rdev->pm.dpm.user_state;
693 } else {
694 if (rdev->pm.dpm.thermal.high_to_low)
695 /* switch back the user state */
696 dpm_state = rdev->pm.dpm.user_state;
697 }
698 mutex_lock(&rdev->pm.mutex);
699 if (dpm_state == POWER_STATE_TYPE_INTERNAL_THERMAL)
700 rdev->pm.dpm.thermal_active = true;
701 else
702 rdev->pm.dpm.thermal_active = false;
703 rdev->pm.dpm.state = dpm_state;
704 mutex_unlock(&rdev->pm.mutex);
705
706 radeon_pm_compute_clocks(rdev);
707 }
708
709 static struct radeon_ps *radeon_dpm_pick_power_state(struct radeon_device *rdev,
710 enum radeon_pm_state_type dpm_state)
711 {
712 int i;
713 struct radeon_ps *ps;
714 u32 ui_class;
715 bool single_display = (rdev->pm.dpm.new_active_crtc_count < 2) ?
716 true : false;
717
718 /* check if the vblank period is too short to adjust the mclk */
719 if (single_display && rdev->asic->dpm.vblank_too_short) {
720 if (radeon_dpm_vblank_too_short(rdev))
721 single_display = false;
722 }
723
724 /* certain older asics have a separare 3D performance state,
725 * so try that first if the user selected performance
726 */
727 if (dpm_state == POWER_STATE_TYPE_PERFORMANCE)
728 dpm_state = POWER_STATE_TYPE_INTERNAL_3DPERF;
729 /* balanced states don't exist at the moment */
730 if (dpm_state == POWER_STATE_TYPE_BALANCED)
731 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
732
733 restart_search:
734 /* Pick the best power state based on current conditions */
735 for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
736 ps = &rdev->pm.dpm.ps[i];
737 ui_class = ps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK;
738 switch (dpm_state) {
739 /* user states */
740 case POWER_STATE_TYPE_BATTERY:
741 if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) {
742 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
743 if (single_display)
744 return ps;
745 } else
746 return ps;
747 }
748 break;
749 case POWER_STATE_TYPE_BALANCED:
750 if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BALANCED) {
751 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
752 if (single_display)
753 return ps;
754 } else
755 return ps;
756 }
757 break;
758 case POWER_STATE_TYPE_PERFORMANCE:
759 if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
760 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
761 if (single_display)
762 return ps;
763 } else
764 return ps;
765 }
766 break;
767 /* internal states */
768 case POWER_STATE_TYPE_INTERNAL_UVD:
769 if (rdev->pm.dpm.uvd_ps)
770 return rdev->pm.dpm.uvd_ps;
771 else
772 break;
773 case POWER_STATE_TYPE_INTERNAL_UVD_SD:
774 if (ps->class & ATOM_PPLIB_CLASSIFICATION_SDSTATE)
775 return ps;
776 break;
777 case POWER_STATE_TYPE_INTERNAL_UVD_HD:
778 if (ps->class & ATOM_PPLIB_CLASSIFICATION_HDSTATE)
779 return ps;
780 break;
781 case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
782 if (ps->class & ATOM_PPLIB_CLASSIFICATION_HD2STATE)
783 return ps;
784 break;
785 case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
786 if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_MVC)
787 return ps;
788 break;
789 case POWER_STATE_TYPE_INTERNAL_BOOT:
790 return rdev->pm.dpm.boot_ps;
791 case POWER_STATE_TYPE_INTERNAL_THERMAL:
792 if (ps->class & ATOM_PPLIB_CLASSIFICATION_THERMAL)
793 return ps;
794 break;
795 case POWER_STATE_TYPE_INTERNAL_ACPI:
796 if (ps->class & ATOM_PPLIB_CLASSIFICATION_ACPI)
797 return ps;
798 break;
799 case POWER_STATE_TYPE_INTERNAL_ULV:
800 if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV)
801 return ps;
802 break;
803 case POWER_STATE_TYPE_INTERNAL_3DPERF:
804 if (ps->class & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
805 return ps;
806 break;
807 default:
808 break;
809 }
810 }
811 /* use a fallback state if we didn't match */
812 switch (dpm_state) {
813 case POWER_STATE_TYPE_INTERNAL_UVD_SD:
814 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD;
815 goto restart_search;
816 case POWER_STATE_TYPE_INTERNAL_UVD_HD:
817 case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
818 case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
819 if (rdev->pm.dpm.uvd_ps) {
820 return rdev->pm.dpm.uvd_ps;
821 } else {
822 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
823 goto restart_search;
824 }
825 case POWER_STATE_TYPE_INTERNAL_THERMAL:
826 dpm_state = POWER_STATE_TYPE_INTERNAL_ACPI;
827 goto restart_search;
828 case POWER_STATE_TYPE_INTERNAL_ACPI:
829 dpm_state = POWER_STATE_TYPE_BATTERY;
830 goto restart_search;
831 case POWER_STATE_TYPE_BATTERY:
832 case POWER_STATE_TYPE_BALANCED:
833 case POWER_STATE_TYPE_INTERNAL_3DPERF:
834 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
835 goto restart_search;
836 default:
837 break;
838 }
839
840 return NULL;
841 }
842
843 static void radeon_dpm_change_power_state_locked(struct radeon_device *rdev)
844 {
845 int i;
846 struct radeon_ps *ps;
847 enum radeon_pm_state_type dpm_state;
848 int ret;
849
850 /* if dpm init failed */
851 if (!rdev->pm.dpm_enabled)
852 return;
853
854 if (rdev->pm.dpm.user_state != rdev->pm.dpm.state) {
855 /* add other state override checks here */
856 if ((!rdev->pm.dpm.thermal_active) &&
857 (!rdev->pm.dpm.uvd_active))
858 rdev->pm.dpm.state = rdev->pm.dpm.user_state;
859 }
860 dpm_state = rdev->pm.dpm.state;
861
862 ps = radeon_dpm_pick_power_state(rdev, dpm_state);
863 if (ps)
864 rdev->pm.dpm.requested_ps = ps;
865 else
866 return;
867
868 /* no need to reprogram if nothing changed unless we are on BTC+ */
869 if (rdev->pm.dpm.current_ps == rdev->pm.dpm.requested_ps) {
870 /* vce just modifies an existing state so force a change */
871 if (ps->vce_active != rdev->pm.dpm.vce_active)
872 goto force;
873 if ((rdev->family < CHIP_BARTS) || (rdev->flags & RADEON_IS_IGP)) {
874 /* for pre-BTC and APUs if the num crtcs changed but state is the same,
875 * all we need to do is update the display configuration.
876 */
877 if (rdev->pm.dpm.new_active_crtcs != rdev->pm.dpm.current_active_crtcs) {
878 /* update display watermarks based on new power state */
879 radeon_bandwidth_update(rdev);
880 /* update displays */
881 radeon_dpm_display_configuration_changed(rdev);
882 rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;
883 rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;
884 }
885 return;
886 } else {
887 /* for BTC+ if the num crtcs hasn't changed and state is the same,
888 * nothing to do, if the num crtcs is > 1 and state is the same,
889 * update display configuration.
890 */
891 if (rdev->pm.dpm.new_active_crtcs ==
892 rdev->pm.dpm.current_active_crtcs) {
893 return;
894 } else {
895 if ((rdev->pm.dpm.current_active_crtc_count > 1) &&
896 (rdev->pm.dpm.new_active_crtc_count > 1)) {
897 /* update display watermarks based on new power state */
898 radeon_bandwidth_update(rdev);
899 /* update displays */
900 radeon_dpm_display_configuration_changed(rdev);
901 rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;
902 rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;
903 return;
904 }
905 }
906 }
907 }
908
909 force:
910 if (radeon_dpm == 1) {
911 printk("switching from power state:\n");
912 radeon_dpm_print_power_state(rdev, rdev->pm.dpm.current_ps);
913 printk("switching to power state:\n");
914 radeon_dpm_print_power_state(rdev, rdev->pm.dpm.requested_ps);
915 }
916
917 mutex_lock(&rdev->ddev->struct_mutex);
918 down_write(&rdev->pm.mclk_lock);
919 mutex_lock(&rdev->ring_lock);
920
921 /* update whether vce is active */
922 ps->vce_active = rdev->pm.dpm.vce_active;
923
924 ret = radeon_dpm_pre_set_power_state(rdev);
925 if (ret)
926 goto done;
927
928 /* update display watermarks based on new power state */
929 radeon_bandwidth_update(rdev);
930 /* update displays */
931 radeon_dpm_display_configuration_changed(rdev);
932
933 rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;
934 rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;
935
936 /* wait for the rings to drain */
937 for (i = 0; i < RADEON_NUM_RINGS; i++) {
938 struct radeon_ring *ring = &rdev->ring[i];
939 if (ring->ready)
940 radeon_fence_wait_empty(rdev, i);
941 }
942
943 /* program the new power state */
944 radeon_dpm_set_power_state(rdev);
945
946 /* update current power state */
947 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps;
948
949 radeon_dpm_post_set_power_state(rdev);
950
951 if (rdev->asic->dpm.force_performance_level) {
952 if (rdev->pm.dpm.thermal_active) {
953 enum radeon_dpm_forced_level level = rdev->pm.dpm.forced_level;
954 /* force low perf level for thermal */
955 radeon_dpm_force_performance_level(rdev, RADEON_DPM_FORCED_LEVEL_LOW);
956 /* save the user's level */
957 rdev->pm.dpm.forced_level = level;
958 } else {
959 /* otherwise, user selected level */
960 radeon_dpm_force_performance_level(rdev, rdev->pm.dpm.forced_level);
961 }
962 }
963
964 done:
965 mutex_unlock(&rdev->ring_lock);
966 up_write(&rdev->pm.mclk_lock);
967 mutex_unlock(&rdev->ddev->struct_mutex);
968 }
969
970 void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable)
971 {
972 enum radeon_pm_state_type dpm_state;
973
974 if (rdev->asic->dpm.powergate_uvd) {
975 mutex_lock(&rdev->pm.mutex);
976 /* don't powergate anything if we
977 have active but pause streams */
978 enable |= rdev->pm.dpm.sd > 0;
979 enable |= rdev->pm.dpm.hd > 0;
980 /* enable/disable UVD */
981 radeon_dpm_powergate_uvd(rdev, !enable);
982 mutex_unlock(&rdev->pm.mutex);
983 } else {
984 if (enable) {
985 mutex_lock(&rdev->pm.mutex);
986 rdev->pm.dpm.uvd_active = true;
987 /* disable this for now */
988 #if 0
989 if ((rdev->pm.dpm.sd == 1) && (rdev->pm.dpm.hd == 0))
990 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_SD;
991 else if ((rdev->pm.dpm.sd == 2) && (rdev->pm.dpm.hd == 0))
992 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD;
993 else if ((rdev->pm.dpm.sd == 0) && (rdev->pm.dpm.hd == 1))
994 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD;
995 else if ((rdev->pm.dpm.sd == 0) && (rdev->pm.dpm.hd == 2))
996 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD2;
997 else
998 #endif
999 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD;
1000 rdev->pm.dpm.state = dpm_state;
1001 mutex_unlock(&rdev->pm.mutex);
1002 } else {
1003 mutex_lock(&rdev->pm.mutex);
1004 rdev->pm.dpm.uvd_active = false;
1005 mutex_unlock(&rdev->pm.mutex);
1006 }
1007
1008 radeon_pm_compute_clocks(rdev);
1009 }
1010 }
1011
1012 void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable)
1013 {
1014 if (enable) {
1015 mutex_lock(&rdev->pm.mutex);
1016 rdev->pm.dpm.vce_active = true;
1017 /* XXX select vce level based on ring/task */
1018 rdev->pm.dpm.vce_level = RADEON_VCE_LEVEL_AC_ALL;
1019 mutex_unlock(&rdev->pm.mutex);
1020 } else {
1021 mutex_lock(&rdev->pm.mutex);
1022 rdev->pm.dpm.vce_active = false;
1023 mutex_unlock(&rdev->pm.mutex);
1024 }
1025
1026 radeon_pm_compute_clocks(rdev);
1027 }
1028
1029 static void radeon_pm_suspend_old(struct radeon_device *rdev)
1030 {
1031 mutex_lock(&rdev->pm.mutex);
1032 if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
1033 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE)
1034 rdev->pm.dynpm_state = DYNPM_STATE_SUSPENDED;
1035 }
1036 mutex_unlock(&rdev->pm.mutex);
1037
1038 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
1039 }
1040
1041 static void radeon_pm_suspend_dpm(struct radeon_device *rdev)
1042 {
1043 mutex_lock(&rdev->pm.mutex);
1044 /* disable dpm */
1045 radeon_dpm_disable(rdev);
1046 /* reset the power state */
1047 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps;
1048 rdev->pm.dpm_enabled = false;
1049 mutex_unlock(&rdev->pm.mutex);
1050 }
1051
1052 void radeon_pm_suspend(struct radeon_device *rdev)
1053 {
1054 if (rdev->pm.pm_method == PM_METHOD_DPM)
1055 radeon_pm_suspend_dpm(rdev);
1056 else
1057 radeon_pm_suspend_old(rdev);
1058 }
1059
1060 static void radeon_pm_resume_old(struct radeon_device *rdev)
1061 {
1062 /* set up the default clocks if the MC ucode is loaded */
1063 if ((rdev->family >= CHIP_BARTS) &&
1064 (rdev->family <= CHIP_CAYMAN) &&
1065 rdev->mc_fw) {
1066 if (rdev->pm.default_vddc)
1067 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
1068 SET_VOLTAGE_TYPE_ASIC_VDDC);
1069 if (rdev->pm.default_vddci)
1070 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
1071 SET_VOLTAGE_TYPE_ASIC_VDDCI);
1072 if (rdev->pm.default_sclk)
1073 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
1074 if (rdev->pm.default_mclk)
1075 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
1076 }
1077 /* asic init will reset the default power state */
1078 mutex_lock(&rdev->pm.mutex);
1079 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
1080 rdev->pm.current_clock_mode_index = 0;
1081 rdev->pm.current_sclk = rdev->pm.default_sclk;
1082 rdev->pm.current_mclk = rdev->pm.default_mclk;
1083 if (rdev->pm.power_state) {
1084 rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
1085 rdev->pm.current_vddci = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.vddci;
1086 }
1087 if (rdev->pm.pm_method == PM_METHOD_DYNPM
1088 && rdev->pm.dynpm_state == DYNPM_STATE_SUSPENDED) {
1089 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
1090 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1091 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
1092 }
1093 mutex_unlock(&rdev->pm.mutex);
1094 radeon_pm_compute_clocks(rdev);
1095 }
1096
1097 static void radeon_pm_resume_dpm(struct radeon_device *rdev)
1098 {
1099 int ret;
1100
1101 /* asic init will reset to the boot state */
1102 mutex_lock(&rdev->pm.mutex);
1103 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps;
1104 radeon_dpm_setup_asic(rdev);
1105 ret = radeon_dpm_enable(rdev);
1106 mutex_unlock(&rdev->pm.mutex);
1107 if (ret)
1108 goto dpm_resume_fail;
1109 rdev->pm.dpm_enabled = true;
1110 return;
1111
1112 dpm_resume_fail:
1113 DRM_ERROR("radeon: dpm resume failed\n");
1114 if ((rdev->family >= CHIP_BARTS) &&
1115 (rdev->family <= CHIP_CAYMAN) &&
1116 rdev->mc_fw) {
1117 if (rdev->pm.default_vddc)
1118 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
1119 SET_VOLTAGE_TYPE_ASIC_VDDC);
1120 if (rdev->pm.default_vddci)
1121 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
1122 SET_VOLTAGE_TYPE_ASIC_VDDCI);
1123 if (rdev->pm.default_sclk)
1124 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
1125 if (rdev->pm.default_mclk)
1126 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
1127 }
1128 }
1129
1130 void radeon_pm_resume(struct radeon_device *rdev)
1131 {
1132 if (rdev->pm.pm_method == PM_METHOD_DPM)
1133 radeon_pm_resume_dpm(rdev);
1134 else
1135 radeon_pm_resume_old(rdev);
1136 }
1137
1138 static int radeon_pm_init_old(struct radeon_device *rdev)
1139 {
1140 int ret;
1141
1142 rdev->pm.profile = PM_PROFILE_DEFAULT;
1143 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
1144 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
1145 rdev->pm.dynpm_can_upclock = true;
1146 rdev->pm.dynpm_can_downclock = true;
1147 rdev->pm.default_sclk = rdev->clock.default_sclk;
1148 rdev->pm.default_mclk = rdev->clock.default_mclk;
1149 rdev->pm.current_sclk = rdev->clock.default_sclk;
1150 rdev->pm.current_mclk = rdev->clock.default_mclk;
1151 rdev->pm.int_thermal_type = THERMAL_TYPE_NONE;
1152
1153 if (rdev->bios) {
1154 if (rdev->is_atom_bios)
1155 radeon_atombios_get_power_modes(rdev);
1156 else
1157 radeon_combios_get_power_modes(rdev);
1158 radeon_pm_print_states(rdev);
1159 radeon_pm_init_profile(rdev);
1160 /* set up the default clocks if the MC ucode is loaded */
1161 if ((rdev->family >= CHIP_BARTS) &&
1162 (rdev->family <= CHIP_CAYMAN) &&
1163 rdev->mc_fw) {
1164 if (rdev->pm.default_vddc)
1165 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
1166 SET_VOLTAGE_TYPE_ASIC_VDDC);
1167 if (rdev->pm.default_vddci)
1168 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
1169 SET_VOLTAGE_TYPE_ASIC_VDDCI);
1170 if (rdev->pm.default_sclk)
1171 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
1172 if (rdev->pm.default_mclk)
1173 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
1174 }
1175 }
1176
1177 /* set up the internal thermal sensor if applicable */
1178 ret = radeon_hwmon_init(rdev);
1179 if (ret)
1180 return ret;
1181
1182 INIT_DELAYED_WORK(&rdev->pm.dynpm_idle_work, radeon_dynpm_idle_work_handler);
1183
1184 if (rdev->pm.num_power_states > 1) {
1185 /* where's the best place to put these? */
1186 ret = device_create_file(rdev->dev, &dev_attr_power_profile);
1187 if (ret)
1188 DRM_ERROR("failed to create device file for power profile\n");
1189 ret = device_create_file(rdev->dev, &dev_attr_power_method);
1190 if (ret)
1191 DRM_ERROR("failed to create device file for power method\n");
1192
1193 if (radeon_debugfs_pm_init(rdev)) {
1194 DRM_ERROR("Failed to register debugfs file for PM!\n");
1195 }
1196
1197 DRM_INFO("radeon: power management initialized\n");
1198 }
1199
1200 return 0;
1201 }
1202
1203 static void radeon_dpm_print_power_states(struct radeon_device *rdev)
1204 {
1205 int i;
1206
1207 for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
1208 printk("== power state %d ==\n", i);
1209 radeon_dpm_print_power_state(rdev, &rdev->pm.dpm.ps[i]);
1210 }
1211 }
1212
1213 static int radeon_pm_init_dpm(struct radeon_device *rdev)
1214 {
1215 int ret;
1216
1217 /* default to balanced state */
1218 rdev->pm.dpm.state = POWER_STATE_TYPE_BALANCED;
1219 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
1220 rdev->pm.dpm.forced_level = RADEON_DPM_FORCED_LEVEL_AUTO;
1221 rdev->pm.default_sclk = rdev->clock.default_sclk;
1222 rdev->pm.default_mclk = rdev->clock.default_mclk;
1223 rdev->pm.current_sclk = rdev->clock.default_sclk;
1224 rdev->pm.current_mclk = rdev->clock.default_mclk;
1225 rdev->pm.int_thermal_type = THERMAL_TYPE_NONE;
1226
1227 if (rdev->bios && rdev->is_atom_bios)
1228 radeon_atombios_get_power_modes(rdev);
1229 else
1230 return -EINVAL;
1231
1232 /* set up the internal thermal sensor if applicable */
1233 ret = radeon_hwmon_init(rdev);
1234 if (ret)
1235 return ret;
1236
1237 INIT_WORK(&rdev->pm.dpm.thermal.work, radeon_dpm_thermal_work_handler);
1238 mutex_lock(&rdev->pm.mutex);
1239 radeon_dpm_init(rdev);
1240 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps;
1241 if (radeon_dpm == 1)
1242 radeon_dpm_print_power_states(rdev);
1243 radeon_dpm_setup_asic(rdev);
1244 ret = radeon_dpm_enable(rdev);
1245 mutex_unlock(&rdev->pm.mutex);
1246 if (ret)
1247 goto dpm_failed;
1248 rdev->pm.dpm_enabled = true;
1249
1250 ret = device_create_file(rdev->dev, &dev_attr_power_dpm_state);
1251 if (ret)
1252 DRM_ERROR("failed to create device file for dpm state\n");
1253 ret = device_create_file(rdev->dev, &dev_attr_power_dpm_force_performance_level);
1254 if (ret)
1255 DRM_ERROR("failed to create device file for dpm state\n");
1256 /* XXX: these are noops for dpm but are here for backwards compat */
1257 ret = device_create_file(rdev->dev, &dev_attr_power_profile);
1258 if (ret)
1259 DRM_ERROR("failed to create device file for power profile\n");
1260 ret = device_create_file(rdev->dev, &dev_attr_power_method);
1261 if (ret)
1262 DRM_ERROR("failed to create device file for power method\n");
1263
1264 if (radeon_debugfs_pm_init(rdev)) {
1265 DRM_ERROR("Failed to register debugfs file for dpm!\n");
1266 }
1267
1268 DRM_INFO("radeon: dpm initialized\n");
1269
1270 return 0;
1271
1272 dpm_failed:
1273 rdev->pm.dpm_enabled = false;
1274 if ((rdev->family >= CHIP_BARTS) &&
1275 (rdev->family <= CHIP_CAYMAN) &&
1276 rdev->mc_fw) {
1277 if (rdev->pm.default_vddc)
1278 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
1279 SET_VOLTAGE_TYPE_ASIC_VDDC);
1280 if (rdev->pm.default_vddci)
1281 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
1282 SET_VOLTAGE_TYPE_ASIC_VDDCI);
1283 if (rdev->pm.default_sclk)
1284 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
1285 if (rdev->pm.default_mclk)
1286 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
1287 }
1288 DRM_ERROR("radeon: dpm initialization failed\n");
1289 return ret;
1290 }
1291
1292 int radeon_pm_init(struct radeon_device *rdev)
1293 {
1294 /* enable dpm on rv6xx+ */
1295 switch (rdev->family) {
1296 case CHIP_RV610:
1297 case CHIP_RV630:
1298 case CHIP_RV620:
1299 case CHIP_RV635:
1300 case CHIP_RV670:
1301 case CHIP_RS780:
1302 case CHIP_RS880:
1303 case CHIP_RV770:
1304 case CHIP_BARTS:
1305 case CHIP_TURKS:
1306 case CHIP_CAICOS:
1307 case CHIP_CAYMAN:
1308 /* DPM requires the RLC, RV770+ dGPU requires SMC */
1309 if (!rdev->rlc_fw)
1310 rdev->pm.pm_method = PM_METHOD_PROFILE;
1311 else if ((rdev->family >= CHIP_RV770) &&
1312 (!(rdev->flags & RADEON_IS_IGP)) &&
1313 (!rdev->smc_fw))
1314 rdev->pm.pm_method = PM_METHOD_PROFILE;
1315 else if (radeon_dpm == 1)
1316 rdev->pm.pm_method = PM_METHOD_DPM;
1317 else
1318 rdev->pm.pm_method = PM_METHOD_PROFILE;
1319 break;
1320 case CHIP_RV730:
1321 case CHIP_RV710:
1322 case CHIP_RV740:
1323 case CHIP_CEDAR:
1324 case CHIP_REDWOOD:
1325 case CHIP_JUNIPER:
1326 case CHIP_CYPRESS:
1327 case CHIP_HEMLOCK:
1328 case CHIP_PALM:
1329 case CHIP_SUMO:
1330 case CHIP_SUMO2:
1331 case CHIP_ARUBA:
1332 case CHIP_TAHITI:
1333 case CHIP_PITCAIRN:
1334 case CHIP_VERDE:
1335 case CHIP_OLAND:
1336 case CHIP_HAINAN:
1337 case CHIP_BONAIRE:
1338 case CHIP_KABINI:
1339 case CHIP_KAVERI:
1340 case CHIP_HAWAII:
1341 case CHIP_MULLINS:
1342 /* DPM requires the RLC, RV770+ dGPU requires SMC */
1343 if (!rdev->rlc_fw)
1344 rdev->pm.pm_method = PM_METHOD_PROFILE;
1345 else if ((rdev->family >= CHIP_RV770) &&
1346 (!(rdev->flags & RADEON_IS_IGP)) &&
1347 (!rdev->smc_fw))
1348 rdev->pm.pm_method = PM_METHOD_PROFILE;
1349 else if (radeon_dpm == 0)
1350 rdev->pm.pm_method = PM_METHOD_PROFILE;
1351 else
1352 rdev->pm.pm_method = PM_METHOD_DPM;
1353 break;
1354 default:
1355 /* default to profile method */
1356 rdev->pm.pm_method = PM_METHOD_PROFILE;
1357 break;
1358 }
1359
1360 if (rdev->pm.pm_method == PM_METHOD_DPM)
1361 return radeon_pm_init_dpm(rdev);
1362 else
1363 return radeon_pm_init_old(rdev);
1364 }
1365
1366 int radeon_pm_late_init(struct radeon_device *rdev)
1367 {
1368 int ret = 0;
1369
1370 if (rdev->pm.pm_method == PM_METHOD_DPM) {
1371 mutex_lock(&rdev->pm.mutex);
1372 ret = radeon_dpm_late_enable(rdev);
1373 mutex_unlock(&rdev->pm.mutex);
1374 }
1375 return ret;
1376 }
1377
1378 static void radeon_pm_fini_old(struct radeon_device *rdev)
1379 {
1380 if (rdev->pm.num_power_states > 1) {
1381 mutex_lock(&rdev->pm.mutex);
1382 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
1383 rdev->pm.profile = PM_PROFILE_DEFAULT;
1384 radeon_pm_update_profile(rdev);
1385 radeon_pm_set_clocks(rdev);
1386 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
1387 /* reset default clocks */
1388 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
1389 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
1390 radeon_pm_set_clocks(rdev);
1391 }
1392 mutex_unlock(&rdev->pm.mutex);
1393
1394 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
1395
1396 device_remove_file(rdev->dev, &dev_attr_power_profile);
1397 device_remove_file(rdev->dev, &dev_attr_power_method);
1398 }
1399
1400 radeon_hwmon_fini(rdev);
1401
1402 if (rdev->pm.power_state)
1403 kfree(rdev->pm.power_state);
1404 }
1405
1406 static void radeon_pm_fini_dpm(struct radeon_device *rdev)
1407 {
1408 if (rdev->pm.num_power_states > 1) {
1409 mutex_lock(&rdev->pm.mutex);
1410 radeon_dpm_disable(rdev);
1411 mutex_unlock(&rdev->pm.mutex);
1412
1413 device_remove_file(rdev->dev, &dev_attr_power_dpm_state);
1414 device_remove_file(rdev->dev, &dev_attr_power_dpm_force_performance_level);
1415 /* XXX backwards compat */
1416 device_remove_file(rdev->dev, &dev_attr_power_profile);
1417 device_remove_file(rdev->dev, &dev_attr_power_method);
1418 }
1419 radeon_dpm_fini(rdev);
1420
1421 radeon_hwmon_fini(rdev);
1422
1423 if (rdev->pm.power_state)
1424 kfree(rdev->pm.power_state);
1425 }
1426
1427 void radeon_pm_fini(struct radeon_device *rdev)
1428 {
1429 if (rdev->pm.pm_method == PM_METHOD_DPM)
1430 radeon_pm_fini_dpm(rdev);
1431 else
1432 radeon_pm_fini_old(rdev);
1433 }
1434
1435 static void radeon_pm_compute_clocks_old(struct radeon_device *rdev)
1436 {
1437 struct drm_device *ddev = rdev->ddev;
1438 struct drm_crtc *crtc;
1439 struct radeon_crtc *radeon_crtc;
1440
1441 if (rdev->pm.num_power_states < 2)
1442 return;
1443
1444 mutex_lock(&rdev->pm.mutex);
1445
1446 rdev->pm.active_crtcs = 0;
1447 rdev->pm.active_crtc_count = 0;
1448 if (rdev->num_crtc && rdev->mode_info.mode_config_initialized) {
1449 list_for_each_entry(crtc,
1450 &ddev->mode_config.crtc_list, head) {
1451 radeon_crtc = to_radeon_crtc(crtc);
1452 if (radeon_crtc->enabled) {
1453 rdev->pm.active_crtcs |= (1 << radeon_crtc->crtc_id);
1454 rdev->pm.active_crtc_count++;
1455 }
1456 }
1457 }
1458
1459 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
1460 radeon_pm_update_profile(rdev);
1461 radeon_pm_set_clocks(rdev);
1462 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
1463 if (rdev->pm.dynpm_state != DYNPM_STATE_DISABLED) {
1464 if (rdev->pm.active_crtc_count > 1) {
1465 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
1466 cancel_delayed_work(&rdev->pm.dynpm_idle_work);
1467
1468 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
1469 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
1470 radeon_pm_get_dynpm_state(rdev);
1471 radeon_pm_set_clocks(rdev);
1472
1473 DRM_DEBUG_DRIVER("radeon: dynamic power management deactivated\n");
1474 }
1475 } else if (rdev->pm.active_crtc_count == 1) {
1476 /* TODO: Increase clocks if needed for current mode */
1477
1478 if (rdev->pm.dynpm_state == DYNPM_STATE_MINIMUM) {
1479 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
1480 rdev->pm.dynpm_planned_action = DYNPM_ACTION_UPCLOCK;
1481 radeon_pm_get_dynpm_state(rdev);
1482 radeon_pm_set_clocks(rdev);
1483
1484 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1485 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
1486 } else if (rdev->pm.dynpm_state == DYNPM_STATE_PAUSED) {
1487 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
1488 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1489 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
1490 DRM_DEBUG_DRIVER("radeon: dynamic power management activated\n");
1491 }
1492 } else { /* count == 0 */
1493 if (rdev->pm.dynpm_state != DYNPM_STATE_MINIMUM) {
1494 cancel_delayed_work(&rdev->pm.dynpm_idle_work);
1495
1496 rdev->pm.dynpm_state = DYNPM_STATE_MINIMUM;
1497 rdev->pm.dynpm_planned_action = DYNPM_ACTION_MINIMUM;
1498 radeon_pm_get_dynpm_state(rdev);
1499 radeon_pm_set_clocks(rdev);
1500 }
1501 }
1502 }
1503 }
1504
1505 mutex_unlock(&rdev->pm.mutex);
1506 }
1507
1508 static void radeon_pm_compute_clocks_dpm(struct radeon_device *rdev)
1509 {
1510 struct drm_device *ddev = rdev->ddev;
1511 struct drm_crtc *crtc;
1512 struct radeon_crtc *radeon_crtc;
1513
1514 if (!rdev->pm.dpm_enabled)
1515 return;
1516
1517 mutex_lock(&rdev->pm.mutex);
1518
1519 /* update active crtc counts */
1520 rdev->pm.dpm.new_active_crtcs = 0;
1521 rdev->pm.dpm.new_active_crtc_count = 0;
1522 if (rdev->num_crtc && rdev->mode_info.mode_config_initialized) {
1523 list_for_each_entry(crtc,
1524 &ddev->mode_config.crtc_list, head) {
1525 radeon_crtc = to_radeon_crtc(crtc);
1526 if (crtc->enabled) {
1527 rdev->pm.dpm.new_active_crtcs |= (1 << radeon_crtc->crtc_id);
1528 rdev->pm.dpm.new_active_crtc_count++;
1529 }
1530 }
1531 }
1532
1533 /* update battery/ac status */
1534 if (power_supply_is_system_supplied() > 0)
1535 rdev->pm.dpm.ac_power = true;
1536 else
1537 rdev->pm.dpm.ac_power = false;
1538
1539 radeon_dpm_change_power_state_locked(rdev);
1540
1541 mutex_unlock(&rdev->pm.mutex);
1542
1543 }
1544
1545 void radeon_pm_compute_clocks(struct radeon_device *rdev)
1546 {
1547 if (rdev->pm.pm_method == PM_METHOD_DPM)
1548 radeon_pm_compute_clocks_dpm(rdev);
1549 else
1550 radeon_pm_compute_clocks_old(rdev);
1551 }
1552
1553 static bool radeon_pm_in_vbl(struct radeon_device *rdev)
1554 {
1555 int crtc, vpos, hpos, vbl_status;
1556 bool in_vbl = true;
1557
1558 /* Iterate over all active crtc's. All crtc's must be in vblank,
1559 * otherwise return in_vbl == false.
1560 */
1561 for (crtc = 0; (crtc < rdev->num_crtc) && in_vbl; crtc++) {
1562 if (rdev->pm.active_crtcs & (1 << crtc)) {
1563 vbl_status = radeon_get_crtc_scanoutpos(rdev->ddev, crtc, 0, &vpos, &hpos, NULL, NULL);
1564 if ((vbl_status & DRM_SCANOUTPOS_VALID) &&
1565 !(vbl_status & DRM_SCANOUTPOS_INVBL))
1566 in_vbl = false;
1567 }
1568 }
1569
1570 return in_vbl;
1571 }
1572
1573 static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish)
1574 {
1575 u32 stat_crtc = 0;
1576 bool in_vbl = radeon_pm_in_vbl(rdev);
1577
1578 if (in_vbl == false)
1579 DRM_DEBUG_DRIVER("not in vbl for pm change %08x at %s\n", stat_crtc,
1580 finish ? "exit" : "entry");
1581 return in_vbl;
1582 }
1583
1584 static void radeon_dynpm_idle_work_handler(struct work_struct *work)
1585 {
1586 struct radeon_device *rdev;
1587 int resched;
1588 rdev = container_of(work, struct radeon_device,
1589 pm.dynpm_idle_work.work);
1590
1591 resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev);
1592 mutex_lock(&rdev->pm.mutex);
1593 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
1594 int not_processed = 0;
1595 int i;
1596
1597 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
1598 struct radeon_ring *ring = &rdev->ring[i];
1599
1600 if (ring->ready) {
1601 not_processed += radeon_fence_count_emitted(rdev, i);
1602 if (not_processed >= 3)
1603 break;
1604 }
1605 }
1606
1607 if (not_processed >= 3) { /* should upclock */
1608 if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_DOWNCLOCK) {
1609 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
1610 } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
1611 rdev->pm.dynpm_can_upclock) {
1612 rdev->pm.dynpm_planned_action =
1613 DYNPM_ACTION_UPCLOCK;
1614 rdev->pm.dynpm_action_timeout = jiffies +
1615 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
1616 }
1617 } else if (not_processed == 0) { /* should downclock */
1618 if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_UPCLOCK) {
1619 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
1620 } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
1621 rdev->pm.dynpm_can_downclock) {
1622 rdev->pm.dynpm_planned_action =
1623 DYNPM_ACTION_DOWNCLOCK;
1624 rdev->pm.dynpm_action_timeout = jiffies +
1625 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
1626 }
1627 }
1628
1629 /* Note, radeon_pm_set_clocks is called with static_switch set
1630 * to false since we want to wait for vbl to avoid flicker.
1631 */
1632 if (rdev->pm.dynpm_planned_action != DYNPM_ACTION_NONE &&
1633 jiffies > rdev->pm.dynpm_action_timeout) {
1634 radeon_pm_get_dynpm_state(rdev);
1635 radeon_pm_set_clocks(rdev);
1636 }
1637
1638 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1639 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
1640 }
1641 mutex_unlock(&rdev->pm.mutex);
1642 ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched);
1643 }
1644
1645 /*
1646 * Debugfs info
1647 */
1648 #if defined(CONFIG_DEBUG_FS)
1649
1650 static int radeon_debugfs_pm_info(struct seq_file *m, void *data)
1651 {
1652 struct drm_info_node *node = (struct drm_info_node *) m->private;
1653 struct drm_device *dev = node->minor->dev;
1654 struct radeon_device *rdev = dev->dev_private;
1655 struct drm_device *ddev = rdev->ddev;
1656
1657 if ((rdev->flags & RADEON_IS_PX) &&
1658 (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) {
1659 seq_printf(m, "PX asic powered off\n");
1660 } else if (rdev->pm.dpm_enabled) {
1661 mutex_lock(&rdev->pm.mutex);
1662 if (rdev->asic->dpm.debugfs_print_current_performance_level)
1663 radeon_dpm_debugfs_print_current_performance_level(rdev, m);
1664 else
1665 seq_printf(m, "Debugfs support not implemented for this asic\n");
1666 mutex_unlock(&rdev->pm.mutex);
1667 } else {
1668 seq_printf(m, "default engine clock: %u0 kHz\n", rdev->pm.default_sclk);
1669 /* radeon_get_engine_clock is not reliable on APUs so just print the current clock */
1670 if ((rdev->family >= CHIP_PALM) && (rdev->flags & RADEON_IS_IGP))
1671 seq_printf(m, "current engine clock: %u0 kHz\n", rdev->pm.current_sclk);
1672 else
1673 seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev));
1674 seq_printf(m, "default memory clock: %u0 kHz\n", rdev->pm.default_mclk);
1675 if (rdev->asic->pm.get_memory_clock)
1676 seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev));
1677 if (rdev->pm.current_vddc)
1678 seq_printf(m, "voltage: %u mV\n", rdev->pm.current_vddc);
1679 if (rdev->asic->pm.get_pcie_lanes)
1680 seq_printf(m, "PCIE lanes: %d\n", radeon_get_pcie_lanes(rdev));
1681 }
1682
1683 return 0;
1684 }
1685
1686 static struct drm_info_list radeon_pm_info_list[] = {
1687 {"radeon_pm_info", radeon_debugfs_pm_info, 0, NULL},
1688 };
1689 #endif
1690
1691 static int radeon_debugfs_pm_init(struct radeon_device *rdev)
1692 {
1693 #if defined(CONFIG_DEBUG_FS)
1694 return radeon_debugfs_add_files(rdev, radeon_pm_info_list, ARRAY_SIZE(radeon_pm_info_list));
1695 #else
1696 return 0;
1697 #endif
1698 }
Linux kernel - Deliverables
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