2 * Permission is hereby granted, free of charge, to any person obtaining a
3 * copy of this software and associated documentation files (the "Software"),
4 * to deal in the Software without restriction, including without limitation
5 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
6 * and/or sell copies of the Software, and to permit persons to whom the
7 * Software is furnished to do so, subject to the following conditions:
9 * The above copyright notice and this permission notice shall be included in
10 * all copies or substantial portions of the Software.
12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
13 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
14 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
15 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
16 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
17 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
18 * OTHER DEALINGS IN THE SOFTWARE.
20 * Authors: Rafał Miłecki <zajec5@gmail.com>
21 * Alex Deucher <alexdeucher@gmail.com>
27 #include <linux/power_supply.h>
28 #include <linux/hwmon.h>
29 #include <linux/hwmon-sysfs.h>
31 #define RADEON_IDLE_LOOP_MS 100
32 #define RADEON_RECLOCK_DELAY_MS 200
33 #define RADEON_WAIT_VBLANK_TIMEOUT 200
35 static const char *radeon_pm_state_type_name
[5] = {
43 static void radeon_dynpm_idle_work_handler(struct work_struct
*work
);
44 static int radeon_debugfs_pm_init(struct radeon_device
*rdev
);
45 static bool radeon_pm_in_vbl(struct radeon_device
*rdev
);
46 static bool radeon_pm_debug_check_in_vbl(struct radeon_device
*rdev
, bool finish
);
47 static void radeon_pm_update_profile(struct radeon_device
*rdev
);
48 static void radeon_pm_set_clocks(struct radeon_device
*rdev
);
50 int radeon_pm_get_type_index(struct radeon_device
*rdev
,
51 enum radeon_pm_state_type ps_type
,
55 int found_instance
= -1;
57 for (i
= 0; i
< rdev
->pm
.num_power_states
; i
++) {
58 if (rdev
->pm
.power_state
[i
].type
== ps_type
) {
60 if (found_instance
== instance
)
64 /* return default if no match */
65 return rdev
->pm
.default_power_state_index
;
68 void radeon_pm_acpi_event_handler(struct radeon_device
*rdev
)
70 if ((rdev
->pm
.pm_method
== PM_METHOD_DPM
) && rdev
->pm
.dpm_enabled
) {
71 mutex_lock(&rdev
->pm
.mutex
);
72 if (power_supply_is_system_supplied() > 0)
73 rdev
->pm
.dpm
.ac_power
= true;
75 rdev
->pm
.dpm
.ac_power
= false;
76 if (rdev
->family
== CHIP_ARUBA
) {
77 if (rdev
->asic
->dpm
.enable_bapm
)
78 radeon_dpm_enable_bapm(rdev
, rdev
->pm
.dpm
.ac_power
);
80 mutex_unlock(&rdev
->pm
.mutex
);
81 } else if (rdev
->pm
.pm_method
== PM_METHOD_PROFILE
) {
82 if (rdev
->pm
.profile
== PM_PROFILE_AUTO
) {
83 mutex_lock(&rdev
->pm
.mutex
);
84 radeon_pm_update_profile(rdev
);
85 radeon_pm_set_clocks(rdev
);
86 mutex_unlock(&rdev
->pm
.mutex
);
91 static void radeon_pm_update_profile(struct radeon_device
*rdev
)
93 switch (rdev
->pm
.profile
) {
94 case PM_PROFILE_DEFAULT
:
95 rdev
->pm
.profile_index
= PM_PROFILE_DEFAULT_IDX
;
98 if (power_supply_is_system_supplied() > 0) {
99 if (rdev
->pm
.active_crtc_count
> 1)
100 rdev
->pm
.profile_index
= PM_PROFILE_HIGH_MH_IDX
;
102 rdev
->pm
.profile_index
= PM_PROFILE_HIGH_SH_IDX
;
104 if (rdev
->pm
.active_crtc_count
> 1)
105 rdev
->pm
.profile_index
= PM_PROFILE_MID_MH_IDX
;
107 rdev
->pm
.profile_index
= PM_PROFILE_MID_SH_IDX
;
111 if (rdev
->pm
.active_crtc_count
> 1)
112 rdev
->pm
.profile_index
= PM_PROFILE_LOW_MH_IDX
;
114 rdev
->pm
.profile_index
= PM_PROFILE_LOW_SH_IDX
;
117 if (rdev
->pm
.active_crtc_count
> 1)
118 rdev
->pm
.profile_index
= PM_PROFILE_MID_MH_IDX
;
120 rdev
->pm
.profile_index
= PM_PROFILE_MID_SH_IDX
;
122 case PM_PROFILE_HIGH
:
123 if (rdev
->pm
.active_crtc_count
> 1)
124 rdev
->pm
.profile_index
= PM_PROFILE_HIGH_MH_IDX
;
126 rdev
->pm
.profile_index
= PM_PROFILE_HIGH_SH_IDX
;
130 if (rdev
->pm
.active_crtc_count
== 0) {
131 rdev
->pm
.requested_power_state_index
=
132 rdev
->pm
.profiles
[rdev
->pm
.profile_index
].dpms_off_ps_idx
;
133 rdev
->pm
.requested_clock_mode_index
=
134 rdev
->pm
.profiles
[rdev
->pm
.profile_index
].dpms_off_cm_idx
;
136 rdev
->pm
.requested_power_state_index
=
137 rdev
->pm
.profiles
[rdev
->pm
.profile_index
].dpms_on_ps_idx
;
138 rdev
->pm
.requested_clock_mode_index
=
139 rdev
->pm
.profiles
[rdev
->pm
.profile_index
].dpms_on_cm_idx
;
143 static void radeon_unmap_vram_bos(struct radeon_device
*rdev
)
145 struct radeon_bo
*bo
, *n
;
147 if (list_empty(&rdev
->gem
.objects
))
150 list_for_each_entry_safe(bo
, n
, &rdev
->gem
.objects
, list
) {
151 if (bo
->tbo
.mem
.mem_type
== TTM_PL_VRAM
)
152 ttm_bo_unmap_virtual(&bo
->tbo
);
156 static void radeon_sync_with_vblank(struct radeon_device
*rdev
)
158 if (rdev
->pm
.active_crtcs
) {
159 rdev
->pm
.vblank_sync
= false;
161 rdev
->irq
.vblank_queue
, rdev
->pm
.vblank_sync
,
162 msecs_to_jiffies(RADEON_WAIT_VBLANK_TIMEOUT
));
166 static void radeon_set_power_state(struct radeon_device
*rdev
)
169 bool misc_after
= false;
171 if ((rdev
->pm
.requested_clock_mode_index
== rdev
->pm
.current_clock_mode_index
) &&
172 (rdev
->pm
.requested_power_state_index
== rdev
->pm
.current_power_state_index
))
175 if (radeon_gui_idle(rdev
)) {
176 sclk
= rdev
->pm
.power_state
[rdev
->pm
.requested_power_state_index
].
177 clock_info
[rdev
->pm
.requested_clock_mode_index
].sclk
;
178 if (sclk
> rdev
->pm
.default_sclk
)
179 sclk
= rdev
->pm
.default_sclk
;
181 /* starting with BTC, there is one state that is used for both
182 * MH and SH. Difference is that we always use the high clock index for
185 if ((rdev
->pm
.pm_method
== PM_METHOD_PROFILE
) &&
186 (rdev
->family
>= CHIP_BARTS
) &&
187 rdev
->pm
.active_crtc_count
&&
188 ((rdev
->pm
.profile_index
== PM_PROFILE_MID_MH_IDX
) ||
189 (rdev
->pm
.profile_index
== PM_PROFILE_LOW_MH_IDX
)))
190 mclk
= rdev
->pm
.power_state
[rdev
->pm
.requested_power_state_index
].
191 clock_info
[rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_on_cm_idx
].mclk
;
193 mclk
= rdev
->pm
.power_state
[rdev
->pm
.requested_power_state_index
].
194 clock_info
[rdev
->pm
.requested_clock_mode_index
].mclk
;
196 if (mclk
> rdev
->pm
.default_mclk
)
197 mclk
= rdev
->pm
.default_mclk
;
199 /* upvolt before raising clocks, downvolt after lowering clocks */
200 if (sclk
< rdev
->pm
.current_sclk
)
203 radeon_sync_with_vblank(rdev
);
205 if (rdev
->pm
.pm_method
== PM_METHOD_DYNPM
) {
206 if (!radeon_pm_in_vbl(rdev
))
210 radeon_pm_prepare(rdev
);
213 /* voltage, pcie lanes, etc.*/
214 radeon_pm_misc(rdev
);
216 /* set engine clock */
217 if (sclk
!= rdev
->pm
.current_sclk
) {
218 radeon_pm_debug_check_in_vbl(rdev
, false);
219 radeon_set_engine_clock(rdev
, sclk
);
220 radeon_pm_debug_check_in_vbl(rdev
, true);
221 rdev
->pm
.current_sclk
= sclk
;
222 DRM_DEBUG_DRIVER("Setting: e: %d\n", sclk
);
225 /* set memory clock */
226 if (rdev
->asic
->pm
.set_memory_clock
&& (mclk
!= rdev
->pm
.current_mclk
)) {
227 radeon_pm_debug_check_in_vbl(rdev
, false);
228 radeon_set_memory_clock(rdev
, mclk
);
229 radeon_pm_debug_check_in_vbl(rdev
, true);
230 rdev
->pm
.current_mclk
= mclk
;
231 DRM_DEBUG_DRIVER("Setting: m: %d\n", mclk
);
235 /* voltage, pcie lanes, etc.*/
236 radeon_pm_misc(rdev
);
238 radeon_pm_finish(rdev
);
240 rdev
->pm
.current_power_state_index
= rdev
->pm
.requested_power_state_index
;
241 rdev
->pm
.current_clock_mode_index
= rdev
->pm
.requested_clock_mode_index
;
243 DRM_DEBUG_DRIVER("pm: GUI not idle!!!\n");
246 static void radeon_pm_set_clocks(struct radeon_device
*rdev
)
250 /* no need to take locks, etc. if nothing's going to change */
251 if ((rdev
->pm
.requested_clock_mode_index
== rdev
->pm
.current_clock_mode_index
) &&
252 (rdev
->pm
.requested_power_state_index
== rdev
->pm
.current_power_state_index
))
255 mutex_lock(&rdev
->ddev
->struct_mutex
);
256 down_write(&rdev
->pm
.mclk_lock
);
257 mutex_lock(&rdev
->ring_lock
);
259 /* wait for the rings to drain */
260 for (i
= 0; i
< RADEON_NUM_RINGS
; i
++) {
261 struct radeon_ring
*ring
= &rdev
->ring
[i
];
265 r
= radeon_fence_wait_empty(rdev
, i
);
267 /* needs a GPU reset dont reset here */
268 mutex_unlock(&rdev
->ring_lock
);
269 up_write(&rdev
->pm
.mclk_lock
);
270 mutex_unlock(&rdev
->ddev
->struct_mutex
);
275 radeon_unmap_vram_bos(rdev
);
277 if (rdev
->irq
.installed
) {
278 for (i
= 0; i
< rdev
->num_crtc
; i
++) {
279 if (rdev
->pm
.active_crtcs
& (1 << i
)) {
280 rdev
->pm
.req_vblank
|= (1 << i
);
281 drm_vblank_get(rdev
->ddev
, i
);
286 radeon_set_power_state(rdev
);
288 if (rdev
->irq
.installed
) {
289 for (i
= 0; i
< rdev
->num_crtc
; i
++) {
290 if (rdev
->pm
.req_vblank
& (1 << i
)) {
291 rdev
->pm
.req_vblank
&= ~(1 << i
);
292 drm_vblank_put(rdev
->ddev
, i
);
297 /* update display watermarks based on new power state */
298 radeon_update_bandwidth_info(rdev
);
299 if (rdev
->pm
.active_crtc_count
)
300 radeon_bandwidth_update(rdev
);
302 rdev
->pm
.dynpm_planned_action
= DYNPM_ACTION_NONE
;
304 mutex_unlock(&rdev
->ring_lock
);
305 up_write(&rdev
->pm
.mclk_lock
);
306 mutex_unlock(&rdev
->ddev
->struct_mutex
);
309 static void radeon_pm_print_states(struct radeon_device
*rdev
)
312 struct radeon_power_state
*power_state
;
313 struct radeon_pm_clock_info
*clock_info
;
315 DRM_DEBUG_DRIVER("%d Power State(s)\n", rdev
->pm
.num_power_states
);
316 for (i
= 0; i
< rdev
->pm
.num_power_states
; i
++) {
317 power_state
= &rdev
->pm
.power_state
[i
];
318 DRM_DEBUG_DRIVER("State %d: %s\n", i
,
319 radeon_pm_state_type_name
[power_state
->type
]);
320 if (i
== rdev
->pm
.default_power_state_index
)
321 DRM_DEBUG_DRIVER("\tDefault");
322 if ((rdev
->flags
& RADEON_IS_PCIE
) && !(rdev
->flags
& RADEON_IS_IGP
))
323 DRM_DEBUG_DRIVER("\t%d PCIE Lanes\n", power_state
->pcie_lanes
);
324 if (power_state
->flags
& RADEON_PM_STATE_SINGLE_DISPLAY_ONLY
)
325 DRM_DEBUG_DRIVER("\tSingle display only\n");
326 DRM_DEBUG_DRIVER("\t%d Clock Mode(s)\n", power_state
->num_clock_modes
);
327 for (j
= 0; j
< power_state
->num_clock_modes
; j
++) {
328 clock_info
= &(power_state
->clock_info
[j
]);
329 if (rdev
->flags
& RADEON_IS_IGP
)
330 DRM_DEBUG_DRIVER("\t\t%d e: %d\n",
332 clock_info
->sclk
* 10);
334 DRM_DEBUG_DRIVER("\t\t%d e: %d\tm: %d\tv: %d\n",
336 clock_info
->sclk
* 10,
337 clock_info
->mclk
* 10,
338 clock_info
->voltage
.voltage
);
343 static ssize_t
radeon_get_pm_profile(struct device
*dev
,
344 struct device_attribute
*attr
,
347 struct drm_device
*ddev
= dev_get_drvdata(dev
);
348 struct radeon_device
*rdev
= ddev
->dev_private
;
349 int cp
= rdev
->pm
.profile
;
351 return snprintf(buf
, PAGE_SIZE
, "%s\n",
352 (cp
== PM_PROFILE_AUTO
) ? "auto" :
353 (cp
== PM_PROFILE_LOW
) ? "low" :
354 (cp
== PM_PROFILE_MID
) ? "mid" :
355 (cp
== PM_PROFILE_HIGH
) ? "high" : "default");
358 static ssize_t
radeon_set_pm_profile(struct device
*dev
,
359 struct device_attribute
*attr
,
363 struct drm_device
*ddev
= dev_get_drvdata(dev
);
364 struct radeon_device
*rdev
= ddev
->dev_private
;
366 /* Can't set profile when the card is off */
367 if ((rdev
->flags
& RADEON_IS_PX
) &&
368 (ddev
->switch_power_state
!= DRM_SWITCH_POWER_ON
))
371 mutex_lock(&rdev
->pm
.mutex
);
372 if (rdev
->pm
.pm_method
== PM_METHOD_PROFILE
) {
373 if (strncmp("default", buf
, strlen("default")) == 0)
374 rdev
->pm
.profile
= PM_PROFILE_DEFAULT
;
375 else if (strncmp("auto", buf
, strlen("auto")) == 0)
376 rdev
->pm
.profile
= PM_PROFILE_AUTO
;
377 else if (strncmp("low", buf
, strlen("low")) == 0)
378 rdev
->pm
.profile
= PM_PROFILE_LOW
;
379 else if (strncmp("mid", buf
, strlen("mid")) == 0)
380 rdev
->pm
.profile
= PM_PROFILE_MID
;
381 else if (strncmp("high", buf
, strlen("high")) == 0)
382 rdev
->pm
.profile
= PM_PROFILE_HIGH
;
387 radeon_pm_update_profile(rdev
);
388 radeon_pm_set_clocks(rdev
);
393 mutex_unlock(&rdev
->pm
.mutex
);
398 static ssize_t
radeon_get_pm_method(struct device
*dev
,
399 struct device_attribute
*attr
,
402 struct drm_device
*ddev
= dev_get_drvdata(dev
);
403 struct radeon_device
*rdev
= ddev
->dev_private
;
404 int pm
= rdev
->pm
.pm_method
;
406 return snprintf(buf
, PAGE_SIZE
, "%s\n",
407 (pm
== PM_METHOD_DYNPM
) ? "dynpm" :
408 (pm
== PM_METHOD_PROFILE
) ? "profile" : "dpm");
411 static ssize_t
radeon_set_pm_method(struct device
*dev
,
412 struct device_attribute
*attr
,
416 struct drm_device
*ddev
= dev_get_drvdata(dev
);
417 struct radeon_device
*rdev
= ddev
->dev_private
;
419 /* Can't set method when the card is off */
420 if ((rdev
->flags
& RADEON_IS_PX
) &&
421 (ddev
->switch_power_state
!= DRM_SWITCH_POWER_ON
)) {
426 /* we don't support the legacy modes with dpm */
427 if (rdev
->pm
.pm_method
== PM_METHOD_DPM
) {
432 if (strncmp("dynpm", buf
, strlen("dynpm")) == 0) {
433 mutex_lock(&rdev
->pm
.mutex
);
434 rdev
->pm
.pm_method
= PM_METHOD_DYNPM
;
435 rdev
->pm
.dynpm_state
= DYNPM_STATE_PAUSED
;
436 rdev
->pm
.dynpm_planned_action
= DYNPM_ACTION_DEFAULT
;
437 mutex_unlock(&rdev
->pm
.mutex
);
438 } else if (strncmp("profile", buf
, strlen("profile")) == 0) {
439 mutex_lock(&rdev
->pm
.mutex
);
441 rdev
->pm
.dynpm_state
= DYNPM_STATE_DISABLED
;
442 rdev
->pm
.dynpm_planned_action
= DYNPM_ACTION_NONE
;
443 rdev
->pm
.pm_method
= PM_METHOD_PROFILE
;
444 mutex_unlock(&rdev
->pm
.mutex
);
445 cancel_delayed_work_sync(&rdev
->pm
.dynpm_idle_work
);
450 radeon_pm_compute_clocks(rdev
);
455 static ssize_t
radeon_get_dpm_state(struct device
*dev
,
456 struct device_attribute
*attr
,
459 struct drm_device
*ddev
= dev_get_drvdata(dev
);
460 struct radeon_device
*rdev
= ddev
->dev_private
;
461 enum radeon_pm_state_type pm
= rdev
->pm
.dpm
.user_state
;
463 return snprintf(buf
, PAGE_SIZE
, "%s\n",
464 (pm
== POWER_STATE_TYPE_BATTERY
) ? "battery" :
465 (pm
== POWER_STATE_TYPE_BALANCED
) ? "balanced" : "performance");
468 static ssize_t
radeon_set_dpm_state(struct device
*dev
,
469 struct device_attribute
*attr
,
473 struct drm_device
*ddev
= dev_get_drvdata(dev
);
474 struct radeon_device
*rdev
= ddev
->dev_private
;
476 mutex_lock(&rdev
->pm
.mutex
);
477 if (strncmp("battery", buf
, strlen("battery")) == 0)
478 rdev
->pm
.dpm
.user_state
= POWER_STATE_TYPE_BATTERY
;
479 else if (strncmp("balanced", buf
, strlen("balanced")) == 0)
480 rdev
->pm
.dpm
.user_state
= POWER_STATE_TYPE_BALANCED
;
481 else if (strncmp("performance", buf
, strlen("performance")) == 0)
482 rdev
->pm
.dpm
.user_state
= POWER_STATE_TYPE_PERFORMANCE
;
484 mutex_unlock(&rdev
->pm
.mutex
);
488 mutex_unlock(&rdev
->pm
.mutex
);
490 /* Can't set dpm state when the card is off */
491 if (!(rdev
->flags
& RADEON_IS_PX
) ||
492 (ddev
->switch_power_state
== DRM_SWITCH_POWER_ON
))
493 radeon_pm_compute_clocks(rdev
);
499 static ssize_t
radeon_get_dpm_forced_performance_level(struct device
*dev
,
500 struct device_attribute
*attr
,
503 struct drm_device
*ddev
= dev_get_drvdata(dev
);
504 struct radeon_device
*rdev
= ddev
->dev_private
;
505 enum radeon_dpm_forced_level level
= rdev
->pm
.dpm
.forced_level
;
507 if ((rdev
->flags
& RADEON_IS_PX
) &&
508 (ddev
->switch_power_state
!= DRM_SWITCH_POWER_ON
))
509 return snprintf(buf
, PAGE_SIZE
, "off\n");
511 return snprintf(buf
, PAGE_SIZE
, "%s\n",
512 (level
== RADEON_DPM_FORCED_LEVEL_AUTO
) ? "auto" :
513 (level
== RADEON_DPM_FORCED_LEVEL_LOW
) ? "low" : "high");
516 static ssize_t
radeon_set_dpm_forced_performance_level(struct device
*dev
,
517 struct device_attribute
*attr
,
521 struct drm_device
*ddev
= dev_get_drvdata(dev
);
522 struct radeon_device
*rdev
= ddev
->dev_private
;
523 enum radeon_dpm_forced_level level
;
526 /* Can't force performance level when the card is off */
527 if ((rdev
->flags
& RADEON_IS_PX
) &&
528 (ddev
->switch_power_state
!= DRM_SWITCH_POWER_ON
))
531 mutex_lock(&rdev
->pm
.mutex
);
532 if (strncmp("low", buf
, strlen("low")) == 0) {
533 level
= RADEON_DPM_FORCED_LEVEL_LOW
;
534 } else if (strncmp("high", buf
, strlen("high")) == 0) {
535 level
= RADEON_DPM_FORCED_LEVEL_HIGH
;
536 } else if (strncmp("auto", buf
, strlen("auto")) == 0) {
537 level
= RADEON_DPM_FORCED_LEVEL_AUTO
;
542 if (rdev
->asic
->dpm
.force_performance_level
) {
543 if (rdev
->pm
.dpm
.thermal_active
) {
547 ret
= radeon_dpm_force_performance_level(rdev
, level
);
552 mutex_unlock(&rdev
->pm
.mutex
);
557 static DEVICE_ATTR(power_profile
, S_IRUGO
| S_IWUSR
, radeon_get_pm_profile
, radeon_set_pm_profile
);
558 static DEVICE_ATTR(power_method
, S_IRUGO
| S_IWUSR
, radeon_get_pm_method
, radeon_set_pm_method
);
559 static DEVICE_ATTR(power_dpm_state
, S_IRUGO
| S_IWUSR
, radeon_get_dpm_state
, radeon_set_dpm_state
);
560 static DEVICE_ATTR(power_dpm_force_performance_level
, S_IRUGO
| S_IWUSR
,
561 radeon_get_dpm_forced_performance_level
,
562 radeon_set_dpm_forced_performance_level
);
564 static ssize_t
radeon_hwmon_show_temp(struct device
*dev
,
565 struct device_attribute
*attr
,
568 struct radeon_device
*rdev
= dev_get_drvdata(dev
);
569 struct drm_device
*ddev
= rdev
->ddev
;
572 /* Can't get temperature when the card is off */
573 if ((rdev
->flags
& RADEON_IS_PX
) &&
574 (ddev
->switch_power_state
!= DRM_SWITCH_POWER_ON
))
577 if (rdev
->asic
->pm
.get_temperature
)
578 temp
= radeon_get_temperature(rdev
);
582 return snprintf(buf
, PAGE_SIZE
, "%d\n", temp
);
585 static ssize_t
radeon_hwmon_show_temp_thresh(struct device
*dev
,
586 struct device_attribute
*attr
,
589 struct radeon_device
*rdev
= dev_get_drvdata(dev
);
590 int hyst
= to_sensor_dev_attr(attr
)->index
;
594 temp
= rdev
->pm
.dpm
.thermal
.min_temp
;
596 temp
= rdev
->pm
.dpm
.thermal
.max_temp
;
598 return snprintf(buf
, PAGE_SIZE
, "%d\n", temp
);
601 static SENSOR_DEVICE_ATTR(temp1_input
, S_IRUGO
, radeon_hwmon_show_temp
, NULL
, 0);
602 static SENSOR_DEVICE_ATTR(temp1_crit
, S_IRUGO
, radeon_hwmon_show_temp_thresh
, NULL
, 0);
603 static SENSOR_DEVICE_ATTR(temp1_crit_hyst
, S_IRUGO
, radeon_hwmon_show_temp_thresh
, NULL
, 1);
605 static struct attribute
*hwmon_attributes
[] = {
606 &sensor_dev_attr_temp1_input
.dev_attr
.attr
,
607 &sensor_dev_attr_temp1_crit
.dev_attr
.attr
,
608 &sensor_dev_attr_temp1_crit_hyst
.dev_attr
.attr
,
612 static umode_t
hwmon_attributes_visible(struct kobject
*kobj
,
613 struct attribute
*attr
, int index
)
615 struct device
*dev
= container_of(kobj
, struct device
, kobj
);
616 struct radeon_device
*rdev
= dev_get_drvdata(dev
);
618 /* Skip limit attributes if DPM is not enabled */
619 if (rdev
->pm
.pm_method
!= PM_METHOD_DPM
&&
620 (attr
== &sensor_dev_attr_temp1_crit
.dev_attr
.attr
||
621 attr
== &sensor_dev_attr_temp1_crit_hyst
.dev_attr
.attr
))
627 static const struct attribute_group hwmon_attrgroup
= {
628 .attrs
= hwmon_attributes
,
629 .is_visible
= hwmon_attributes_visible
,
632 static const struct attribute_group
*hwmon_groups
[] = {
637 static int radeon_hwmon_init(struct radeon_device
*rdev
)
641 switch (rdev
->pm
.int_thermal_type
) {
642 case THERMAL_TYPE_RV6XX
:
643 case THERMAL_TYPE_RV770
:
644 case THERMAL_TYPE_EVERGREEN
:
645 case THERMAL_TYPE_NI
:
646 case THERMAL_TYPE_SUMO
:
647 case THERMAL_TYPE_SI
:
648 case THERMAL_TYPE_CI
:
649 case THERMAL_TYPE_KV
:
650 if (rdev
->asic
->pm
.get_temperature
== NULL
)
652 rdev
->pm
.int_hwmon_dev
= hwmon_device_register_with_groups(rdev
->dev
,
655 if (IS_ERR(rdev
->pm
.int_hwmon_dev
)) {
656 err
= PTR_ERR(rdev
->pm
.int_hwmon_dev
);
658 "Unable to register hwmon device: %d\n", err
);
668 static void radeon_hwmon_fini(struct radeon_device
*rdev
)
670 if (rdev
->pm
.int_hwmon_dev
)
671 hwmon_device_unregister(rdev
->pm
.int_hwmon_dev
);
674 static void radeon_dpm_thermal_work_handler(struct work_struct
*work
)
676 struct radeon_device
*rdev
=
677 container_of(work
, struct radeon_device
,
678 pm
.dpm
.thermal
.work
);
679 /* switch to the thermal state */
680 enum radeon_pm_state_type dpm_state
= POWER_STATE_TYPE_INTERNAL_THERMAL
;
682 if (!rdev
->pm
.dpm_enabled
)
685 if (rdev
->asic
->pm
.get_temperature
) {
686 int temp
= radeon_get_temperature(rdev
);
688 if (temp
< rdev
->pm
.dpm
.thermal
.min_temp
)
689 /* switch back the user state */
690 dpm_state
= rdev
->pm
.dpm
.user_state
;
692 if (rdev
->pm
.dpm
.thermal
.high_to_low
)
693 /* switch back the user state */
694 dpm_state
= rdev
->pm
.dpm
.user_state
;
696 mutex_lock(&rdev
->pm
.mutex
);
697 if (dpm_state
== POWER_STATE_TYPE_INTERNAL_THERMAL
)
698 rdev
->pm
.dpm
.thermal_active
= true;
700 rdev
->pm
.dpm
.thermal_active
= false;
701 rdev
->pm
.dpm
.state
= dpm_state
;
702 mutex_unlock(&rdev
->pm
.mutex
);
704 radeon_pm_compute_clocks(rdev
);
707 static struct radeon_ps
*radeon_dpm_pick_power_state(struct radeon_device
*rdev
,
708 enum radeon_pm_state_type dpm_state
)
711 struct radeon_ps
*ps
;
713 bool single_display
= (rdev
->pm
.dpm
.new_active_crtc_count
< 2) ?
716 /* check if the vblank period is too short to adjust the mclk */
717 if (single_display
&& rdev
->asic
->dpm
.vblank_too_short
) {
718 if (radeon_dpm_vblank_too_short(rdev
))
719 single_display
= false;
722 /* certain older asics have a separare 3D performance state,
723 * so try that first if the user selected performance
725 if (dpm_state
== POWER_STATE_TYPE_PERFORMANCE
)
726 dpm_state
= POWER_STATE_TYPE_INTERNAL_3DPERF
;
727 /* balanced states don't exist at the moment */
728 if (dpm_state
== POWER_STATE_TYPE_BALANCED
)
729 dpm_state
= POWER_STATE_TYPE_PERFORMANCE
;
732 /* Pick the best power state based on current conditions */
733 for (i
= 0; i
< rdev
->pm
.dpm
.num_ps
; i
++) {
734 ps
= &rdev
->pm
.dpm
.ps
[i
];
735 ui_class
= ps
->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK
;
738 case POWER_STATE_TYPE_BATTERY
:
739 if (ui_class
== ATOM_PPLIB_CLASSIFICATION_UI_BATTERY
) {
740 if (ps
->caps
& ATOM_PPLIB_SINGLE_DISPLAY_ONLY
) {
747 case POWER_STATE_TYPE_BALANCED
:
748 if (ui_class
== ATOM_PPLIB_CLASSIFICATION_UI_BALANCED
) {
749 if (ps
->caps
& ATOM_PPLIB_SINGLE_DISPLAY_ONLY
) {
756 case POWER_STATE_TYPE_PERFORMANCE
:
757 if (ui_class
== ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE
) {
758 if (ps
->caps
& ATOM_PPLIB_SINGLE_DISPLAY_ONLY
) {
765 /* internal states */
766 case POWER_STATE_TYPE_INTERNAL_UVD
:
767 if (rdev
->pm
.dpm
.uvd_ps
)
768 return rdev
->pm
.dpm
.uvd_ps
;
771 case POWER_STATE_TYPE_INTERNAL_UVD_SD
:
772 if (ps
->class & ATOM_PPLIB_CLASSIFICATION_SDSTATE
)
775 case POWER_STATE_TYPE_INTERNAL_UVD_HD
:
776 if (ps
->class & ATOM_PPLIB_CLASSIFICATION_HDSTATE
)
779 case POWER_STATE_TYPE_INTERNAL_UVD_HD2
:
780 if (ps
->class & ATOM_PPLIB_CLASSIFICATION_HD2STATE
)
783 case POWER_STATE_TYPE_INTERNAL_UVD_MVC
:
784 if (ps
->class2
& ATOM_PPLIB_CLASSIFICATION2_MVC
)
787 case POWER_STATE_TYPE_INTERNAL_BOOT
:
788 return rdev
->pm
.dpm
.boot_ps
;
789 case POWER_STATE_TYPE_INTERNAL_THERMAL
:
790 if (ps
->class & ATOM_PPLIB_CLASSIFICATION_THERMAL
)
793 case POWER_STATE_TYPE_INTERNAL_ACPI
:
794 if (ps
->class & ATOM_PPLIB_CLASSIFICATION_ACPI
)
797 case POWER_STATE_TYPE_INTERNAL_ULV
:
798 if (ps
->class2
& ATOM_PPLIB_CLASSIFICATION2_ULV
)
801 case POWER_STATE_TYPE_INTERNAL_3DPERF
:
802 if (ps
->class & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE
)
809 /* use a fallback state if we didn't match */
811 case POWER_STATE_TYPE_INTERNAL_UVD_SD
:
812 dpm_state
= POWER_STATE_TYPE_INTERNAL_UVD_HD
;
814 case POWER_STATE_TYPE_INTERNAL_UVD_HD
:
815 case POWER_STATE_TYPE_INTERNAL_UVD_HD2
:
816 case POWER_STATE_TYPE_INTERNAL_UVD_MVC
:
817 if (rdev
->pm
.dpm
.uvd_ps
) {
818 return rdev
->pm
.dpm
.uvd_ps
;
820 dpm_state
= POWER_STATE_TYPE_PERFORMANCE
;
823 case POWER_STATE_TYPE_INTERNAL_THERMAL
:
824 dpm_state
= POWER_STATE_TYPE_INTERNAL_ACPI
;
826 case POWER_STATE_TYPE_INTERNAL_ACPI
:
827 dpm_state
= POWER_STATE_TYPE_BATTERY
;
829 case POWER_STATE_TYPE_BATTERY
:
830 case POWER_STATE_TYPE_BALANCED
:
831 case POWER_STATE_TYPE_INTERNAL_3DPERF
:
832 dpm_state
= POWER_STATE_TYPE_PERFORMANCE
;
841 static void radeon_dpm_change_power_state_locked(struct radeon_device
*rdev
)
844 struct radeon_ps
*ps
;
845 enum radeon_pm_state_type dpm_state
;
848 /* if dpm init failed */
849 if (!rdev
->pm
.dpm_enabled
)
852 if (rdev
->pm
.dpm
.user_state
!= rdev
->pm
.dpm
.state
) {
853 /* add other state override checks here */
854 if ((!rdev
->pm
.dpm
.thermal_active
) &&
855 (!rdev
->pm
.dpm
.uvd_active
))
856 rdev
->pm
.dpm
.state
= rdev
->pm
.dpm
.user_state
;
858 dpm_state
= rdev
->pm
.dpm
.state
;
860 ps
= radeon_dpm_pick_power_state(rdev
, dpm_state
);
862 rdev
->pm
.dpm
.requested_ps
= ps
;
866 /* no need to reprogram if nothing changed unless we are on BTC+ */
867 if (rdev
->pm
.dpm
.current_ps
== rdev
->pm
.dpm
.requested_ps
) {
868 /* vce just modifies an existing state so force a change */
869 if (ps
->vce_active
!= rdev
->pm
.dpm
.vce_active
)
871 if ((rdev
->family
< CHIP_BARTS
) || (rdev
->flags
& RADEON_IS_IGP
)) {
872 /* for pre-BTC and APUs if the num crtcs changed but state is the same,
873 * all we need to do is update the display configuration.
875 if (rdev
->pm
.dpm
.new_active_crtcs
!= rdev
->pm
.dpm
.current_active_crtcs
) {
876 /* update display watermarks based on new power state */
877 radeon_bandwidth_update(rdev
);
878 /* update displays */
879 radeon_dpm_display_configuration_changed(rdev
);
880 rdev
->pm
.dpm
.current_active_crtcs
= rdev
->pm
.dpm
.new_active_crtcs
;
881 rdev
->pm
.dpm
.current_active_crtc_count
= rdev
->pm
.dpm
.new_active_crtc_count
;
885 /* for BTC+ if the num crtcs hasn't changed and state is the same,
886 * nothing to do, if the num crtcs is > 1 and state is the same,
887 * update display configuration.
889 if (rdev
->pm
.dpm
.new_active_crtcs
==
890 rdev
->pm
.dpm
.current_active_crtcs
) {
893 if ((rdev
->pm
.dpm
.current_active_crtc_count
> 1) &&
894 (rdev
->pm
.dpm
.new_active_crtc_count
> 1)) {
895 /* update display watermarks based on new power state */
896 radeon_bandwidth_update(rdev
);
897 /* update displays */
898 radeon_dpm_display_configuration_changed(rdev
);
899 rdev
->pm
.dpm
.current_active_crtcs
= rdev
->pm
.dpm
.new_active_crtcs
;
900 rdev
->pm
.dpm
.current_active_crtc_count
= rdev
->pm
.dpm
.new_active_crtc_count
;
908 if (radeon_dpm
== 1) {
909 printk("switching from power state:\n");
910 radeon_dpm_print_power_state(rdev
, rdev
->pm
.dpm
.current_ps
);
911 printk("switching to power state:\n");
912 radeon_dpm_print_power_state(rdev
, rdev
->pm
.dpm
.requested_ps
);
915 mutex_lock(&rdev
->ddev
->struct_mutex
);
916 down_write(&rdev
->pm
.mclk_lock
);
917 mutex_lock(&rdev
->ring_lock
);
919 /* update whether vce is active */
920 ps
->vce_active
= rdev
->pm
.dpm
.vce_active
;
922 ret
= radeon_dpm_pre_set_power_state(rdev
);
926 /* update display watermarks based on new power state */
927 radeon_bandwidth_update(rdev
);
928 /* update displays */
929 radeon_dpm_display_configuration_changed(rdev
);
931 rdev
->pm
.dpm
.current_active_crtcs
= rdev
->pm
.dpm
.new_active_crtcs
;
932 rdev
->pm
.dpm
.current_active_crtc_count
= rdev
->pm
.dpm
.new_active_crtc_count
;
934 /* wait for the rings to drain */
935 for (i
= 0; i
< RADEON_NUM_RINGS
; i
++) {
936 struct radeon_ring
*ring
= &rdev
->ring
[i
];
938 radeon_fence_wait_empty(rdev
, i
);
941 /* program the new power state */
942 radeon_dpm_set_power_state(rdev
);
944 /* update current power state */
945 rdev
->pm
.dpm
.current_ps
= rdev
->pm
.dpm
.requested_ps
;
947 radeon_dpm_post_set_power_state(rdev
);
949 if (rdev
->asic
->dpm
.force_performance_level
) {
950 if (rdev
->pm
.dpm
.thermal_active
) {
951 enum radeon_dpm_forced_level level
= rdev
->pm
.dpm
.forced_level
;
952 /* force low perf level for thermal */
953 radeon_dpm_force_performance_level(rdev
, RADEON_DPM_FORCED_LEVEL_LOW
);
954 /* save the user's level */
955 rdev
->pm
.dpm
.forced_level
= level
;
957 /* otherwise, user selected level */
958 radeon_dpm_force_performance_level(rdev
, rdev
->pm
.dpm
.forced_level
);
963 mutex_unlock(&rdev
->ring_lock
);
964 up_write(&rdev
->pm
.mclk_lock
);
965 mutex_unlock(&rdev
->ddev
->struct_mutex
);
968 void radeon_dpm_enable_uvd(struct radeon_device
*rdev
, bool enable
)
970 enum radeon_pm_state_type dpm_state
;
972 if (rdev
->asic
->dpm
.powergate_uvd
) {
973 mutex_lock(&rdev
->pm
.mutex
);
974 /* don't powergate anything if we
975 have active but pause streams */
976 enable
|= rdev
->pm
.dpm
.sd
> 0;
977 enable
|= rdev
->pm
.dpm
.hd
> 0;
978 /* enable/disable UVD */
979 radeon_dpm_powergate_uvd(rdev
, !enable
);
980 mutex_unlock(&rdev
->pm
.mutex
);
983 mutex_lock(&rdev
->pm
.mutex
);
984 rdev
->pm
.dpm
.uvd_active
= true;
985 /* disable this for now */
987 if ((rdev
->pm
.dpm
.sd
== 1) && (rdev
->pm
.dpm
.hd
== 0))
988 dpm_state
= POWER_STATE_TYPE_INTERNAL_UVD_SD
;
989 else if ((rdev
->pm
.dpm
.sd
== 2) && (rdev
->pm
.dpm
.hd
== 0))
990 dpm_state
= POWER_STATE_TYPE_INTERNAL_UVD_HD
;
991 else if ((rdev
->pm
.dpm
.sd
== 0) && (rdev
->pm
.dpm
.hd
== 1))
992 dpm_state
= POWER_STATE_TYPE_INTERNAL_UVD_HD
;
993 else if ((rdev
->pm
.dpm
.sd
== 0) && (rdev
->pm
.dpm
.hd
== 2))
994 dpm_state
= POWER_STATE_TYPE_INTERNAL_UVD_HD2
;
997 dpm_state
= POWER_STATE_TYPE_INTERNAL_UVD
;
998 rdev
->pm
.dpm
.state
= dpm_state
;
999 mutex_unlock(&rdev
->pm
.mutex
);
1001 mutex_lock(&rdev
->pm
.mutex
);
1002 rdev
->pm
.dpm
.uvd_active
= false;
1003 mutex_unlock(&rdev
->pm
.mutex
);
1006 radeon_pm_compute_clocks(rdev
);
1010 void radeon_dpm_enable_vce(struct radeon_device
*rdev
, bool enable
)
1013 mutex_lock(&rdev
->pm
.mutex
);
1014 rdev
->pm
.dpm
.vce_active
= true;
1015 /* XXX select vce level based on ring/task */
1016 rdev
->pm
.dpm
.vce_level
= RADEON_VCE_LEVEL_AC_ALL
;
1017 mutex_unlock(&rdev
->pm
.mutex
);
1019 mutex_lock(&rdev
->pm
.mutex
);
1020 rdev
->pm
.dpm
.vce_active
= false;
1021 mutex_unlock(&rdev
->pm
.mutex
);
1024 radeon_pm_compute_clocks(rdev
);
1027 static void radeon_pm_suspend_old(struct radeon_device
*rdev
)
1029 mutex_lock(&rdev
->pm
.mutex
);
1030 if (rdev
->pm
.pm_method
== PM_METHOD_DYNPM
) {
1031 if (rdev
->pm
.dynpm_state
== DYNPM_STATE_ACTIVE
)
1032 rdev
->pm
.dynpm_state
= DYNPM_STATE_SUSPENDED
;
1034 mutex_unlock(&rdev
->pm
.mutex
);
1036 cancel_delayed_work_sync(&rdev
->pm
.dynpm_idle_work
);
1039 static void radeon_pm_suspend_dpm(struct radeon_device
*rdev
)
1041 mutex_lock(&rdev
->pm
.mutex
);
1043 radeon_dpm_disable(rdev
);
1044 /* reset the power state */
1045 rdev
->pm
.dpm
.current_ps
= rdev
->pm
.dpm
.requested_ps
= rdev
->pm
.dpm
.boot_ps
;
1046 rdev
->pm
.dpm_enabled
= false;
1047 mutex_unlock(&rdev
->pm
.mutex
);
1050 void radeon_pm_suspend(struct radeon_device
*rdev
)
1052 if (rdev
->pm
.pm_method
== PM_METHOD_DPM
)
1053 radeon_pm_suspend_dpm(rdev
);
1055 radeon_pm_suspend_old(rdev
);
1058 static void radeon_pm_resume_old(struct radeon_device
*rdev
)
1060 /* set up the default clocks if the MC ucode is loaded */
1061 if ((rdev
->family
>= CHIP_BARTS
) &&
1062 (rdev
->family
<= CHIP_CAYMAN
) &&
1064 if (rdev
->pm
.default_vddc
)
1065 radeon_atom_set_voltage(rdev
, rdev
->pm
.default_vddc
,
1066 SET_VOLTAGE_TYPE_ASIC_VDDC
);
1067 if (rdev
->pm
.default_vddci
)
1068 radeon_atom_set_voltage(rdev
, rdev
->pm
.default_vddci
,
1069 SET_VOLTAGE_TYPE_ASIC_VDDCI
);
1070 if (rdev
->pm
.default_sclk
)
1071 radeon_set_engine_clock(rdev
, rdev
->pm
.default_sclk
);
1072 if (rdev
->pm
.default_mclk
)
1073 radeon_set_memory_clock(rdev
, rdev
->pm
.default_mclk
);
1075 /* asic init will reset the default power state */
1076 mutex_lock(&rdev
->pm
.mutex
);
1077 rdev
->pm
.current_power_state_index
= rdev
->pm
.default_power_state_index
;
1078 rdev
->pm
.current_clock_mode_index
= 0;
1079 rdev
->pm
.current_sclk
= rdev
->pm
.default_sclk
;
1080 rdev
->pm
.current_mclk
= rdev
->pm
.default_mclk
;
1081 if (rdev
->pm
.power_state
) {
1082 rdev
->pm
.current_vddc
= rdev
->pm
.power_state
[rdev
->pm
.default_power_state_index
].clock_info
[0].voltage
.voltage
;
1083 rdev
->pm
.current_vddci
= rdev
->pm
.power_state
[rdev
->pm
.default_power_state_index
].clock_info
[0].voltage
.vddci
;
1085 if (rdev
->pm
.pm_method
== PM_METHOD_DYNPM
1086 && rdev
->pm
.dynpm_state
== DYNPM_STATE_SUSPENDED
) {
1087 rdev
->pm
.dynpm_state
= DYNPM_STATE_ACTIVE
;
1088 schedule_delayed_work(&rdev
->pm
.dynpm_idle_work
,
1089 msecs_to_jiffies(RADEON_IDLE_LOOP_MS
));
1091 mutex_unlock(&rdev
->pm
.mutex
);
1092 radeon_pm_compute_clocks(rdev
);
1095 static void radeon_pm_resume_dpm(struct radeon_device
*rdev
)
1099 /* asic init will reset to the boot state */
1100 mutex_lock(&rdev
->pm
.mutex
);
1101 rdev
->pm
.dpm
.current_ps
= rdev
->pm
.dpm
.requested_ps
= rdev
->pm
.dpm
.boot_ps
;
1102 radeon_dpm_setup_asic(rdev
);
1103 ret
= radeon_dpm_enable(rdev
);
1104 mutex_unlock(&rdev
->pm
.mutex
);
1106 goto dpm_resume_fail
;
1107 rdev
->pm
.dpm_enabled
= true;
1111 DRM_ERROR("radeon: dpm resume failed\n");
1112 if ((rdev
->family
>= CHIP_BARTS
) &&
1113 (rdev
->family
<= CHIP_CAYMAN
) &&
1115 if (rdev
->pm
.default_vddc
)
1116 radeon_atom_set_voltage(rdev
, rdev
->pm
.default_vddc
,
1117 SET_VOLTAGE_TYPE_ASIC_VDDC
);
1118 if (rdev
->pm
.default_vddci
)
1119 radeon_atom_set_voltage(rdev
, rdev
->pm
.default_vddci
,
1120 SET_VOLTAGE_TYPE_ASIC_VDDCI
);
1121 if (rdev
->pm
.default_sclk
)
1122 radeon_set_engine_clock(rdev
, rdev
->pm
.default_sclk
);
1123 if (rdev
->pm
.default_mclk
)
1124 radeon_set_memory_clock(rdev
, rdev
->pm
.default_mclk
);
1128 void radeon_pm_resume(struct radeon_device
*rdev
)
1130 if (rdev
->pm
.pm_method
== PM_METHOD_DPM
)
1131 radeon_pm_resume_dpm(rdev
);
1133 radeon_pm_resume_old(rdev
);
1136 static int radeon_pm_init_old(struct radeon_device
*rdev
)
1140 rdev
->pm
.profile
= PM_PROFILE_DEFAULT
;
1141 rdev
->pm
.dynpm_state
= DYNPM_STATE_DISABLED
;
1142 rdev
->pm
.dynpm_planned_action
= DYNPM_ACTION_NONE
;
1143 rdev
->pm
.dynpm_can_upclock
= true;
1144 rdev
->pm
.dynpm_can_downclock
= true;
1145 rdev
->pm
.default_sclk
= rdev
->clock
.default_sclk
;
1146 rdev
->pm
.default_mclk
= rdev
->clock
.default_mclk
;
1147 rdev
->pm
.current_sclk
= rdev
->clock
.default_sclk
;
1148 rdev
->pm
.current_mclk
= rdev
->clock
.default_mclk
;
1149 rdev
->pm
.int_thermal_type
= THERMAL_TYPE_NONE
;
1152 if (rdev
->is_atom_bios
)
1153 radeon_atombios_get_power_modes(rdev
);
1155 radeon_combios_get_power_modes(rdev
);
1156 radeon_pm_print_states(rdev
);
1157 radeon_pm_init_profile(rdev
);
1158 /* set up the default clocks if the MC ucode is loaded */
1159 if ((rdev
->family
>= CHIP_BARTS
) &&
1160 (rdev
->family
<= CHIP_CAYMAN
) &&
1162 if (rdev
->pm
.default_vddc
)
1163 radeon_atom_set_voltage(rdev
, rdev
->pm
.default_vddc
,
1164 SET_VOLTAGE_TYPE_ASIC_VDDC
);
1165 if (rdev
->pm
.default_vddci
)
1166 radeon_atom_set_voltage(rdev
, rdev
->pm
.default_vddci
,
1167 SET_VOLTAGE_TYPE_ASIC_VDDCI
);
1168 if (rdev
->pm
.default_sclk
)
1169 radeon_set_engine_clock(rdev
, rdev
->pm
.default_sclk
);
1170 if (rdev
->pm
.default_mclk
)
1171 radeon_set_memory_clock(rdev
, rdev
->pm
.default_mclk
);
1175 /* set up the internal thermal sensor if applicable */
1176 ret
= radeon_hwmon_init(rdev
);
1180 INIT_DELAYED_WORK(&rdev
->pm
.dynpm_idle_work
, radeon_dynpm_idle_work_handler
);
1182 if (rdev
->pm
.num_power_states
> 1) {
1183 /* where's the best place to put these? */
1184 ret
= device_create_file(rdev
->dev
, &dev_attr_power_profile
);
1186 DRM_ERROR("failed to create device file for power profile\n");
1187 ret
= device_create_file(rdev
->dev
, &dev_attr_power_method
);
1189 DRM_ERROR("failed to create device file for power method\n");
1191 if (radeon_debugfs_pm_init(rdev
)) {
1192 DRM_ERROR("Failed to register debugfs file for PM!\n");
1195 DRM_INFO("radeon: power management initialized\n");
1201 static void radeon_dpm_print_power_states(struct radeon_device
*rdev
)
1205 for (i
= 0; i
< rdev
->pm
.dpm
.num_ps
; i
++) {
1206 printk("== power state %d ==\n", i
);
1207 radeon_dpm_print_power_state(rdev
, &rdev
->pm
.dpm
.ps
[i
]);
1211 static int radeon_pm_init_dpm(struct radeon_device
*rdev
)
1215 /* default to balanced state */
1216 rdev
->pm
.dpm
.state
= POWER_STATE_TYPE_BALANCED
;
1217 rdev
->pm
.dpm
.user_state
= POWER_STATE_TYPE_BALANCED
;
1218 rdev
->pm
.dpm
.forced_level
= RADEON_DPM_FORCED_LEVEL_AUTO
;
1219 rdev
->pm
.default_sclk
= rdev
->clock
.default_sclk
;
1220 rdev
->pm
.default_mclk
= rdev
->clock
.default_mclk
;
1221 rdev
->pm
.current_sclk
= rdev
->clock
.default_sclk
;
1222 rdev
->pm
.current_mclk
= rdev
->clock
.default_mclk
;
1223 rdev
->pm
.int_thermal_type
= THERMAL_TYPE_NONE
;
1225 if (rdev
->bios
&& rdev
->is_atom_bios
)
1226 radeon_atombios_get_power_modes(rdev
);
1230 /* set up the internal thermal sensor if applicable */
1231 ret
= radeon_hwmon_init(rdev
);
1235 INIT_WORK(&rdev
->pm
.dpm
.thermal
.work
, radeon_dpm_thermal_work_handler
);
1236 mutex_lock(&rdev
->pm
.mutex
);
1237 radeon_dpm_init(rdev
);
1238 rdev
->pm
.dpm
.current_ps
= rdev
->pm
.dpm
.requested_ps
= rdev
->pm
.dpm
.boot_ps
;
1239 if (radeon_dpm
== 1)
1240 radeon_dpm_print_power_states(rdev
);
1241 radeon_dpm_setup_asic(rdev
);
1242 ret
= radeon_dpm_enable(rdev
);
1243 mutex_unlock(&rdev
->pm
.mutex
);
1246 rdev
->pm
.dpm_enabled
= true;
1248 ret
= device_create_file(rdev
->dev
, &dev_attr_power_dpm_state
);
1250 DRM_ERROR("failed to create device file for dpm state\n");
1251 ret
= device_create_file(rdev
->dev
, &dev_attr_power_dpm_force_performance_level
);
1253 DRM_ERROR("failed to create device file for dpm state\n");
1254 /* XXX: these are noops for dpm but are here for backwards compat */
1255 ret
= device_create_file(rdev
->dev
, &dev_attr_power_profile
);
1257 DRM_ERROR("failed to create device file for power profile\n");
1258 ret
= device_create_file(rdev
->dev
, &dev_attr_power_method
);
1260 DRM_ERROR("failed to create device file for power method\n");
1262 if (radeon_debugfs_pm_init(rdev
)) {
1263 DRM_ERROR("Failed to register debugfs file for dpm!\n");
1266 DRM_INFO("radeon: dpm initialized\n");
1271 rdev
->pm
.dpm_enabled
= false;
1272 if ((rdev
->family
>= CHIP_BARTS
) &&
1273 (rdev
->family
<= CHIP_CAYMAN
) &&
1275 if (rdev
->pm
.default_vddc
)
1276 radeon_atom_set_voltage(rdev
, rdev
->pm
.default_vddc
,
1277 SET_VOLTAGE_TYPE_ASIC_VDDC
);
1278 if (rdev
->pm
.default_vddci
)
1279 radeon_atom_set_voltage(rdev
, rdev
->pm
.default_vddci
,
1280 SET_VOLTAGE_TYPE_ASIC_VDDCI
);
1281 if (rdev
->pm
.default_sclk
)
1282 radeon_set_engine_clock(rdev
, rdev
->pm
.default_sclk
);
1283 if (rdev
->pm
.default_mclk
)
1284 radeon_set_memory_clock(rdev
, rdev
->pm
.default_mclk
);
1286 DRM_ERROR("radeon: dpm initialization failed\n");
1290 int radeon_pm_init(struct radeon_device
*rdev
)
1292 /* enable dpm on rv6xx+ */
1293 switch (rdev
->family
) {
1302 /* DPM requires the RLC, RV770+ dGPU requires SMC */
1304 rdev
->pm
.pm_method
= PM_METHOD_PROFILE
;
1305 else if ((rdev
->family
>= CHIP_RV770
) &&
1306 (!(rdev
->flags
& RADEON_IS_IGP
)) &&
1308 rdev
->pm
.pm_method
= PM_METHOD_PROFILE
;
1309 else if (radeon_dpm
== 1)
1310 rdev
->pm
.pm_method
= PM_METHOD_DPM
;
1312 rdev
->pm
.pm_method
= PM_METHOD_PROFILE
;
1340 /* DPM requires the RLC, RV770+ dGPU requires SMC */
1342 rdev
->pm
.pm_method
= PM_METHOD_PROFILE
;
1343 else if ((rdev
->family
>= CHIP_RV770
) &&
1344 (!(rdev
->flags
& RADEON_IS_IGP
)) &&
1346 rdev
->pm
.pm_method
= PM_METHOD_PROFILE
;
1347 else if (radeon_dpm
== 0)
1348 rdev
->pm
.pm_method
= PM_METHOD_PROFILE
;
1350 rdev
->pm
.pm_method
= PM_METHOD_DPM
;
1353 /* default to profile method */
1354 rdev
->pm
.pm_method
= PM_METHOD_PROFILE
;
1358 if (rdev
->pm
.pm_method
== PM_METHOD_DPM
)
1359 return radeon_pm_init_dpm(rdev
);
1361 return radeon_pm_init_old(rdev
);
1364 int radeon_pm_late_init(struct radeon_device
*rdev
)
1368 if (rdev
->pm
.pm_method
== PM_METHOD_DPM
) {
1369 mutex_lock(&rdev
->pm
.mutex
);
1370 ret
= radeon_dpm_late_enable(rdev
);
1371 mutex_unlock(&rdev
->pm
.mutex
);
1376 static void radeon_pm_fini_old(struct radeon_device
*rdev
)
1378 if (rdev
->pm
.num_power_states
> 1) {
1379 mutex_lock(&rdev
->pm
.mutex
);
1380 if (rdev
->pm
.pm_method
== PM_METHOD_PROFILE
) {
1381 rdev
->pm
.profile
= PM_PROFILE_DEFAULT
;
1382 radeon_pm_update_profile(rdev
);
1383 radeon_pm_set_clocks(rdev
);
1384 } else if (rdev
->pm
.pm_method
== PM_METHOD_DYNPM
) {
1385 /* reset default clocks */
1386 rdev
->pm
.dynpm_state
= DYNPM_STATE_DISABLED
;
1387 rdev
->pm
.dynpm_planned_action
= DYNPM_ACTION_DEFAULT
;
1388 radeon_pm_set_clocks(rdev
);
1390 mutex_unlock(&rdev
->pm
.mutex
);
1392 cancel_delayed_work_sync(&rdev
->pm
.dynpm_idle_work
);
1394 device_remove_file(rdev
->dev
, &dev_attr_power_profile
);
1395 device_remove_file(rdev
->dev
, &dev_attr_power_method
);
1398 radeon_hwmon_fini(rdev
);
1399 kfree(rdev
->pm
.power_state
);
1402 static void radeon_pm_fini_dpm(struct radeon_device
*rdev
)
1404 if (rdev
->pm
.num_power_states
> 1) {
1405 mutex_lock(&rdev
->pm
.mutex
);
1406 radeon_dpm_disable(rdev
);
1407 mutex_unlock(&rdev
->pm
.mutex
);
1409 device_remove_file(rdev
->dev
, &dev_attr_power_dpm_state
);
1410 device_remove_file(rdev
->dev
, &dev_attr_power_dpm_force_performance_level
);
1411 /* XXX backwards compat */
1412 device_remove_file(rdev
->dev
, &dev_attr_power_profile
);
1413 device_remove_file(rdev
->dev
, &dev_attr_power_method
);
1415 radeon_dpm_fini(rdev
);
1417 radeon_hwmon_fini(rdev
);
1418 kfree(rdev
->pm
.power_state
);
1421 void radeon_pm_fini(struct radeon_device
*rdev
)
1423 if (rdev
->pm
.pm_method
== PM_METHOD_DPM
)
1424 radeon_pm_fini_dpm(rdev
);
1426 radeon_pm_fini_old(rdev
);
1429 static void radeon_pm_compute_clocks_old(struct radeon_device
*rdev
)
1431 struct drm_device
*ddev
= rdev
->ddev
;
1432 struct drm_crtc
*crtc
;
1433 struct radeon_crtc
*radeon_crtc
;
1435 if (rdev
->pm
.num_power_states
< 2)
1438 mutex_lock(&rdev
->pm
.mutex
);
1440 rdev
->pm
.active_crtcs
= 0;
1441 rdev
->pm
.active_crtc_count
= 0;
1442 if (rdev
->num_crtc
&& rdev
->mode_info
.mode_config_initialized
) {
1443 list_for_each_entry(crtc
,
1444 &ddev
->mode_config
.crtc_list
, head
) {
1445 radeon_crtc
= to_radeon_crtc(crtc
);
1446 if (radeon_crtc
->enabled
) {
1447 rdev
->pm
.active_crtcs
|= (1 << radeon_crtc
->crtc_id
);
1448 rdev
->pm
.active_crtc_count
++;
1453 if (rdev
->pm
.pm_method
== PM_METHOD_PROFILE
) {
1454 radeon_pm_update_profile(rdev
);
1455 radeon_pm_set_clocks(rdev
);
1456 } else if (rdev
->pm
.pm_method
== PM_METHOD_DYNPM
) {
1457 if (rdev
->pm
.dynpm_state
!= DYNPM_STATE_DISABLED
) {
1458 if (rdev
->pm
.active_crtc_count
> 1) {
1459 if (rdev
->pm
.dynpm_state
== DYNPM_STATE_ACTIVE
) {
1460 cancel_delayed_work(&rdev
->pm
.dynpm_idle_work
);
1462 rdev
->pm
.dynpm_state
= DYNPM_STATE_PAUSED
;
1463 rdev
->pm
.dynpm_planned_action
= DYNPM_ACTION_DEFAULT
;
1464 radeon_pm_get_dynpm_state(rdev
);
1465 radeon_pm_set_clocks(rdev
);
1467 DRM_DEBUG_DRIVER("radeon: dynamic power management deactivated\n");
1469 } else if (rdev
->pm
.active_crtc_count
== 1) {
1470 /* TODO: Increase clocks if needed for current mode */
1472 if (rdev
->pm
.dynpm_state
== DYNPM_STATE_MINIMUM
) {
1473 rdev
->pm
.dynpm_state
= DYNPM_STATE_ACTIVE
;
1474 rdev
->pm
.dynpm_planned_action
= DYNPM_ACTION_UPCLOCK
;
1475 radeon_pm_get_dynpm_state(rdev
);
1476 radeon_pm_set_clocks(rdev
);
1478 schedule_delayed_work(&rdev
->pm
.dynpm_idle_work
,
1479 msecs_to_jiffies(RADEON_IDLE_LOOP_MS
));
1480 } else if (rdev
->pm
.dynpm_state
== DYNPM_STATE_PAUSED
) {
1481 rdev
->pm
.dynpm_state
= DYNPM_STATE_ACTIVE
;
1482 schedule_delayed_work(&rdev
->pm
.dynpm_idle_work
,
1483 msecs_to_jiffies(RADEON_IDLE_LOOP_MS
));
1484 DRM_DEBUG_DRIVER("radeon: dynamic power management activated\n");
1486 } else { /* count == 0 */
1487 if (rdev
->pm
.dynpm_state
!= DYNPM_STATE_MINIMUM
) {
1488 cancel_delayed_work(&rdev
->pm
.dynpm_idle_work
);
1490 rdev
->pm
.dynpm_state
= DYNPM_STATE_MINIMUM
;
1491 rdev
->pm
.dynpm_planned_action
= DYNPM_ACTION_MINIMUM
;
1492 radeon_pm_get_dynpm_state(rdev
);
1493 radeon_pm_set_clocks(rdev
);
1499 mutex_unlock(&rdev
->pm
.mutex
);
1502 static void radeon_pm_compute_clocks_dpm(struct radeon_device
*rdev
)
1504 struct drm_device
*ddev
= rdev
->ddev
;
1505 struct drm_crtc
*crtc
;
1506 struct radeon_crtc
*radeon_crtc
;
1508 if (!rdev
->pm
.dpm_enabled
)
1511 mutex_lock(&rdev
->pm
.mutex
);
1513 /* update active crtc counts */
1514 rdev
->pm
.dpm
.new_active_crtcs
= 0;
1515 rdev
->pm
.dpm
.new_active_crtc_count
= 0;
1516 if (rdev
->num_crtc
&& rdev
->mode_info
.mode_config_initialized
) {
1517 list_for_each_entry(crtc
,
1518 &ddev
->mode_config
.crtc_list
, head
) {
1519 radeon_crtc
= to_radeon_crtc(crtc
);
1520 if (crtc
->enabled
) {
1521 rdev
->pm
.dpm
.new_active_crtcs
|= (1 << radeon_crtc
->crtc_id
);
1522 rdev
->pm
.dpm
.new_active_crtc_count
++;
1527 /* update battery/ac status */
1528 if (power_supply_is_system_supplied() > 0)
1529 rdev
->pm
.dpm
.ac_power
= true;
1531 rdev
->pm
.dpm
.ac_power
= false;
1533 radeon_dpm_change_power_state_locked(rdev
);
1535 mutex_unlock(&rdev
->pm
.mutex
);
1539 void radeon_pm_compute_clocks(struct radeon_device
*rdev
)
1541 if (rdev
->pm
.pm_method
== PM_METHOD_DPM
)
1542 radeon_pm_compute_clocks_dpm(rdev
);
1544 radeon_pm_compute_clocks_old(rdev
);
1547 static bool radeon_pm_in_vbl(struct radeon_device
*rdev
)
1549 int crtc
, vpos
, hpos
, vbl_status
;
1552 /* Iterate over all active crtc's. All crtc's must be in vblank,
1553 * otherwise return in_vbl == false.
1555 for (crtc
= 0; (crtc
< rdev
->num_crtc
) && in_vbl
; crtc
++) {
1556 if (rdev
->pm
.active_crtcs
& (1 << crtc
)) {
1557 vbl_status
= radeon_get_crtc_scanoutpos(rdev
->ddev
, crtc
, 0, &vpos
, &hpos
, NULL
, NULL
);
1558 if ((vbl_status
& DRM_SCANOUTPOS_VALID
) &&
1559 !(vbl_status
& DRM_SCANOUTPOS_IN_VBLANK
))
1567 static bool radeon_pm_debug_check_in_vbl(struct radeon_device
*rdev
, bool finish
)
1570 bool in_vbl
= radeon_pm_in_vbl(rdev
);
1572 if (in_vbl
== false)
1573 DRM_DEBUG_DRIVER("not in vbl for pm change %08x at %s\n", stat_crtc
,
1574 finish
? "exit" : "entry");
1578 static void radeon_dynpm_idle_work_handler(struct work_struct
*work
)
1580 struct radeon_device
*rdev
;
1582 rdev
= container_of(work
, struct radeon_device
,
1583 pm
.dynpm_idle_work
.work
);
1585 resched
= ttm_bo_lock_delayed_workqueue(&rdev
->mman
.bdev
);
1586 mutex_lock(&rdev
->pm
.mutex
);
1587 if (rdev
->pm
.dynpm_state
== DYNPM_STATE_ACTIVE
) {
1588 int not_processed
= 0;
1591 for (i
= 0; i
< RADEON_NUM_RINGS
; ++i
) {
1592 struct radeon_ring
*ring
= &rdev
->ring
[i
];
1595 not_processed
+= radeon_fence_count_emitted(rdev
, i
);
1596 if (not_processed
>= 3)
1601 if (not_processed
>= 3) { /* should upclock */
1602 if (rdev
->pm
.dynpm_planned_action
== DYNPM_ACTION_DOWNCLOCK
) {
1603 rdev
->pm
.dynpm_planned_action
= DYNPM_ACTION_NONE
;
1604 } else if (rdev
->pm
.dynpm_planned_action
== DYNPM_ACTION_NONE
&&
1605 rdev
->pm
.dynpm_can_upclock
) {
1606 rdev
->pm
.dynpm_planned_action
=
1607 DYNPM_ACTION_UPCLOCK
;
1608 rdev
->pm
.dynpm_action_timeout
= jiffies
+
1609 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS
);
1611 } else if (not_processed
== 0) { /* should downclock */
1612 if (rdev
->pm
.dynpm_planned_action
== DYNPM_ACTION_UPCLOCK
) {
1613 rdev
->pm
.dynpm_planned_action
= DYNPM_ACTION_NONE
;
1614 } else if (rdev
->pm
.dynpm_planned_action
== DYNPM_ACTION_NONE
&&
1615 rdev
->pm
.dynpm_can_downclock
) {
1616 rdev
->pm
.dynpm_planned_action
=
1617 DYNPM_ACTION_DOWNCLOCK
;
1618 rdev
->pm
.dynpm_action_timeout
= jiffies
+
1619 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS
);
1623 /* Note, radeon_pm_set_clocks is called with static_switch set
1624 * to false since we want to wait for vbl to avoid flicker.
1626 if (rdev
->pm
.dynpm_planned_action
!= DYNPM_ACTION_NONE
&&
1627 jiffies
> rdev
->pm
.dynpm_action_timeout
) {
1628 radeon_pm_get_dynpm_state(rdev
);
1629 radeon_pm_set_clocks(rdev
);
1632 schedule_delayed_work(&rdev
->pm
.dynpm_idle_work
,
1633 msecs_to_jiffies(RADEON_IDLE_LOOP_MS
));
1635 mutex_unlock(&rdev
->pm
.mutex
);
1636 ttm_bo_unlock_delayed_workqueue(&rdev
->mman
.bdev
, resched
);
1642 #if defined(CONFIG_DEBUG_FS)
1644 static int radeon_debugfs_pm_info(struct seq_file
*m
, void *data
)
1646 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
1647 struct drm_device
*dev
= node
->minor
->dev
;
1648 struct radeon_device
*rdev
= dev
->dev_private
;
1649 struct drm_device
*ddev
= rdev
->ddev
;
1651 if ((rdev
->flags
& RADEON_IS_PX
) &&
1652 (ddev
->switch_power_state
!= DRM_SWITCH_POWER_ON
)) {
1653 seq_printf(m
, "PX asic powered off\n");
1654 } else if (rdev
->pm
.dpm_enabled
) {
1655 mutex_lock(&rdev
->pm
.mutex
);
1656 if (rdev
->asic
->dpm
.debugfs_print_current_performance_level
)
1657 radeon_dpm_debugfs_print_current_performance_level(rdev
, m
);
1659 seq_printf(m
, "Debugfs support not implemented for this asic\n");
1660 mutex_unlock(&rdev
->pm
.mutex
);
1662 seq_printf(m
, "default engine clock: %u0 kHz\n", rdev
->pm
.default_sclk
);
1663 /* radeon_get_engine_clock is not reliable on APUs so just print the current clock */
1664 if ((rdev
->family
>= CHIP_PALM
) && (rdev
->flags
& RADEON_IS_IGP
))
1665 seq_printf(m
, "current engine clock: %u0 kHz\n", rdev
->pm
.current_sclk
);
1667 seq_printf(m
, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev
));
1668 seq_printf(m
, "default memory clock: %u0 kHz\n", rdev
->pm
.default_mclk
);
1669 if (rdev
->asic
->pm
.get_memory_clock
)
1670 seq_printf(m
, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev
));
1671 if (rdev
->pm
.current_vddc
)
1672 seq_printf(m
, "voltage: %u mV\n", rdev
->pm
.current_vddc
);
1673 if (rdev
->asic
->pm
.get_pcie_lanes
)
1674 seq_printf(m
, "PCIE lanes: %d\n", radeon_get_pcie_lanes(rdev
));
1680 static struct drm_info_list radeon_pm_info_list
[] = {
1681 {"radeon_pm_info", radeon_debugfs_pm_info
, 0, NULL
},
1685 static int radeon_debugfs_pm_init(struct radeon_device
*rdev
)
1687 #if defined(CONFIG_DEBUG_FS)
1688 return radeon_debugfs_add_files(rdev
, radeon_pm_info_list
, ARRAY_SIZE(radeon_pm_info_list
));