2 * Permission is hereby granted, free of charge, to any person obtaining a
3 * copy of this software and associated documentation files (the "Software"),
4 * to deal in the Software without restriction, including without limitation
5 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
6 * and/or sell copies of the Software, and to permit persons to whom the
7 * Software is furnished to do so, subject to the following conditions:
9 * The above copyright notice and this permission notice shall be included in
10 * all copies or substantial portions of the Software.
12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
13 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
14 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
15 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
16 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
17 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
18 * OTHER DEALINGS IN THE SOFTWARE.
20 * Authors: Rafał Miłecki <zajec5@gmail.com>
21 * Alex Deucher <alexdeucher@gmail.com>
27 #define RADEON_IDLE_LOOP_MS 100
28 #define RADEON_RECLOCK_DELAY_MS 200
29 #define RADEON_WAIT_VBLANK_TIMEOUT 200
30 #define RADEON_WAIT_IDLE_TIMEOUT 200
32 static bool radeon_pm_debug_check_in_vbl(struct radeon_device
*rdev
, bool finish
);
33 static void radeon_pm_set_clocks_locked(struct radeon_device
*rdev
);
34 static void radeon_pm_set_clocks(struct radeon_device
*rdev
);
35 static void radeon_pm_idle_work_handler(struct work_struct
*work
);
36 static int radeon_debugfs_pm_init(struct radeon_device
*rdev
);
38 static const char *pm_state_names
[4] = {
45 static const char *pm_state_types
[5] = {
53 static void radeon_print_power_mode_info(struct radeon_device
*rdev
)
58 DRM_INFO("%d Power State(s)\n", rdev
->pm
.num_power_states
);
59 for (i
= 0; i
< rdev
->pm
.num_power_states
; i
++) {
60 if (rdev
->pm
.default_power_state
== &rdev
->pm
.power_state
[i
])
64 DRM_INFO("State %d %s %s\n", i
,
65 pm_state_types
[rdev
->pm
.power_state
[i
].type
],
66 is_default
? "(default)" : "");
67 if ((rdev
->flags
& RADEON_IS_PCIE
) && !(rdev
->flags
& RADEON_IS_IGP
))
68 DRM_INFO("\t%d PCIE Lanes\n", rdev
->pm
.power_state
[i
].non_clock_info
.pcie_lanes
);
69 DRM_INFO("\t%d Clock Mode(s)\n", rdev
->pm
.power_state
[i
].num_clock_modes
);
70 for (j
= 0; j
< rdev
->pm
.power_state
[i
].num_clock_modes
; j
++) {
71 if (rdev
->flags
& RADEON_IS_IGP
)
72 DRM_INFO("\t\t%d engine: %d\n",
74 rdev
->pm
.power_state
[i
].clock_info
[j
].sclk
* 10);
76 DRM_INFO("\t\t%d engine/memory: %d/%d\n",
78 rdev
->pm
.power_state
[i
].clock_info
[j
].sclk
* 10,
79 rdev
->pm
.power_state
[i
].clock_info
[j
].mclk
* 10);
84 static struct radeon_power_state
* radeon_pick_power_state(struct radeon_device
*rdev
,
85 enum radeon_pm_state_type type
)
88 enum radeon_pm_state_type wanted_types
[2];
92 case POWER_STATE_TYPE_DEFAULT
:
94 return rdev
->pm
.default_power_state
;
95 case POWER_STATE_TYPE_POWERSAVE
:
96 if (rdev
->flags
& RADEON_IS_MOBILITY
) {
97 wanted_types
[0] = POWER_STATE_TYPE_POWERSAVE
;
98 wanted_types
[1] = POWER_STATE_TYPE_BATTERY
;
101 wanted_types
[0] = POWER_STATE_TYPE_PERFORMANCE
;
105 case POWER_STATE_TYPE_BATTERY
:
106 if (rdev
->flags
& RADEON_IS_MOBILITY
) {
107 wanted_types
[0] = POWER_STATE_TYPE_BATTERY
;
108 wanted_types
[1] = POWER_STATE_TYPE_POWERSAVE
;
111 wanted_types
[0] = POWER_STATE_TYPE_PERFORMANCE
;
115 case POWER_STATE_TYPE_BALANCED
:
116 case POWER_STATE_TYPE_PERFORMANCE
:
117 wanted_types
[0] = type
;
122 for (i
= 0; i
< wanted_count
; i
++) {
123 for (j
= 0; j
< rdev
->pm
.num_power_states
; j
++) {
124 if (rdev
->pm
.power_state
[j
].type
== wanted_types
[i
])
125 return &rdev
->pm
.power_state
[j
];
129 return rdev
->pm
.default_power_state
;
132 static struct radeon_pm_clock_info
* radeon_pick_clock_mode(struct radeon_device
*rdev
,
133 struct radeon_power_state
*power_state
,
134 enum radeon_pm_clock_mode_type type
)
137 case POWER_MODE_TYPE_DEFAULT
:
139 return power_state
->default_clock_mode
;
140 case POWER_MODE_TYPE_LOW
:
141 return &power_state
->clock_info
[0];
142 case POWER_MODE_TYPE_MID
:
143 if (power_state
->num_clock_modes
> 2)
144 return &power_state
->clock_info
[1];
146 return &power_state
->clock_info
[0];
148 case POWER_MODE_TYPE_HIGH
:
149 return &power_state
->clock_info
[power_state
->num_clock_modes
- 1];
154 static void radeon_get_power_state(struct radeon_device
*rdev
,
155 enum radeon_pm_action action
)
158 case PM_ACTION_MINIMUM
:
159 rdev
->pm
.requested_power_state
= radeon_pick_power_state(rdev
, POWER_STATE_TYPE_BATTERY
);
160 rdev
->pm
.requested_clock_mode
=
161 radeon_pick_clock_mode(rdev
, rdev
->pm
.requested_power_state
, POWER_MODE_TYPE_LOW
);
163 case PM_ACTION_DOWNCLOCK
:
164 rdev
->pm
.requested_power_state
= radeon_pick_power_state(rdev
, POWER_STATE_TYPE_POWERSAVE
);
165 rdev
->pm
.requested_clock_mode
=
166 radeon_pick_clock_mode(rdev
, rdev
->pm
.requested_power_state
, POWER_MODE_TYPE_MID
);
168 case PM_ACTION_UPCLOCK
:
169 rdev
->pm
.requested_power_state
= radeon_pick_power_state(rdev
, POWER_STATE_TYPE_DEFAULT
);
170 rdev
->pm
.requested_clock_mode
=
171 radeon_pick_clock_mode(rdev
, rdev
->pm
.requested_power_state
, POWER_MODE_TYPE_HIGH
);
175 DRM_ERROR("Requested mode for not defined action\n");
178 DRM_INFO("Requested: e: %d m: %d p: %d\n",
179 rdev
->pm
.requested_clock_mode
->sclk
,
180 rdev
->pm
.requested_clock_mode
->mclk
,
181 rdev
->pm
.requested_power_state
->non_clock_info
.pcie_lanes
);
184 static inline void radeon_sync_with_vblank(struct radeon_device
*rdev
)
186 if (rdev
->pm
.active_crtcs
) {
187 rdev
->pm
.vblank_sync
= false;
189 rdev
->irq
.vblank_queue
, rdev
->pm
.vblank_sync
,
190 msecs_to_jiffies(RADEON_WAIT_VBLANK_TIMEOUT
));
194 static void radeon_set_power_state(struct radeon_device
*rdev
)
196 /* if *_clock_mode are the same, *_power_state are as well */
197 if (rdev
->pm
.requested_clock_mode
== rdev
->pm
.current_clock_mode
)
200 DRM_INFO("Setting: e: %d m: %d p: %d\n",
201 rdev
->pm
.requested_clock_mode
->sclk
,
202 rdev
->pm
.requested_clock_mode
->mclk
,
203 rdev
->pm
.requested_power_state
->non_clock_info
.pcie_lanes
);
211 /* set engine clock */
212 radeon_sync_with_vblank(rdev
);
213 radeon_pm_debug_check_in_vbl(rdev
, false);
214 radeon_set_engine_clock(rdev
, rdev
->pm
.requested_clock_mode
->sclk
);
215 radeon_pm_debug_check_in_vbl(rdev
, true);
218 /* set memory clock */
219 if (rdev
->asic
->set_memory_clock
) {
220 radeon_sync_with_vblank(rdev
);
221 radeon_pm_debug_check_in_vbl(rdev
, false);
222 radeon_set_memory_clock(rdev
, rdev
->pm
.requested_clock_mode
->mclk
);
223 radeon_pm_debug_check_in_vbl(rdev
, true);
227 rdev
->pm
.current_power_state
= rdev
->pm
.requested_power_state
;
228 rdev
->pm
.current_clock_mode
= rdev
->pm
.requested_clock_mode
;
231 int radeon_pm_init(struct radeon_device
*rdev
)
233 rdev
->pm
.state
= PM_STATE_DISABLED
;
234 rdev
->pm
.planned_action
= PM_ACTION_NONE
;
235 rdev
->pm
.downclocked
= false;
238 if (rdev
->is_atom_bios
)
239 radeon_atombios_get_power_modes(rdev
);
241 radeon_combios_get_power_modes(rdev
);
242 radeon_print_power_mode_info(rdev
);
245 if (radeon_debugfs_pm_init(rdev
)) {
246 DRM_ERROR("Failed to register debugfs file for PM!\n");
249 INIT_DELAYED_WORK(&rdev
->pm
.idle_work
, radeon_pm_idle_work_handler
);
251 if (radeon_dynpm
!= -1 && radeon_dynpm
) {
252 rdev
->pm
.state
= PM_STATE_PAUSED
;
253 DRM_INFO("radeon: dynamic power management enabled\n");
256 DRM_INFO("radeon: power management initialized\n");
261 void radeon_pm_fini(struct radeon_device
*rdev
)
263 if (rdev
->pm
.i2c_bus
)
264 radeon_i2c_destroy(rdev
->pm
.i2c_bus
);
267 void radeon_pm_compute_clocks(struct radeon_device
*rdev
)
269 struct drm_device
*ddev
= rdev
->ddev
;
270 struct drm_connector
*connector
;
271 struct radeon_crtc
*radeon_crtc
;
274 if (rdev
->pm
.state
== PM_STATE_DISABLED
)
277 mutex_lock(&rdev
->pm
.mutex
);
279 rdev
->pm
.active_crtcs
= 0;
280 list_for_each_entry(connector
,
281 &ddev
->mode_config
.connector_list
, head
) {
282 if (connector
->encoder
&&
283 connector
->encoder
->crtc
&&
284 connector
->dpms
!= DRM_MODE_DPMS_OFF
) {
285 radeon_crtc
= to_radeon_crtc(connector
->encoder
->crtc
);
286 rdev
->pm
.active_crtcs
|= (1 << radeon_crtc
->crtc_id
);
292 if (rdev
->pm
.state
== PM_STATE_ACTIVE
) {
293 cancel_delayed_work(&rdev
->pm
.idle_work
);
295 rdev
->pm
.state
= PM_STATE_PAUSED
;
296 rdev
->pm
.planned_action
= PM_ACTION_UPCLOCK
;
297 if (rdev
->pm
.downclocked
)
298 radeon_pm_set_clocks(rdev
);
300 DRM_DEBUG("radeon: dynamic power management deactivated\n");
302 } else if (count
== 1) {
303 /* TODO: Increase clocks if needed for current mode */
305 if (rdev
->pm
.state
== PM_STATE_MINIMUM
) {
306 rdev
->pm
.state
= PM_STATE_ACTIVE
;
307 rdev
->pm
.planned_action
= PM_ACTION_UPCLOCK
;
308 radeon_pm_set_clocks(rdev
);
310 queue_delayed_work(rdev
->wq
, &rdev
->pm
.idle_work
,
311 msecs_to_jiffies(RADEON_IDLE_LOOP_MS
));
313 else if (rdev
->pm
.state
== PM_STATE_PAUSED
) {
314 rdev
->pm
.state
= PM_STATE_ACTIVE
;
315 queue_delayed_work(rdev
->wq
, &rdev
->pm
.idle_work
,
316 msecs_to_jiffies(RADEON_IDLE_LOOP_MS
));
317 DRM_DEBUG("radeon: dynamic power management activated\n");
320 else { /* count == 0 */
321 if (rdev
->pm
.state
!= PM_STATE_MINIMUM
) {
322 cancel_delayed_work(&rdev
->pm
.idle_work
);
324 rdev
->pm
.state
= PM_STATE_MINIMUM
;
325 rdev
->pm
.planned_action
= PM_ACTION_MINIMUM
;
326 radeon_pm_set_clocks(rdev
);
330 mutex_unlock(&rdev
->pm
.mutex
);
333 static bool radeon_pm_debug_check_in_vbl(struct radeon_device
*rdev
, bool finish
)
335 u32 stat_crtc1
= 0, stat_crtc2
= 0;
338 if (ASIC_IS_AVIVO(rdev
)) {
339 if (rdev
->pm
.active_crtcs
& (1 << 0)) {
340 stat_crtc1
= RREG32(D1CRTC_STATUS
);
341 if (!(stat_crtc1
& 1))
344 if (rdev
->pm
.active_crtcs
& (1 << 1)) {
345 stat_crtc2
= RREG32(D2CRTC_STATUS
);
346 if (!(stat_crtc2
& 1))
351 DRM_INFO("not in vbl for pm change %08x %08x at %s\n", stat_crtc1
,
352 stat_crtc2
, finish
? "exit" : "entry");
355 static void radeon_pm_set_clocks_locked(struct radeon_device
*rdev
)
357 /*radeon_fence_wait_last(rdev);*/
358 switch (rdev
->pm
.planned_action
) {
359 case PM_ACTION_UPCLOCK
:
360 rdev
->pm
.downclocked
= false;
362 case PM_ACTION_DOWNCLOCK
:
363 rdev
->pm
.downclocked
= true;
365 case PM_ACTION_MINIMUM
:
368 DRM_ERROR("%s: PM_ACTION_NONE\n", __func__
);
372 radeon_set_power_state(rdev
);
373 rdev
->pm
.planned_action
= PM_ACTION_NONE
;
376 static void radeon_pm_set_clocks(struct radeon_device
*rdev
)
378 radeon_get_power_state(rdev
, rdev
->pm
.planned_action
);
379 mutex_lock(&rdev
->cp
.mutex
);
381 if (rdev
->pm
.active_crtcs
& (1 << 0)) {
382 rdev
->pm
.req_vblank
|= (1 << 0);
383 drm_vblank_get(rdev
->ddev
, 0);
385 if (rdev
->pm
.active_crtcs
& (1 << 1)) {
386 rdev
->pm
.req_vblank
|= (1 << 1);
387 drm_vblank_get(rdev
->ddev
, 1);
389 radeon_pm_set_clocks_locked(rdev
);
390 if (rdev
->pm
.req_vblank
& (1 << 0)) {
391 rdev
->pm
.req_vblank
&= ~(1 << 0);
392 drm_vblank_put(rdev
->ddev
, 0);
394 if (rdev
->pm
.req_vblank
& (1 << 1)) {
395 rdev
->pm
.req_vblank
&= ~(1 << 1);
396 drm_vblank_put(rdev
->ddev
, 1);
399 mutex_unlock(&rdev
->cp
.mutex
);
402 static void radeon_pm_idle_work_handler(struct work_struct
*work
)
404 struct radeon_device
*rdev
;
405 rdev
= container_of(work
, struct radeon_device
,
408 mutex_lock(&rdev
->pm
.mutex
);
409 if (rdev
->pm
.state
== PM_STATE_ACTIVE
) {
410 unsigned long irq_flags
;
411 int not_processed
= 0;
413 read_lock_irqsave(&rdev
->fence_drv
.lock
, irq_flags
);
414 if (!list_empty(&rdev
->fence_drv
.emited
)) {
415 struct list_head
*ptr
;
416 list_for_each(ptr
, &rdev
->fence_drv
.emited
) {
417 /* count up to 3, that's enought info */
418 if (++not_processed
>= 3)
422 read_unlock_irqrestore(&rdev
->fence_drv
.lock
, irq_flags
);
424 if (not_processed
>= 3) { /* should upclock */
425 if (rdev
->pm
.planned_action
== PM_ACTION_DOWNCLOCK
) {
426 rdev
->pm
.planned_action
= PM_ACTION_NONE
;
427 } else if (rdev
->pm
.planned_action
== PM_ACTION_NONE
&&
428 rdev
->pm
.downclocked
) {
429 rdev
->pm
.planned_action
=
431 rdev
->pm
.action_timeout
= jiffies
+
432 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS
);
434 } else if (not_processed
== 0) { /* should downclock */
435 if (rdev
->pm
.planned_action
== PM_ACTION_UPCLOCK
) {
436 rdev
->pm
.planned_action
= PM_ACTION_NONE
;
437 } else if (rdev
->pm
.planned_action
== PM_ACTION_NONE
&&
438 !rdev
->pm
.downclocked
) {
439 rdev
->pm
.planned_action
=
441 rdev
->pm
.action_timeout
= jiffies
+
442 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS
);
446 if (rdev
->pm
.planned_action
!= PM_ACTION_NONE
&&
447 jiffies
> rdev
->pm
.action_timeout
) {
448 radeon_pm_set_clocks(rdev
);
451 mutex_unlock(&rdev
->pm
.mutex
);
453 queue_delayed_work(rdev
->wq
, &rdev
->pm
.idle_work
,
454 msecs_to_jiffies(RADEON_IDLE_LOOP_MS
));
460 #if defined(CONFIG_DEBUG_FS)
462 static int radeon_debugfs_pm_info(struct seq_file
*m
, void *data
)
464 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
465 struct drm_device
*dev
= node
->minor
->dev
;
466 struct radeon_device
*rdev
= dev
->dev_private
;
468 seq_printf(m
, "state: %s\n", pm_state_names
[rdev
->pm
.state
]);
469 seq_printf(m
, "default engine clock: %u0 kHz\n", rdev
->clock
.default_sclk
);
470 seq_printf(m
, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev
));
471 seq_printf(m
, "default memory clock: %u0 kHz\n", rdev
->clock
.default_mclk
);
472 if (rdev
->asic
->get_memory_clock
)
473 seq_printf(m
, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev
));
474 if (rdev
->asic
->get_pcie_lanes
)
475 seq_printf(m
, "PCIE lanes: %d\n", radeon_get_pcie_lanes(rdev
));
480 static struct drm_info_list radeon_pm_info_list
[] = {
481 {"radeon_pm_info", radeon_debugfs_pm_info
, 0, NULL
},
485 static int radeon_debugfs_pm_init(struct radeon_device
*rdev
)
487 #if defined(CONFIG_DEBUG_FS)
488 return radeon_debugfs_add_files(rdev
, radeon_pm_info_list
, ARRAY_SIZE(radeon_pm_info_list
));