2 * Permission is hereby granted, free of charge, to any person obtaining a
3 * copy of this software and associated documentation files (the "Software"),
4 * to deal in the Software without restriction, including without limitation
5 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
6 * and/or sell copies of the Software, and to permit persons to whom the
7 * Software is furnished to do so, subject to the following conditions:
9 * The above copyright notice and this permission notice shall be included in
10 * all copies or substantial portions of the Software.
12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
13 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
14 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
15 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
16 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
17 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
18 * OTHER DEALINGS IN THE SOFTWARE.
20 * Authors: Rafał Miłecki <zajec5@gmail.com>
21 * Alex Deucher <alexdeucher@gmail.com>
27 #include <linux/power_supply.h>
28 #include <linux/hwmon.h>
29 #include <linux/hwmon-sysfs.h>
31 #define RADEON_IDLE_LOOP_MS 100
32 #define RADEON_RECLOCK_DELAY_MS 200
33 #define RADEON_WAIT_VBLANK_TIMEOUT 200
35 static const char *radeon_pm_state_type_name
[5] = {
43 static void radeon_dynpm_idle_work_handler(struct work_struct
*work
);
44 static int radeon_debugfs_pm_init(struct radeon_device
*rdev
);
45 static bool radeon_pm_in_vbl(struct radeon_device
*rdev
);
46 static bool radeon_pm_debug_check_in_vbl(struct radeon_device
*rdev
, bool finish
);
47 static void radeon_pm_update_profile(struct radeon_device
*rdev
);
48 static void radeon_pm_set_clocks(struct radeon_device
*rdev
);
50 int radeon_pm_get_type_index(struct radeon_device
*rdev
,
51 enum radeon_pm_state_type ps_type
,
55 int found_instance
= -1;
57 for (i
= 0; i
< rdev
->pm
.num_power_states
; i
++) {
58 if (rdev
->pm
.power_state
[i
].type
== ps_type
) {
60 if (found_instance
== instance
)
64 /* return default if no match */
65 return rdev
->pm
.default_power_state_index
;
68 void radeon_pm_acpi_event_handler(struct radeon_device
*rdev
)
70 if ((rdev
->pm
.pm_method
== PM_METHOD_DPM
) && rdev
->pm
.dpm_enabled
) {
71 mutex_lock(&rdev
->pm
.mutex
);
72 if (power_supply_is_system_supplied() > 0)
73 rdev
->pm
.dpm
.ac_power
= true;
75 rdev
->pm
.dpm
.ac_power
= false;
76 if (rdev
->asic
->dpm
.enable_bapm
)
77 radeon_dpm_enable_bapm(rdev
, rdev
->pm
.dpm
.ac_power
);
78 mutex_unlock(&rdev
->pm
.mutex
);
79 } else if (rdev
->pm
.pm_method
== PM_METHOD_PROFILE
) {
80 if (rdev
->pm
.profile
== PM_PROFILE_AUTO
) {
81 mutex_lock(&rdev
->pm
.mutex
);
82 radeon_pm_update_profile(rdev
);
83 radeon_pm_set_clocks(rdev
);
84 mutex_unlock(&rdev
->pm
.mutex
);
89 static void radeon_pm_update_profile(struct radeon_device
*rdev
)
91 switch (rdev
->pm
.profile
) {
92 case PM_PROFILE_DEFAULT
:
93 rdev
->pm
.profile_index
= PM_PROFILE_DEFAULT_IDX
;
96 if (power_supply_is_system_supplied() > 0) {
97 if (rdev
->pm
.active_crtc_count
> 1)
98 rdev
->pm
.profile_index
= PM_PROFILE_HIGH_MH_IDX
;
100 rdev
->pm
.profile_index
= PM_PROFILE_HIGH_SH_IDX
;
102 if (rdev
->pm
.active_crtc_count
> 1)
103 rdev
->pm
.profile_index
= PM_PROFILE_MID_MH_IDX
;
105 rdev
->pm
.profile_index
= PM_PROFILE_MID_SH_IDX
;
109 if (rdev
->pm
.active_crtc_count
> 1)
110 rdev
->pm
.profile_index
= PM_PROFILE_LOW_MH_IDX
;
112 rdev
->pm
.profile_index
= PM_PROFILE_LOW_SH_IDX
;
115 if (rdev
->pm
.active_crtc_count
> 1)
116 rdev
->pm
.profile_index
= PM_PROFILE_MID_MH_IDX
;
118 rdev
->pm
.profile_index
= PM_PROFILE_MID_SH_IDX
;
120 case PM_PROFILE_HIGH
:
121 if (rdev
->pm
.active_crtc_count
> 1)
122 rdev
->pm
.profile_index
= PM_PROFILE_HIGH_MH_IDX
;
124 rdev
->pm
.profile_index
= PM_PROFILE_HIGH_SH_IDX
;
128 if (rdev
->pm
.active_crtc_count
== 0) {
129 rdev
->pm
.requested_power_state_index
=
130 rdev
->pm
.profiles
[rdev
->pm
.profile_index
].dpms_off_ps_idx
;
131 rdev
->pm
.requested_clock_mode_index
=
132 rdev
->pm
.profiles
[rdev
->pm
.profile_index
].dpms_off_cm_idx
;
134 rdev
->pm
.requested_power_state_index
=
135 rdev
->pm
.profiles
[rdev
->pm
.profile_index
].dpms_on_ps_idx
;
136 rdev
->pm
.requested_clock_mode_index
=
137 rdev
->pm
.profiles
[rdev
->pm
.profile_index
].dpms_on_cm_idx
;
141 static void radeon_unmap_vram_bos(struct radeon_device
*rdev
)
143 struct radeon_bo
*bo
, *n
;
145 if (list_empty(&rdev
->gem
.objects
))
148 list_for_each_entry_safe(bo
, n
, &rdev
->gem
.objects
, list
) {
149 if (bo
->tbo
.mem
.mem_type
== TTM_PL_VRAM
)
150 ttm_bo_unmap_virtual(&bo
->tbo
);
154 static void radeon_sync_with_vblank(struct radeon_device
*rdev
)
156 if (rdev
->pm
.active_crtcs
) {
157 rdev
->pm
.vblank_sync
= false;
159 rdev
->irq
.vblank_queue
, rdev
->pm
.vblank_sync
,
160 msecs_to_jiffies(RADEON_WAIT_VBLANK_TIMEOUT
));
164 static void radeon_set_power_state(struct radeon_device
*rdev
)
167 bool misc_after
= false;
169 if ((rdev
->pm
.requested_clock_mode_index
== rdev
->pm
.current_clock_mode_index
) &&
170 (rdev
->pm
.requested_power_state_index
== rdev
->pm
.current_power_state_index
))
173 if (radeon_gui_idle(rdev
)) {
174 sclk
= rdev
->pm
.power_state
[rdev
->pm
.requested_power_state_index
].
175 clock_info
[rdev
->pm
.requested_clock_mode_index
].sclk
;
176 if (sclk
> rdev
->pm
.default_sclk
)
177 sclk
= rdev
->pm
.default_sclk
;
179 /* starting with BTC, there is one state that is used for both
180 * MH and SH. Difference is that we always use the high clock index for
183 if ((rdev
->pm
.pm_method
== PM_METHOD_PROFILE
) &&
184 (rdev
->family
>= CHIP_BARTS
) &&
185 rdev
->pm
.active_crtc_count
&&
186 ((rdev
->pm
.profile_index
== PM_PROFILE_MID_MH_IDX
) ||
187 (rdev
->pm
.profile_index
== PM_PROFILE_LOW_MH_IDX
)))
188 mclk
= rdev
->pm
.power_state
[rdev
->pm
.requested_power_state_index
].
189 clock_info
[rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_on_cm_idx
].mclk
;
191 mclk
= rdev
->pm
.power_state
[rdev
->pm
.requested_power_state_index
].
192 clock_info
[rdev
->pm
.requested_clock_mode_index
].mclk
;
194 if (mclk
> rdev
->pm
.default_mclk
)
195 mclk
= rdev
->pm
.default_mclk
;
197 /* upvolt before raising clocks, downvolt after lowering clocks */
198 if (sclk
< rdev
->pm
.current_sclk
)
201 radeon_sync_with_vblank(rdev
);
203 if (rdev
->pm
.pm_method
== PM_METHOD_DYNPM
) {
204 if (!radeon_pm_in_vbl(rdev
))
208 radeon_pm_prepare(rdev
);
211 /* voltage, pcie lanes, etc.*/
212 radeon_pm_misc(rdev
);
214 /* set engine clock */
215 if (sclk
!= rdev
->pm
.current_sclk
) {
216 radeon_pm_debug_check_in_vbl(rdev
, false);
217 radeon_set_engine_clock(rdev
, sclk
);
218 radeon_pm_debug_check_in_vbl(rdev
, true);
219 rdev
->pm
.current_sclk
= sclk
;
220 DRM_DEBUG_DRIVER("Setting: e: %d\n", sclk
);
223 /* set memory clock */
224 if (rdev
->asic
->pm
.set_memory_clock
&& (mclk
!= rdev
->pm
.current_mclk
)) {
225 radeon_pm_debug_check_in_vbl(rdev
, false);
226 radeon_set_memory_clock(rdev
, mclk
);
227 radeon_pm_debug_check_in_vbl(rdev
, true);
228 rdev
->pm
.current_mclk
= mclk
;
229 DRM_DEBUG_DRIVER("Setting: m: %d\n", mclk
);
233 /* voltage, pcie lanes, etc.*/
234 radeon_pm_misc(rdev
);
236 radeon_pm_finish(rdev
);
238 rdev
->pm
.current_power_state_index
= rdev
->pm
.requested_power_state_index
;
239 rdev
->pm
.current_clock_mode_index
= rdev
->pm
.requested_clock_mode_index
;
241 DRM_DEBUG_DRIVER("pm: GUI not idle!!!\n");
244 static void radeon_pm_set_clocks(struct radeon_device
*rdev
)
248 /* no need to take locks, etc. if nothing's going to change */
249 if ((rdev
->pm
.requested_clock_mode_index
== rdev
->pm
.current_clock_mode_index
) &&
250 (rdev
->pm
.requested_power_state_index
== rdev
->pm
.current_power_state_index
))
253 mutex_lock(&rdev
->ddev
->struct_mutex
);
254 down_write(&rdev
->pm
.mclk_lock
);
255 mutex_lock(&rdev
->ring_lock
);
257 /* wait for the rings to drain */
258 for (i
= 0; i
< RADEON_NUM_RINGS
; i
++) {
259 struct radeon_ring
*ring
= &rdev
->ring
[i
];
263 r
= radeon_fence_wait_empty_locked(rdev
, i
);
265 /* needs a GPU reset dont reset here */
266 mutex_unlock(&rdev
->ring_lock
);
267 up_write(&rdev
->pm
.mclk_lock
);
268 mutex_unlock(&rdev
->ddev
->struct_mutex
);
273 radeon_unmap_vram_bos(rdev
);
275 if (rdev
->irq
.installed
) {
276 for (i
= 0; i
< rdev
->num_crtc
; i
++) {
277 if (rdev
->pm
.active_crtcs
& (1 << i
)) {
278 rdev
->pm
.req_vblank
|= (1 << i
);
279 drm_vblank_get(rdev
->ddev
, i
);
284 radeon_set_power_state(rdev
);
286 if (rdev
->irq
.installed
) {
287 for (i
= 0; i
< rdev
->num_crtc
; i
++) {
288 if (rdev
->pm
.req_vblank
& (1 << i
)) {
289 rdev
->pm
.req_vblank
&= ~(1 << i
);
290 drm_vblank_put(rdev
->ddev
, i
);
295 /* update display watermarks based on new power state */
296 radeon_update_bandwidth_info(rdev
);
297 if (rdev
->pm
.active_crtc_count
)
298 radeon_bandwidth_update(rdev
);
300 rdev
->pm
.dynpm_planned_action
= DYNPM_ACTION_NONE
;
302 mutex_unlock(&rdev
->ring_lock
);
303 up_write(&rdev
->pm
.mclk_lock
);
304 mutex_unlock(&rdev
->ddev
->struct_mutex
);
307 static void radeon_pm_print_states(struct radeon_device
*rdev
)
310 struct radeon_power_state
*power_state
;
311 struct radeon_pm_clock_info
*clock_info
;
313 DRM_DEBUG_DRIVER("%d Power State(s)\n", rdev
->pm
.num_power_states
);
314 for (i
= 0; i
< rdev
->pm
.num_power_states
; i
++) {
315 power_state
= &rdev
->pm
.power_state
[i
];
316 DRM_DEBUG_DRIVER("State %d: %s\n", i
,
317 radeon_pm_state_type_name
[power_state
->type
]);
318 if (i
== rdev
->pm
.default_power_state_index
)
319 DRM_DEBUG_DRIVER("\tDefault");
320 if ((rdev
->flags
& RADEON_IS_PCIE
) && !(rdev
->flags
& RADEON_IS_IGP
))
321 DRM_DEBUG_DRIVER("\t%d PCIE Lanes\n", power_state
->pcie_lanes
);
322 if (power_state
->flags
& RADEON_PM_STATE_SINGLE_DISPLAY_ONLY
)
323 DRM_DEBUG_DRIVER("\tSingle display only\n");
324 DRM_DEBUG_DRIVER("\t%d Clock Mode(s)\n", power_state
->num_clock_modes
);
325 for (j
= 0; j
< power_state
->num_clock_modes
; j
++) {
326 clock_info
= &(power_state
->clock_info
[j
]);
327 if (rdev
->flags
& RADEON_IS_IGP
)
328 DRM_DEBUG_DRIVER("\t\t%d e: %d\n",
330 clock_info
->sclk
* 10);
332 DRM_DEBUG_DRIVER("\t\t%d e: %d\tm: %d\tv: %d\n",
334 clock_info
->sclk
* 10,
335 clock_info
->mclk
* 10,
336 clock_info
->voltage
.voltage
);
341 static ssize_t
radeon_get_pm_profile(struct device
*dev
,
342 struct device_attribute
*attr
,
345 struct drm_device
*ddev
= dev_get_drvdata(dev
);
346 struct radeon_device
*rdev
= ddev
->dev_private
;
347 int cp
= rdev
->pm
.profile
;
349 return snprintf(buf
, PAGE_SIZE
, "%s\n",
350 (cp
== PM_PROFILE_AUTO
) ? "auto" :
351 (cp
== PM_PROFILE_LOW
) ? "low" :
352 (cp
== PM_PROFILE_MID
) ? "mid" :
353 (cp
== PM_PROFILE_HIGH
) ? "high" : "default");
356 static ssize_t
radeon_set_pm_profile(struct device
*dev
,
357 struct device_attribute
*attr
,
361 struct drm_device
*ddev
= dev_get_drvdata(dev
);
362 struct radeon_device
*rdev
= ddev
->dev_private
;
364 mutex_lock(&rdev
->pm
.mutex
);
365 if (rdev
->pm
.pm_method
== PM_METHOD_PROFILE
) {
366 if (strncmp("default", buf
, strlen("default")) == 0)
367 rdev
->pm
.profile
= PM_PROFILE_DEFAULT
;
368 else if (strncmp("auto", buf
, strlen("auto")) == 0)
369 rdev
->pm
.profile
= PM_PROFILE_AUTO
;
370 else if (strncmp("low", buf
, strlen("low")) == 0)
371 rdev
->pm
.profile
= PM_PROFILE_LOW
;
372 else if (strncmp("mid", buf
, strlen("mid")) == 0)
373 rdev
->pm
.profile
= PM_PROFILE_MID
;
374 else if (strncmp("high", buf
, strlen("high")) == 0)
375 rdev
->pm
.profile
= PM_PROFILE_HIGH
;
380 radeon_pm_update_profile(rdev
);
381 radeon_pm_set_clocks(rdev
);
386 mutex_unlock(&rdev
->pm
.mutex
);
391 static ssize_t
radeon_get_pm_method(struct device
*dev
,
392 struct device_attribute
*attr
,
395 struct drm_device
*ddev
= dev_get_drvdata(dev
);
396 struct radeon_device
*rdev
= ddev
->dev_private
;
397 int pm
= rdev
->pm
.pm_method
;
399 return snprintf(buf
, PAGE_SIZE
, "%s\n",
400 (pm
== PM_METHOD_DYNPM
) ? "dynpm" :
401 (pm
== PM_METHOD_PROFILE
) ? "profile" : "dpm");
404 static ssize_t
radeon_set_pm_method(struct device
*dev
,
405 struct device_attribute
*attr
,
409 struct drm_device
*ddev
= dev_get_drvdata(dev
);
410 struct radeon_device
*rdev
= ddev
->dev_private
;
412 /* we don't support the legacy modes with dpm */
413 if (rdev
->pm
.pm_method
== PM_METHOD_DPM
) {
418 if (strncmp("dynpm", buf
, strlen("dynpm")) == 0) {
419 mutex_lock(&rdev
->pm
.mutex
);
420 rdev
->pm
.pm_method
= PM_METHOD_DYNPM
;
421 rdev
->pm
.dynpm_state
= DYNPM_STATE_PAUSED
;
422 rdev
->pm
.dynpm_planned_action
= DYNPM_ACTION_DEFAULT
;
423 mutex_unlock(&rdev
->pm
.mutex
);
424 } else if (strncmp("profile", buf
, strlen("profile")) == 0) {
425 mutex_lock(&rdev
->pm
.mutex
);
427 rdev
->pm
.dynpm_state
= DYNPM_STATE_DISABLED
;
428 rdev
->pm
.dynpm_planned_action
= DYNPM_ACTION_NONE
;
429 rdev
->pm
.pm_method
= PM_METHOD_PROFILE
;
430 mutex_unlock(&rdev
->pm
.mutex
);
431 cancel_delayed_work_sync(&rdev
->pm
.dynpm_idle_work
);
436 radeon_pm_compute_clocks(rdev
);
441 static ssize_t
radeon_get_dpm_state(struct device
*dev
,
442 struct device_attribute
*attr
,
445 struct drm_device
*ddev
= dev_get_drvdata(dev
);
446 struct radeon_device
*rdev
= ddev
->dev_private
;
447 enum radeon_pm_state_type pm
= rdev
->pm
.dpm
.user_state
;
449 return snprintf(buf
, PAGE_SIZE
, "%s\n",
450 (pm
== POWER_STATE_TYPE_BATTERY
) ? "battery" :
451 (pm
== POWER_STATE_TYPE_BALANCED
) ? "balanced" : "performance");
454 static ssize_t
radeon_set_dpm_state(struct device
*dev
,
455 struct device_attribute
*attr
,
459 struct drm_device
*ddev
= dev_get_drvdata(dev
);
460 struct radeon_device
*rdev
= ddev
->dev_private
;
462 mutex_lock(&rdev
->pm
.mutex
);
463 if (strncmp("battery", buf
, strlen("battery")) == 0)
464 rdev
->pm
.dpm
.user_state
= POWER_STATE_TYPE_BATTERY
;
465 else if (strncmp("balanced", buf
, strlen("balanced")) == 0)
466 rdev
->pm
.dpm
.user_state
= POWER_STATE_TYPE_BALANCED
;
467 else if (strncmp("performance", buf
, strlen("performance")) == 0)
468 rdev
->pm
.dpm
.user_state
= POWER_STATE_TYPE_PERFORMANCE
;
470 mutex_unlock(&rdev
->pm
.mutex
);
474 mutex_unlock(&rdev
->pm
.mutex
);
475 radeon_pm_compute_clocks(rdev
);
480 static ssize_t
radeon_get_dpm_forced_performance_level(struct device
*dev
,
481 struct device_attribute
*attr
,
484 struct drm_device
*ddev
= dev_get_drvdata(dev
);
485 struct radeon_device
*rdev
= ddev
->dev_private
;
486 enum radeon_dpm_forced_level level
= rdev
->pm
.dpm
.forced_level
;
488 return snprintf(buf
, PAGE_SIZE
, "%s\n",
489 (level
== RADEON_DPM_FORCED_LEVEL_AUTO
) ? "auto" :
490 (level
== RADEON_DPM_FORCED_LEVEL_LOW
) ? "low" : "high");
493 static ssize_t
radeon_set_dpm_forced_performance_level(struct device
*dev
,
494 struct device_attribute
*attr
,
498 struct drm_device
*ddev
= dev_get_drvdata(dev
);
499 struct radeon_device
*rdev
= ddev
->dev_private
;
500 enum radeon_dpm_forced_level level
;
503 mutex_lock(&rdev
->pm
.mutex
);
504 if (strncmp("low", buf
, strlen("low")) == 0) {
505 level
= RADEON_DPM_FORCED_LEVEL_LOW
;
506 } else if (strncmp("high", buf
, strlen("high")) == 0) {
507 level
= RADEON_DPM_FORCED_LEVEL_HIGH
;
508 } else if (strncmp("auto", buf
, strlen("auto")) == 0) {
509 level
= RADEON_DPM_FORCED_LEVEL_AUTO
;
511 mutex_unlock(&rdev
->pm
.mutex
);
515 if (rdev
->asic
->dpm
.force_performance_level
) {
516 ret
= radeon_dpm_force_performance_level(rdev
, level
);
520 mutex_unlock(&rdev
->pm
.mutex
);
525 static DEVICE_ATTR(power_profile
, S_IRUGO
| S_IWUSR
, radeon_get_pm_profile
, radeon_set_pm_profile
);
526 static DEVICE_ATTR(power_method
, S_IRUGO
| S_IWUSR
, radeon_get_pm_method
, radeon_set_pm_method
);
527 static DEVICE_ATTR(power_dpm_state
, S_IRUGO
| S_IWUSR
, radeon_get_dpm_state
, radeon_set_dpm_state
);
528 static DEVICE_ATTR(power_dpm_force_performance_level
, S_IRUGO
| S_IWUSR
,
529 radeon_get_dpm_forced_performance_level
,
530 radeon_set_dpm_forced_performance_level
);
532 static ssize_t
radeon_hwmon_show_temp(struct device
*dev
,
533 struct device_attribute
*attr
,
536 struct drm_device
*ddev
= dev_get_drvdata(dev
);
537 struct radeon_device
*rdev
= ddev
->dev_private
;
540 if (rdev
->asic
->pm
.get_temperature
)
541 temp
= radeon_get_temperature(rdev
);
545 return snprintf(buf
, PAGE_SIZE
, "%d\n", temp
);
548 static ssize_t
radeon_hwmon_show_temp_thresh(struct device
*dev
,
549 struct device_attribute
*attr
,
552 struct drm_device
*ddev
= dev_get_drvdata(dev
);
553 struct radeon_device
*rdev
= ddev
->dev_private
;
554 int hyst
= to_sensor_dev_attr(attr
)->index
;
558 temp
= rdev
->pm
.dpm
.thermal
.min_temp
;
560 temp
= rdev
->pm
.dpm
.thermal
.max_temp
;
562 return snprintf(buf
, PAGE_SIZE
, "%d\n", temp
);
565 static ssize_t
radeon_hwmon_show_name(struct device
*dev
,
566 struct device_attribute
*attr
,
569 return sprintf(buf
, "radeon\n");
572 static SENSOR_DEVICE_ATTR(temp1_input
, S_IRUGO
, radeon_hwmon_show_temp
, NULL
, 0);
573 static SENSOR_DEVICE_ATTR(temp1_crit
, S_IRUGO
, radeon_hwmon_show_temp_thresh
, NULL
, 0);
574 static SENSOR_DEVICE_ATTR(temp1_crit_hyst
, S_IRUGO
, radeon_hwmon_show_temp_thresh
, NULL
, 1);
575 static SENSOR_DEVICE_ATTR(name
, S_IRUGO
, radeon_hwmon_show_name
, NULL
, 0);
577 static struct attribute
*hwmon_attributes
[] = {
578 &sensor_dev_attr_temp1_input
.dev_attr
.attr
,
579 &sensor_dev_attr_temp1_crit
.dev_attr
.attr
,
580 &sensor_dev_attr_temp1_crit_hyst
.dev_attr
.attr
,
581 &sensor_dev_attr_name
.dev_attr
.attr
,
585 static umode_t
hwmon_attributes_visible(struct kobject
*kobj
,
586 struct attribute
*attr
, int index
)
588 struct device
*dev
= container_of(kobj
, struct device
, kobj
);
589 struct drm_device
*ddev
= dev_get_drvdata(dev
);
590 struct radeon_device
*rdev
= ddev
->dev_private
;
592 /* Skip limit attributes if DPM is not enabled */
593 if (rdev
->pm
.pm_method
!= PM_METHOD_DPM
&&
594 (attr
== &sensor_dev_attr_temp1_crit
.dev_attr
.attr
||
595 attr
== &sensor_dev_attr_temp1_crit_hyst
.dev_attr
.attr
))
601 static const struct attribute_group hwmon_attrgroup
= {
602 .attrs
= hwmon_attributes
,
603 .is_visible
= hwmon_attributes_visible
,
606 static int radeon_hwmon_init(struct radeon_device
*rdev
)
610 rdev
->pm
.int_hwmon_dev
= NULL
;
612 switch (rdev
->pm
.int_thermal_type
) {
613 case THERMAL_TYPE_RV6XX
:
614 case THERMAL_TYPE_RV770
:
615 case THERMAL_TYPE_EVERGREEN
:
616 case THERMAL_TYPE_NI
:
617 case THERMAL_TYPE_SUMO
:
618 case THERMAL_TYPE_SI
:
619 case THERMAL_TYPE_CI
:
620 case THERMAL_TYPE_KV
:
621 if (rdev
->asic
->pm
.get_temperature
== NULL
)
623 rdev
->pm
.int_hwmon_dev
= hwmon_device_register(rdev
->dev
);
624 if (IS_ERR(rdev
->pm
.int_hwmon_dev
)) {
625 err
= PTR_ERR(rdev
->pm
.int_hwmon_dev
);
627 "Unable to register hwmon device: %d\n", err
);
630 dev_set_drvdata(rdev
->pm
.int_hwmon_dev
, rdev
->ddev
);
631 err
= sysfs_create_group(&rdev
->pm
.int_hwmon_dev
->kobj
,
635 "Unable to create hwmon sysfs file: %d\n", err
);
636 hwmon_device_unregister(rdev
->dev
);
646 static void radeon_hwmon_fini(struct radeon_device
*rdev
)
648 if (rdev
->pm
.int_hwmon_dev
) {
649 sysfs_remove_group(&rdev
->pm
.int_hwmon_dev
->kobj
, &hwmon_attrgroup
);
650 hwmon_device_unregister(rdev
->pm
.int_hwmon_dev
);
654 static void radeon_dpm_thermal_work_handler(struct work_struct
*work
)
656 struct radeon_device
*rdev
=
657 container_of(work
, struct radeon_device
,
658 pm
.dpm
.thermal
.work
);
659 /* switch to the thermal state */
660 enum radeon_pm_state_type dpm_state
= POWER_STATE_TYPE_INTERNAL_THERMAL
;
662 if (!rdev
->pm
.dpm_enabled
)
665 if (rdev
->asic
->pm
.get_temperature
) {
666 int temp
= radeon_get_temperature(rdev
);
668 if (temp
< rdev
->pm
.dpm
.thermal
.min_temp
)
669 /* switch back the user state */
670 dpm_state
= rdev
->pm
.dpm
.user_state
;
672 if (rdev
->pm
.dpm
.thermal
.high_to_low
)
673 /* switch back the user state */
674 dpm_state
= rdev
->pm
.dpm
.user_state
;
676 mutex_lock(&rdev
->pm
.mutex
);
677 if (dpm_state
== POWER_STATE_TYPE_INTERNAL_THERMAL
)
678 rdev
->pm
.dpm
.thermal_active
= true;
680 rdev
->pm
.dpm
.thermal_active
= false;
681 rdev
->pm
.dpm
.state
= dpm_state
;
682 mutex_unlock(&rdev
->pm
.mutex
);
684 radeon_pm_compute_clocks(rdev
);
687 static struct radeon_ps
*radeon_dpm_pick_power_state(struct radeon_device
*rdev
,
688 enum radeon_pm_state_type dpm_state
)
691 struct radeon_ps
*ps
;
693 bool single_display
= (rdev
->pm
.dpm
.new_active_crtc_count
< 2) ?
696 /* check if the vblank period is too short to adjust the mclk */
697 if (single_display
&& rdev
->asic
->dpm
.vblank_too_short
) {
698 if (radeon_dpm_vblank_too_short(rdev
))
699 single_display
= false;
702 /* certain older asics have a separare 3D performance state,
703 * so try that first if the user selected performance
705 if (dpm_state
== POWER_STATE_TYPE_PERFORMANCE
)
706 dpm_state
= POWER_STATE_TYPE_INTERNAL_3DPERF
;
707 /* balanced states don't exist at the moment */
708 if (dpm_state
== POWER_STATE_TYPE_BALANCED
)
709 dpm_state
= POWER_STATE_TYPE_PERFORMANCE
;
712 /* Pick the best power state based on current conditions */
713 for (i
= 0; i
< rdev
->pm
.dpm
.num_ps
; i
++) {
714 ps
= &rdev
->pm
.dpm
.ps
[i
];
715 ui_class
= ps
->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK
;
718 case POWER_STATE_TYPE_BATTERY
:
719 if (ui_class
== ATOM_PPLIB_CLASSIFICATION_UI_BATTERY
) {
720 if (ps
->caps
& ATOM_PPLIB_SINGLE_DISPLAY_ONLY
) {
727 case POWER_STATE_TYPE_BALANCED
:
728 if (ui_class
== ATOM_PPLIB_CLASSIFICATION_UI_BALANCED
) {
729 if (ps
->caps
& ATOM_PPLIB_SINGLE_DISPLAY_ONLY
) {
736 case POWER_STATE_TYPE_PERFORMANCE
:
737 if (ui_class
== ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE
) {
738 if (ps
->caps
& ATOM_PPLIB_SINGLE_DISPLAY_ONLY
) {
745 /* internal states */
746 case POWER_STATE_TYPE_INTERNAL_UVD
:
747 if (rdev
->pm
.dpm
.uvd_ps
)
748 return rdev
->pm
.dpm
.uvd_ps
;
751 case POWER_STATE_TYPE_INTERNAL_UVD_SD
:
752 if (ps
->class & ATOM_PPLIB_CLASSIFICATION_SDSTATE
)
755 case POWER_STATE_TYPE_INTERNAL_UVD_HD
:
756 if (ps
->class & ATOM_PPLIB_CLASSIFICATION_HDSTATE
)
759 case POWER_STATE_TYPE_INTERNAL_UVD_HD2
:
760 if (ps
->class & ATOM_PPLIB_CLASSIFICATION_HD2STATE
)
763 case POWER_STATE_TYPE_INTERNAL_UVD_MVC
:
764 if (ps
->class2
& ATOM_PPLIB_CLASSIFICATION2_MVC
)
767 case POWER_STATE_TYPE_INTERNAL_BOOT
:
768 return rdev
->pm
.dpm
.boot_ps
;
769 case POWER_STATE_TYPE_INTERNAL_THERMAL
:
770 if (ps
->class & ATOM_PPLIB_CLASSIFICATION_THERMAL
)
773 case POWER_STATE_TYPE_INTERNAL_ACPI
:
774 if (ps
->class & ATOM_PPLIB_CLASSIFICATION_ACPI
)
777 case POWER_STATE_TYPE_INTERNAL_ULV
:
778 if (ps
->class2
& ATOM_PPLIB_CLASSIFICATION2_ULV
)
781 case POWER_STATE_TYPE_INTERNAL_3DPERF
:
782 if (ps
->class & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE
)
789 /* use a fallback state if we didn't match */
791 case POWER_STATE_TYPE_INTERNAL_UVD_SD
:
792 dpm_state
= POWER_STATE_TYPE_INTERNAL_UVD_HD
;
794 case POWER_STATE_TYPE_INTERNAL_UVD_HD
:
795 case POWER_STATE_TYPE_INTERNAL_UVD_HD2
:
796 case POWER_STATE_TYPE_INTERNAL_UVD_MVC
:
797 if (rdev
->pm
.dpm
.uvd_ps
) {
798 return rdev
->pm
.dpm
.uvd_ps
;
800 dpm_state
= POWER_STATE_TYPE_PERFORMANCE
;
803 case POWER_STATE_TYPE_INTERNAL_THERMAL
:
804 dpm_state
= POWER_STATE_TYPE_INTERNAL_ACPI
;
806 case POWER_STATE_TYPE_INTERNAL_ACPI
:
807 dpm_state
= POWER_STATE_TYPE_BATTERY
;
809 case POWER_STATE_TYPE_BATTERY
:
810 case POWER_STATE_TYPE_BALANCED
:
811 case POWER_STATE_TYPE_INTERNAL_3DPERF
:
812 dpm_state
= POWER_STATE_TYPE_PERFORMANCE
;
821 static void radeon_dpm_change_power_state_locked(struct radeon_device
*rdev
)
824 struct radeon_ps
*ps
;
825 enum radeon_pm_state_type dpm_state
;
828 /* if dpm init failed */
829 if (!rdev
->pm
.dpm_enabled
)
832 if (rdev
->pm
.dpm
.user_state
!= rdev
->pm
.dpm
.state
) {
833 /* add other state override checks here */
834 if ((!rdev
->pm
.dpm
.thermal_active
) &&
835 (!rdev
->pm
.dpm
.uvd_active
))
836 rdev
->pm
.dpm
.state
= rdev
->pm
.dpm
.user_state
;
838 dpm_state
= rdev
->pm
.dpm
.state
;
840 ps
= radeon_dpm_pick_power_state(rdev
, dpm_state
);
842 rdev
->pm
.dpm
.requested_ps
= ps
;
846 /* no need to reprogram if nothing changed unless we are on BTC+ */
847 if (rdev
->pm
.dpm
.current_ps
== rdev
->pm
.dpm
.requested_ps
) {
848 if ((rdev
->family
< CHIP_BARTS
) || (rdev
->flags
& RADEON_IS_IGP
)) {
849 /* for pre-BTC and APUs if the num crtcs changed but state is the same,
850 * all we need to do is update the display configuration.
852 if (rdev
->pm
.dpm
.new_active_crtcs
!= rdev
->pm
.dpm
.current_active_crtcs
) {
853 /* update display watermarks based on new power state */
854 radeon_bandwidth_update(rdev
);
855 /* update displays */
856 radeon_dpm_display_configuration_changed(rdev
);
857 rdev
->pm
.dpm
.current_active_crtcs
= rdev
->pm
.dpm
.new_active_crtcs
;
858 rdev
->pm
.dpm
.current_active_crtc_count
= rdev
->pm
.dpm
.new_active_crtc_count
;
862 /* for BTC+ if the num crtcs hasn't changed and state is the same,
863 * nothing to do, if the num crtcs is > 1 and state is the same,
864 * update display configuration.
866 if (rdev
->pm
.dpm
.new_active_crtcs
==
867 rdev
->pm
.dpm
.current_active_crtcs
) {
870 if ((rdev
->pm
.dpm
.current_active_crtc_count
> 1) &&
871 (rdev
->pm
.dpm
.new_active_crtc_count
> 1)) {
872 /* update display watermarks based on new power state */
873 radeon_bandwidth_update(rdev
);
874 /* update displays */
875 radeon_dpm_display_configuration_changed(rdev
);
876 rdev
->pm
.dpm
.current_active_crtcs
= rdev
->pm
.dpm
.new_active_crtcs
;
877 rdev
->pm
.dpm
.current_active_crtc_count
= rdev
->pm
.dpm
.new_active_crtc_count
;
884 printk("switching from power state:\n");
885 radeon_dpm_print_power_state(rdev
, rdev
->pm
.dpm
.current_ps
);
886 printk("switching to power state:\n");
887 radeon_dpm_print_power_state(rdev
, rdev
->pm
.dpm
.requested_ps
);
889 mutex_lock(&rdev
->ddev
->struct_mutex
);
890 down_write(&rdev
->pm
.mclk_lock
);
891 mutex_lock(&rdev
->ring_lock
);
893 ret
= radeon_dpm_pre_set_power_state(rdev
);
897 /* update display watermarks based on new power state */
898 radeon_bandwidth_update(rdev
);
899 /* update displays */
900 radeon_dpm_display_configuration_changed(rdev
);
902 rdev
->pm
.dpm
.current_active_crtcs
= rdev
->pm
.dpm
.new_active_crtcs
;
903 rdev
->pm
.dpm
.current_active_crtc_count
= rdev
->pm
.dpm
.new_active_crtc_count
;
905 /* wait for the rings to drain */
906 for (i
= 0; i
< RADEON_NUM_RINGS
; i
++) {
907 struct radeon_ring
*ring
= &rdev
->ring
[i
];
909 radeon_fence_wait_empty_locked(rdev
, i
);
912 /* program the new power state */
913 radeon_dpm_set_power_state(rdev
);
915 /* update current power state */
916 rdev
->pm
.dpm
.current_ps
= rdev
->pm
.dpm
.requested_ps
;
918 radeon_dpm_post_set_power_state(rdev
);
920 if (rdev
->asic
->dpm
.force_performance_level
) {
921 if (rdev
->pm
.dpm
.thermal_active
)
922 /* force low perf level for thermal */
923 radeon_dpm_force_performance_level(rdev
, RADEON_DPM_FORCED_LEVEL_LOW
);
925 /* otherwise, enable auto */
926 radeon_dpm_force_performance_level(rdev
, RADEON_DPM_FORCED_LEVEL_AUTO
);
930 mutex_unlock(&rdev
->ring_lock
);
931 up_write(&rdev
->pm
.mclk_lock
);
932 mutex_unlock(&rdev
->ddev
->struct_mutex
);
935 void radeon_dpm_enable_uvd(struct radeon_device
*rdev
, bool enable
)
937 enum radeon_pm_state_type dpm_state
;
939 if (rdev
->asic
->dpm
.powergate_uvd
) {
940 mutex_lock(&rdev
->pm
.mutex
);
941 /* enable/disable UVD */
942 radeon_dpm_powergate_uvd(rdev
, !enable
);
943 mutex_unlock(&rdev
->pm
.mutex
);
946 mutex_lock(&rdev
->pm
.mutex
);
947 rdev
->pm
.dpm
.uvd_active
= true;
948 if ((rdev
->pm
.dpm
.sd
== 1) && (rdev
->pm
.dpm
.hd
== 0))
949 dpm_state
= POWER_STATE_TYPE_INTERNAL_UVD_SD
;
950 else if ((rdev
->pm
.dpm
.sd
== 2) && (rdev
->pm
.dpm
.hd
== 0))
951 dpm_state
= POWER_STATE_TYPE_INTERNAL_UVD_HD
;
952 else if ((rdev
->pm
.dpm
.sd
== 0) && (rdev
->pm
.dpm
.hd
== 1))
953 dpm_state
= POWER_STATE_TYPE_INTERNAL_UVD_HD
;
954 else if ((rdev
->pm
.dpm
.sd
== 0) && (rdev
->pm
.dpm
.hd
== 2))
955 dpm_state
= POWER_STATE_TYPE_INTERNAL_UVD_HD2
;
957 dpm_state
= POWER_STATE_TYPE_INTERNAL_UVD
;
958 rdev
->pm
.dpm
.state
= dpm_state
;
959 mutex_unlock(&rdev
->pm
.mutex
);
961 mutex_lock(&rdev
->pm
.mutex
);
962 rdev
->pm
.dpm
.uvd_active
= false;
963 mutex_unlock(&rdev
->pm
.mutex
);
966 radeon_pm_compute_clocks(rdev
);
970 static void radeon_pm_suspend_old(struct radeon_device
*rdev
)
972 mutex_lock(&rdev
->pm
.mutex
);
973 if (rdev
->pm
.pm_method
== PM_METHOD_DYNPM
) {
974 if (rdev
->pm
.dynpm_state
== DYNPM_STATE_ACTIVE
)
975 rdev
->pm
.dynpm_state
= DYNPM_STATE_SUSPENDED
;
977 mutex_unlock(&rdev
->pm
.mutex
);
979 cancel_delayed_work_sync(&rdev
->pm
.dynpm_idle_work
);
982 static void radeon_pm_suspend_dpm(struct radeon_device
*rdev
)
984 mutex_lock(&rdev
->pm
.mutex
);
986 radeon_dpm_disable(rdev
);
987 /* reset the power state */
988 rdev
->pm
.dpm
.current_ps
= rdev
->pm
.dpm
.requested_ps
= rdev
->pm
.dpm
.boot_ps
;
989 rdev
->pm
.dpm_enabled
= false;
990 mutex_unlock(&rdev
->pm
.mutex
);
993 void radeon_pm_suspend(struct radeon_device
*rdev
)
995 if (rdev
->pm
.pm_method
== PM_METHOD_DPM
)
996 radeon_pm_suspend_dpm(rdev
);
998 radeon_pm_suspend_old(rdev
);
1001 static void radeon_pm_resume_old(struct radeon_device
*rdev
)
1003 /* set up the default clocks if the MC ucode is loaded */
1004 if ((rdev
->family
>= CHIP_BARTS
) &&
1005 (rdev
->family
<= CHIP_HAINAN
) &&
1007 if (rdev
->pm
.default_vddc
)
1008 radeon_atom_set_voltage(rdev
, rdev
->pm
.default_vddc
,
1009 SET_VOLTAGE_TYPE_ASIC_VDDC
);
1010 if (rdev
->pm
.default_vddci
)
1011 radeon_atom_set_voltage(rdev
, rdev
->pm
.default_vddci
,
1012 SET_VOLTAGE_TYPE_ASIC_VDDCI
);
1013 if (rdev
->pm
.default_sclk
)
1014 radeon_set_engine_clock(rdev
, rdev
->pm
.default_sclk
);
1015 if (rdev
->pm
.default_mclk
)
1016 radeon_set_memory_clock(rdev
, rdev
->pm
.default_mclk
);
1018 /* asic init will reset the default power state */
1019 mutex_lock(&rdev
->pm
.mutex
);
1020 rdev
->pm
.current_power_state_index
= rdev
->pm
.default_power_state_index
;
1021 rdev
->pm
.current_clock_mode_index
= 0;
1022 rdev
->pm
.current_sclk
= rdev
->pm
.default_sclk
;
1023 rdev
->pm
.current_mclk
= rdev
->pm
.default_mclk
;
1024 rdev
->pm
.current_vddc
= rdev
->pm
.power_state
[rdev
->pm
.default_power_state_index
].clock_info
[0].voltage
.voltage
;
1025 rdev
->pm
.current_vddci
= rdev
->pm
.power_state
[rdev
->pm
.default_power_state_index
].clock_info
[0].voltage
.vddci
;
1026 if (rdev
->pm
.pm_method
== PM_METHOD_DYNPM
1027 && rdev
->pm
.dynpm_state
== DYNPM_STATE_SUSPENDED
) {
1028 rdev
->pm
.dynpm_state
= DYNPM_STATE_ACTIVE
;
1029 schedule_delayed_work(&rdev
->pm
.dynpm_idle_work
,
1030 msecs_to_jiffies(RADEON_IDLE_LOOP_MS
));
1032 mutex_unlock(&rdev
->pm
.mutex
);
1033 radeon_pm_compute_clocks(rdev
);
1036 static void radeon_pm_resume_dpm(struct radeon_device
*rdev
)
1040 /* asic init will reset to the boot state */
1041 mutex_lock(&rdev
->pm
.mutex
);
1042 rdev
->pm
.dpm
.current_ps
= rdev
->pm
.dpm
.requested_ps
= rdev
->pm
.dpm
.boot_ps
;
1043 radeon_dpm_setup_asic(rdev
);
1044 ret
= radeon_dpm_enable(rdev
);
1045 mutex_unlock(&rdev
->pm
.mutex
);
1047 DRM_ERROR("radeon: dpm resume failed\n");
1048 if ((rdev
->family
>= CHIP_BARTS
) &&
1049 (rdev
->family
<= CHIP_HAINAN
) &&
1051 if (rdev
->pm
.default_vddc
)
1052 radeon_atom_set_voltage(rdev
, rdev
->pm
.default_vddc
,
1053 SET_VOLTAGE_TYPE_ASIC_VDDC
);
1054 if (rdev
->pm
.default_vddci
)
1055 radeon_atom_set_voltage(rdev
, rdev
->pm
.default_vddci
,
1056 SET_VOLTAGE_TYPE_ASIC_VDDCI
);
1057 if (rdev
->pm
.default_sclk
)
1058 radeon_set_engine_clock(rdev
, rdev
->pm
.default_sclk
);
1059 if (rdev
->pm
.default_mclk
)
1060 radeon_set_memory_clock(rdev
, rdev
->pm
.default_mclk
);
1063 rdev
->pm
.dpm_enabled
= true;
1064 radeon_pm_compute_clocks(rdev
);
1068 void radeon_pm_resume(struct radeon_device
*rdev
)
1070 if (rdev
->pm
.pm_method
== PM_METHOD_DPM
)
1071 radeon_pm_resume_dpm(rdev
);
1073 radeon_pm_resume_old(rdev
);
1076 static int radeon_pm_init_old(struct radeon_device
*rdev
)
1080 rdev
->pm
.profile
= PM_PROFILE_DEFAULT
;
1081 rdev
->pm
.dynpm_state
= DYNPM_STATE_DISABLED
;
1082 rdev
->pm
.dynpm_planned_action
= DYNPM_ACTION_NONE
;
1083 rdev
->pm
.dynpm_can_upclock
= true;
1084 rdev
->pm
.dynpm_can_downclock
= true;
1085 rdev
->pm
.default_sclk
= rdev
->clock
.default_sclk
;
1086 rdev
->pm
.default_mclk
= rdev
->clock
.default_mclk
;
1087 rdev
->pm
.current_sclk
= rdev
->clock
.default_sclk
;
1088 rdev
->pm
.current_mclk
= rdev
->clock
.default_mclk
;
1089 rdev
->pm
.int_thermal_type
= THERMAL_TYPE_NONE
;
1092 if (rdev
->is_atom_bios
)
1093 radeon_atombios_get_power_modes(rdev
);
1095 radeon_combios_get_power_modes(rdev
);
1096 radeon_pm_print_states(rdev
);
1097 radeon_pm_init_profile(rdev
);
1098 /* set up the default clocks if the MC ucode is loaded */
1099 if ((rdev
->family
>= CHIP_BARTS
) &&
1100 (rdev
->family
<= CHIP_HAINAN
) &&
1102 if (rdev
->pm
.default_vddc
)
1103 radeon_atom_set_voltage(rdev
, rdev
->pm
.default_vddc
,
1104 SET_VOLTAGE_TYPE_ASIC_VDDC
);
1105 if (rdev
->pm
.default_vddci
)
1106 radeon_atom_set_voltage(rdev
, rdev
->pm
.default_vddci
,
1107 SET_VOLTAGE_TYPE_ASIC_VDDCI
);
1108 if (rdev
->pm
.default_sclk
)
1109 radeon_set_engine_clock(rdev
, rdev
->pm
.default_sclk
);
1110 if (rdev
->pm
.default_mclk
)
1111 radeon_set_memory_clock(rdev
, rdev
->pm
.default_mclk
);
1115 /* set up the internal thermal sensor if applicable */
1116 ret
= radeon_hwmon_init(rdev
);
1120 INIT_DELAYED_WORK(&rdev
->pm
.dynpm_idle_work
, radeon_dynpm_idle_work_handler
);
1122 if (rdev
->pm
.num_power_states
> 1) {
1123 /* where's the best place to put these? */
1124 ret
= device_create_file(rdev
->dev
, &dev_attr_power_profile
);
1126 DRM_ERROR("failed to create device file for power profile\n");
1127 ret
= device_create_file(rdev
->dev
, &dev_attr_power_method
);
1129 DRM_ERROR("failed to create device file for power method\n");
1131 if (radeon_debugfs_pm_init(rdev
)) {
1132 DRM_ERROR("Failed to register debugfs file for PM!\n");
1135 DRM_INFO("radeon: power management initialized\n");
1141 static void radeon_dpm_print_power_states(struct radeon_device
*rdev
)
1145 for (i
= 0; i
< rdev
->pm
.dpm
.num_ps
; i
++) {
1146 printk("== power state %d ==\n", i
);
1147 radeon_dpm_print_power_state(rdev
, &rdev
->pm
.dpm
.ps
[i
]);
1151 static int radeon_pm_init_dpm(struct radeon_device
*rdev
)
1155 /* default to balanced state */
1156 rdev
->pm
.dpm
.state
= POWER_STATE_TYPE_BALANCED
;
1157 rdev
->pm
.dpm
.user_state
= POWER_STATE_TYPE_BALANCED
;
1158 rdev
->pm
.dpm
.forced_level
= RADEON_DPM_FORCED_LEVEL_AUTO
;
1159 rdev
->pm
.default_sclk
= rdev
->clock
.default_sclk
;
1160 rdev
->pm
.default_mclk
= rdev
->clock
.default_mclk
;
1161 rdev
->pm
.current_sclk
= rdev
->clock
.default_sclk
;
1162 rdev
->pm
.current_mclk
= rdev
->clock
.default_mclk
;
1163 rdev
->pm
.int_thermal_type
= THERMAL_TYPE_NONE
;
1165 if (rdev
->bios
&& rdev
->is_atom_bios
)
1166 radeon_atombios_get_power_modes(rdev
);
1170 /* set up the internal thermal sensor if applicable */
1171 ret
= radeon_hwmon_init(rdev
);
1175 INIT_WORK(&rdev
->pm
.dpm
.thermal
.work
, radeon_dpm_thermal_work_handler
);
1176 mutex_lock(&rdev
->pm
.mutex
);
1177 radeon_dpm_init(rdev
);
1178 rdev
->pm
.dpm
.current_ps
= rdev
->pm
.dpm
.requested_ps
= rdev
->pm
.dpm
.boot_ps
;
1179 radeon_dpm_print_power_states(rdev
);
1180 radeon_dpm_setup_asic(rdev
);
1181 ret
= radeon_dpm_enable(rdev
);
1182 mutex_unlock(&rdev
->pm
.mutex
);
1184 rdev
->pm
.dpm_enabled
= false;
1185 if ((rdev
->family
>= CHIP_BARTS
) &&
1186 (rdev
->family
<= CHIP_HAINAN
) &&
1188 if (rdev
->pm
.default_vddc
)
1189 radeon_atom_set_voltage(rdev
, rdev
->pm
.default_vddc
,
1190 SET_VOLTAGE_TYPE_ASIC_VDDC
);
1191 if (rdev
->pm
.default_vddci
)
1192 radeon_atom_set_voltage(rdev
, rdev
->pm
.default_vddci
,
1193 SET_VOLTAGE_TYPE_ASIC_VDDCI
);
1194 if (rdev
->pm
.default_sclk
)
1195 radeon_set_engine_clock(rdev
, rdev
->pm
.default_sclk
);
1196 if (rdev
->pm
.default_mclk
)
1197 radeon_set_memory_clock(rdev
, rdev
->pm
.default_mclk
);
1199 DRM_ERROR("radeon: dpm initialization failed\n");
1202 rdev
->pm
.dpm_enabled
= true;
1203 radeon_pm_compute_clocks(rdev
);
1205 if (rdev
->pm
.num_power_states
> 1) {
1206 ret
= device_create_file(rdev
->dev
, &dev_attr_power_dpm_state
);
1208 DRM_ERROR("failed to create device file for dpm state\n");
1209 ret
= device_create_file(rdev
->dev
, &dev_attr_power_dpm_force_performance_level
);
1211 DRM_ERROR("failed to create device file for dpm state\n");
1212 /* XXX: these are noops for dpm but are here for backwards compat */
1213 ret
= device_create_file(rdev
->dev
, &dev_attr_power_profile
);
1215 DRM_ERROR("failed to create device file for power profile\n");
1216 ret
= device_create_file(rdev
->dev
, &dev_attr_power_method
);
1218 DRM_ERROR("failed to create device file for power method\n");
1220 if (radeon_debugfs_pm_init(rdev
)) {
1221 DRM_ERROR("Failed to register debugfs file for dpm!\n");
1224 DRM_INFO("radeon: dpm initialized\n");
1230 int radeon_pm_init(struct radeon_device
*rdev
)
1232 /* enable dpm on rv6xx+ */
1233 switch (rdev
->family
) {
1266 /* DPM requires the RLC, RV770+ dGPU requires SMC */
1268 rdev
->pm
.pm_method
= PM_METHOD_PROFILE
;
1269 else if ((rdev
->family
>= CHIP_RV770
) &&
1270 (!(rdev
->flags
& RADEON_IS_IGP
)) &&
1272 rdev
->pm
.pm_method
= PM_METHOD_PROFILE
;
1273 else if (radeon_dpm
== 1)
1274 rdev
->pm
.pm_method
= PM_METHOD_DPM
;
1276 rdev
->pm
.pm_method
= PM_METHOD_PROFILE
;
1279 /* default to profile method */
1280 rdev
->pm
.pm_method
= PM_METHOD_PROFILE
;
1284 if (rdev
->pm
.pm_method
== PM_METHOD_DPM
)
1285 return radeon_pm_init_dpm(rdev
);
1287 return radeon_pm_init_old(rdev
);
1290 static void radeon_pm_fini_old(struct radeon_device
*rdev
)
1292 if (rdev
->pm
.num_power_states
> 1) {
1293 mutex_lock(&rdev
->pm
.mutex
);
1294 if (rdev
->pm
.pm_method
== PM_METHOD_PROFILE
) {
1295 rdev
->pm
.profile
= PM_PROFILE_DEFAULT
;
1296 radeon_pm_update_profile(rdev
);
1297 radeon_pm_set_clocks(rdev
);
1298 } else if (rdev
->pm
.pm_method
== PM_METHOD_DYNPM
) {
1299 /* reset default clocks */
1300 rdev
->pm
.dynpm_state
= DYNPM_STATE_DISABLED
;
1301 rdev
->pm
.dynpm_planned_action
= DYNPM_ACTION_DEFAULT
;
1302 radeon_pm_set_clocks(rdev
);
1304 mutex_unlock(&rdev
->pm
.mutex
);
1306 cancel_delayed_work_sync(&rdev
->pm
.dynpm_idle_work
);
1308 device_remove_file(rdev
->dev
, &dev_attr_power_profile
);
1309 device_remove_file(rdev
->dev
, &dev_attr_power_method
);
1312 if (rdev
->pm
.power_state
)
1313 kfree(rdev
->pm
.power_state
);
1315 radeon_hwmon_fini(rdev
);
1318 static void radeon_pm_fini_dpm(struct radeon_device
*rdev
)
1320 if (rdev
->pm
.num_power_states
> 1) {
1321 mutex_lock(&rdev
->pm
.mutex
);
1322 radeon_dpm_disable(rdev
);
1323 mutex_unlock(&rdev
->pm
.mutex
);
1325 device_remove_file(rdev
->dev
, &dev_attr_power_dpm_state
);
1326 device_remove_file(rdev
->dev
, &dev_attr_power_dpm_force_performance_level
);
1327 /* XXX backwards compat */
1328 device_remove_file(rdev
->dev
, &dev_attr_power_profile
);
1329 device_remove_file(rdev
->dev
, &dev_attr_power_method
);
1331 radeon_dpm_fini(rdev
);
1333 if (rdev
->pm
.power_state
)
1334 kfree(rdev
->pm
.power_state
);
1336 radeon_hwmon_fini(rdev
);
1339 void radeon_pm_fini(struct radeon_device
*rdev
)
1341 if (rdev
->pm
.pm_method
== PM_METHOD_DPM
)
1342 radeon_pm_fini_dpm(rdev
);
1344 radeon_pm_fini_old(rdev
);
1347 static void radeon_pm_compute_clocks_old(struct radeon_device
*rdev
)
1349 struct drm_device
*ddev
= rdev
->ddev
;
1350 struct drm_crtc
*crtc
;
1351 struct radeon_crtc
*radeon_crtc
;
1353 if (rdev
->pm
.num_power_states
< 2)
1356 mutex_lock(&rdev
->pm
.mutex
);
1358 rdev
->pm
.active_crtcs
= 0;
1359 rdev
->pm
.active_crtc_count
= 0;
1360 list_for_each_entry(crtc
,
1361 &ddev
->mode_config
.crtc_list
, head
) {
1362 radeon_crtc
= to_radeon_crtc(crtc
);
1363 if (radeon_crtc
->enabled
) {
1364 rdev
->pm
.active_crtcs
|= (1 << radeon_crtc
->crtc_id
);
1365 rdev
->pm
.active_crtc_count
++;
1369 if (rdev
->pm
.pm_method
== PM_METHOD_PROFILE
) {
1370 radeon_pm_update_profile(rdev
);
1371 radeon_pm_set_clocks(rdev
);
1372 } else if (rdev
->pm
.pm_method
== PM_METHOD_DYNPM
) {
1373 if (rdev
->pm
.dynpm_state
!= DYNPM_STATE_DISABLED
) {
1374 if (rdev
->pm
.active_crtc_count
> 1) {
1375 if (rdev
->pm
.dynpm_state
== DYNPM_STATE_ACTIVE
) {
1376 cancel_delayed_work(&rdev
->pm
.dynpm_idle_work
);
1378 rdev
->pm
.dynpm_state
= DYNPM_STATE_PAUSED
;
1379 rdev
->pm
.dynpm_planned_action
= DYNPM_ACTION_DEFAULT
;
1380 radeon_pm_get_dynpm_state(rdev
);
1381 radeon_pm_set_clocks(rdev
);
1383 DRM_DEBUG_DRIVER("radeon: dynamic power management deactivated\n");
1385 } else if (rdev
->pm
.active_crtc_count
== 1) {
1386 /* TODO: Increase clocks if needed for current mode */
1388 if (rdev
->pm
.dynpm_state
== DYNPM_STATE_MINIMUM
) {
1389 rdev
->pm
.dynpm_state
= DYNPM_STATE_ACTIVE
;
1390 rdev
->pm
.dynpm_planned_action
= DYNPM_ACTION_UPCLOCK
;
1391 radeon_pm_get_dynpm_state(rdev
);
1392 radeon_pm_set_clocks(rdev
);
1394 schedule_delayed_work(&rdev
->pm
.dynpm_idle_work
,
1395 msecs_to_jiffies(RADEON_IDLE_LOOP_MS
));
1396 } else if (rdev
->pm
.dynpm_state
== DYNPM_STATE_PAUSED
) {
1397 rdev
->pm
.dynpm_state
= DYNPM_STATE_ACTIVE
;
1398 schedule_delayed_work(&rdev
->pm
.dynpm_idle_work
,
1399 msecs_to_jiffies(RADEON_IDLE_LOOP_MS
));
1400 DRM_DEBUG_DRIVER("radeon: dynamic power management activated\n");
1402 } else { /* count == 0 */
1403 if (rdev
->pm
.dynpm_state
!= DYNPM_STATE_MINIMUM
) {
1404 cancel_delayed_work(&rdev
->pm
.dynpm_idle_work
);
1406 rdev
->pm
.dynpm_state
= DYNPM_STATE_MINIMUM
;
1407 rdev
->pm
.dynpm_planned_action
= DYNPM_ACTION_MINIMUM
;
1408 radeon_pm_get_dynpm_state(rdev
);
1409 radeon_pm_set_clocks(rdev
);
1415 mutex_unlock(&rdev
->pm
.mutex
);
1418 static void radeon_pm_compute_clocks_dpm(struct radeon_device
*rdev
)
1420 struct drm_device
*ddev
= rdev
->ddev
;
1421 struct drm_crtc
*crtc
;
1422 struct radeon_crtc
*radeon_crtc
;
1424 mutex_lock(&rdev
->pm
.mutex
);
1426 /* update active crtc counts */
1427 rdev
->pm
.dpm
.new_active_crtcs
= 0;
1428 rdev
->pm
.dpm
.new_active_crtc_count
= 0;
1429 list_for_each_entry(crtc
,
1430 &ddev
->mode_config
.crtc_list
, head
) {
1431 radeon_crtc
= to_radeon_crtc(crtc
);
1432 if (crtc
->enabled
) {
1433 rdev
->pm
.dpm
.new_active_crtcs
|= (1 << radeon_crtc
->crtc_id
);
1434 rdev
->pm
.dpm
.new_active_crtc_count
++;
1438 /* update battery/ac status */
1439 if (power_supply_is_system_supplied() > 0)
1440 rdev
->pm
.dpm
.ac_power
= true;
1442 rdev
->pm
.dpm
.ac_power
= false;
1444 radeon_dpm_change_power_state_locked(rdev
);
1446 mutex_unlock(&rdev
->pm
.mutex
);
1450 void radeon_pm_compute_clocks(struct radeon_device
*rdev
)
1452 if (rdev
->pm
.pm_method
== PM_METHOD_DPM
)
1453 radeon_pm_compute_clocks_dpm(rdev
);
1455 radeon_pm_compute_clocks_old(rdev
);
1458 static bool radeon_pm_in_vbl(struct radeon_device
*rdev
)
1460 int crtc
, vpos
, hpos
, vbl_status
;
1463 /* Iterate over all active crtc's. All crtc's must be in vblank,
1464 * otherwise return in_vbl == false.
1466 for (crtc
= 0; (crtc
< rdev
->num_crtc
) && in_vbl
; crtc
++) {
1467 if (rdev
->pm
.active_crtcs
& (1 << crtc
)) {
1468 vbl_status
= radeon_get_crtc_scanoutpos(rdev
->ddev
, crtc
, &vpos
, &hpos
);
1469 if ((vbl_status
& DRM_SCANOUTPOS_VALID
) &&
1470 !(vbl_status
& DRM_SCANOUTPOS_INVBL
))
1478 static bool radeon_pm_debug_check_in_vbl(struct radeon_device
*rdev
, bool finish
)
1481 bool in_vbl
= radeon_pm_in_vbl(rdev
);
1483 if (in_vbl
== false)
1484 DRM_DEBUG_DRIVER("not in vbl for pm change %08x at %s\n", stat_crtc
,
1485 finish
? "exit" : "entry");
1489 static void radeon_dynpm_idle_work_handler(struct work_struct
*work
)
1491 struct radeon_device
*rdev
;
1493 rdev
= container_of(work
, struct radeon_device
,
1494 pm
.dynpm_idle_work
.work
);
1496 resched
= ttm_bo_lock_delayed_workqueue(&rdev
->mman
.bdev
);
1497 mutex_lock(&rdev
->pm
.mutex
);
1498 if (rdev
->pm
.dynpm_state
== DYNPM_STATE_ACTIVE
) {
1499 int not_processed
= 0;
1502 for (i
= 0; i
< RADEON_NUM_RINGS
; ++i
) {
1503 struct radeon_ring
*ring
= &rdev
->ring
[i
];
1506 not_processed
+= radeon_fence_count_emitted(rdev
, i
);
1507 if (not_processed
>= 3)
1512 if (not_processed
>= 3) { /* should upclock */
1513 if (rdev
->pm
.dynpm_planned_action
== DYNPM_ACTION_DOWNCLOCK
) {
1514 rdev
->pm
.dynpm_planned_action
= DYNPM_ACTION_NONE
;
1515 } else if (rdev
->pm
.dynpm_planned_action
== DYNPM_ACTION_NONE
&&
1516 rdev
->pm
.dynpm_can_upclock
) {
1517 rdev
->pm
.dynpm_planned_action
=
1518 DYNPM_ACTION_UPCLOCK
;
1519 rdev
->pm
.dynpm_action_timeout
= jiffies
+
1520 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS
);
1522 } else if (not_processed
== 0) { /* should downclock */
1523 if (rdev
->pm
.dynpm_planned_action
== DYNPM_ACTION_UPCLOCK
) {
1524 rdev
->pm
.dynpm_planned_action
= DYNPM_ACTION_NONE
;
1525 } else if (rdev
->pm
.dynpm_planned_action
== DYNPM_ACTION_NONE
&&
1526 rdev
->pm
.dynpm_can_downclock
) {
1527 rdev
->pm
.dynpm_planned_action
=
1528 DYNPM_ACTION_DOWNCLOCK
;
1529 rdev
->pm
.dynpm_action_timeout
= jiffies
+
1530 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS
);
1534 /* Note, radeon_pm_set_clocks is called with static_switch set
1535 * to false since we want to wait for vbl to avoid flicker.
1537 if (rdev
->pm
.dynpm_planned_action
!= DYNPM_ACTION_NONE
&&
1538 jiffies
> rdev
->pm
.dynpm_action_timeout
) {
1539 radeon_pm_get_dynpm_state(rdev
);
1540 radeon_pm_set_clocks(rdev
);
1543 schedule_delayed_work(&rdev
->pm
.dynpm_idle_work
,
1544 msecs_to_jiffies(RADEON_IDLE_LOOP_MS
));
1546 mutex_unlock(&rdev
->pm
.mutex
);
1547 ttm_bo_unlock_delayed_workqueue(&rdev
->mman
.bdev
, resched
);
1553 #if defined(CONFIG_DEBUG_FS)
1555 static int radeon_debugfs_pm_info(struct seq_file
*m
, void *data
)
1557 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
1558 struct drm_device
*dev
= node
->minor
->dev
;
1559 struct radeon_device
*rdev
= dev
->dev_private
;
1561 if (rdev
->pm
.dpm_enabled
) {
1562 mutex_lock(&rdev
->pm
.mutex
);
1563 if (rdev
->asic
->dpm
.debugfs_print_current_performance_level
)
1564 radeon_dpm_debugfs_print_current_performance_level(rdev
, m
);
1566 seq_printf(m
, "Debugfs support not implemented for this asic\n");
1567 mutex_unlock(&rdev
->pm
.mutex
);
1569 seq_printf(m
, "default engine clock: %u0 kHz\n", rdev
->pm
.default_sclk
);
1570 /* radeon_get_engine_clock is not reliable on APUs so just print the current clock */
1571 if ((rdev
->family
>= CHIP_PALM
) && (rdev
->flags
& RADEON_IS_IGP
))
1572 seq_printf(m
, "current engine clock: %u0 kHz\n", rdev
->pm
.current_sclk
);
1574 seq_printf(m
, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev
));
1575 seq_printf(m
, "default memory clock: %u0 kHz\n", rdev
->pm
.default_mclk
);
1576 if (rdev
->asic
->pm
.get_memory_clock
)
1577 seq_printf(m
, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev
));
1578 if (rdev
->pm
.current_vddc
)
1579 seq_printf(m
, "voltage: %u mV\n", rdev
->pm
.current_vddc
);
1580 if (rdev
->asic
->pm
.get_pcie_lanes
)
1581 seq_printf(m
, "PCIE lanes: %d\n", radeon_get_pcie_lanes(rdev
));
1587 static struct drm_info_list radeon_pm_info_list
[] = {
1588 {"radeon_pm_info", radeon_debugfs_pm_info
, 0, NULL
},
1592 static int radeon_debugfs_pm_init(struct radeon_device
*rdev
)
1594 #if defined(CONFIG_DEBUG_FS)
1595 return radeon_debugfs_add_files(rdev
, radeon_pm_info_list
, ARRAY_SIZE(radeon_pm_info_list
));