2 * Permission is hereby granted, free of charge, to any person obtaining a
3 * copy of this software and associated documentation files (the "Software"),
4 * to deal in the Software without restriction, including without limitation
5 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
6 * and/or sell copies of the Software, and to permit persons to whom the
7 * Software is furnished to do so, subject to the following conditions:
9 * The above copyright notice and this permission notice shall be included in
10 * all copies or substantial portions of the Software.
12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
13 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
14 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
15 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
16 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
17 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
18 * OTHER DEALINGS IN THE SOFTWARE.
20 * Authors: Rafał Miłecki <zajec5@gmail.com>
21 * Alex Deucher <alexdeucher@gmail.com>
27 #include <linux/power_supply.h>
28 #include <linux/hwmon.h>
29 #include <linux/hwmon-sysfs.h>
31 #define RADEON_IDLE_LOOP_MS 100
32 #define RADEON_RECLOCK_DELAY_MS 200
33 #define RADEON_WAIT_VBLANK_TIMEOUT 200
35 static const char *radeon_pm_state_type_name
[5] = {
43 static void radeon_dynpm_idle_work_handler(struct work_struct
*work
);
44 static int radeon_debugfs_pm_init(struct radeon_device
*rdev
);
45 static bool radeon_pm_in_vbl(struct radeon_device
*rdev
);
46 static bool radeon_pm_debug_check_in_vbl(struct radeon_device
*rdev
, bool finish
);
47 static void radeon_pm_update_profile(struct radeon_device
*rdev
);
48 static void radeon_pm_set_clocks(struct radeon_device
*rdev
);
50 int radeon_pm_get_type_index(struct radeon_device
*rdev
,
51 enum radeon_pm_state_type ps_type
,
55 int found_instance
= -1;
57 for (i
= 0; i
< rdev
->pm
.num_power_states
; i
++) {
58 if (rdev
->pm
.power_state
[i
].type
== ps_type
) {
60 if (found_instance
== instance
)
64 /* return default if no match */
65 return rdev
->pm
.default_power_state_index
;
68 void radeon_pm_acpi_event_handler(struct radeon_device
*rdev
)
70 if (rdev
->pm
.pm_method
== PM_METHOD_PROFILE
) {
71 if (rdev
->pm
.profile
== PM_PROFILE_AUTO
) {
72 mutex_lock(&rdev
->pm
.mutex
);
73 radeon_pm_update_profile(rdev
);
74 radeon_pm_set_clocks(rdev
);
75 mutex_unlock(&rdev
->pm
.mutex
);
80 static void radeon_pm_update_profile(struct radeon_device
*rdev
)
82 switch (rdev
->pm
.profile
) {
83 case PM_PROFILE_DEFAULT
:
84 rdev
->pm
.profile_index
= PM_PROFILE_DEFAULT_IDX
;
87 if (power_supply_is_system_supplied() > 0) {
88 if (rdev
->pm
.active_crtc_count
> 1)
89 rdev
->pm
.profile_index
= PM_PROFILE_HIGH_MH_IDX
;
91 rdev
->pm
.profile_index
= PM_PROFILE_HIGH_SH_IDX
;
93 if (rdev
->pm
.active_crtc_count
> 1)
94 rdev
->pm
.profile_index
= PM_PROFILE_MID_MH_IDX
;
96 rdev
->pm
.profile_index
= PM_PROFILE_MID_SH_IDX
;
100 if (rdev
->pm
.active_crtc_count
> 1)
101 rdev
->pm
.profile_index
= PM_PROFILE_LOW_MH_IDX
;
103 rdev
->pm
.profile_index
= PM_PROFILE_LOW_SH_IDX
;
106 if (rdev
->pm
.active_crtc_count
> 1)
107 rdev
->pm
.profile_index
= PM_PROFILE_MID_MH_IDX
;
109 rdev
->pm
.profile_index
= PM_PROFILE_MID_SH_IDX
;
111 case PM_PROFILE_HIGH
:
112 if (rdev
->pm
.active_crtc_count
> 1)
113 rdev
->pm
.profile_index
= PM_PROFILE_HIGH_MH_IDX
;
115 rdev
->pm
.profile_index
= PM_PROFILE_HIGH_SH_IDX
;
119 if (rdev
->pm
.active_crtc_count
== 0) {
120 rdev
->pm
.requested_power_state_index
=
121 rdev
->pm
.profiles
[rdev
->pm
.profile_index
].dpms_off_ps_idx
;
122 rdev
->pm
.requested_clock_mode_index
=
123 rdev
->pm
.profiles
[rdev
->pm
.profile_index
].dpms_off_cm_idx
;
125 rdev
->pm
.requested_power_state_index
=
126 rdev
->pm
.profiles
[rdev
->pm
.profile_index
].dpms_on_ps_idx
;
127 rdev
->pm
.requested_clock_mode_index
=
128 rdev
->pm
.profiles
[rdev
->pm
.profile_index
].dpms_on_cm_idx
;
132 static void radeon_unmap_vram_bos(struct radeon_device
*rdev
)
134 struct radeon_bo
*bo
, *n
;
136 if (list_empty(&rdev
->gem
.objects
))
139 list_for_each_entry_safe(bo
, n
, &rdev
->gem
.objects
, list
) {
140 if (bo
->tbo
.mem
.mem_type
== TTM_PL_VRAM
)
141 ttm_bo_unmap_virtual(&bo
->tbo
);
145 static void radeon_sync_with_vblank(struct radeon_device
*rdev
)
147 if (rdev
->pm
.active_crtcs
) {
148 rdev
->pm
.vblank_sync
= false;
150 rdev
->irq
.vblank_queue
, rdev
->pm
.vblank_sync
,
151 msecs_to_jiffies(RADEON_WAIT_VBLANK_TIMEOUT
));
155 static void radeon_set_power_state(struct radeon_device
*rdev
)
158 bool misc_after
= false;
160 if ((rdev
->pm
.requested_clock_mode_index
== rdev
->pm
.current_clock_mode_index
) &&
161 (rdev
->pm
.requested_power_state_index
== rdev
->pm
.current_power_state_index
))
164 if (radeon_gui_idle(rdev
)) {
165 sclk
= rdev
->pm
.power_state
[rdev
->pm
.requested_power_state_index
].
166 clock_info
[rdev
->pm
.requested_clock_mode_index
].sclk
;
167 if (sclk
> rdev
->pm
.default_sclk
)
168 sclk
= rdev
->pm
.default_sclk
;
170 /* starting with BTC, there is one state that is used for both
171 * MH and SH. Difference is that we always use the high clock index for
174 if ((rdev
->pm
.pm_method
== PM_METHOD_PROFILE
) &&
175 (rdev
->family
>= CHIP_BARTS
) &&
176 rdev
->pm
.active_crtc_count
&&
177 ((rdev
->pm
.profile_index
== PM_PROFILE_MID_MH_IDX
) ||
178 (rdev
->pm
.profile_index
== PM_PROFILE_LOW_MH_IDX
)))
179 mclk
= rdev
->pm
.power_state
[rdev
->pm
.requested_power_state_index
].
180 clock_info
[rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_on_cm_idx
].mclk
;
182 mclk
= rdev
->pm
.power_state
[rdev
->pm
.requested_power_state_index
].
183 clock_info
[rdev
->pm
.requested_clock_mode_index
].mclk
;
185 if (mclk
> rdev
->pm
.default_mclk
)
186 mclk
= rdev
->pm
.default_mclk
;
188 /* upvolt before raising clocks, downvolt after lowering clocks */
189 if (sclk
< rdev
->pm
.current_sclk
)
192 radeon_sync_with_vblank(rdev
);
194 if (rdev
->pm
.pm_method
== PM_METHOD_DYNPM
) {
195 if (!radeon_pm_in_vbl(rdev
))
199 radeon_pm_prepare(rdev
);
202 /* voltage, pcie lanes, etc.*/
203 radeon_pm_misc(rdev
);
205 /* set engine clock */
206 if (sclk
!= rdev
->pm
.current_sclk
) {
207 radeon_pm_debug_check_in_vbl(rdev
, false);
208 radeon_set_engine_clock(rdev
, sclk
);
209 radeon_pm_debug_check_in_vbl(rdev
, true);
210 rdev
->pm
.current_sclk
= sclk
;
211 DRM_DEBUG_DRIVER("Setting: e: %d\n", sclk
);
214 /* set memory clock */
215 if (rdev
->asic
->pm
.set_memory_clock
&& (mclk
!= rdev
->pm
.current_mclk
)) {
216 radeon_pm_debug_check_in_vbl(rdev
, false);
217 radeon_set_memory_clock(rdev
, mclk
);
218 radeon_pm_debug_check_in_vbl(rdev
, true);
219 rdev
->pm
.current_mclk
= mclk
;
220 DRM_DEBUG_DRIVER("Setting: m: %d\n", mclk
);
224 /* voltage, pcie lanes, etc.*/
225 radeon_pm_misc(rdev
);
227 radeon_pm_finish(rdev
);
229 rdev
->pm
.current_power_state_index
= rdev
->pm
.requested_power_state_index
;
230 rdev
->pm
.current_clock_mode_index
= rdev
->pm
.requested_clock_mode_index
;
232 DRM_DEBUG_DRIVER("pm: GUI not idle!!!\n");
235 static void radeon_pm_set_clocks(struct radeon_device
*rdev
)
239 /* no need to take locks, etc. if nothing's going to change */
240 if ((rdev
->pm
.requested_clock_mode_index
== rdev
->pm
.current_clock_mode_index
) &&
241 (rdev
->pm
.requested_power_state_index
== rdev
->pm
.current_power_state_index
))
244 mutex_lock(&rdev
->ddev
->struct_mutex
);
245 down_write(&rdev
->pm
.mclk_lock
);
246 mutex_lock(&rdev
->ring_lock
);
248 /* wait for the rings to drain */
249 for (i
= 0; i
< RADEON_NUM_RINGS
; i
++) {
250 struct radeon_ring
*ring
= &rdev
->ring
[i
];
254 r
= radeon_fence_wait_empty_locked(rdev
, i
);
256 /* needs a GPU reset dont reset here */
257 mutex_unlock(&rdev
->ring_lock
);
258 up_write(&rdev
->pm
.mclk_lock
);
259 mutex_unlock(&rdev
->ddev
->struct_mutex
);
264 radeon_unmap_vram_bos(rdev
);
266 if (rdev
->irq
.installed
) {
267 for (i
= 0; i
< rdev
->num_crtc
; i
++) {
268 if (rdev
->pm
.active_crtcs
& (1 << i
)) {
269 rdev
->pm
.req_vblank
|= (1 << i
);
270 drm_vblank_get(rdev
->ddev
, i
);
275 radeon_set_power_state(rdev
);
277 if (rdev
->irq
.installed
) {
278 for (i
= 0; i
< rdev
->num_crtc
; i
++) {
279 if (rdev
->pm
.req_vblank
& (1 << i
)) {
280 rdev
->pm
.req_vblank
&= ~(1 << i
);
281 drm_vblank_put(rdev
->ddev
, i
);
286 /* update display watermarks based on new power state */
287 radeon_update_bandwidth_info(rdev
);
288 if (rdev
->pm
.active_crtc_count
)
289 radeon_bandwidth_update(rdev
);
291 rdev
->pm
.dynpm_planned_action
= DYNPM_ACTION_NONE
;
293 mutex_unlock(&rdev
->ring_lock
);
294 up_write(&rdev
->pm
.mclk_lock
);
295 mutex_unlock(&rdev
->ddev
->struct_mutex
);
298 static void radeon_pm_print_states(struct radeon_device
*rdev
)
301 struct radeon_power_state
*power_state
;
302 struct radeon_pm_clock_info
*clock_info
;
304 DRM_DEBUG_DRIVER("%d Power State(s)\n", rdev
->pm
.num_power_states
);
305 for (i
= 0; i
< rdev
->pm
.num_power_states
; i
++) {
306 power_state
= &rdev
->pm
.power_state
[i
];
307 DRM_DEBUG_DRIVER("State %d: %s\n", i
,
308 radeon_pm_state_type_name
[power_state
->type
]);
309 if (i
== rdev
->pm
.default_power_state_index
)
310 DRM_DEBUG_DRIVER("\tDefault");
311 if ((rdev
->flags
& RADEON_IS_PCIE
) && !(rdev
->flags
& RADEON_IS_IGP
))
312 DRM_DEBUG_DRIVER("\t%d PCIE Lanes\n", power_state
->pcie_lanes
);
313 if (power_state
->flags
& RADEON_PM_STATE_SINGLE_DISPLAY_ONLY
)
314 DRM_DEBUG_DRIVER("\tSingle display only\n");
315 DRM_DEBUG_DRIVER("\t%d Clock Mode(s)\n", power_state
->num_clock_modes
);
316 for (j
= 0; j
< power_state
->num_clock_modes
; j
++) {
317 clock_info
= &(power_state
->clock_info
[j
]);
318 if (rdev
->flags
& RADEON_IS_IGP
)
319 DRM_DEBUG_DRIVER("\t\t%d e: %d\n",
321 clock_info
->sclk
* 10);
323 DRM_DEBUG_DRIVER("\t\t%d e: %d\tm: %d\tv: %d\n",
325 clock_info
->sclk
* 10,
326 clock_info
->mclk
* 10,
327 clock_info
->voltage
.voltage
);
332 static ssize_t
radeon_get_pm_profile(struct device
*dev
,
333 struct device_attribute
*attr
,
336 struct drm_device
*ddev
= pci_get_drvdata(to_pci_dev(dev
));
337 struct radeon_device
*rdev
= ddev
->dev_private
;
338 int cp
= rdev
->pm
.profile
;
340 return snprintf(buf
, PAGE_SIZE
, "%s\n",
341 (cp
== PM_PROFILE_AUTO
) ? "auto" :
342 (cp
== PM_PROFILE_LOW
) ? "low" :
343 (cp
== PM_PROFILE_MID
) ? "mid" :
344 (cp
== PM_PROFILE_HIGH
) ? "high" : "default");
347 static ssize_t
radeon_set_pm_profile(struct device
*dev
,
348 struct device_attribute
*attr
,
352 struct drm_device
*ddev
= pci_get_drvdata(to_pci_dev(dev
));
353 struct radeon_device
*rdev
= ddev
->dev_private
;
355 mutex_lock(&rdev
->pm
.mutex
);
356 if (rdev
->pm
.pm_method
== PM_METHOD_PROFILE
) {
357 if (strncmp("default", buf
, strlen("default")) == 0)
358 rdev
->pm
.profile
= PM_PROFILE_DEFAULT
;
359 else if (strncmp("auto", buf
, strlen("auto")) == 0)
360 rdev
->pm
.profile
= PM_PROFILE_AUTO
;
361 else if (strncmp("low", buf
, strlen("low")) == 0)
362 rdev
->pm
.profile
= PM_PROFILE_LOW
;
363 else if (strncmp("mid", buf
, strlen("mid")) == 0)
364 rdev
->pm
.profile
= PM_PROFILE_MID
;
365 else if (strncmp("high", buf
, strlen("high")) == 0)
366 rdev
->pm
.profile
= PM_PROFILE_HIGH
;
371 radeon_pm_update_profile(rdev
);
372 radeon_pm_set_clocks(rdev
);
377 mutex_unlock(&rdev
->pm
.mutex
);
382 static ssize_t
radeon_get_pm_method(struct device
*dev
,
383 struct device_attribute
*attr
,
386 struct drm_device
*ddev
= pci_get_drvdata(to_pci_dev(dev
));
387 struct radeon_device
*rdev
= ddev
->dev_private
;
388 int pm
= rdev
->pm
.pm_method
;
390 return snprintf(buf
, PAGE_SIZE
, "%s\n",
391 (pm
== PM_METHOD_DYNPM
) ? "dynpm" :
392 (pm
== PM_METHOD_PROFILE
) ? "profile" : "dpm");
395 static ssize_t
radeon_set_pm_method(struct device
*dev
,
396 struct device_attribute
*attr
,
400 struct drm_device
*ddev
= pci_get_drvdata(to_pci_dev(dev
));
401 struct radeon_device
*rdev
= ddev
->dev_private
;
403 /* we don't support the legacy modes with dpm */
404 if (rdev
->pm
.pm_method
== PM_METHOD_DPM
) {
409 if (strncmp("dynpm", buf
, strlen("dynpm")) == 0) {
410 mutex_lock(&rdev
->pm
.mutex
);
411 rdev
->pm
.pm_method
= PM_METHOD_DYNPM
;
412 rdev
->pm
.dynpm_state
= DYNPM_STATE_PAUSED
;
413 rdev
->pm
.dynpm_planned_action
= DYNPM_ACTION_DEFAULT
;
414 mutex_unlock(&rdev
->pm
.mutex
);
415 } else if (strncmp("profile", buf
, strlen("profile")) == 0) {
416 mutex_lock(&rdev
->pm
.mutex
);
418 rdev
->pm
.dynpm_state
= DYNPM_STATE_DISABLED
;
419 rdev
->pm
.dynpm_planned_action
= DYNPM_ACTION_NONE
;
420 rdev
->pm
.pm_method
= PM_METHOD_PROFILE
;
421 mutex_unlock(&rdev
->pm
.mutex
);
422 cancel_delayed_work_sync(&rdev
->pm
.dynpm_idle_work
);
427 radeon_pm_compute_clocks(rdev
);
432 static ssize_t
radeon_get_dpm_state(struct device
*dev
,
433 struct device_attribute
*attr
,
436 struct drm_device
*ddev
= pci_get_drvdata(to_pci_dev(dev
));
437 struct radeon_device
*rdev
= ddev
->dev_private
;
438 enum radeon_pm_state_type pm
= rdev
->pm
.dpm
.user_state
;
440 return snprintf(buf
, PAGE_SIZE
, "%s\n",
441 (pm
== POWER_STATE_TYPE_BATTERY
) ? "battery" :
442 (pm
== POWER_STATE_TYPE_BALANCED
) ? "balanced" : "performance");
445 static ssize_t
radeon_set_dpm_state(struct device
*dev
,
446 struct device_attribute
*attr
,
450 struct drm_device
*ddev
= pci_get_drvdata(to_pci_dev(dev
));
451 struct radeon_device
*rdev
= ddev
->dev_private
;
453 mutex_lock(&rdev
->pm
.mutex
);
454 if (strncmp("battery", buf
, strlen("battery")) == 0)
455 rdev
->pm
.dpm
.user_state
= POWER_STATE_TYPE_BATTERY
;
456 else if (strncmp("balanced", buf
, strlen("balanced")) == 0)
457 rdev
->pm
.dpm
.user_state
= POWER_STATE_TYPE_BALANCED
;
458 else if (strncmp("performance", buf
, strlen("performance")) == 0)
459 rdev
->pm
.dpm
.user_state
= POWER_STATE_TYPE_PERFORMANCE
;
461 mutex_unlock(&rdev
->pm
.mutex
);
465 mutex_unlock(&rdev
->pm
.mutex
);
466 radeon_pm_compute_clocks(rdev
);
471 static DEVICE_ATTR(power_profile
, S_IRUGO
| S_IWUSR
, radeon_get_pm_profile
, radeon_set_pm_profile
);
472 static DEVICE_ATTR(power_method
, S_IRUGO
| S_IWUSR
, radeon_get_pm_method
, radeon_set_pm_method
);
473 static DEVICE_ATTR(power_dpm_state
, S_IRUGO
| S_IWUSR
, radeon_get_dpm_state
, radeon_set_dpm_state
);
475 static ssize_t
radeon_hwmon_show_temp(struct device
*dev
,
476 struct device_attribute
*attr
,
479 struct drm_device
*ddev
= pci_get_drvdata(to_pci_dev(dev
));
480 struct radeon_device
*rdev
= ddev
->dev_private
;
483 if (rdev
->asic
->pm
.get_temperature
)
484 temp
= radeon_get_temperature(rdev
);
488 return snprintf(buf
, PAGE_SIZE
, "%d\n", temp
);
491 static ssize_t
radeon_hwmon_show_name(struct device
*dev
,
492 struct device_attribute
*attr
,
495 return sprintf(buf
, "radeon\n");
498 static SENSOR_DEVICE_ATTR(temp1_input
, S_IRUGO
, radeon_hwmon_show_temp
, NULL
, 0);
499 static SENSOR_DEVICE_ATTR(name
, S_IRUGO
, radeon_hwmon_show_name
, NULL
, 0);
501 static struct attribute
*hwmon_attributes
[] = {
502 &sensor_dev_attr_temp1_input
.dev_attr
.attr
,
503 &sensor_dev_attr_name
.dev_attr
.attr
,
507 static const struct attribute_group hwmon_attrgroup
= {
508 .attrs
= hwmon_attributes
,
511 static int radeon_hwmon_init(struct radeon_device
*rdev
)
515 rdev
->pm
.int_hwmon_dev
= NULL
;
517 switch (rdev
->pm
.int_thermal_type
) {
518 case THERMAL_TYPE_RV6XX
:
519 case THERMAL_TYPE_RV770
:
520 case THERMAL_TYPE_EVERGREEN
:
521 case THERMAL_TYPE_NI
:
522 case THERMAL_TYPE_SUMO
:
523 case THERMAL_TYPE_SI
:
524 if (rdev
->asic
->pm
.get_temperature
== NULL
)
526 rdev
->pm
.int_hwmon_dev
= hwmon_device_register(rdev
->dev
);
527 if (IS_ERR(rdev
->pm
.int_hwmon_dev
)) {
528 err
= PTR_ERR(rdev
->pm
.int_hwmon_dev
);
530 "Unable to register hwmon device: %d\n", err
);
533 dev_set_drvdata(rdev
->pm
.int_hwmon_dev
, rdev
->ddev
);
534 err
= sysfs_create_group(&rdev
->pm
.int_hwmon_dev
->kobj
,
538 "Unable to create hwmon sysfs file: %d\n", err
);
539 hwmon_device_unregister(rdev
->dev
);
549 static void radeon_hwmon_fini(struct radeon_device
*rdev
)
551 if (rdev
->pm
.int_hwmon_dev
) {
552 sysfs_remove_group(&rdev
->pm
.int_hwmon_dev
->kobj
, &hwmon_attrgroup
);
553 hwmon_device_unregister(rdev
->pm
.int_hwmon_dev
);
557 static void radeon_dpm_thermal_work_handler(struct work_struct
*work
)
559 struct radeon_device
*rdev
=
560 container_of(work
, struct radeon_device
,
561 pm
.dpm
.thermal
.work
);
562 /* switch to the thermal state */
563 enum radeon_pm_state_type dpm_state
= POWER_STATE_TYPE_INTERNAL_THERMAL
;
565 if (!rdev
->pm
.dpm_enabled
)
568 if (rdev
->asic
->pm
.get_temperature
) {
569 int temp
= radeon_get_temperature(rdev
);
571 if (temp
< rdev
->pm
.dpm
.thermal
.min_temp
)
572 /* switch back the user state */
573 dpm_state
= rdev
->pm
.dpm
.user_state
;
575 if (rdev
->pm
.dpm
.thermal
.high_to_low
)
576 /* switch back the user state */
577 dpm_state
= rdev
->pm
.dpm
.user_state
;
579 radeon_dpm_enable_power_state(rdev
, dpm_state
);
582 static struct radeon_ps
*radeon_dpm_pick_power_state(struct radeon_device
*rdev
,
583 enum radeon_pm_state_type dpm_state
)
586 struct radeon_ps
*ps
;
590 /* balanced states don't exist at the moment */
591 if (dpm_state
== POWER_STATE_TYPE_BALANCED
)
592 dpm_state
= POWER_STATE_TYPE_PERFORMANCE
;
594 /* Pick the best power state based on current conditions */
595 for (i
= 0; i
< rdev
->pm
.dpm
.num_ps
; i
++) {
596 ps
= &rdev
->pm
.dpm
.ps
[i
];
597 ui_class
= ps
->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK
;
600 case POWER_STATE_TYPE_BATTERY
:
601 if (ui_class
== ATOM_PPLIB_CLASSIFICATION_UI_BATTERY
) {
602 if (ps
->caps
& ATOM_PPLIB_SINGLE_DISPLAY_ONLY
) {
603 if (rdev
->pm
.dpm
.new_active_crtc_count
< 2)
609 case POWER_STATE_TYPE_BALANCED
:
610 if (ui_class
== ATOM_PPLIB_CLASSIFICATION_UI_BALANCED
) {
611 if (ps
->caps
& ATOM_PPLIB_SINGLE_DISPLAY_ONLY
) {
612 if (rdev
->pm
.dpm
.new_active_crtc_count
< 2)
618 case POWER_STATE_TYPE_PERFORMANCE
:
619 if (ui_class
== ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE
) {
620 if (ps
->caps
& ATOM_PPLIB_SINGLE_DISPLAY_ONLY
) {
621 if (rdev
->pm
.dpm
.new_active_crtc_count
< 2)
627 /* internal states */
628 case POWER_STATE_TYPE_INTERNAL_UVD
:
629 return rdev
->pm
.dpm
.uvd_ps
;
630 case POWER_STATE_TYPE_INTERNAL_UVD_SD
:
631 if (ps
->class & ATOM_PPLIB_CLASSIFICATION_SDSTATE
)
634 case POWER_STATE_TYPE_INTERNAL_UVD_HD
:
635 if (ps
->class & ATOM_PPLIB_CLASSIFICATION_HDSTATE
)
638 case POWER_STATE_TYPE_INTERNAL_UVD_HD2
:
639 if (ps
->class & ATOM_PPLIB_CLASSIFICATION_HD2STATE
)
642 case POWER_STATE_TYPE_INTERNAL_UVD_MVC
:
643 if (ps
->class2
& ATOM_PPLIB_CLASSIFICATION2_MVC
)
646 case POWER_STATE_TYPE_INTERNAL_BOOT
:
647 return rdev
->pm
.dpm
.boot_ps
;
648 case POWER_STATE_TYPE_INTERNAL_THERMAL
:
649 if (ps
->class & ATOM_PPLIB_CLASSIFICATION_THERMAL
)
652 case POWER_STATE_TYPE_INTERNAL_ACPI
:
653 if (ps
->class & ATOM_PPLIB_CLASSIFICATION_ACPI
)
656 case POWER_STATE_TYPE_INTERNAL_ULV
:
657 if (ps
->class2
& ATOM_PPLIB_CLASSIFICATION2_ULV
)
664 /* use a fallback state if we didn't match */
666 case POWER_STATE_TYPE_INTERNAL_UVD_SD
:
667 case POWER_STATE_TYPE_INTERNAL_UVD_HD
:
668 case POWER_STATE_TYPE_INTERNAL_UVD_HD2
:
669 case POWER_STATE_TYPE_INTERNAL_UVD_MVC
:
670 return rdev
->pm
.dpm
.uvd_ps
;
671 case POWER_STATE_TYPE_INTERNAL_THERMAL
:
672 dpm_state
= POWER_STATE_TYPE_INTERNAL_ACPI
;
674 case POWER_STATE_TYPE_INTERNAL_ACPI
:
675 dpm_state
= POWER_STATE_TYPE_BATTERY
;
677 case POWER_STATE_TYPE_BATTERY
:
678 dpm_state
= POWER_STATE_TYPE_PERFORMANCE
;
687 static void radeon_dpm_change_power_state_locked(struct radeon_device
*rdev
)
690 struct radeon_ps
*ps
;
691 enum radeon_pm_state_type dpm_state
;
693 /* if dpm init failed */
694 if (!rdev
->pm
.dpm_enabled
)
697 if (rdev
->pm
.dpm
.user_state
!= rdev
->pm
.dpm
.state
) {
698 /* add other state override checks here */
699 if ((!rdev
->pm
.dpm
.thermal_active
) &&
700 (!rdev
->pm
.dpm
.uvd_active
))
701 rdev
->pm
.dpm
.state
= rdev
->pm
.dpm
.user_state
;
703 dpm_state
= rdev
->pm
.dpm
.state
;
705 ps
= radeon_dpm_pick_power_state(rdev
, dpm_state
);
707 rdev
->pm
.dpm
.requested_ps
= ps
;
711 /* no need to reprogram if nothing changed */
712 if (rdev
->pm
.dpm
.current_ps
== rdev
->pm
.dpm
.requested_ps
) {
713 /* update display watermarks based on new power state */
714 if (rdev
->pm
.dpm
.new_active_crtcs
!= rdev
->pm
.dpm
.current_active_crtcs
) {
715 radeon_bandwidth_update(rdev
);
716 /* update displays */
717 radeon_dpm_display_configuration_changed(rdev
);
718 rdev
->pm
.dpm
.current_active_crtcs
= rdev
->pm
.dpm
.new_active_crtcs
;
719 rdev
->pm
.dpm
.current_active_crtc_count
= rdev
->pm
.dpm
.new_active_crtc_count
;
724 printk("switching from power state:\n");
725 radeon_dpm_print_power_state(rdev
, rdev
->pm
.dpm
.current_ps
);
726 printk("switching to power state:\n");
727 radeon_dpm_print_power_state(rdev
, rdev
->pm
.dpm
.requested_ps
);
729 mutex_lock(&rdev
->ddev
->struct_mutex
);
730 down_write(&rdev
->pm
.mclk_lock
);
731 mutex_lock(&rdev
->ring_lock
);
733 /* update display watermarks based on new power state */
734 radeon_bandwidth_update(rdev
);
735 /* update displays */
736 radeon_dpm_display_configuration_changed(rdev
);
738 rdev
->pm
.dpm
.current_active_crtcs
= rdev
->pm
.dpm
.new_active_crtcs
;
739 rdev
->pm
.dpm
.current_active_crtc_count
= rdev
->pm
.dpm
.new_active_crtc_count
;
741 /* wait for the rings to drain */
742 for (i
= 0; i
< RADEON_NUM_RINGS
; i
++) {
743 struct radeon_ring
*ring
= &rdev
->ring
[i
];
745 radeon_fence_wait_empty_locked(rdev
, i
);
748 /* program the new power state */
749 radeon_dpm_set_power_state(rdev
);
751 /* update current power state */
752 rdev
->pm
.dpm
.current_ps
= rdev
->pm
.dpm
.requested_ps
;
754 mutex_unlock(&rdev
->ring_lock
);
755 up_write(&rdev
->pm
.mclk_lock
);
756 mutex_unlock(&rdev
->ddev
->struct_mutex
);
759 void radeon_dpm_enable_power_state(struct radeon_device
*rdev
,
760 enum radeon_pm_state_type dpm_state
)
762 if (!rdev
->pm
.dpm_enabled
)
765 mutex_lock(&rdev
->pm
.mutex
);
767 case POWER_STATE_TYPE_INTERNAL_THERMAL
:
768 rdev
->pm
.dpm
.thermal_active
= true;
770 case POWER_STATE_TYPE_INTERNAL_UVD
:
771 case POWER_STATE_TYPE_INTERNAL_UVD_SD
:
772 case POWER_STATE_TYPE_INTERNAL_UVD_HD
:
773 case POWER_STATE_TYPE_INTERNAL_UVD_HD2
:
774 case POWER_STATE_TYPE_INTERNAL_UVD_MVC
:
775 rdev
->pm
.dpm
.uvd_active
= true;
778 rdev
->pm
.dpm
.thermal_active
= false;
779 rdev
->pm
.dpm
.uvd_active
= false;
782 rdev
->pm
.dpm
.state
= dpm_state
;
783 mutex_unlock(&rdev
->pm
.mutex
);
784 radeon_pm_compute_clocks(rdev
);
787 static void radeon_pm_suspend_old(struct radeon_device
*rdev
)
789 mutex_lock(&rdev
->pm
.mutex
);
790 if (rdev
->pm
.pm_method
== PM_METHOD_DYNPM
) {
791 if (rdev
->pm
.dynpm_state
== DYNPM_STATE_ACTIVE
)
792 rdev
->pm
.dynpm_state
= DYNPM_STATE_SUSPENDED
;
794 mutex_unlock(&rdev
->pm
.mutex
);
796 cancel_delayed_work_sync(&rdev
->pm
.dynpm_idle_work
);
799 static void radeon_pm_suspend_dpm(struct radeon_device
*rdev
)
801 mutex_lock(&rdev
->pm
.mutex
);
803 radeon_dpm_disable(rdev
);
804 /* reset the power state */
805 rdev
->pm
.dpm
.current_ps
= rdev
->pm
.dpm
.requested_ps
= rdev
->pm
.dpm
.boot_ps
;
806 rdev
->pm
.dpm_enabled
= false;
807 mutex_unlock(&rdev
->pm
.mutex
);
810 void radeon_pm_suspend(struct radeon_device
*rdev
)
812 if (rdev
->pm
.pm_method
== PM_METHOD_DPM
)
813 radeon_pm_suspend_dpm(rdev
);
815 radeon_pm_suspend_old(rdev
);
818 static void radeon_pm_resume_old(struct radeon_device
*rdev
)
820 /* set up the default clocks if the MC ucode is loaded */
821 if ((rdev
->family
>= CHIP_BARTS
) &&
822 (rdev
->family
<= CHIP_CAYMAN
) &&
824 if (rdev
->pm
.default_vddc
)
825 radeon_atom_set_voltage(rdev
, rdev
->pm
.default_vddc
,
826 SET_VOLTAGE_TYPE_ASIC_VDDC
);
827 if (rdev
->pm
.default_vddci
)
828 radeon_atom_set_voltage(rdev
, rdev
->pm
.default_vddci
,
829 SET_VOLTAGE_TYPE_ASIC_VDDCI
);
830 if (rdev
->pm
.default_sclk
)
831 radeon_set_engine_clock(rdev
, rdev
->pm
.default_sclk
);
832 if (rdev
->pm
.default_mclk
)
833 radeon_set_memory_clock(rdev
, rdev
->pm
.default_mclk
);
835 /* asic init will reset the default power state */
836 mutex_lock(&rdev
->pm
.mutex
);
837 rdev
->pm
.current_power_state_index
= rdev
->pm
.default_power_state_index
;
838 rdev
->pm
.current_clock_mode_index
= 0;
839 rdev
->pm
.current_sclk
= rdev
->pm
.default_sclk
;
840 rdev
->pm
.current_mclk
= rdev
->pm
.default_mclk
;
841 rdev
->pm
.current_vddc
= rdev
->pm
.power_state
[rdev
->pm
.default_power_state_index
].clock_info
[0].voltage
.voltage
;
842 rdev
->pm
.current_vddci
= rdev
->pm
.power_state
[rdev
->pm
.default_power_state_index
].clock_info
[0].voltage
.vddci
;
843 if (rdev
->pm
.pm_method
== PM_METHOD_DYNPM
844 && rdev
->pm
.dynpm_state
== DYNPM_STATE_SUSPENDED
) {
845 rdev
->pm
.dynpm_state
= DYNPM_STATE_ACTIVE
;
846 schedule_delayed_work(&rdev
->pm
.dynpm_idle_work
,
847 msecs_to_jiffies(RADEON_IDLE_LOOP_MS
));
849 mutex_unlock(&rdev
->pm
.mutex
);
850 radeon_pm_compute_clocks(rdev
);
853 static void radeon_pm_resume_dpm(struct radeon_device
*rdev
)
857 /* asic init will reset to the boot state */
858 mutex_lock(&rdev
->pm
.mutex
);
859 rdev
->pm
.dpm
.current_ps
= rdev
->pm
.dpm
.requested_ps
= rdev
->pm
.dpm
.boot_ps
;
860 radeon_dpm_setup_asic(rdev
);
861 ret
= radeon_dpm_enable(rdev
);
862 mutex_unlock(&rdev
->pm
.mutex
);
864 DRM_ERROR("radeon: dpm resume failed\n");
865 if ((rdev
->family
>= CHIP_BARTS
) &&
866 (rdev
->family
<= CHIP_CAYMAN
) &&
868 if (rdev
->pm
.default_vddc
)
869 radeon_atom_set_voltage(rdev
, rdev
->pm
.default_vddc
,
870 SET_VOLTAGE_TYPE_ASIC_VDDC
);
871 if (rdev
->pm
.default_vddci
)
872 radeon_atom_set_voltage(rdev
, rdev
->pm
.default_vddci
,
873 SET_VOLTAGE_TYPE_ASIC_VDDCI
);
874 if (rdev
->pm
.default_sclk
)
875 radeon_set_engine_clock(rdev
, rdev
->pm
.default_sclk
);
876 if (rdev
->pm
.default_mclk
)
877 radeon_set_memory_clock(rdev
, rdev
->pm
.default_mclk
);
880 rdev
->pm
.dpm_enabled
= true;
881 radeon_pm_compute_clocks(rdev
);
885 void radeon_pm_resume(struct radeon_device
*rdev
)
887 if (rdev
->pm
.pm_method
== PM_METHOD_DPM
)
888 radeon_pm_resume_dpm(rdev
);
890 radeon_pm_resume_old(rdev
);
893 static int radeon_pm_init_old(struct radeon_device
*rdev
)
897 rdev
->pm
.profile
= PM_PROFILE_DEFAULT
;
898 rdev
->pm
.dynpm_state
= DYNPM_STATE_DISABLED
;
899 rdev
->pm
.dynpm_planned_action
= DYNPM_ACTION_NONE
;
900 rdev
->pm
.dynpm_can_upclock
= true;
901 rdev
->pm
.dynpm_can_downclock
= true;
902 rdev
->pm
.default_sclk
= rdev
->clock
.default_sclk
;
903 rdev
->pm
.default_mclk
= rdev
->clock
.default_mclk
;
904 rdev
->pm
.current_sclk
= rdev
->clock
.default_sclk
;
905 rdev
->pm
.current_mclk
= rdev
->clock
.default_mclk
;
906 rdev
->pm
.int_thermal_type
= THERMAL_TYPE_NONE
;
909 if (rdev
->is_atom_bios
)
910 radeon_atombios_get_power_modes(rdev
);
912 radeon_combios_get_power_modes(rdev
);
913 radeon_pm_print_states(rdev
);
914 radeon_pm_init_profile(rdev
);
915 /* set up the default clocks if the MC ucode is loaded */
916 if ((rdev
->family
>= CHIP_BARTS
) &&
917 (rdev
->family
<= CHIP_CAYMAN
) &&
919 if (rdev
->pm
.default_vddc
)
920 radeon_atom_set_voltage(rdev
, rdev
->pm
.default_vddc
,
921 SET_VOLTAGE_TYPE_ASIC_VDDC
);
922 if (rdev
->pm
.default_vddci
)
923 radeon_atom_set_voltage(rdev
, rdev
->pm
.default_vddci
,
924 SET_VOLTAGE_TYPE_ASIC_VDDCI
);
925 if (rdev
->pm
.default_sclk
)
926 radeon_set_engine_clock(rdev
, rdev
->pm
.default_sclk
);
927 if (rdev
->pm
.default_mclk
)
928 radeon_set_memory_clock(rdev
, rdev
->pm
.default_mclk
);
932 /* set up the internal thermal sensor if applicable */
933 ret
= radeon_hwmon_init(rdev
);
937 INIT_DELAYED_WORK(&rdev
->pm
.dynpm_idle_work
, radeon_dynpm_idle_work_handler
);
939 if (rdev
->pm
.num_power_states
> 1) {
940 /* where's the best place to put these? */
941 ret
= device_create_file(rdev
->dev
, &dev_attr_power_profile
);
943 DRM_ERROR("failed to create device file for power profile\n");
944 ret
= device_create_file(rdev
->dev
, &dev_attr_power_method
);
946 DRM_ERROR("failed to create device file for power method\n");
948 if (radeon_debugfs_pm_init(rdev
)) {
949 DRM_ERROR("Failed to register debugfs file for PM!\n");
952 DRM_INFO("radeon: power management initialized\n");
958 static void radeon_dpm_print_power_states(struct radeon_device
*rdev
)
962 for (i
= 0; i
< rdev
->pm
.dpm
.num_ps
; i
++) {
963 printk("== power state %d ==\n", i
);
964 radeon_dpm_print_power_state(rdev
, &rdev
->pm
.dpm
.ps
[i
]);
968 static int radeon_pm_init_dpm(struct radeon_device
*rdev
)
972 /* default to performance state */
973 rdev
->pm
.dpm
.state
= POWER_STATE_TYPE_PERFORMANCE
;
974 rdev
->pm
.dpm
.user_state
= POWER_STATE_TYPE_PERFORMANCE
;
975 rdev
->pm
.default_sclk
= rdev
->clock
.default_sclk
;
976 rdev
->pm
.default_mclk
= rdev
->clock
.default_mclk
;
977 rdev
->pm
.current_sclk
= rdev
->clock
.default_sclk
;
978 rdev
->pm
.current_mclk
= rdev
->clock
.default_mclk
;
979 rdev
->pm
.int_thermal_type
= THERMAL_TYPE_NONE
;
981 if (rdev
->bios
&& rdev
->is_atom_bios
)
982 radeon_atombios_get_power_modes(rdev
);
986 /* set up the internal thermal sensor if applicable */
987 ret
= radeon_hwmon_init(rdev
);
991 INIT_WORK(&rdev
->pm
.dpm
.thermal
.work
, radeon_dpm_thermal_work_handler
);
992 mutex_lock(&rdev
->pm
.mutex
);
993 radeon_dpm_init(rdev
);
994 rdev
->pm
.dpm
.current_ps
= rdev
->pm
.dpm
.requested_ps
= rdev
->pm
.dpm
.boot_ps
;
995 radeon_dpm_print_power_states(rdev
);
996 radeon_dpm_setup_asic(rdev
);
997 ret
= radeon_dpm_enable(rdev
);
998 mutex_unlock(&rdev
->pm
.mutex
);
1000 rdev
->pm
.dpm_enabled
= false;
1001 if ((rdev
->family
>= CHIP_BARTS
) &&
1002 (rdev
->family
<= CHIP_CAYMAN
) &&
1004 if (rdev
->pm
.default_vddc
)
1005 radeon_atom_set_voltage(rdev
, rdev
->pm
.default_vddc
,
1006 SET_VOLTAGE_TYPE_ASIC_VDDC
);
1007 if (rdev
->pm
.default_vddci
)
1008 radeon_atom_set_voltage(rdev
, rdev
->pm
.default_vddci
,
1009 SET_VOLTAGE_TYPE_ASIC_VDDCI
);
1010 if (rdev
->pm
.default_sclk
)
1011 radeon_set_engine_clock(rdev
, rdev
->pm
.default_sclk
);
1012 if (rdev
->pm
.default_mclk
)
1013 radeon_set_memory_clock(rdev
, rdev
->pm
.default_mclk
);
1015 DRM_ERROR("radeon: dpm initialization failed\n");
1018 rdev
->pm
.dpm_enabled
= true;
1019 radeon_pm_compute_clocks(rdev
);
1021 if (rdev
->pm
.num_power_states
> 1) {
1022 ret
= device_create_file(rdev
->dev
, &dev_attr_power_dpm_state
);
1024 DRM_ERROR("failed to create device file for dpm state\n");
1025 /* XXX: these are noops for dpm but are here for backwards compat */
1026 ret
= device_create_file(rdev
->dev
, &dev_attr_power_profile
);
1028 DRM_ERROR("failed to create device file for power profile\n");
1029 ret
= device_create_file(rdev
->dev
, &dev_attr_power_method
);
1031 DRM_ERROR("failed to create device file for power method\n");
1032 DRM_INFO("radeon: dpm initialized\n");
1038 int radeon_pm_init(struct radeon_device
*rdev
)
1040 /* enable dpm on rv6xx+ */
1041 switch (rdev
->family
) {
1065 if (radeon_dpm
== 1)
1066 rdev
->pm
.pm_method
= PM_METHOD_DPM
;
1068 rdev
->pm
.pm_method
= PM_METHOD_PROFILE
;
1071 /* default to profile method */
1072 rdev
->pm
.pm_method
= PM_METHOD_PROFILE
;
1076 if (rdev
->pm
.pm_method
== PM_METHOD_DPM
)
1077 return radeon_pm_init_dpm(rdev
);
1079 return radeon_pm_init_old(rdev
);
1082 static void radeon_pm_fini_old(struct radeon_device
*rdev
)
1084 if (rdev
->pm
.num_power_states
> 1) {
1085 mutex_lock(&rdev
->pm
.mutex
);
1086 if (rdev
->pm
.pm_method
== PM_METHOD_PROFILE
) {
1087 rdev
->pm
.profile
= PM_PROFILE_DEFAULT
;
1088 radeon_pm_update_profile(rdev
);
1089 radeon_pm_set_clocks(rdev
);
1090 } else if (rdev
->pm
.pm_method
== PM_METHOD_DYNPM
) {
1091 /* reset default clocks */
1092 rdev
->pm
.dynpm_state
= DYNPM_STATE_DISABLED
;
1093 rdev
->pm
.dynpm_planned_action
= DYNPM_ACTION_DEFAULT
;
1094 radeon_pm_set_clocks(rdev
);
1096 mutex_unlock(&rdev
->pm
.mutex
);
1098 cancel_delayed_work_sync(&rdev
->pm
.dynpm_idle_work
);
1100 device_remove_file(rdev
->dev
, &dev_attr_power_profile
);
1101 device_remove_file(rdev
->dev
, &dev_attr_power_method
);
1104 if (rdev
->pm
.power_state
)
1105 kfree(rdev
->pm
.power_state
);
1107 radeon_hwmon_fini(rdev
);
1110 static void radeon_pm_fini_dpm(struct radeon_device
*rdev
)
1112 if (rdev
->pm
.num_power_states
> 1) {
1113 mutex_lock(&rdev
->pm
.mutex
);
1114 radeon_dpm_disable(rdev
);
1115 mutex_unlock(&rdev
->pm
.mutex
);
1117 device_remove_file(rdev
->dev
, &dev_attr_power_dpm_state
);
1118 /* XXX backwards compat */
1119 device_remove_file(rdev
->dev
, &dev_attr_power_profile
);
1120 device_remove_file(rdev
->dev
, &dev_attr_power_method
);
1122 radeon_dpm_fini(rdev
);
1124 if (rdev
->pm
.power_state
)
1125 kfree(rdev
->pm
.power_state
);
1127 radeon_hwmon_fini(rdev
);
1130 void radeon_pm_fini(struct radeon_device
*rdev
)
1132 if (rdev
->pm
.pm_method
== PM_METHOD_DPM
)
1133 radeon_pm_fini_dpm(rdev
);
1135 radeon_pm_fini_old(rdev
);
1138 static void radeon_pm_compute_clocks_old(struct radeon_device
*rdev
)
1140 struct drm_device
*ddev
= rdev
->ddev
;
1141 struct drm_crtc
*crtc
;
1142 struct radeon_crtc
*radeon_crtc
;
1144 if (rdev
->pm
.num_power_states
< 2)
1147 INIT_WORK(&rdev
->pm
.dpm
.thermal
.work
, radeon_dpm_thermal_work_handler
);
1148 mutex_lock(&rdev
->pm
.mutex
);
1150 rdev
->pm
.active_crtcs
= 0;
1151 rdev
->pm
.active_crtc_count
= 0;
1152 list_for_each_entry(crtc
,
1153 &ddev
->mode_config
.crtc_list
, head
) {
1154 radeon_crtc
= to_radeon_crtc(crtc
);
1155 if (radeon_crtc
->enabled
) {
1156 rdev
->pm
.active_crtcs
|= (1 << radeon_crtc
->crtc_id
);
1157 rdev
->pm
.active_crtc_count
++;
1161 if (rdev
->pm
.pm_method
== PM_METHOD_PROFILE
) {
1162 radeon_pm_update_profile(rdev
);
1163 radeon_pm_set_clocks(rdev
);
1164 } else if (rdev
->pm
.pm_method
== PM_METHOD_DYNPM
) {
1165 if (rdev
->pm
.dynpm_state
!= DYNPM_STATE_DISABLED
) {
1166 if (rdev
->pm
.active_crtc_count
> 1) {
1167 if (rdev
->pm
.dynpm_state
== DYNPM_STATE_ACTIVE
) {
1168 cancel_delayed_work(&rdev
->pm
.dynpm_idle_work
);
1170 rdev
->pm
.dynpm_state
= DYNPM_STATE_PAUSED
;
1171 rdev
->pm
.dynpm_planned_action
= DYNPM_ACTION_DEFAULT
;
1172 radeon_pm_get_dynpm_state(rdev
);
1173 radeon_pm_set_clocks(rdev
);
1175 DRM_DEBUG_DRIVER("radeon: dynamic power management deactivated\n");
1177 } else if (rdev
->pm
.active_crtc_count
== 1) {
1178 /* TODO: Increase clocks if needed for current mode */
1180 if (rdev
->pm
.dynpm_state
== DYNPM_STATE_MINIMUM
) {
1181 rdev
->pm
.dynpm_state
= DYNPM_STATE_ACTIVE
;
1182 rdev
->pm
.dynpm_planned_action
= DYNPM_ACTION_UPCLOCK
;
1183 radeon_pm_get_dynpm_state(rdev
);
1184 radeon_pm_set_clocks(rdev
);
1186 schedule_delayed_work(&rdev
->pm
.dynpm_idle_work
,
1187 msecs_to_jiffies(RADEON_IDLE_LOOP_MS
));
1188 } else if (rdev
->pm
.dynpm_state
== DYNPM_STATE_PAUSED
) {
1189 rdev
->pm
.dynpm_state
= DYNPM_STATE_ACTIVE
;
1190 schedule_delayed_work(&rdev
->pm
.dynpm_idle_work
,
1191 msecs_to_jiffies(RADEON_IDLE_LOOP_MS
));
1192 DRM_DEBUG_DRIVER("radeon: dynamic power management activated\n");
1194 } else { /* count == 0 */
1195 if (rdev
->pm
.dynpm_state
!= DYNPM_STATE_MINIMUM
) {
1196 cancel_delayed_work(&rdev
->pm
.dynpm_idle_work
);
1198 rdev
->pm
.dynpm_state
= DYNPM_STATE_MINIMUM
;
1199 rdev
->pm
.dynpm_planned_action
= DYNPM_ACTION_MINIMUM
;
1200 radeon_pm_get_dynpm_state(rdev
);
1201 radeon_pm_set_clocks(rdev
);
1207 mutex_unlock(&rdev
->pm
.mutex
);
1210 static void radeon_pm_compute_clocks_dpm(struct radeon_device
*rdev
)
1212 struct drm_device
*ddev
= rdev
->ddev
;
1213 struct drm_crtc
*crtc
;
1214 struct radeon_crtc
*radeon_crtc
;
1216 mutex_lock(&rdev
->pm
.mutex
);
1218 rdev
->pm
.dpm
.new_active_crtcs
= 0;
1219 rdev
->pm
.dpm
.new_active_crtc_count
= 0;
1220 list_for_each_entry(crtc
,
1221 &ddev
->mode_config
.crtc_list
, head
) {
1222 radeon_crtc
= to_radeon_crtc(crtc
);
1223 if (crtc
->enabled
) {
1224 rdev
->pm
.dpm
.new_active_crtcs
|= (1 << radeon_crtc
->crtc_id
);
1225 rdev
->pm
.dpm
.new_active_crtc_count
++;
1229 radeon_dpm_change_power_state_locked(rdev
);
1231 mutex_unlock(&rdev
->pm
.mutex
);
1235 void radeon_pm_compute_clocks(struct radeon_device
*rdev
)
1237 if (rdev
->pm
.pm_method
== PM_METHOD_DPM
)
1238 radeon_pm_compute_clocks_dpm(rdev
);
1240 radeon_pm_compute_clocks_old(rdev
);
1243 static bool radeon_pm_in_vbl(struct radeon_device
*rdev
)
1245 int crtc
, vpos
, hpos
, vbl_status
;
1248 /* Iterate over all active crtc's. All crtc's must be in vblank,
1249 * otherwise return in_vbl == false.
1251 for (crtc
= 0; (crtc
< rdev
->num_crtc
) && in_vbl
; crtc
++) {
1252 if (rdev
->pm
.active_crtcs
& (1 << crtc
)) {
1253 vbl_status
= radeon_get_crtc_scanoutpos(rdev
->ddev
, crtc
, &vpos
, &hpos
);
1254 if ((vbl_status
& DRM_SCANOUTPOS_VALID
) &&
1255 !(vbl_status
& DRM_SCANOUTPOS_INVBL
))
1263 static bool radeon_pm_debug_check_in_vbl(struct radeon_device
*rdev
, bool finish
)
1266 bool in_vbl
= radeon_pm_in_vbl(rdev
);
1268 if (in_vbl
== false)
1269 DRM_DEBUG_DRIVER("not in vbl for pm change %08x at %s\n", stat_crtc
,
1270 finish
? "exit" : "entry");
1274 static void radeon_dynpm_idle_work_handler(struct work_struct
*work
)
1276 struct radeon_device
*rdev
;
1278 rdev
= container_of(work
, struct radeon_device
,
1279 pm
.dynpm_idle_work
.work
);
1281 resched
= ttm_bo_lock_delayed_workqueue(&rdev
->mman
.bdev
);
1282 mutex_lock(&rdev
->pm
.mutex
);
1283 if (rdev
->pm
.dynpm_state
== DYNPM_STATE_ACTIVE
) {
1284 int not_processed
= 0;
1287 for (i
= 0; i
< RADEON_NUM_RINGS
; ++i
) {
1288 struct radeon_ring
*ring
= &rdev
->ring
[i
];
1291 not_processed
+= radeon_fence_count_emitted(rdev
, i
);
1292 if (not_processed
>= 3)
1297 if (not_processed
>= 3) { /* should upclock */
1298 if (rdev
->pm
.dynpm_planned_action
== DYNPM_ACTION_DOWNCLOCK
) {
1299 rdev
->pm
.dynpm_planned_action
= DYNPM_ACTION_NONE
;
1300 } else if (rdev
->pm
.dynpm_planned_action
== DYNPM_ACTION_NONE
&&
1301 rdev
->pm
.dynpm_can_upclock
) {
1302 rdev
->pm
.dynpm_planned_action
=
1303 DYNPM_ACTION_UPCLOCK
;
1304 rdev
->pm
.dynpm_action_timeout
= jiffies
+
1305 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS
);
1307 } else if (not_processed
== 0) { /* should downclock */
1308 if (rdev
->pm
.dynpm_planned_action
== DYNPM_ACTION_UPCLOCK
) {
1309 rdev
->pm
.dynpm_planned_action
= DYNPM_ACTION_NONE
;
1310 } else if (rdev
->pm
.dynpm_planned_action
== DYNPM_ACTION_NONE
&&
1311 rdev
->pm
.dynpm_can_downclock
) {
1312 rdev
->pm
.dynpm_planned_action
=
1313 DYNPM_ACTION_DOWNCLOCK
;
1314 rdev
->pm
.dynpm_action_timeout
= jiffies
+
1315 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS
);
1319 /* Note, radeon_pm_set_clocks is called with static_switch set
1320 * to false since we want to wait for vbl to avoid flicker.
1322 if (rdev
->pm
.dynpm_planned_action
!= DYNPM_ACTION_NONE
&&
1323 jiffies
> rdev
->pm
.dynpm_action_timeout
) {
1324 radeon_pm_get_dynpm_state(rdev
);
1325 radeon_pm_set_clocks(rdev
);
1328 schedule_delayed_work(&rdev
->pm
.dynpm_idle_work
,
1329 msecs_to_jiffies(RADEON_IDLE_LOOP_MS
));
1331 mutex_unlock(&rdev
->pm
.mutex
);
1332 ttm_bo_unlock_delayed_workqueue(&rdev
->mman
.bdev
, resched
);
1338 #if defined(CONFIG_DEBUG_FS)
1340 static int radeon_debugfs_pm_info(struct seq_file
*m
, void *data
)
1342 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
1343 struct drm_device
*dev
= node
->minor
->dev
;
1344 struct radeon_device
*rdev
= dev
->dev_private
;
1346 seq_printf(m
, "default engine clock: %u0 kHz\n", rdev
->pm
.default_sclk
);
1347 /* radeon_get_engine_clock is not reliable on APUs so just print the current clock */
1348 if ((rdev
->family
>= CHIP_PALM
) && (rdev
->flags
& RADEON_IS_IGP
))
1349 seq_printf(m
, "current engine clock: %u0 kHz\n", rdev
->pm
.current_sclk
);
1351 seq_printf(m
, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev
));
1352 seq_printf(m
, "default memory clock: %u0 kHz\n", rdev
->pm
.default_mclk
);
1353 if (rdev
->asic
->pm
.get_memory_clock
)
1354 seq_printf(m
, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev
));
1355 if (rdev
->pm
.current_vddc
)
1356 seq_printf(m
, "voltage: %u mV\n", rdev
->pm
.current_vddc
);
1357 if (rdev
->asic
->pm
.get_pcie_lanes
)
1358 seq_printf(m
, "PCIE lanes: %d\n", radeon_get_pcie_lanes(rdev
));
1363 static struct drm_info_list radeon_pm_info_list
[] = {
1364 {"radeon_pm_info", radeon_debugfs_pm_info
, 0, NULL
},
1368 static int radeon_debugfs_pm_init(struct radeon_device
*rdev
)
1370 #if defined(CONFIG_DEBUG_FS)
1371 return radeon_debugfs_add_files(rdev
, radeon_pm_info_list
, ARRAY_SIZE(radeon_pm_info_list
));