2 * Permission is hereby granted, free of charge, to any person obtaining a
3 * copy of this software and associated documentation files (the "Software"),
4 * to deal in the Software without restriction, including without limitation
5 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
6 * and/or sell copies of the Software, and to permit persons to whom the
7 * Software is furnished to do so, subject to the following conditions:
9 * The above copyright notice and this permission notice shall be included in
10 * all copies or substantial portions of the Software.
12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
13 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
14 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
15 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
16 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
17 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
18 * OTHER DEALINGS IN THE SOFTWARE.
20 * Authors: Rafał Miłecki <zajec5@gmail.com>
21 * Alex Deucher <alexdeucher@gmail.com>
27 #include <linux/power_supply.h>
28 #include <linux/hwmon.h>
29 #include <linux/hwmon-sysfs.h>
31 #define RADEON_IDLE_LOOP_MS 100
32 #define RADEON_RECLOCK_DELAY_MS 200
33 #define RADEON_WAIT_VBLANK_TIMEOUT 200
35 static const char *radeon_pm_state_type_name
[5] = {
43 static void radeon_dynpm_idle_work_handler(struct work_struct
*work
);
44 static int radeon_debugfs_pm_init(struct radeon_device
*rdev
);
45 static bool radeon_pm_in_vbl(struct radeon_device
*rdev
);
46 static bool radeon_pm_debug_check_in_vbl(struct radeon_device
*rdev
, bool finish
);
47 static void radeon_pm_update_profile(struct radeon_device
*rdev
);
48 static void radeon_pm_set_clocks(struct radeon_device
*rdev
);
50 int radeon_pm_get_type_index(struct radeon_device
*rdev
,
51 enum radeon_pm_state_type ps_type
,
55 int found_instance
= -1;
57 for (i
= 0; i
< rdev
->pm
.num_power_states
; i
++) {
58 if (rdev
->pm
.power_state
[i
].type
== ps_type
) {
60 if (found_instance
== instance
)
64 /* return default if no match */
65 return rdev
->pm
.default_power_state_index
;
68 void radeon_pm_acpi_event_handler(struct radeon_device
*rdev
)
70 if (rdev
->pm
.pm_method
== PM_METHOD_PROFILE
) {
71 if (rdev
->pm
.profile
== PM_PROFILE_AUTO
) {
72 mutex_lock(&rdev
->pm
.mutex
);
73 radeon_pm_update_profile(rdev
);
74 radeon_pm_set_clocks(rdev
);
75 mutex_unlock(&rdev
->pm
.mutex
);
80 static void radeon_pm_update_profile(struct radeon_device
*rdev
)
82 switch (rdev
->pm
.profile
) {
83 case PM_PROFILE_DEFAULT
:
84 rdev
->pm
.profile_index
= PM_PROFILE_DEFAULT_IDX
;
87 if (power_supply_is_system_supplied() > 0) {
88 if (rdev
->pm
.active_crtc_count
> 1)
89 rdev
->pm
.profile_index
= PM_PROFILE_HIGH_MH_IDX
;
91 rdev
->pm
.profile_index
= PM_PROFILE_HIGH_SH_IDX
;
93 if (rdev
->pm
.active_crtc_count
> 1)
94 rdev
->pm
.profile_index
= PM_PROFILE_MID_MH_IDX
;
96 rdev
->pm
.profile_index
= PM_PROFILE_MID_SH_IDX
;
100 if (rdev
->pm
.active_crtc_count
> 1)
101 rdev
->pm
.profile_index
= PM_PROFILE_LOW_MH_IDX
;
103 rdev
->pm
.profile_index
= PM_PROFILE_LOW_SH_IDX
;
106 if (rdev
->pm
.active_crtc_count
> 1)
107 rdev
->pm
.profile_index
= PM_PROFILE_MID_MH_IDX
;
109 rdev
->pm
.profile_index
= PM_PROFILE_MID_SH_IDX
;
111 case PM_PROFILE_HIGH
:
112 if (rdev
->pm
.active_crtc_count
> 1)
113 rdev
->pm
.profile_index
= PM_PROFILE_HIGH_MH_IDX
;
115 rdev
->pm
.profile_index
= PM_PROFILE_HIGH_SH_IDX
;
119 if (rdev
->pm
.active_crtc_count
== 0) {
120 rdev
->pm
.requested_power_state_index
=
121 rdev
->pm
.profiles
[rdev
->pm
.profile_index
].dpms_off_ps_idx
;
122 rdev
->pm
.requested_clock_mode_index
=
123 rdev
->pm
.profiles
[rdev
->pm
.profile_index
].dpms_off_cm_idx
;
125 rdev
->pm
.requested_power_state_index
=
126 rdev
->pm
.profiles
[rdev
->pm
.profile_index
].dpms_on_ps_idx
;
127 rdev
->pm
.requested_clock_mode_index
=
128 rdev
->pm
.profiles
[rdev
->pm
.profile_index
].dpms_on_cm_idx
;
132 static void radeon_unmap_vram_bos(struct radeon_device
*rdev
)
134 struct radeon_bo
*bo
, *n
;
136 if (list_empty(&rdev
->gem
.objects
))
139 list_for_each_entry_safe(bo
, n
, &rdev
->gem
.objects
, list
) {
140 if (bo
->tbo
.mem
.mem_type
== TTM_PL_VRAM
)
141 ttm_bo_unmap_virtual(&bo
->tbo
);
145 static void radeon_sync_with_vblank(struct radeon_device
*rdev
)
147 if (rdev
->pm
.active_crtcs
) {
148 rdev
->pm
.vblank_sync
= false;
150 rdev
->irq
.vblank_queue
, rdev
->pm
.vblank_sync
,
151 msecs_to_jiffies(RADEON_WAIT_VBLANK_TIMEOUT
));
155 static void radeon_set_power_state(struct radeon_device
*rdev
)
158 bool misc_after
= false;
160 if ((rdev
->pm
.requested_clock_mode_index
== rdev
->pm
.current_clock_mode_index
) &&
161 (rdev
->pm
.requested_power_state_index
== rdev
->pm
.current_power_state_index
))
164 if (radeon_gui_idle(rdev
)) {
165 sclk
= rdev
->pm
.power_state
[rdev
->pm
.requested_power_state_index
].
166 clock_info
[rdev
->pm
.requested_clock_mode_index
].sclk
;
167 if (sclk
> rdev
->pm
.default_sclk
)
168 sclk
= rdev
->pm
.default_sclk
;
170 /* starting with BTC, there is one state that is used for both
171 * MH and SH. Difference is that we always use the high clock index for
174 if ((rdev
->pm
.pm_method
== PM_METHOD_PROFILE
) &&
175 (rdev
->family
>= CHIP_BARTS
) &&
176 rdev
->pm
.active_crtc_count
&&
177 ((rdev
->pm
.profile_index
== PM_PROFILE_MID_MH_IDX
) ||
178 (rdev
->pm
.profile_index
== PM_PROFILE_LOW_MH_IDX
)))
179 mclk
= rdev
->pm
.power_state
[rdev
->pm
.requested_power_state_index
].
180 clock_info
[rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_on_cm_idx
].mclk
;
182 mclk
= rdev
->pm
.power_state
[rdev
->pm
.requested_power_state_index
].
183 clock_info
[rdev
->pm
.requested_clock_mode_index
].mclk
;
185 if (mclk
> rdev
->pm
.default_mclk
)
186 mclk
= rdev
->pm
.default_mclk
;
188 /* upvolt before raising clocks, downvolt after lowering clocks */
189 if (sclk
< rdev
->pm
.current_sclk
)
192 radeon_sync_with_vblank(rdev
);
194 if (rdev
->pm
.pm_method
== PM_METHOD_DYNPM
) {
195 if (!radeon_pm_in_vbl(rdev
))
199 radeon_pm_prepare(rdev
);
202 /* voltage, pcie lanes, etc.*/
203 radeon_pm_misc(rdev
);
205 /* set engine clock */
206 if (sclk
!= rdev
->pm
.current_sclk
) {
207 radeon_pm_debug_check_in_vbl(rdev
, false);
208 radeon_set_engine_clock(rdev
, sclk
);
209 radeon_pm_debug_check_in_vbl(rdev
, true);
210 rdev
->pm
.current_sclk
= sclk
;
211 DRM_DEBUG_DRIVER("Setting: e: %d\n", sclk
);
214 /* set memory clock */
215 if (rdev
->asic
->pm
.set_memory_clock
&& (mclk
!= rdev
->pm
.current_mclk
)) {
216 radeon_pm_debug_check_in_vbl(rdev
, false);
217 radeon_set_memory_clock(rdev
, mclk
);
218 radeon_pm_debug_check_in_vbl(rdev
, true);
219 rdev
->pm
.current_mclk
= mclk
;
220 DRM_DEBUG_DRIVER("Setting: m: %d\n", mclk
);
224 /* voltage, pcie lanes, etc.*/
225 radeon_pm_misc(rdev
);
227 radeon_pm_finish(rdev
);
229 rdev
->pm
.current_power_state_index
= rdev
->pm
.requested_power_state_index
;
230 rdev
->pm
.current_clock_mode_index
= rdev
->pm
.requested_clock_mode_index
;
232 DRM_DEBUG_DRIVER("pm: GUI not idle!!!\n");
235 static void radeon_pm_set_clocks(struct radeon_device
*rdev
)
239 /* no need to take locks, etc. if nothing's going to change */
240 if ((rdev
->pm
.requested_clock_mode_index
== rdev
->pm
.current_clock_mode_index
) &&
241 (rdev
->pm
.requested_power_state_index
== rdev
->pm
.current_power_state_index
))
244 mutex_lock(&rdev
->ddev
->struct_mutex
);
245 down_write(&rdev
->pm
.mclk_lock
);
246 mutex_lock(&rdev
->ring_lock
);
248 /* wait for the rings to drain */
249 for (i
= 0; i
< RADEON_NUM_RINGS
; i
++) {
250 struct radeon_ring
*ring
= &rdev
->ring
[i
];
254 r
= radeon_fence_wait_empty_locked(rdev
, i
);
256 /* needs a GPU reset dont reset here */
257 mutex_unlock(&rdev
->ring_lock
);
258 up_write(&rdev
->pm
.mclk_lock
);
259 mutex_unlock(&rdev
->ddev
->struct_mutex
);
264 radeon_unmap_vram_bos(rdev
);
266 if (rdev
->irq
.installed
) {
267 for (i
= 0; i
< rdev
->num_crtc
; i
++) {
268 if (rdev
->pm
.active_crtcs
& (1 << i
)) {
269 rdev
->pm
.req_vblank
|= (1 << i
);
270 drm_vblank_get(rdev
->ddev
, i
);
275 radeon_set_power_state(rdev
);
277 if (rdev
->irq
.installed
) {
278 for (i
= 0; i
< rdev
->num_crtc
; i
++) {
279 if (rdev
->pm
.req_vblank
& (1 << i
)) {
280 rdev
->pm
.req_vblank
&= ~(1 << i
);
281 drm_vblank_put(rdev
->ddev
, i
);
286 /* update display watermarks based on new power state */
287 radeon_update_bandwidth_info(rdev
);
288 if (rdev
->pm
.active_crtc_count
)
289 radeon_bandwidth_update(rdev
);
291 rdev
->pm
.dynpm_planned_action
= DYNPM_ACTION_NONE
;
293 mutex_unlock(&rdev
->ring_lock
);
294 up_write(&rdev
->pm
.mclk_lock
);
295 mutex_unlock(&rdev
->ddev
->struct_mutex
);
298 static void radeon_pm_print_states(struct radeon_device
*rdev
)
301 struct radeon_power_state
*power_state
;
302 struct radeon_pm_clock_info
*clock_info
;
304 DRM_DEBUG_DRIVER("%d Power State(s)\n", rdev
->pm
.num_power_states
);
305 for (i
= 0; i
< rdev
->pm
.num_power_states
; i
++) {
306 power_state
= &rdev
->pm
.power_state
[i
];
307 DRM_DEBUG_DRIVER("State %d: %s\n", i
,
308 radeon_pm_state_type_name
[power_state
->type
]);
309 if (i
== rdev
->pm
.default_power_state_index
)
310 DRM_DEBUG_DRIVER("\tDefault");
311 if ((rdev
->flags
& RADEON_IS_PCIE
) && !(rdev
->flags
& RADEON_IS_IGP
))
312 DRM_DEBUG_DRIVER("\t%d PCIE Lanes\n", power_state
->pcie_lanes
);
313 if (power_state
->flags
& RADEON_PM_STATE_SINGLE_DISPLAY_ONLY
)
314 DRM_DEBUG_DRIVER("\tSingle display only\n");
315 DRM_DEBUG_DRIVER("\t%d Clock Mode(s)\n", power_state
->num_clock_modes
);
316 for (j
= 0; j
< power_state
->num_clock_modes
; j
++) {
317 clock_info
= &(power_state
->clock_info
[j
]);
318 if (rdev
->flags
& RADEON_IS_IGP
)
319 DRM_DEBUG_DRIVER("\t\t%d e: %d\n",
321 clock_info
->sclk
* 10);
323 DRM_DEBUG_DRIVER("\t\t%d e: %d\tm: %d\tv: %d\n",
325 clock_info
->sclk
* 10,
326 clock_info
->mclk
* 10,
327 clock_info
->voltage
.voltage
);
332 static ssize_t
radeon_get_pm_profile(struct device
*dev
,
333 struct device_attribute
*attr
,
336 struct drm_device
*ddev
= pci_get_drvdata(to_pci_dev(dev
));
337 struct radeon_device
*rdev
= ddev
->dev_private
;
338 int cp
= rdev
->pm
.profile
;
340 return snprintf(buf
, PAGE_SIZE
, "%s\n",
341 (cp
== PM_PROFILE_AUTO
) ? "auto" :
342 (cp
== PM_PROFILE_LOW
) ? "low" :
343 (cp
== PM_PROFILE_MID
) ? "mid" :
344 (cp
== PM_PROFILE_HIGH
) ? "high" : "default");
347 static ssize_t
radeon_set_pm_profile(struct device
*dev
,
348 struct device_attribute
*attr
,
352 struct drm_device
*ddev
= pci_get_drvdata(to_pci_dev(dev
));
353 struct radeon_device
*rdev
= ddev
->dev_private
;
355 mutex_lock(&rdev
->pm
.mutex
);
356 if (rdev
->pm
.pm_method
== PM_METHOD_PROFILE
) {
357 if (strncmp("default", buf
, strlen("default")) == 0)
358 rdev
->pm
.profile
= PM_PROFILE_DEFAULT
;
359 else if (strncmp("auto", buf
, strlen("auto")) == 0)
360 rdev
->pm
.profile
= PM_PROFILE_AUTO
;
361 else if (strncmp("low", buf
, strlen("low")) == 0)
362 rdev
->pm
.profile
= PM_PROFILE_LOW
;
363 else if (strncmp("mid", buf
, strlen("mid")) == 0)
364 rdev
->pm
.profile
= PM_PROFILE_MID
;
365 else if (strncmp("high", buf
, strlen("high")) == 0)
366 rdev
->pm
.profile
= PM_PROFILE_HIGH
;
371 radeon_pm_update_profile(rdev
);
372 radeon_pm_set_clocks(rdev
);
377 mutex_unlock(&rdev
->pm
.mutex
);
382 static ssize_t
radeon_get_pm_method(struct device
*dev
,
383 struct device_attribute
*attr
,
386 struct drm_device
*ddev
= pci_get_drvdata(to_pci_dev(dev
));
387 struct radeon_device
*rdev
= ddev
->dev_private
;
388 int pm
= rdev
->pm
.pm_method
;
390 return snprintf(buf
, PAGE_SIZE
, "%s\n",
391 (pm
== PM_METHOD_DYNPM
) ? "dynpm" :
392 (pm
== PM_METHOD_PROFILE
) ? "profile" : "dpm");
395 static ssize_t
radeon_set_pm_method(struct device
*dev
,
396 struct device_attribute
*attr
,
400 struct drm_device
*ddev
= pci_get_drvdata(to_pci_dev(dev
));
401 struct radeon_device
*rdev
= ddev
->dev_private
;
403 /* we don't support the legacy modes with dpm */
404 if (rdev
->pm
.pm_method
== PM_METHOD_DPM
) {
409 if (strncmp("dynpm", buf
, strlen("dynpm")) == 0) {
410 mutex_lock(&rdev
->pm
.mutex
);
411 rdev
->pm
.pm_method
= PM_METHOD_DYNPM
;
412 rdev
->pm
.dynpm_state
= DYNPM_STATE_PAUSED
;
413 rdev
->pm
.dynpm_planned_action
= DYNPM_ACTION_DEFAULT
;
414 mutex_unlock(&rdev
->pm
.mutex
);
415 } else if (strncmp("profile", buf
, strlen("profile")) == 0) {
416 mutex_lock(&rdev
->pm
.mutex
);
418 rdev
->pm
.dynpm_state
= DYNPM_STATE_DISABLED
;
419 rdev
->pm
.dynpm_planned_action
= DYNPM_ACTION_NONE
;
420 rdev
->pm
.pm_method
= PM_METHOD_PROFILE
;
421 mutex_unlock(&rdev
->pm
.mutex
);
422 cancel_delayed_work_sync(&rdev
->pm
.dynpm_idle_work
);
427 radeon_pm_compute_clocks(rdev
);
432 static ssize_t
radeon_get_dpm_state(struct device
*dev
,
433 struct device_attribute
*attr
,
436 struct drm_device
*ddev
= pci_get_drvdata(to_pci_dev(dev
));
437 struct radeon_device
*rdev
= ddev
->dev_private
;
438 enum radeon_pm_state_type pm
= rdev
->pm
.dpm
.user_state
;
440 return snprintf(buf
, PAGE_SIZE
, "%s\n",
441 (pm
== POWER_STATE_TYPE_BATTERY
) ? "battery" :
442 (pm
== POWER_STATE_TYPE_BALANCED
) ? "balanced" : "performance");
445 static ssize_t
radeon_set_dpm_state(struct device
*dev
,
446 struct device_attribute
*attr
,
450 struct drm_device
*ddev
= pci_get_drvdata(to_pci_dev(dev
));
451 struct radeon_device
*rdev
= ddev
->dev_private
;
453 mutex_lock(&rdev
->pm
.mutex
);
454 if (strncmp("battery", buf
, strlen("battery")) == 0)
455 rdev
->pm
.dpm
.user_state
= POWER_STATE_TYPE_BATTERY
;
456 else if (strncmp("balanced", buf
, strlen("balanced")) == 0)
457 rdev
->pm
.dpm
.user_state
= POWER_STATE_TYPE_BALANCED
;
458 else if (strncmp("performance", buf
, strlen("performance")) == 0)
459 rdev
->pm
.dpm
.user_state
= POWER_STATE_TYPE_PERFORMANCE
;
461 mutex_unlock(&rdev
->pm
.mutex
);
465 mutex_unlock(&rdev
->pm
.mutex
);
466 radeon_pm_compute_clocks(rdev
);
471 static ssize_t
radeon_get_dpm_forced_performance_level(struct device
*dev
,
472 struct device_attribute
*attr
,
475 struct drm_device
*ddev
= pci_get_drvdata(to_pci_dev(dev
));
476 struct radeon_device
*rdev
= ddev
->dev_private
;
477 enum radeon_dpm_forced_level level
= rdev
->pm
.dpm
.forced_level
;
479 return snprintf(buf
, PAGE_SIZE
, "%s\n",
480 (level
== RADEON_DPM_FORCED_LEVEL_AUTO
) ? "auto" :
481 (level
== RADEON_DPM_FORCED_LEVEL_LOW
) ? "low" : "high");
484 static ssize_t
radeon_set_dpm_forced_performance_level(struct device
*dev
,
485 struct device_attribute
*attr
,
489 struct drm_device
*ddev
= pci_get_drvdata(to_pci_dev(dev
));
490 struct radeon_device
*rdev
= ddev
->dev_private
;
491 enum radeon_dpm_forced_level level
;
494 mutex_lock(&rdev
->pm
.mutex
);
495 if (strncmp("low", buf
, strlen("low")) == 0) {
496 level
= RADEON_DPM_FORCED_LEVEL_LOW
;
497 } else if (strncmp("high", buf
, strlen("high")) == 0) {
498 level
= RADEON_DPM_FORCED_LEVEL_HIGH
;
499 } else if (strncmp("auto", buf
, strlen("auto")) == 0) {
500 level
= RADEON_DPM_FORCED_LEVEL_AUTO
;
502 mutex_unlock(&rdev
->pm
.mutex
);
506 if (rdev
->asic
->dpm
.force_performance_level
) {
507 ret
= radeon_dpm_force_performance_level(rdev
, level
);
511 mutex_unlock(&rdev
->pm
.mutex
);
516 static DEVICE_ATTR(power_profile
, S_IRUGO
| S_IWUSR
, radeon_get_pm_profile
, radeon_set_pm_profile
);
517 static DEVICE_ATTR(power_method
, S_IRUGO
| S_IWUSR
, radeon_get_pm_method
, radeon_set_pm_method
);
518 static DEVICE_ATTR(power_dpm_state
, S_IRUGO
| S_IWUSR
, radeon_get_dpm_state
, radeon_set_dpm_state
);
519 static DEVICE_ATTR(power_dpm_force_performance_level
, S_IRUGO
| S_IWUSR
,
520 radeon_get_dpm_forced_performance_level
,
521 radeon_set_dpm_forced_performance_level
);
523 static ssize_t
radeon_hwmon_show_temp(struct device
*dev
,
524 struct device_attribute
*attr
,
527 struct drm_device
*ddev
= pci_get_drvdata(to_pci_dev(dev
));
528 struct radeon_device
*rdev
= ddev
->dev_private
;
531 if (rdev
->asic
->pm
.get_temperature
)
532 temp
= radeon_get_temperature(rdev
);
536 return snprintf(buf
, PAGE_SIZE
, "%d\n", temp
);
539 static ssize_t
radeon_hwmon_show_name(struct device
*dev
,
540 struct device_attribute
*attr
,
543 return sprintf(buf
, "radeon\n");
546 static SENSOR_DEVICE_ATTR(temp1_input
, S_IRUGO
, radeon_hwmon_show_temp
, NULL
, 0);
547 static SENSOR_DEVICE_ATTR(name
, S_IRUGO
, radeon_hwmon_show_name
, NULL
, 0);
549 static struct attribute
*hwmon_attributes
[] = {
550 &sensor_dev_attr_temp1_input
.dev_attr
.attr
,
551 &sensor_dev_attr_name
.dev_attr
.attr
,
555 static const struct attribute_group hwmon_attrgroup
= {
556 .attrs
= hwmon_attributes
,
559 static int radeon_hwmon_init(struct radeon_device
*rdev
)
563 rdev
->pm
.int_hwmon_dev
= NULL
;
565 switch (rdev
->pm
.int_thermal_type
) {
566 case THERMAL_TYPE_RV6XX
:
567 case THERMAL_TYPE_RV770
:
568 case THERMAL_TYPE_EVERGREEN
:
569 case THERMAL_TYPE_NI
:
570 case THERMAL_TYPE_SUMO
:
571 case THERMAL_TYPE_SI
:
572 if (rdev
->asic
->pm
.get_temperature
== NULL
)
574 rdev
->pm
.int_hwmon_dev
= hwmon_device_register(rdev
->dev
);
575 if (IS_ERR(rdev
->pm
.int_hwmon_dev
)) {
576 err
= PTR_ERR(rdev
->pm
.int_hwmon_dev
);
578 "Unable to register hwmon device: %d\n", err
);
581 dev_set_drvdata(rdev
->pm
.int_hwmon_dev
, rdev
->ddev
);
582 err
= sysfs_create_group(&rdev
->pm
.int_hwmon_dev
->kobj
,
586 "Unable to create hwmon sysfs file: %d\n", err
);
587 hwmon_device_unregister(rdev
->dev
);
597 static void radeon_hwmon_fini(struct radeon_device
*rdev
)
599 if (rdev
->pm
.int_hwmon_dev
) {
600 sysfs_remove_group(&rdev
->pm
.int_hwmon_dev
->kobj
, &hwmon_attrgroup
);
601 hwmon_device_unregister(rdev
->pm
.int_hwmon_dev
);
605 static void radeon_dpm_thermal_work_handler(struct work_struct
*work
)
607 struct radeon_device
*rdev
=
608 container_of(work
, struct radeon_device
,
609 pm
.dpm
.thermal
.work
);
610 /* switch to the thermal state */
611 enum radeon_pm_state_type dpm_state
= POWER_STATE_TYPE_INTERNAL_THERMAL
;
613 if (!rdev
->pm
.dpm_enabled
)
616 if (rdev
->asic
->pm
.get_temperature
) {
617 int temp
= radeon_get_temperature(rdev
);
619 if (temp
< rdev
->pm
.dpm
.thermal
.min_temp
)
620 /* switch back the user state */
621 dpm_state
= rdev
->pm
.dpm
.user_state
;
623 if (rdev
->pm
.dpm
.thermal
.high_to_low
)
624 /* switch back the user state */
625 dpm_state
= rdev
->pm
.dpm
.user_state
;
627 radeon_dpm_enable_power_state(rdev
, dpm_state
);
630 static struct radeon_ps
*radeon_dpm_pick_power_state(struct radeon_device
*rdev
,
631 enum radeon_pm_state_type dpm_state
)
634 struct radeon_ps
*ps
;
636 bool single_display
= (rdev
->pm
.dpm
.new_active_crtc_count
< 2) ?
639 /* check if the vblank period is too short to adjust the mclk */
640 if (single_display
&& rdev
->asic
->dpm
.vblank_too_short
) {
641 if (radeon_dpm_vblank_too_short(rdev
))
642 single_display
= false;
645 /* certain older asics have a separare 3D performance state,
646 * so try that first if the user selected performance
648 if (dpm_state
== POWER_STATE_TYPE_PERFORMANCE
)
649 dpm_state
= POWER_STATE_TYPE_INTERNAL_3DPERF
;
650 /* balanced states don't exist at the moment */
651 if (dpm_state
== POWER_STATE_TYPE_BALANCED
)
652 dpm_state
= POWER_STATE_TYPE_PERFORMANCE
;
655 /* Pick the best power state based on current conditions */
656 for (i
= 0; i
< rdev
->pm
.dpm
.num_ps
; i
++) {
657 ps
= &rdev
->pm
.dpm
.ps
[i
];
658 ui_class
= ps
->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK
;
661 case POWER_STATE_TYPE_BATTERY
:
662 if (ui_class
== ATOM_PPLIB_CLASSIFICATION_UI_BATTERY
) {
663 if (ps
->caps
& ATOM_PPLIB_SINGLE_DISPLAY_ONLY
) {
670 case POWER_STATE_TYPE_BALANCED
:
671 if (ui_class
== ATOM_PPLIB_CLASSIFICATION_UI_BALANCED
) {
672 if (ps
->caps
& ATOM_PPLIB_SINGLE_DISPLAY_ONLY
) {
679 case POWER_STATE_TYPE_PERFORMANCE
:
680 if (ui_class
== ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE
) {
681 if (ps
->caps
& ATOM_PPLIB_SINGLE_DISPLAY_ONLY
) {
688 /* internal states */
689 case POWER_STATE_TYPE_INTERNAL_UVD
:
690 return rdev
->pm
.dpm
.uvd_ps
;
691 case POWER_STATE_TYPE_INTERNAL_UVD_SD
:
692 if (ps
->class & ATOM_PPLIB_CLASSIFICATION_SDSTATE
)
695 case POWER_STATE_TYPE_INTERNAL_UVD_HD
:
696 if (ps
->class & ATOM_PPLIB_CLASSIFICATION_HDSTATE
)
699 case POWER_STATE_TYPE_INTERNAL_UVD_HD2
:
700 if (ps
->class & ATOM_PPLIB_CLASSIFICATION_HD2STATE
)
703 case POWER_STATE_TYPE_INTERNAL_UVD_MVC
:
704 if (ps
->class2
& ATOM_PPLIB_CLASSIFICATION2_MVC
)
707 case POWER_STATE_TYPE_INTERNAL_BOOT
:
708 return rdev
->pm
.dpm
.boot_ps
;
709 case POWER_STATE_TYPE_INTERNAL_THERMAL
:
710 if (ps
->class & ATOM_PPLIB_CLASSIFICATION_THERMAL
)
713 case POWER_STATE_TYPE_INTERNAL_ACPI
:
714 if (ps
->class & ATOM_PPLIB_CLASSIFICATION_ACPI
)
717 case POWER_STATE_TYPE_INTERNAL_ULV
:
718 if (ps
->class2
& ATOM_PPLIB_CLASSIFICATION2_ULV
)
721 case POWER_STATE_TYPE_INTERNAL_3DPERF
:
722 if (ps
->class & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE
)
729 /* use a fallback state if we didn't match */
731 case POWER_STATE_TYPE_INTERNAL_UVD_SD
:
732 case POWER_STATE_TYPE_INTERNAL_UVD_HD
:
733 case POWER_STATE_TYPE_INTERNAL_UVD_HD2
:
734 case POWER_STATE_TYPE_INTERNAL_UVD_MVC
:
735 return rdev
->pm
.dpm
.uvd_ps
;
736 case POWER_STATE_TYPE_INTERNAL_THERMAL
:
737 dpm_state
= POWER_STATE_TYPE_INTERNAL_ACPI
;
739 case POWER_STATE_TYPE_INTERNAL_ACPI
:
740 dpm_state
= POWER_STATE_TYPE_BATTERY
;
742 case POWER_STATE_TYPE_BATTERY
:
743 case POWER_STATE_TYPE_BALANCED
:
744 case POWER_STATE_TYPE_INTERNAL_3DPERF
:
745 dpm_state
= POWER_STATE_TYPE_PERFORMANCE
;
754 static void radeon_dpm_change_power_state_locked(struct radeon_device
*rdev
)
757 struct radeon_ps
*ps
;
758 enum radeon_pm_state_type dpm_state
;
761 /* if dpm init failed */
762 if (!rdev
->pm
.dpm_enabled
)
765 if (rdev
->pm
.dpm
.user_state
!= rdev
->pm
.dpm
.state
) {
766 /* add other state override checks here */
767 if ((!rdev
->pm
.dpm
.thermal_active
) &&
768 (!rdev
->pm
.dpm
.uvd_active
))
769 rdev
->pm
.dpm
.state
= rdev
->pm
.dpm
.user_state
;
771 dpm_state
= rdev
->pm
.dpm
.state
;
773 ps
= radeon_dpm_pick_power_state(rdev
, dpm_state
);
775 rdev
->pm
.dpm
.requested_ps
= ps
;
779 /* no need to reprogram if nothing changed unless we are on BTC+ */
780 if (rdev
->pm
.dpm
.current_ps
== rdev
->pm
.dpm
.requested_ps
) {
781 if ((rdev
->family
< CHIP_BARTS
) || (rdev
->flags
& RADEON_IS_IGP
)) {
782 /* for pre-BTC and APUs if the num crtcs changed but state is the same,
783 * all we need to do is update the display configuration.
785 if (rdev
->pm
.dpm
.new_active_crtcs
!= rdev
->pm
.dpm
.current_active_crtcs
) {
786 /* update display watermarks based on new power state */
787 radeon_bandwidth_update(rdev
);
788 /* update displays */
789 radeon_dpm_display_configuration_changed(rdev
);
790 rdev
->pm
.dpm
.current_active_crtcs
= rdev
->pm
.dpm
.new_active_crtcs
;
791 rdev
->pm
.dpm
.current_active_crtc_count
= rdev
->pm
.dpm
.new_active_crtc_count
;
795 /* for BTC+ if the num crtcs hasn't changed and state is the same,
796 * nothing to do, if the num crtcs is > 1 and state is the same,
797 * update display configuration.
799 if (rdev
->pm
.dpm
.new_active_crtcs
==
800 rdev
->pm
.dpm
.current_active_crtcs
) {
803 if ((rdev
->pm
.dpm
.current_active_crtc_count
> 1) &&
804 (rdev
->pm
.dpm
.new_active_crtc_count
> 1)) {
805 /* update display watermarks based on new power state */
806 radeon_bandwidth_update(rdev
);
807 /* update displays */
808 radeon_dpm_display_configuration_changed(rdev
);
809 rdev
->pm
.dpm
.current_active_crtcs
= rdev
->pm
.dpm
.new_active_crtcs
;
810 rdev
->pm
.dpm
.current_active_crtc_count
= rdev
->pm
.dpm
.new_active_crtc_count
;
817 printk("switching from power state:\n");
818 radeon_dpm_print_power_state(rdev
, rdev
->pm
.dpm
.current_ps
);
819 printk("switching to power state:\n");
820 radeon_dpm_print_power_state(rdev
, rdev
->pm
.dpm
.requested_ps
);
822 mutex_lock(&rdev
->ddev
->struct_mutex
);
823 down_write(&rdev
->pm
.mclk_lock
);
824 mutex_lock(&rdev
->ring_lock
);
826 ret
= radeon_dpm_pre_set_power_state(rdev
);
830 /* update display watermarks based on new power state */
831 radeon_bandwidth_update(rdev
);
832 /* update displays */
833 radeon_dpm_display_configuration_changed(rdev
);
835 rdev
->pm
.dpm
.current_active_crtcs
= rdev
->pm
.dpm
.new_active_crtcs
;
836 rdev
->pm
.dpm
.current_active_crtc_count
= rdev
->pm
.dpm
.new_active_crtc_count
;
838 /* wait for the rings to drain */
839 for (i
= 0; i
< RADEON_NUM_RINGS
; i
++) {
840 struct radeon_ring
*ring
= &rdev
->ring
[i
];
842 radeon_fence_wait_empty_locked(rdev
, i
);
845 /* program the new power state */
846 radeon_dpm_set_power_state(rdev
);
848 /* update current power state */
849 rdev
->pm
.dpm
.current_ps
= rdev
->pm
.dpm
.requested_ps
;
851 radeon_dpm_post_set_power_state(rdev
);
854 mutex_unlock(&rdev
->ring_lock
);
855 up_write(&rdev
->pm
.mclk_lock
);
856 mutex_unlock(&rdev
->ddev
->struct_mutex
);
859 void radeon_dpm_enable_power_state(struct radeon_device
*rdev
,
860 enum radeon_pm_state_type dpm_state
)
862 if (!rdev
->pm
.dpm_enabled
)
865 mutex_lock(&rdev
->pm
.mutex
);
867 case POWER_STATE_TYPE_INTERNAL_THERMAL
:
868 rdev
->pm
.dpm
.thermal_active
= true;
870 case POWER_STATE_TYPE_INTERNAL_UVD
:
871 case POWER_STATE_TYPE_INTERNAL_UVD_SD
:
872 case POWER_STATE_TYPE_INTERNAL_UVD_HD
:
873 case POWER_STATE_TYPE_INTERNAL_UVD_HD2
:
874 case POWER_STATE_TYPE_INTERNAL_UVD_MVC
:
875 rdev
->pm
.dpm
.uvd_active
= true;
878 rdev
->pm
.dpm
.thermal_active
= false;
879 rdev
->pm
.dpm
.uvd_active
= false;
882 rdev
->pm
.dpm
.state
= dpm_state
;
883 mutex_unlock(&rdev
->pm
.mutex
);
884 radeon_pm_compute_clocks(rdev
);
887 static void radeon_pm_suspend_old(struct radeon_device
*rdev
)
889 mutex_lock(&rdev
->pm
.mutex
);
890 if (rdev
->pm
.pm_method
== PM_METHOD_DYNPM
) {
891 if (rdev
->pm
.dynpm_state
== DYNPM_STATE_ACTIVE
)
892 rdev
->pm
.dynpm_state
= DYNPM_STATE_SUSPENDED
;
894 mutex_unlock(&rdev
->pm
.mutex
);
896 cancel_delayed_work_sync(&rdev
->pm
.dynpm_idle_work
);
899 static void radeon_pm_suspend_dpm(struct radeon_device
*rdev
)
901 mutex_lock(&rdev
->pm
.mutex
);
903 radeon_dpm_disable(rdev
);
904 /* reset the power state */
905 rdev
->pm
.dpm
.current_ps
= rdev
->pm
.dpm
.requested_ps
= rdev
->pm
.dpm
.boot_ps
;
906 rdev
->pm
.dpm_enabled
= false;
907 mutex_unlock(&rdev
->pm
.mutex
);
910 void radeon_pm_suspend(struct radeon_device
*rdev
)
912 if (rdev
->pm
.pm_method
== PM_METHOD_DPM
)
913 radeon_pm_suspend_dpm(rdev
);
915 radeon_pm_suspend_old(rdev
);
918 static void radeon_pm_resume_old(struct radeon_device
*rdev
)
920 /* set up the default clocks if the MC ucode is loaded */
921 if ((rdev
->family
>= CHIP_BARTS
) &&
922 (rdev
->family
<= CHIP_HAINAN
) &&
924 if (rdev
->pm
.default_vddc
)
925 radeon_atom_set_voltage(rdev
, rdev
->pm
.default_vddc
,
926 SET_VOLTAGE_TYPE_ASIC_VDDC
);
927 if (rdev
->pm
.default_vddci
)
928 radeon_atom_set_voltage(rdev
, rdev
->pm
.default_vddci
,
929 SET_VOLTAGE_TYPE_ASIC_VDDCI
);
930 if (rdev
->pm
.default_sclk
)
931 radeon_set_engine_clock(rdev
, rdev
->pm
.default_sclk
);
932 if (rdev
->pm
.default_mclk
)
933 radeon_set_memory_clock(rdev
, rdev
->pm
.default_mclk
);
935 /* asic init will reset the default power state */
936 mutex_lock(&rdev
->pm
.mutex
);
937 rdev
->pm
.current_power_state_index
= rdev
->pm
.default_power_state_index
;
938 rdev
->pm
.current_clock_mode_index
= 0;
939 rdev
->pm
.current_sclk
= rdev
->pm
.default_sclk
;
940 rdev
->pm
.current_mclk
= rdev
->pm
.default_mclk
;
941 rdev
->pm
.current_vddc
= rdev
->pm
.power_state
[rdev
->pm
.default_power_state_index
].clock_info
[0].voltage
.voltage
;
942 rdev
->pm
.current_vddci
= rdev
->pm
.power_state
[rdev
->pm
.default_power_state_index
].clock_info
[0].voltage
.vddci
;
943 if (rdev
->pm
.pm_method
== PM_METHOD_DYNPM
944 && rdev
->pm
.dynpm_state
== DYNPM_STATE_SUSPENDED
) {
945 rdev
->pm
.dynpm_state
= DYNPM_STATE_ACTIVE
;
946 schedule_delayed_work(&rdev
->pm
.dynpm_idle_work
,
947 msecs_to_jiffies(RADEON_IDLE_LOOP_MS
));
949 mutex_unlock(&rdev
->pm
.mutex
);
950 radeon_pm_compute_clocks(rdev
);
953 static void radeon_pm_resume_dpm(struct radeon_device
*rdev
)
957 /* asic init will reset to the boot state */
958 mutex_lock(&rdev
->pm
.mutex
);
959 rdev
->pm
.dpm
.current_ps
= rdev
->pm
.dpm
.requested_ps
= rdev
->pm
.dpm
.boot_ps
;
960 radeon_dpm_setup_asic(rdev
);
961 ret
= radeon_dpm_enable(rdev
);
962 mutex_unlock(&rdev
->pm
.mutex
);
964 DRM_ERROR("radeon: dpm resume failed\n");
965 if ((rdev
->family
>= CHIP_BARTS
) &&
966 (rdev
->family
<= CHIP_HAINAN
) &&
968 if (rdev
->pm
.default_vddc
)
969 radeon_atom_set_voltage(rdev
, rdev
->pm
.default_vddc
,
970 SET_VOLTAGE_TYPE_ASIC_VDDC
);
971 if (rdev
->pm
.default_vddci
)
972 radeon_atom_set_voltage(rdev
, rdev
->pm
.default_vddci
,
973 SET_VOLTAGE_TYPE_ASIC_VDDCI
);
974 if (rdev
->pm
.default_sclk
)
975 radeon_set_engine_clock(rdev
, rdev
->pm
.default_sclk
);
976 if (rdev
->pm
.default_mclk
)
977 radeon_set_memory_clock(rdev
, rdev
->pm
.default_mclk
);
980 rdev
->pm
.dpm_enabled
= true;
981 radeon_pm_compute_clocks(rdev
);
985 void radeon_pm_resume(struct radeon_device
*rdev
)
987 if (rdev
->pm
.pm_method
== PM_METHOD_DPM
)
988 radeon_pm_resume_dpm(rdev
);
990 radeon_pm_resume_old(rdev
);
993 static int radeon_pm_init_old(struct radeon_device
*rdev
)
997 rdev
->pm
.profile
= PM_PROFILE_DEFAULT
;
998 rdev
->pm
.dynpm_state
= DYNPM_STATE_DISABLED
;
999 rdev
->pm
.dynpm_planned_action
= DYNPM_ACTION_NONE
;
1000 rdev
->pm
.dynpm_can_upclock
= true;
1001 rdev
->pm
.dynpm_can_downclock
= true;
1002 rdev
->pm
.default_sclk
= rdev
->clock
.default_sclk
;
1003 rdev
->pm
.default_mclk
= rdev
->clock
.default_mclk
;
1004 rdev
->pm
.current_sclk
= rdev
->clock
.default_sclk
;
1005 rdev
->pm
.current_mclk
= rdev
->clock
.default_mclk
;
1006 rdev
->pm
.int_thermal_type
= THERMAL_TYPE_NONE
;
1009 if (rdev
->is_atom_bios
)
1010 radeon_atombios_get_power_modes(rdev
);
1012 radeon_combios_get_power_modes(rdev
);
1013 radeon_pm_print_states(rdev
);
1014 radeon_pm_init_profile(rdev
);
1015 /* set up the default clocks if the MC ucode is loaded */
1016 if ((rdev
->family
>= CHIP_BARTS
) &&
1017 (rdev
->family
<= CHIP_HAINAN
) &&
1019 if (rdev
->pm
.default_vddc
)
1020 radeon_atom_set_voltage(rdev
, rdev
->pm
.default_vddc
,
1021 SET_VOLTAGE_TYPE_ASIC_VDDC
);
1022 if (rdev
->pm
.default_vddci
)
1023 radeon_atom_set_voltage(rdev
, rdev
->pm
.default_vddci
,
1024 SET_VOLTAGE_TYPE_ASIC_VDDCI
);
1025 if (rdev
->pm
.default_sclk
)
1026 radeon_set_engine_clock(rdev
, rdev
->pm
.default_sclk
);
1027 if (rdev
->pm
.default_mclk
)
1028 radeon_set_memory_clock(rdev
, rdev
->pm
.default_mclk
);
1032 /* set up the internal thermal sensor if applicable */
1033 ret
= radeon_hwmon_init(rdev
);
1037 INIT_DELAYED_WORK(&rdev
->pm
.dynpm_idle_work
, radeon_dynpm_idle_work_handler
);
1039 if (rdev
->pm
.num_power_states
> 1) {
1040 /* where's the best place to put these? */
1041 ret
= device_create_file(rdev
->dev
, &dev_attr_power_profile
);
1043 DRM_ERROR("failed to create device file for power profile\n");
1044 ret
= device_create_file(rdev
->dev
, &dev_attr_power_method
);
1046 DRM_ERROR("failed to create device file for power method\n");
1048 if (radeon_debugfs_pm_init(rdev
)) {
1049 DRM_ERROR("Failed to register debugfs file for PM!\n");
1052 DRM_INFO("radeon: power management initialized\n");
1058 static void radeon_dpm_print_power_states(struct radeon_device
*rdev
)
1062 for (i
= 0; i
< rdev
->pm
.dpm
.num_ps
; i
++) {
1063 printk("== power state %d ==\n", i
);
1064 radeon_dpm_print_power_state(rdev
, &rdev
->pm
.dpm
.ps
[i
]);
1068 static int radeon_pm_init_dpm(struct radeon_device
*rdev
)
1072 /* default to performance state */
1073 rdev
->pm
.dpm
.state
= POWER_STATE_TYPE_BALANCED
;
1074 rdev
->pm
.dpm
.user_state
= POWER_STATE_TYPE_BALANCED
;
1075 rdev
->pm
.default_sclk
= rdev
->clock
.default_sclk
;
1076 rdev
->pm
.default_mclk
= rdev
->clock
.default_mclk
;
1077 rdev
->pm
.current_sclk
= rdev
->clock
.default_sclk
;
1078 rdev
->pm
.current_mclk
= rdev
->clock
.default_mclk
;
1079 rdev
->pm
.int_thermal_type
= THERMAL_TYPE_NONE
;
1081 if (rdev
->bios
&& rdev
->is_atom_bios
)
1082 radeon_atombios_get_power_modes(rdev
);
1086 /* set up the internal thermal sensor if applicable */
1087 ret
= radeon_hwmon_init(rdev
);
1091 INIT_WORK(&rdev
->pm
.dpm
.thermal
.work
, radeon_dpm_thermal_work_handler
);
1092 mutex_lock(&rdev
->pm
.mutex
);
1093 radeon_dpm_init(rdev
);
1094 rdev
->pm
.dpm
.current_ps
= rdev
->pm
.dpm
.requested_ps
= rdev
->pm
.dpm
.boot_ps
;
1095 radeon_dpm_print_power_states(rdev
);
1096 radeon_dpm_setup_asic(rdev
);
1097 ret
= radeon_dpm_enable(rdev
);
1098 mutex_unlock(&rdev
->pm
.mutex
);
1100 rdev
->pm
.dpm_enabled
= false;
1101 if ((rdev
->family
>= CHIP_BARTS
) &&
1102 (rdev
->family
<= CHIP_HAINAN
) &&
1104 if (rdev
->pm
.default_vddc
)
1105 radeon_atom_set_voltage(rdev
, rdev
->pm
.default_vddc
,
1106 SET_VOLTAGE_TYPE_ASIC_VDDC
);
1107 if (rdev
->pm
.default_vddci
)
1108 radeon_atom_set_voltage(rdev
, rdev
->pm
.default_vddci
,
1109 SET_VOLTAGE_TYPE_ASIC_VDDCI
);
1110 if (rdev
->pm
.default_sclk
)
1111 radeon_set_engine_clock(rdev
, rdev
->pm
.default_sclk
);
1112 if (rdev
->pm
.default_mclk
)
1113 radeon_set_memory_clock(rdev
, rdev
->pm
.default_mclk
);
1115 DRM_ERROR("radeon: dpm initialization failed\n");
1118 rdev
->pm
.dpm_enabled
= true;
1119 radeon_pm_compute_clocks(rdev
);
1121 if (rdev
->pm
.num_power_states
> 1) {
1122 ret
= device_create_file(rdev
->dev
, &dev_attr_power_dpm_state
);
1124 DRM_ERROR("failed to create device file for dpm state\n");
1125 ret
= device_create_file(rdev
->dev
, &dev_attr_power_dpm_force_performance_level
);
1127 DRM_ERROR("failed to create device file for dpm state\n");
1128 /* XXX: these are noops for dpm but are here for backwards compat */
1129 ret
= device_create_file(rdev
->dev
, &dev_attr_power_profile
);
1131 DRM_ERROR("failed to create device file for power profile\n");
1132 ret
= device_create_file(rdev
->dev
, &dev_attr_power_method
);
1134 DRM_ERROR("failed to create device file for power method\n");
1136 if (radeon_debugfs_pm_init(rdev
)) {
1137 DRM_ERROR("Failed to register debugfs file for dpm!\n");
1140 DRM_INFO("radeon: dpm initialized\n");
1146 int radeon_pm_init(struct radeon_device
*rdev
)
1148 /* enable dpm on rv6xx+ */
1149 switch (rdev
->family
) {
1179 if (radeon_dpm
== 1)
1180 rdev
->pm
.pm_method
= PM_METHOD_DPM
;
1182 rdev
->pm
.pm_method
= PM_METHOD_PROFILE
;
1185 /* default to profile method */
1186 rdev
->pm
.pm_method
= PM_METHOD_PROFILE
;
1190 if (rdev
->pm
.pm_method
== PM_METHOD_DPM
)
1191 return radeon_pm_init_dpm(rdev
);
1193 return radeon_pm_init_old(rdev
);
1196 static void radeon_pm_fini_old(struct radeon_device
*rdev
)
1198 if (rdev
->pm
.num_power_states
> 1) {
1199 mutex_lock(&rdev
->pm
.mutex
);
1200 if (rdev
->pm
.pm_method
== PM_METHOD_PROFILE
) {
1201 rdev
->pm
.profile
= PM_PROFILE_DEFAULT
;
1202 radeon_pm_update_profile(rdev
);
1203 radeon_pm_set_clocks(rdev
);
1204 } else if (rdev
->pm
.pm_method
== PM_METHOD_DYNPM
) {
1205 /* reset default clocks */
1206 rdev
->pm
.dynpm_state
= DYNPM_STATE_DISABLED
;
1207 rdev
->pm
.dynpm_planned_action
= DYNPM_ACTION_DEFAULT
;
1208 radeon_pm_set_clocks(rdev
);
1210 mutex_unlock(&rdev
->pm
.mutex
);
1212 cancel_delayed_work_sync(&rdev
->pm
.dynpm_idle_work
);
1214 device_remove_file(rdev
->dev
, &dev_attr_power_profile
);
1215 device_remove_file(rdev
->dev
, &dev_attr_power_method
);
1218 if (rdev
->pm
.power_state
)
1219 kfree(rdev
->pm
.power_state
);
1221 radeon_hwmon_fini(rdev
);
1224 static void radeon_pm_fini_dpm(struct radeon_device
*rdev
)
1226 if (rdev
->pm
.num_power_states
> 1) {
1227 mutex_lock(&rdev
->pm
.mutex
);
1228 radeon_dpm_disable(rdev
);
1229 mutex_unlock(&rdev
->pm
.mutex
);
1231 device_remove_file(rdev
->dev
, &dev_attr_power_dpm_state
);
1232 device_remove_file(rdev
->dev
, &dev_attr_power_dpm_force_performance_level
);
1233 /* XXX backwards compat */
1234 device_remove_file(rdev
->dev
, &dev_attr_power_profile
);
1235 device_remove_file(rdev
->dev
, &dev_attr_power_method
);
1237 radeon_dpm_fini(rdev
);
1239 if (rdev
->pm
.power_state
)
1240 kfree(rdev
->pm
.power_state
);
1242 radeon_hwmon_fini(rdev
);
1245 void radeon_pm_fini(struct radeon_device
*rdev
)
1247 if (rdev
->pm
.pm_method
== PM_METHOD_DPM
)
1248 radeon_pm_fini_dpm(rdev
);
1250 radeon_pm_fini_old(rdev
);
1253 static void radeon_pm_compute_clocks_old(struct radeon_device
*rdev
)
1255 struct drm_device
*ddev
= rdev
->ddev
;
1256 struct drm_crtc
*crtc
;
1257 struct radeon_crtc
*radeon_crtc
;
1259 if (rdev
->pm
.num_power_states
< 2)
1262 mutex_lock(&rdev
->pm
.mutex
);
1264 rdev
->pm
.active_crtcs
= 0;
1265 rdev
->pm
.active_crtc_count
= 0;
1266 list_for_each_entry(crtc
,
1267 &ddev
->mode_config
.crtc_list
, head
) {
1268 radeon_crtc
= to_radeon_crtc(crtc
);
1269 if (radeon_crtc
->enabled
) {
1270 rdev
->pm
.active_crtcs
|= (1 << radeon_crtc
->crtc_id
);
1271 rdev
->pm
.active_crtc_count
++;
1275 if (rdev
->pm
.pm_method
== PM_METHOD_PROFILE
) {
1276 radeon_pm_update_profile(rdev
);
1277 radeon_pm_set_clocks(rdev
);
1278 } else if (rdev
->pm
.pm_method
== PM_METHOD_DYNPM
) {
1279 if (rdev
->pm
.dynpm_state
!= DYNPM_STATE_DISABLED
) {
1280 if (rdev
->pm
.active_crtc_count
> 1) {
1281 if (rdev
->pm
.dynpm_state
== DYNPM_STATE_ACTIVE
) {
1282 cancel_delayed_work(&rdev
->pm
.dynpm_idle_work
);
1284 rdev
->pm
.dynpm_state
= DYNPM_STATE_PAUSED
;
1285 rdev
->pm
.dynpm_planned_action
= DYNPM_ACTION_DEFAULT
;
1286 radeon_pm_get_dynpm_state(rdev
);
1287 radeon_pm_set_clocks(rdev
);
1289 DRM_DEBUG_DRIVER("radeon: dynamic power management deactivated\n");
1291 } else if (rdev
->pm
.active_crtc_count
== 1) {
1292 /* TODO: Increase clocks if needed for current mode */
1294 if (rdev
->pm
.dynpm_state
== DYNPM_STATE_MINIMUM
) {
1295 rdev
->pm
.dynpm_state
= DYNPM_STATE_ACTIVE
;
1296 rdev
->pm
.dynpm_planned_action
= DYNPM_ACTION_UPCLOCK
;
1297 radeon_pm_get_dynpm_state(rdev
);
1298 radeon_pm_set_clocks(rdev
);
1300 schedule_delayed_work(&rdev
->pm
.dynpm_idle_work
,
1301 msecs_to_jiffies(RADEON_IDLE_LOOP_MS
));
1302 } else if (rdev
->pm
.dynpm_state
== DYNPM_STATE_PAUSED
) {
1303 rdev
->pm
.dynpm_state
= DYNPM_STATE_ACTIVE
;
1304 schedule_delayed_work(&rdev
->pm
.dynpm_idle_work
,
1305 msecs_to_jiffies(RADEON_IDLE_LOOP_MS
));
1306 DRM_DEBUG_DRIVER("radeon: dynamic power management activated\n");
1308 } else { /* count == 0 */
1309 if (rdev
->pm
.dynpm_state
!= DYNPM_STATE_MINIMUM
) {
1310 cancel_delayed_work(&rdev
->pm
.dynpm_idle_work
);
1312 rdev
->pm
.dynpm_state
= DYNPM_STATE_MINIMUM
;
1313 rdev
->pm
.dynpm_planned_action
= DYNPM_ACTION_MINIMUM
;
1314 radeon_pm_get_dynpm_state(rdev
);
1315 radeon_pm_set_clocks(rdev
);
1321 mutex_unlock(&rdev
->pm
.mutex
);
1324 static void radeon_pm_compute_clocks_dpm(struct radeon_device
*rdev
)
1326 struct drm_device
*ddev
= rdev
->ddev
;
1327 struct drm_crtc
*crtc
;
1328 struct radeon_crtc
*radeon_crtc
;
1330 mutex_lock(&rdev
->pm
.mutex
);
1332 /* update active crtc counts */
1333 rdev
->pm
.dpm
.new_active_crtcs
= 0;
1334 rdev
->pm
.dpm
.new_active_crtc_count
= 0;
1335 list_for_each_entry(crtc
,
1336 &ddev
->mode_config
.crtc_list
, head
) {
1337 radeon_crtc
= to_radeon_crtc(crtc
);
1338 if (crtc
->enabled
) {
1339 rdev
->pm
.dpm
.new_active_crtcs
|= (1 << radeon_crtc
->crtc_id
);
1340 rdev
->pm
.dpm
.new_active_crtc_count
++;
1344 /* update battery/ac status */
1345 if (power_supply_is_system_supplied() > 0)
1346 rdev
->pm
.dpm
.ac_power
= true;
1348 rdev
->pm
.dpm
.ac_power
= false;
1350 radeon_dpm_change_power_state_locked(rdev
);
1352 mutex_unlock(&rdev
->pm
.mutex
);
1356 void radeon_pm_compute_clocks(struct radeon_device
*rdev
)
1358 if (rdev
->pm
.pm_method
== PM_METHOD_DPM
)
1359 radeon_pm_compute_clocks_dpm(rdev
);
1361 radeon_pm_compute_clocks_old(rdev
);
1364 static bool radeon_pm_in_vbl(struct radeon_device
*rdev
)
1366 int crtc
, vpos
, hpos
, vbl_status
;
1369 /* Iterate over all active crtc's. All crtc's must be in vblank,
1370 * otherwise return in_vbl == false.
1372 for (crtc
= 0; (crtc
< rdev
->num_crtc
) && in_vbl
; crtc
++) {
1373 if (rdev
->pm
.active_crtcs
& (1 << crtc
)) {
1374 vbl_status
= radeon_get_crtc_scanoutpos(rdev
->ddev
, crtc
, &vpos
, &hpos
);
1375 if ((vbl_status
& DRM_SCANOUTPOS_VALID
) &&
1376 !(vbl_status
& DRM_SCANOUTPOS_INVBL
))
1384 static bool radeon_pm_debug_check_in_vbl(struct radeon_device
*rdev
, bool finish
)
1387 bool in_vbl
= radeon_pm_in_vbl(rdev
);
1389 if (in_vbl
== false)
1390 DRM_DEBUG_DRIVER("not in vbl for pm change %08x at %s\n", stat_crtc
,
1391 finish
? "exit" : "entry");
1395 static void radeon_dynpm_idle_work_handler(struct work_struct
*work
)
1397 struct radeon_device
*rdev
;
1399 rdev
= container_of(work
, struct radeon_device
,
1400 pm
.dynpm_idle_work
.work
);
1402 resched
= ttm_bo_lock_delayed_workqueue(&rdev
->mman
.bdev
);
1403 mutex_lock(&rdev
->pm
.mutex
);
1404 if (rdev
->pm
.dynpm_state
== DYNPM_STATE_ACTIVE
) {
1405 int not_processed
= 0;
1408 for (i
= 0; i
< RADEON_NUM_RINGS
; ++i
) {
1409 struct radeon_ring
*ring
= &rdev
->ring
[i
];
1412 not_processed
+= radeon_fence_count_emitted(rdev
, i
);
1413 if (not_processed
>= 3)
1418 if (not_processed
>= 3) { /* should upclock */
1419 if (rdev
->pm
.dynpm_planned_action
== DYNPM_ACTION_DOWNCLOCK
) {
1420 rdev
->pm
.dynpm_planned_action
= DYNPM_ACTION_NONE
;
1421 } else if (rdev
->pm
.dynpm_planned_action
== DYNPM_ACTION_NONE
&&
1422 rdev
->pm
.dynpm_can_upclock
) {
1423 rdev
->pm
.dynpm_planned_action
=
1424 DYNPM_ACTION_UPCLOCK
;
1425 rdev
->pm
.dynpm_action_timeout
= jiffies
+
1426 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS
);
1428 } else if (not_processed
== 0) { /* should downclock */
1429 if (rdev
->pm
.dynpm_planned_action
== DYNPM_ACTION_UPCLOCK
) {
1430 rdev
->pm
.dynpm_planned_action
= DYNPM_ACTION_NONE
;
1431 } else if (rdev
->pm
.dynpm_planned_action
== DYNPM_ACTION_NONE
&&
1432 rdev
->pm
.dynpm_can_downclock
) {
1433 rdev
->pm
.dynpm_planned_action
=
1434 DYNPM_ACTION_DOWNCLOCK
;
1435 rdev
->pm
.dynpm_action_timeout
= jiffies
+
1436 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS
);
1440 /* Note, radeon_pm_set_clocks is called with static_switch set
1441 * to false since we want to wait for vbl to avoid flicker.
1443 if (rdev
->pm
.dynpm_planned_action
!= DYNPM_ACTION_NONE
&&
1444 jiffies
> rdev
->pm
.dynpm_action_timeout
) {
1445 radeon_pm_get_dynpm_state(rdev
);
1446 radeon_pm_set_clocks(rdev
);
1449 schedule_delayed_work(&rdev
->pm
.dynpm_idle_work
,
1450 msecs_to_jiffies(RADEON_IDLE_LOOP_MS
));
1452 mutex_unlock(&rdev
->pm
.mutex
);
1453 ttm_bo_unlock_delayed_workqueue(&rdev
->mman
.bdev
, resched
);
1459 #if defined(CONFIG_DEBUG_FS)
1461 static int radeon_debugfs_pm_info(struct seq_file
*m
, void *data
)
1463 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
1464 struct drm_device
*dev
= node
->minor
->dev
;
1465 struct radeon_device
*rdev
= dev
->dev_private
;
1467 if (rdev
->pm
.dpm_enabled
) {
1468 mutex_lock(&rdev
->pm
.mutex
);
1469 if (rdev
->asic
->dpm
.debugfs_print_current_performance_level
)
1470 radeon_dpm_debugfs_print_current_performance_level(rdev
, m
);
1472 seq_printf(m
, "Debugfs support not implemented for this asic\n");
1473 mutex_unlock(&rdev
->pm
.mutex
);
1475 seq_printf(m
, "default engine clock: %u0 kHz\n", rdev
->pm
.default_sclk
);
1476 /* radeon_get_engine_clock is not reliable on APUs so just print the current clock */
1477 if ((rdev
->family
>= CHIP_PALM
) && (rdev
->flags
& RADEON_IS_IGP
))
1478 seq_printf(m
, "current engine clock: %u0 kHz\n", rdev
->pm
.current_sclk
);
1480 seq_printf(m
, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev
));
1481 seq_printf(m
, "default memory clock: %u0 kHz\n", rdev
->pm
.default_mclk
);
1482 if (rdev
->asic
->pm
.get_memory_clock
)
1483 seq_printf(m
, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev
));
1484 if (rdev
->pm
.current_vddc
)
1485 seq_printf(m
, "voltage: %u mV\n", rdev
->pm
.current_vddc
);
1486 if (rdev
->asic
->pm
.get_pcie_lanes
)
1487 seq_printf(m
, "PCIE lanes: %d\n", radeon_get_pcie_lanes(rdev
));
1493 static struct drm_info_list radeon_pm_info_list
[] = {
1494 {"radeon_pm_info", radeon_debugfs_pm_info
, 0, NULL
},
1498 static int radeon_debugfs_pm_init(struct radeon_device
*rdev
)
1500 #if defined(CONFIG_DEBUG_FS)
1501 return radeon_debugfs_add_files(rdev
, radeon_pm_info_list
, ARRAY_SIZE(radeon_pm_info_list
));