2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
29 #include <linux/seq_file.h>
30 #include <linux/slab.h>
32 #include <drm/radeon_drm.h>
33 #include "radeon_reg.h"
39 * IBs (Indirect Buffers) and areas of GPU accessible memory where
40 * commands are stored. You can put a pointer to the IB in the
41 * command ring and the hw will fetch the commands from the IB
42 * and execute them. Generally userspace acceleration drivers
43 * produce command buffers which are send to the kernel and
44 * put in IBs for execution by the requested ring.
46 static int radeon_debugfs_sa_init(struct radeon_device
*rdev
);
49 * radeon_ib_get - request an IB (Indirect Buffer)
51 * @rdev: radeon_device pointer
52 * @ring: ring index the IB is associated with
53 * @ib: IB object returned
54 * @size: requested IB size
56 * Request an IB (all asics). IBs are allocated using the
58 * Returns 0 on success, error on failure.
60 int radeon_ib_get(struct radeon_device
*rdev
, int ring
,
61 struct radeon_ib
*ib
, struct radeon_vm
*vm
,
66 r
= radeon_sa_bo_new(rdev
, &rdev
->ring_tmp_bo
, &ib
->sa_bo
, size
, 256);
68 dev_err(rdev
->dev
, "failed to get a new IB (%d)\n", r
);
72 r
= radeon_semaphore_create(rdev
, &ib
->semaphore
);
79 ib
->ptr
= radeon_sa_bo_cpu_addr(ib
->sa_bo
);
82 /* ib pool is bound at RADEON_VA_IB_OFFSET in virtual address
83 * space and soffset is the offset inside the pool bo
85 ib
->gpu_addr
= ib
->sa_bo
->soffset
+ RADEON_VA_IB_OFFSET
;
87 ib
->gpu_addr
= radeon_sa_bo_gpu_addr(ib
->sa_bo
);
89 ib
->is_const_ib
= false;
95 * radeon_ib_free - free an IB (Indirect Buffer)
97 * @rdev: radeon_device pointer
98 * @ib: IB object to free
100 * Free an IB (all asics).
102 void radeon_ib_free(struct radeon_device
*rdev
, struct radeon_ib
*ib
)
104 radeon_semaphore_free(rdev
, &ib
->semaphore
, ib
->fence
);
105 radeon_sa_bo_free(rdev
, &ib
->sa_bo
, ib
->fence
);
106 radeon_fence_unref(&ib
->fence
);
110 * radeon_ib_schedule - schedule an IB (Indirect Buffer) on the ring
112 * @rdev: radeon_device pointer
113 * @ib: IB object to schedule
114 * @const_ib: Const IB to schedule (SI only)
116 * Schedule an IB on the associated ring (all asics).
117 * Returns 0 on success, error on failure.
119 * On SI, there are two parallel engines fed from the primary ring,
120 * the CE (Constant Engine) and the DE (Drawing Engine). Since
121 * resource descriptors have moved to memory, the CE allows you to
122 * prime the caches while the DE is updating register state so that
123 * the resource descriptors will be already in cache when the draw is
124 * processed. To accomplish this, the userspace driver submits two
125 * IBs, one for the CE and one for the DE. If there is a CE IB (called
126 * a CONST_IB), it will be put on the ring prior to the DE IB. Prior
127 * to SI there was just a DE IB.
129 int radeon_ib_schedule(struct radeon_device
*rdev
, struct radeon_ib
*ib
,
130 struct radeon_ib
*const_ib
)
132 struct radeon_ring
*ring
= &rdev
->ring
[ib
->ring
];
135 if (!ib
->length_dw
|| !ring
->ready
) {
136 /* TODO: Nothings in the ib we should report. */
137 dev_err(rdev
->dev
, "couldn't schedule ib\n");
141 /* 64 dwords should be enough for fence too */
142 r
= radeon_ring_lock(rdev
, ring
, 64 + RADEON_NUM_SYNCS
* 8);
144 dev_err(rdev
->dev
, "scheduling IB failed (%d).\n", r
);
148 /* grab a vm id if necessary */
150 struct radeon_fence
*vm_id_fence
;
151 vm_id_fence
= radeon_vm_grab_id(rdev
, ib
->vm
, ib
->ring
);
152 radeon_semaphore_sync_to(ib
->semaphore
, vm_id_fence
);
155 /* sync with other rings */
156 r
= radeon_semaphore_sync_rings(rdev
, ib
->semaphore
, ib
->ring
);
158 dev_err(rdev
->dev
, "failed to sync rings (%d)\n", r
);
159 radeon_ring_unlock_undo(rdev
, ring
);
164 radeon_vm_flush(rdev
, ib
->vm
, ib
->ring
);
167 radeon_ring_ib_execute(rdev
, const_ib
->ring
, const_ib
);
168 radeon_semaphore_free(rdev
, &const_ib
->semaphore
, NULL
);
170 radeon_ring_ib_execute(rdev
, ib
->ring
, ib
);
171 r
= radeon_fence_emit(rdev
, &ib
->fence
, ib
->ring
);
173 dev_err(rdev
->dev
, "failed to emit fence for new IB (%d)\n", r
);
174 radeon_ring_unlock_undo(rdev
, ring
);
178 const_ib
->fence
= radeon_fence_ref(ib
->fence
);
182 radeon_vm_fence(rdev
, ib
->vm
, ib
->fence
);
184 radeon_ring_unlock_commit(rdev
, ring
);
189 * radeon_ib_pool_init - Init the IB (Indirect Buffer) pool
191 * @rdev: radeon_device pointer
193 * Initialize the suballocator to manage a pool of memory
194 * for use as IBs (all asics).
195 * Returns 0 on success, error on failure.
197 int radeon_ib_pool_init(struct radeon_device
*rdev
)
201 if (rdev
->ib_pool_ready
) {
204 r
= radeon_sa_bo_manager_init(rdev
, &rdev
->ring_tmp_bo
,
205 RADEON_IB_POOL_SIZE
*64*1024,
206 RADEON_GPU_PAGE_SIZE
,
207 RADEON_GEM_DOMAIN_GTT
);
212 r
= radeon_sa_bo_manager_start(rdev
, &rdev
->ring_tmp_bo
);
217 rdev
->ib_pool_ready
= true;
218 if (radeon_debugfs_sa_init(rdev
)) {
219 dev_err(rdev
->dev
, "failed to register debugfs file for SA\n");
225 * radeon_ib_pool_fini - Free the IB (Indirect Buffer) pool
227 * @rdev: radeon_device pointer
229 * Tear down the suballocator managing the pool of memory
230 * for use as IBs (all asics).
232 void radeon_ib_pool_fini(struct radeon_device
*rdev
)
234 if (rdev
->ib_pool_ready
) {
235 radeon_sa_bo_manager_suspend(rdev
, &rdev
->ring_tmp_bo
);
236 radeon_sa_bo_manager_fini(rdev
, &rdev
->ring_tmp_bo
);
237 rdev
->ib_pool_ready
= false;
242 * radeon_ib_ring_tests - test IBs on the rings
244 * @rdev: radeon_device pointer
246 * Test an IB (Indirect Buffer) on each ring.
247 * If the test fails, disable the ring.
248 * Returns 0 on success, error if the primary GFX ring
251 int radeon_ib_ring_tests(struct radeon_device
*rdev
)
256 for (i
= 0; i
< RADEON_NUM_RINGS
; ++i
) {
257 struct radeon_ring
*ring
= &rdev
->ring
[i
];
262 r
= radeon_ib_test(rdev
, i
, ring
);
266 if (i
== RADEON_RING_TYPE_GFX_INDEX
) {
267 /* oh, oh, that's really bad */
268 DRM_ERROR("radeon: failed testing IB on GFX ring (%d).\n", r
);
269 rdev
->accel_working
= false;
273 /* still not good, but we can live with it */
274 DRM_ERROR("radeon: failed testing IB on ring %d (%d).\n", i
, r
);
283 * Most engines on the GPU are fed via ring buffers. Ring
284 * buffers are areas of GPU accessible memory that the host
285 * writes commands into and the GPU reads commands out of.
286 * There is a rptr (read pointer) that determines where the
287 * GPU is currently reading, and a wptr (write pointer)
288 * which determines where the host has written. When the
289 * pointers are equal, the ring is idle. When the host
290 * writes commands to the ring buffer, it increments the
291 * wptr. The GPU then starts fetching commands and executes
292 * them until the pointers are equal again.
294 static int radeon_debugfs_ring_init(struct radeon_device
*rdev
, struct radeon_ring
*ring
);
297 * radeon_ring_write - write a value to the ring
299 * @ring: radeon_ring structure holding ring information
300 * @v: dword (dw) value to write
302 * Write a value to the requested ring buffer (all asics).
304 void radeon_ring_write(struct radeon_ring
*ring
, uint32_t v
)
307 if (ring
->count_dw
<= 0) {
308 DRM_ERROR("radeon: writing more dwords to the ring than expected!\n");
311 ring
->ring
[ring
->wptr
++] = v
;
312 ring
->wptr
&= ring
->ptr_mask
;
314 ring
->ring_free_dw
--;
318 * radeon_ring_supports_scratch_reg - check if the ring supports
319 * writing to scratch registers
321 * @rdev: radeon_device pointer
322 * @ring: radeon_ring structure holding ring information
324 * Check if a specific ring supports writing to scratch registers (all asics).
325 * Returns true if the ring supports writing to scratch regs, false if not.
327 bool radeon_ring_supports_scratch_reg(struct radeon_device
*rdev
,
328 struct radeon_ring
*ring
)
331 case RADEON_RING_TYPE_GFX_INDEX
:
332 case CAYMAN_RING_TYPE_CP1_INDEX
:
333 case CAYMAN_RING_TYPE_CP2_INDEX
:
341 * radeon_ring_free_size - update the free size
343 * @rdev: radeon_device pointer
344 * @ring: radeon_ring structure holding ring information
346 * Update the free dw slots in the ring buffer (all asics).
348 void radeon_ring_free_size(struct radeon_device
*rdev
, struct radeon_ring
*ring
)
350 uint32_t rptr
= radeon_ring_get_rptr(rdev
, ring
);
352 /* This works because ring_size is a power of 2 */
353 ring
->ring_free_dw
= rptr
+ (ring
->ring_size
/ 4);
354 ring
->ring_free_dw
-= ring
->wptr
;
355 ring
->ring_free_dw
&= ring
->ptr_mask
;
356 if (!ring
->ring_free_dw
) {
357 /* this is an empty ring */
358 ring
->ring_free_dw
= ring
->ring_size
/ 4;
359 /* update lockup info to avoid false positive */
360 radeon_ring_lockup_update(rdev
, ring
);
365 * radeon_ring_alloc - allocate space on the ring buffer
367 * @rdev: radeon_device pointer
368 * @ring: radeon_ring structure holding ring information
369 * @ndw: number of dwords to allocate in the ring buffer
371 * Allocate @ndw dwords in the ring buffer (all asics).
372 * Returns 0 on success, error on failure.
374 int radeon_ring_alloc(struct radeon_device
*rdev
, struct radeon_ring
*ring
, unsigned ndw
)
378 /* make sure we aren't trying to allocate more space than there is on the ring */
379 if (ndw
> (ring
->ring_size
/ 4))
381 /* Align requested size with padding so unlock_commit can
383 radeon_ring_free_size(rdev
, ring
);
384 ndw
= (ndw
+ ring
->align_mask
) & ~ring
->align_mask
;
385 while (ndw
> (ring
->ring_free_dw
- 1)) {
386 radeon_ring_free_size(rdev
, ring
);
387 if (ndw
< ring
->ring_free_dw
) {
390 r
= radeon_fence_wait_next(rdev
, ring
->idx
);
394 ring
->count_dw
= ndw
;
395 ring
->wptr_old
= ring
->wptr
;
400 * radeon_ring_lock - lock the ring and allocate space on it
402 * @rdev: radeon_device pointer
403 * @ring: radeon_ring structure holding ring information
404 * @ndw: number of dwords to allocate in the ring buffer
406 * Lock the ring and allocate @ndw dwords in the ring buffer
408 * Returns 0 on success, error on failure.
410 int radeon_ring_lock(struct radeon_device
*rdev
, struct radeon_ring
*ring
, unsigned ndw
)
414 mutex_lock(&rdev
->ring_lock
);
415 r
= radeon_ring_alloc(rdev
, ring
, ndw
);
417 mutex_unlock(&rdev
->ring_lock
);
424 * radeon_ring_commit - tell the GPU to execute the new
425 * commands on the ring buffer
427 * @rdev: radeon_device pointer
428 * @ring: radeon_ring structure holding ring information
430 * Update the wptr (write pointer) to tell the GPU to
431 * execute new commands on the ring buffer (all asics).
433 void radeon_ring_commit(struct radeon_device
*rdev
, struct radeon_ring
*ring
)
435 /* We pad to match fetch size */
436 while (ring
->wptr
& ring
->align_mask
) {
437 radeon_ring_write(ring
, ring
->nop
);
440 radeon_ring_set_wptr(rdev
, ring
);
444 * radeon_ring_unlock_commit - tell the GPU to execute the new
445 * commands on the ring buffer and unlock it
447 * @rdev: radeon_device pointer
448 * @ring: radeon_ring structure holding ring information
450 * Call radeon_ring_commit() then unlock the ring (all asics).
452 void radeon_ring_unlock_commit(struct radeon_device
*rdev
, struct radeon_ring
*ring
)
454 radeon_ring_commit(rdev
, ring
);
455 mutex_unlock(&rdev
->ring_lock
);
459 * radeon_ring_undo - reset the wptr
461 * @ring: radeon_ring structure holding ring information
463 * Reset the driver's copy of the wptr (all asics).
465 void radeon_ring_undo(struct radeon_ring
*ring
)
467 ring
->wptr
= ring
->wptr_old
;
471 * radeon_ring_unlock_undo - reset the wptr and unlock the ring
473 * @ring: radeon_ring structure holding ring information
475 * Call radeon_ring_undo() then unlock the ring (all asics).
477 void radeon_ring_unlock_undo(struct radeon_device
*rdev
, struct radeon_ring
*ring
)
479 radeon_ring_undo(ring
);
480 mutex_unlock(&rdev
->ring_lock
);
484 * radeon_ring_lockup_update - update lockup variables
486 * @ring: radeon_ring structure holding ring information
488 * Update the last rptr value and timestamp (all asics).
490 void radeon_ring_lockup_update(struct radeon_device
*rdev
,
491 struct radeon_ring
*ring
)
493 atomic_set(&ring
->last_rptr
, radeon_ring_get_rptr(rdev
, ring
));
494 atomic64_set(&ring
->last_activity
, jiffies_64
);
498 * radeon_ring_test_lockup() - check if ring is lockedup by recording information
499 * @rdev: radeon device structure
500 * @ring: radeon_ring structure holding ring information
503 bool radeon_ring_test_lockup(struct radeon_device
*rdev
, struct radeon_ring
*ring
)
505 uint32_t rptr
= radeon_ring_get_rptr(rdev
, ring
);
506 uint64_t last
= atomic64_read(&ring
->last_activity
);
509 if (rptr
!= atomic_read(&ring
->last_rptr
)) {
510 /* ring is still working, no lockup */
511 radeon_ring_lockup_update(rdev
, ring
);
515 elapsed
= jiffies_to_msecs(jiffies_64
- last
);
516 if (radeon_lockup_timeout
&& elapsed
>= radeon_lockup_timeout
) {
517 dev_err(rdev
->dev
, "ring %d stalled for more than %llumsec\n",
521 /* give a chance to the GPU ... */
526 * radeon_ring_backup - Back up the content of a ring
528 * @rdev: radeon_device pointer
529 * @ring: the ring we want to back up
531 * Saves all unprocessed commits from a ring, returns the number of dwords saved.
533 unsigned radeon_ring_backup(struct radeon_device
*rdev
, struct radeon_ring
*ring
,
536 unsigned size
, ptr
, i
;
538 /* just in case lock the ring */
539 mutex_lock(&rdev
->ring_lock
);
542 if (ring
->ring_obj
== NULL
) {
543 mutex_unlock(&rdev
->ring_lock
);
547 /* it doesn't make sense to save anything if all fences are signaled */
548 if (!radeon_fence_count_emitted(rdev
, ring
->idx
)) {
549 mutex_unlock(&rdev
->ring_lock
);
553 /* calculate the number of dw on the ring */
554 if (ring
->rptr_save_reg
)
555 ptr
= RREG32(ring
->rptr_save_reg
);
556 else if (rdev
->wb
.enabled
)
557 ptr
= le32_to_cpu(*ring
->next_rptr_cpu_addr
);
559 /* no way to read back the next rptr */
560 mutex_unlock(&rdev
->ring_lock
);
564 size
= ring
->wptr
+ (ring
->ring_size
/ 4);
566 size
&= ring
->ptr_mask
;
568 mutex_unlock(&rdev
->ring_lock
);
572 /* and then save the content of the ring */
573 *data
= kmalloc_array(size
, sizeof(uint32_t), GFP_KERNEL
);
575 mutex_unlock(&rdev
->ring_lock
);
578 for (i
= 0; i
< size
; ++i
) {
579 (*data
)[i
] = ring
->ring
[ptr
++];
580 ptr
&= ring
->ptr_mask
;
583 mutex_unlock(&rdev
->ring_lock
);
588 * radeon_ring_restore - append saved commands to the ring again
590 * @rdev: radeon_device pointer
591 * @ring: ring to append commands to
592 * @size: number of dwords we want to write
593 * @data: saved commands
595 * Allocates space on the ring and restore the previously saved commands.
597 int radeon_ring_restore(struct radeon_device
*rdev
, struct radeon_ring
*ring
,
598 unsigned size
, uint32_t *data
)
605 /* restore the saved ring content */
606 r
= radeon_ring_lock(rdev
, ring
, size
);
610 for (i
= 0; i
< size
; ++i
) {
611 radeon_ring_write(ring
, data
[i
]);
614 radeon_ring_unlock_commit(rdev
, ring
);
620 * radeon_ring_init - init driver ring struct.
622 * @rdev: radeon_device pointer
623 * @ring: radeon_ring structure holding ring information
624 * @ring_size: size of the ring
625 * @rptr_offs: offset of the rptr writeback location in the WB buffer
626 * @nop: nop packet for this ring
628 * Initialize the driver information for the selected ring (all asics).
629 * Returns 0 on success, error on failure.
631 int radeon_ring_init(struct radeon_device
*rdev
, struct radeon_ring
*ring
, unsigned ring_size
,
632 unsigned rptr_offs
, u32 nop
)
636 ring
->ring_size
= ring_size
;
637 ring
->rptr_offs
= rptr_offs
;
639 /* Allocate ring buffer */
640 if (ring
->ring_obj
== NULL
) {
641 r
= radeon_bo_create(rdev
, ring
->ring_size
, PAGE_SIZE
, true,
642 RADEON_GEM_DOMAIN_GTT
,
643 NULL
, &ring
->ring_obj
);
645 dev_err(rdev
->dev
, "(%d) ring create failed\n", r
);
648 r
= radeon_bo_reserve(ring
->ring_obj
, false);
649 if (unlikely(r
!= 0))
651 r
= radeon_bo_pin(ring
->ring_obj
, RADEON_GEM_DOMAIN_GTT
,
654 radeon_bo_unreserve(ring
->ring_obj
);
655 dev_err(rdev
->dev
, "(%d) ring pin failed\n", r
);
658 r
= radeon_bo_kmap(ring
->ring_obj
,
659 (void **)&ring
->ring
);
660 radeon_bo_unreserve(ring
->ring_obj
);
662 dev_err(rdev
->dev
, "(%d) ring map failed\n", r
);
666 ring
->ptr_mask
= (ring
->ring_size
/ 4) - 1;
667 ring
->ring_free_dw
= ring
->ring_size
/ 4;
668 if (rdev
->wb
.enabled
) {
669 u32 index
= RADEON_WB_RING0_NEXT_RPTR
+ (ring
->idx
* 4);
670 ring
->next_rptr_gpu_addr
= rdev
->wb
.gpu_addr
+ index
;
671 ring
->next_rptr_cpu_addr
= &rdev
->wb
.wb
[index
/4];
673 if (radeon_debugfs_ring_init(rdev
, ring
)) {
674 DRM_ERROR("Failed to register debugfs file for rings !\n");
676 radeon_ring_lockup_update(rdev
, ring
);
681 * radeon_ring_fini - tear down the driver ring struct.
683 * @rdev: radeon_device pointer
684 * @ring: radeon_ring structure holding ring information
686 * Tear down the driver information for the selected ring (all asics).
688 void radeon_ring_fini(struct radeon_device
*rdev
, struct radeon_ring
*ring
)
691 struct radeon_bo
*ring_obj
;
693 mutex_lock(&rdev
->ring_lock
);
694 ring_obj
= ring
->ring_obj
;
697 ring
->ring_obj
= NULL
;
698 mutex_unlock(&rdev
->ring_lock
);
701 r
= radeon_bo_reserve(ring_obj
, false);
702 if (likely(r
== 0)) {
703 radeon_bo_kunmap(ring_obj
);
704 radeon_bo_unpin(ring_obj
);
705 radeon_bo_unreserve(ring_obj
);
707 radeon_bo_unref(&ring_obj
);
714 #if defined(CONFIG_DEBUG_FS)
716 static int radeon_debugfs_ring_info(struct seq_file
*m
, void *data
)
718 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
719 struct drm_device
*dev
= node
->minor
->dev
;
720 struct radeon_device
*rdev
= dev
->dev_private
;
721 int ridx
= *(int*)node
->info_ent
->data
;
722 struct radeon_ring
*ring
= &rdev
->ring
[ridx
];
724 uint32_t rptr
, wptr
, rptr_next
;
725 unsigned count
, i
, j
;
727 radeon_ring_free_size(rdev
, ring
);
728 count
= (ring
->ring_size
/ 4) - ring
->ring_free_dw
;
730 wptr
= radeon_ring_get_wptr(rdev
, ring
);
731 seq_printf(m
, "wptr: 0x%08x [%5d]\n",
734 rptr
= radeon_ring_get_rptr(rdev
, ring
);
735 seq_printf(m
, "rptr: 0x%08x [%5d]\n",
738 if (ring
->rptr_save_reg
) {
739 rptr_next
= RREG32(ring
->rptr_save_reg
);
740 seq_printf(m
, "rptr next(0x%04x): 0x%08x [%5d]\n",
741 ring
->rptr_save_reg
, rptr_next
, rptr_next
);
745 seq_printf(m
, "driver's copy of the wptr: 0x%08x [%5d]\n",
746 ring
->wptr
, ring
->wptr
);
747 seq_printf(m
, "last semaphore signal addr : 0x%016llx\n",
748 ring
->last_semaphore_signal_addr
);
749 seq_printf(m
, "last semaphore wait addr : 0x%016llx\n",
750 ring
->last_semaphore_wait_addr
);
751 seq_printf(m
, "%u free dwords in ring\n", ring
->ring_free_dw
);
752 seq_printf(m
, "%u dwords in ring\n", count
);
757 /* print 8 dw before current rptr as often it's the last executed
758 * packet that is the root issue
760 i
= (rptr
+ ring
->ptr_mask
+ 1 - 32) & ring
->ptr_mask
;
761 for (j
= 0; j
<= (count
+ 32); j
++) {
762 seq_printf(m
, "r[%5d]=0x%08x", i
, ring
->ring
[i
]);
768 i
= (i
+ 1) & ring
->ptr_mask
;
773 static int radeon_gfx_index
= RADEON_RING_TYPE_GFX_INDEX
;
774 static int cayman_cp1_index
= CAYMAN_RING_TYPE_CP1_INDEX
;
775 static int cayman_cp2_index
= CAYMAN_RING_TYPE_CP2_INDEX
;
776 static int radeon_dma1_index
= R600_RING_TYPE_DMA_INDEX
;
777 static int radeon_dma2_index
= CAYMAN_RING_TYPE_DMA1_INDEX
;
778 static int r600_uvd_index
= R600_RING_TYPE_UVD_INDEX
;
779 static int si_vce1_index
= TN_RING_TYPE_VCE1_INDEX
;
780 static int si_vce2_index
= TN_RING_TYPE_VCE2_INDEX
;
782 static struct drm_info_list radeon_debugfs_ring_info_list
[] = {
783 {"radeon_ring_gfx", radeon_debugfs_ring_info
, 0, &radeon_gfx_index
},
784 {"radeon_ring_cp1", radeon_debugfs_ring_info
, 0, &cayman_cp1_index
},
785 {"radeon_ring_cp2", radeon_debugfs_ring_info
, 0, &cayman_cp2_index
},
786 {"radeon_ring_dma1", radeon_debugfs_ring_info
, 0, &radeon_dma1_index
},
787 {"radeon_ring_dma2", radeon_debugfs_ring_info
, 0, &radeon_dma2_index
},
788 {"radeon_ring_uvd", radeon_debugfs_ring_info
, 0, &r600_uvd_index
},
789 {"radeon_ring_vce1", radeon_debugfs_ring_info
, 0, &si_vce1_index
},
790 {"radeon_ring_vce2", radeon_debugfs_ring_info
, 0, &si_vce2_index
},
793 static int radeon_debugfs_sa_info(struct seq_file
*m
, void *data
)
795 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
796 struct drm_device
*dev
= node
->minor
->dev
;
797 struct radeon_device
*rdev
= dev
->dev_private
;
799 radeon_sa_bo_dump_debug_info(&rdev
->ring_tmp_bo
, m
);
805 static struct drm_info_list radeon_debugfs_sa_list
[] = {
806 {"radeon_sa_info", &radeon_debugfs_sa_info
, 0, NULL
},
811 static int radeon_debugfs_ring_init(struct radeon_device
*rdev
, struct radeon_ring
*ring
)
813 #if defined(CONFIG_DEBUG_FS)
815 for (i
= 0; i
< ARRAY_SIZE(radeon_debugfs_ring_info_list
); ++i
) {
816 struct drm_info_list
*info
= &radeon_debugfs_ring_info_list
[i
];
817 int ridx
= *(int*)radeon_debugfs_ring_info_list
[i
].data
;
820 if (&rdev
->ring
[ridx
] != ring
)
823 r
= radeon_debugfs_add_files(rdev
, info
, 1);
831 static int radeon_debugfs_sa_init(struct radeon_device
*rdev
)
833 #if defined(CONFIG_DEBUG_FS)
834 return radeon_debugfs_add_files(rdev
, radeon_debugfs_sa_list
, 1);