2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
29 #include <linux/seq_file.h>
30 #include <linux/slab.h>
32 #include <drm/radeon_drm.h>
33 #include "radeon_reg.h"
39 * IBs (Indirect Buffers) and areas of GPU accessible memory where
40 * commands are stored. You can put a pointer to the IB in the
41 * command ring and the hw will fetch the commands from the IB
42 * and execute them. Generally userspace acceleration drivers
43 * produce command buffers which are send to the kernel and
44 * put in IBs for execution by the requested ring.
46 static int radeon_debugfs_sa_init(struct radeon_device
*rdev
);
49 * radeon_ib_get - request an IB (Indirect Buffer)
51 * @rdev: radeon_device pointer
52 * @ring: ring index the IB is associated with
53 * @ib: IB object returned
54 * @size: requested IB size
56 * Request an IB (all asics). IBs are allocated using the
58 * Returns 0 on success, error on failure.
60 int radeon_ib_get(struct radeon_device
*rdev
, int ring
,
61 struct radeon_ib
*ib
, struct radeon_vm
*vm
,
66 r
= radeon_sa_bo_new(rdev
, &rdev
->ring_tmp_bo
, &ib
->sa_bo
, size
, 256, true);
68 dev_err(rdev
->dev
, "failed to get a new IB (%d)\n", r
);
72 r
= radeon_semaphore_create(rdev
, &ib
->semaphore
);
79 ib
->ptr
= radeon_sa_bo_cpu_addr(ib
->sa_bo
);
82 /* ib pool is bound at RADEON_VA_IB_OFFSET in virtual address
83 * space and soffset is the offset inside the pool bo
85 ib
->gpu_addr
= ib
->sa_bo
->soffset
+ RADEON_VA_IB_OFFSET
;
87 ib
->gpu_addr
= radeon_sa_bo_gpu_addr(ib
->sa_bo
);
89 ib
->is_const_ib
= false;
95 * radeon_ib_free - free an IB (Indirect Buffer)
97 * @rdev: radeon_device pointer
98 * @ib: IB object to free
100 * Free an IB (all asics).
102 void radeon_ib_free(struct radeon_device
*rdev
, struct radeon_ib
*ib
)
104 radeon_semaphore_free(rdev
, &ib
->semaphore
, ib
->fence
);
105 radeon_sa_bo_free(rdev
, &ib
->sa_bo
, ib
->fence
);
106 radeon_fence_unref(&ib
->fence
);
110 * radeon_ib_schedule - schedule an IB (Indirect Buffer) on the ring
112 * @rdev: radeon_device pointer
113 * @ib: IB object to schedule
114 * @const_ib: Const IB to schedule (SI only)
116 * Schedule an IB on the associated ring (all asics).
117 * Returns 0 on success, error on failure.
119 * On SI, there are two parallel engines fed from the primary ring,
120 * the CE (Constant Engine) and the DE (Drawing Engine). Since
121 * resource descriptors have moved to memory, the CE allows you to
122 * prime the caches while the DE is updating register state so that
123 * the resource descriptors will be already in cache when the draw is
124 * processed. To accomplish this, the userspace driver submits two
125 * IBs, one for the CE and one for the DE. If there is a CE IB (called
126 * a CONST_IB), it will be put on the ring prior to the DE IB. Prior
127 * to SI there was just a DE IB.
129 int radeon_ib_schedule(struct radeon_device
*rdev
, struct radeon_ib
*ib
,
130 struct radeon_ib
*const_ib
)
132 struct radeon_ring
*ring
= &rdev
->ring
[ib
->ring
];
135 if (!ib
->length_dw
|| !ring
->ready
) {
136 /* TODO: Nothings in the ib we should report. */
137 dev_err(rdev
->dev
, "couldn't schedule ib\n");
141 /* 64 dwords should be enough for fence too */
142 r
= radeon_ring_lock(rdev
, ring
, 64 + RADEON_NUM_SYNCS
* 8);
144 dev_err(rdev
->dev
, "scheduling IB failed (%d).\n", r
);
148 /* sync with other rings */
149 r
= radeon_semaphore_sync_rings(rdev
, ib
->semaphore
, ib
->ring
);
151 dev_err(rdev
->dev
, "failed to sync rings (%d)\n", r
);
152 radeon_ring_unlock_undo(rdev
, ring
);
156 /* if we can't remember our last VM flush then flush now! */
157 /* XXX figure out why we have to flush for every IB */
158 if (ib
->vm
/*&& !ib->vm->last_flush*/) {
159 radeon_ring_vm_flush(rdev
, ib
->ring
, ib
->vm
);
162 radeon_ring_ib_execute(rdev
, const_ib
->ring
, const_ib
);
163 radeon_semaphore_free(rdev
, &const_ib
->semaphore
, NULL
);
165 radeon_ring_ib_execute(rdev
, ib
->ring
, ib
);
166 r
= radeon_fence_emit(rdev
, &ib
->fence
, ib
->ring
);
168 dev_err(rdev
->dev
, "failed to emit fence for new IB (%d)\n", r
);
169 radeon_ring_unlock_undo(rdev
, ring
);
173 const_ib
->fence
= radeon_fence_ref(ib
->fence
);
175 /* we just flushed the VM, remember that */
176 if (ib
->vm
&& !ib
->vm
->last_flush
) {
177 ib
->vm
->last_flush
= radeon_fence_ref(ib
->fence
);
179 radeon_ring_unlock_commit(rdev
, ring
);
184 * radeon_ib_pool_init - Init the IB (Indirect Buffer) pool
186 * @rdev: radeon_device pointer
188 * Initialize the suballocator to manage a pool of memory
189 * for use as IBs (all asics).
190 * Returns 0 on success, error on failure.
192 int radeon_ib_pool_init(struct radeon_device
*rdev
)
196 if (rdev
->ib_pool_ready
) {
199 r
= radeon_sa_bo_manager_init(rdev
, &rdev
->ring_tmp_bo
,
200 RADEON_IB_POOL_SIZE
*64*1024,
201 RADEON_GPU_PAGE_SIZE
,
202 RADEON_GEM_DOMAIN_GTT
);
207 r
= radeon_sa_bo_manager_start(rdev
, &rdev
->ring_tmp_bo
);
212 rdev
->ib_pool_ready
= true;
213 if (radeon_debugfs_sa_init(rdev
)) {
214 dev_err(rdev
->dev
, "failed to register debugfs file for SA\n");
220 * radeon_ib_pool_fini - Free the IB (Indirect Buffer) pool
222 * @rdev: radeon_device pointer
224 * Tear down the suballocator managing the pool of memory
225 * for use as IBs (all asics).
227 void radeon_ib_pool_fini(struct radeon_device
*rdev
)
229 if (rdev
->ib_pool_ready
) {
230 radeon_sa_bo_manager_suspend(rdev
, &rdev
->ring_tmp_bo
);
231 radeon_sa_bo_manager_fini(rdev
, &rdev
->ring_tmp_bo
);
232 rdev
->ib_pool_ready
= false;
237 * radeon_ib_ring_tests - test IBs on the rings
239 * @rdev: radeon_device pointer
241 * Test an IB (Indirect Buffer) on each ring.
242 * If the test fails, disable the ring.
243 * Returns 0 on success, error if the primary GFX ring
246 int radeon_ib_ring_tests(struct radeon_device
*rdev
)
251 for (i
= 0; i
< RADEON_NUM_RINGS
; ++i
) {
252 struct radeon_ring
*ring
= &rdev
->ring
[i
];
257 r
= radeon_ib_test(rdev
, i
, ring
);
261 if (i
== RADEON_RING_TYPE_GFX_INDEX
) {
262 /* oh, oh, that's really bad */
263 DRM_ERROR("radeon: failed testing IB on GFX ring (%d).\n", r
);
264 rdev
->accel_working
= false;
268 /* still not good, but we can live with it */
269 DRM_ERROR("radeon: failed testing IB on ring %d (%d).\n", i
, r
);
278 * Most engines on the GPU are fed via ring buffers. Ring
279 * buffers are areas of GPU accessible memory that the host
280 * writes commands into and the GPU reads commands out of.
281 * There is a rptr (read pointer) that determines where the
282 * GPU is currently reading, and a wptr (write pointer)
283 * which determines where the host has written. When the
284 * pointers are equal, the ring is idle. When the host
285 * writes commands to the ring buffer, it increments the
286 * wptr. The GPU then starts fetching commands and executes
287 * them until the pointers are equal again.
289 static int radeon_debugfs_ring_init(struct radeon_device
*rdev
, struct radeon_ring
*ring
);
292 * radeon_ring_write - write a value to the ring
294 * @ring: radeon_ring structure holding ring information
295 * @v: dword (dw) value to write
297 * Write a value to the requested ring buffer (all asics).
299 void radeon_ring_write(struct radeon_ring
*ring
, uint32_t v
)
302 if (ring
->count_dw
<= 0) {
303 DRM_ERROR("radeon: writing more dwords to the ring than expected!\n");
306 ring
->ring
[ring
->wptr
++] = v
;
307 ring
->wptr
&= ring
->ptr_mask
;
309 ring
->ring_free_dw
--;
313 * radeon_ring_supports_scratch_reg - check if the ring supports
314 * writing to scratch registers
316 * @rdev: radeon_device pointer
317 * @ring: radeon_ring structure holding ring information
319 * Check if a specific ring supports writing to scratch registers (all asics).
320 * Returns true if the ring supports writing to scratch regs, false if not.
322 bool radeon_ring_supports_scratch_reg(struct radeon_device
*rdev
,
323 struct radeon_ring
*ring
)
326 case RADEON_RING_TYPE_GFX_INDEX
:
327 case CAYMAN_RING_TYPE_CP1_INDEX
:
328 case CAYMAN_RING_TYPE_CP2_INDEX
:
336 * radeon_ring_free_size - update the free size
338 * @rdev: radeon_device pointer
339 * @ring: radeon_ring structure holding ring information
341 * Update the free dw slots in the ring buffer (all asics).
343 void radeon_ring_free_size(struct radeon_device
*rdev
, struct radeon_ring
*ring
)
345 uint32_t rptr
= radeon_ring_get_rptr(rdev
, ring
);
347 /* This works because ring_size is a power of 2 */
348 ring
->ring_free_dw
= rptr
+ (ring
->ring_size
/ 4);
349 ring
->ring_free_dw
-= ring
->wptr
;
350 ring
->ring_free_dw
&= ring
->ptr_mask
;
351 if (!ring
->ring_free_dw
) {
352 /* this is an empty ring */
353 ring
->ring_free_dw
= ring
->ring_size
/ 4;
354 /* update lockup info to avoid false positive */
355 radeon_ring_lockup_update(rdev
, ring
);
360 * radeon_ring_alloc - allocate space on the ring buffer
362 * @rdev: radeon_device pointer
363 * @ring: radeon_ring structure holding ring information
364 * @ndw: number of dwords to allocate in the ring buffer
366 * Allocate @ndw dwords in the ring buffer (all asics).
367 * Returns 0 on success, error on failure.
369 int radeon_ring_alloc(struct radeon_device
*rdev
, struct radeon_ring
*ring
, unsigned ndw
)
373 /* make sure we aren't trying to allocate more space than there is on the ring */
374 if (ndw
> (ring
->ring_size
/ 4))
376 /* Align requested size with padding so unlock_commit can
378 radeon_ring_free_size(rdev
, ring
);
379 ndw
= (ndw
+ ring
->align_mask
) & ~ring
->align_mask
;
380 while (ndw
> (ring
->ring_free_dw
- 1)) {
381 radeon_ring_free_size(rdev
, ring
);
382 if (ndw
< ring
->ring_free_dw
) {
385 r
= radeon_fence_wait_next_locked(rdev
, ring
->idx
);
389 ring
->count_dw
= ndw
;
390 ring
->wptr_old
= ring
->wptr
;
395 * radeon_ring_lock - lock the ring and allocate space on it
397 * @rdev: radeon_device pointer
398 * @ring: radeon_ring structure holding ring information
399 * @ndw: number of dwords to allocate in the ring buffer
401 * Lock the ring and allocate @ndw dwords in the ring buffer
403 * Returns 0 on success, error on failure.
405 int radeon_ring_lock(struct radeon_device
*rdev
, struct radeon_ring
*ring
, unsigned ndw
)
409 mutex_lock(&rdev
->ring_lock
);
410 r
= radeon_ring_alloc(rdev
, ring
, ndw
);
412 mutex_unlock(&rdev
->ring_lock
);
419 * radeon_ring_commit - tell the GPU to execute the new
420 * commands on the ring buffer
422 * @rdev: radeon_device pointer
423 * @ring: radeon_ring structure holding ring information
425 * Update the wptr (write pointer) to tell the GPU to
426 * execute new commands on the ring buffer (all asics).
428 void radeon_ring_commit(struct radeon_device
*rdev
, struct radeon_ring
*ring
)
430 /* We pad to match fetch size */
431 while (ring
->wptr
& ring
->align_mask
) {
432 radeon_ring_write(ring
, ring
->nop
);
435 radeon_ring_set_wptr(rdev
, ring
);
439 * radeon_ring_unlock_commit - tell the GPU to execute the new
440 * commands on the ring buffer and unlock it
442 * @rdev: radeon_device pointer
443 * @ring: radeon_ring structure holding ring information
445 * Call radeon_ring_commit() then unlock the ring (all asics).
447 void radeon_ring_unlock_commit(struct radeon_device
*rdev
, struct radeon_ring
*ring
)
449 radeon_ring_commit(rdev
, ring
);
450 mutex_unlock(&rdev
->ring_lock
);
454 * radeon_ring_undo - reset the wptr
456 * @ring: radeon_ring structure holding ring information
458 * Reset the driver's copy of the wptr (all asics).
460 void radeon_ring_undo(struct radeon_ring
*ring
)
462 ring
->wptr
= ring
->wptr_old
;
466 * radeon_ring_unlock_undo - reset the wptr and unlock the ring
468 * @ring: radeon_ring structure holding ring information
470 * Call radeon_ring_undo() then unlock the ring (all asics).
472 void radeon_ring_unlock_undo(struct radeon_device
*rdev
, struct radeon_ring
*ring
)
474 radeon_ring_undo(ring
);
475 mutex_unlock(&rdev
->ring_lock
);
479 * radeon_ring_lockup_update - update lockup variables
481 * @ring: radeon_ring structure holding ring information
483 * Update the last rptr value and timestamp (all asics).
485 void radeon_ring_lockup_update(struct radeon_device
*rdev
,
486 struct radeon_ring
*ring
)
488 ring
->last_rptr
= radeon_ring_get_rptr(rdev
, ring
);
489 ring
->last_activity
= jiffies
;
493 * radeon_ring_test_lockup() - check if ring is lockedup by recording information
494 * @rdev: radeon device structure
495 * @ring: radeon_ring structure holding ring information
498 bool radeon_ring_test_lockup(struct radeon_device
*rdev
, struct radeon_ring
*ring
)
500 uint32_t rptr
= radeon_ring_get_rptr(rdev
, ring
);
501 unsigned long cjiffies
, elapsed
;
504 if (!time_after(cjiffies
, ring
->last_activity
)) {
505 /* likely a wrap around */
506 radeon_ring_lockup_update(rdev
, ring
);
509 if (rptr
!= ring
->last_rptr
) {
510 /* CP is still working no lockup */
511 radeon_ring_lockup_update(rdev
, ring
);
514 elapsed
= jiffies_to_msecs(cjiffies
- ring
->last_activity
);
515 if (radeon_lockup_timeout
&& elapsed
>= radeon_lockup_timeout
) {
516 dev_err(rdev
->dev
, "GPU lockup CP stall for more than %lumsec\n", elapsed
);
519 /* give a chance to the GPU ... */
524 * radeon_ring_backup - Back up the content of a ring
526 * @rdev: radeon_device pointer
527 * @ring: the ring we want to back up
529 * Saves all unprocessed commits from a ring, returns the number of dwords saved.
531 unsigned radeon_ring_backup(struct radeon_device
*rdev
, struct radeon_ring
*ring
,
534 unsigned size
, ptr
, i
;
536 /* just in case lock the ring */
537 mutex_lock(&rdev
->ring_lock
);
540 if (ring
->ring_obj
== NULL
) {
541 mutex_unlock(&rdev
->ring_lock
);
545 /* it doesn't make sense to save anything if all fences are signaled */
546 if (!radeon_fence_count_emitted(rdev
, ring
->idx
)) {
547 mutex_unlock(&rdev
->ring_lock
);
551 /* calculate the number of dw on the ring */
552 if (ring
->rptr_save_reg
)
553 ptr
= RREG32(ring
->rptr_save_reg
);
554 else if (rdev
->wb
.enabled
)
555 ptr
= le32_to_cpu(*ring
->next_rptr_cpu_addr
);
557 /* no way to read back the next rptr */
558 mutex_unlock(&rdev
->ring_lock
);
562 size
= ring
->wptr
+ (ring
->ring_size
/ 4);
564 size
&= ring
->ptr_mask
;
566 mutex_unlock(&rdev
->ring_lock
);
570 /* and then save the content of the ring */
571 *data
= kmalloc_array(size
, sizeof(uint32_t), GFP_KERNEL
);
573 mutex_unlock(&rdev
->ring_lock
);
576 for (i
= 0; i
< size
; ++i
) {
577 (*data
)[i
] = ring
->ring
[ptr
++];
578 ptr
&= ring
->ptr_mask
;
581 mutex_unlock(&rdev
->ring_lock
);
586 * radeon_ring_restore - append saved commands to the ring again
588 * @rdev: radeon_device pointer
589 * @ring: ring to append commands to
590 * @size: number of dwords we want to write
591 * @data: saved commands
593 * Allocates space on the ring and restore the previously saved commands.
595 int radeon_ring_restore(struct radeon_device
*rdev
, struct radeon_ring
*ring
,
596 unsigned size
, uint32_t *data
)
603 /* restore the saved ring content */
604 r
= radeon_ring_lock(rdev
, ring
, size
);
608 for (i
= 0; i
< size
; ++i
) {
609 radeon_ring_write(ring
, data
[i
]);
612 radeon_ring_unlock_commit(rdev
, ring
);
618 * radeon_ring_init - init driver ring struct.
620 * @rdev: radeon_device pointer
621 * @ring: radeon_ring structure holding ring information
622 * @ring_size: size of the ring
623 * @rptr_offs: offset of the rptr writeback location in the WB buffer
624 * @nop: nop packet for this ring
626 * Initialize the driver information for the selected ring (all asics).
627 * Returns 0 on success, error on failure.
629 int radeon_ring_init(struct radeon_device
*rdev
, struct radeon_ring
*ring
, unsigned ring_size
,
630 unsigned rptr_offs
, u32 nop
)
634 ring
->ring_size
= ring_size
;
635 ring
->rptr_offs
= rptr_offs
;
637 /* Allocate ring buffer */
638 if (ring
->ring_obj
== NULL
) {
639 r
= radeon_bo_create(rdev
, ring
->ring_size
, PAGE_SIZE
, true,
640 RADEON_GEM_DOMAIN_GTT
,
641 NULL
, &ring
->ring_obj
);
643 dev_err(rdev
->dev
, "(%d) ring create failed\n", r
);
646 r
= radeon_bo_reserve(ring
->ring_obj
, false);
647 if (unlikely(r
!= 0))
649 r
= radeon_bo_pin(ring
->ring_obj
, RADEON_GEM_DOMAIN_GTT
,
652 radeon_bo_unreserve(ring
->ring_obj
);
653 dev_err(rdev
->dev
, "(%d) ring pin failed\n", r
);
656 r
= radeon_bo_kmap(ring
->ring_obj
,
657 (void **)&ring
->ring
);
658 radeon_bo_unreserve(ring
->ring_obj
);
660 dev_err(rdev
->dev
, "(%d) ring map failed\n", r
);
664 ring
->ptr_mask
= (ring
->ring_size
/ 4) - 1;
665 ring
->ring_free_dw
= ring
->ring_size
/ 4;
666 if (rdev
->wb
.enabled
) {
667 u32 index
= RADEON_WB_RING0_NEXT_RPTR
+ (ring
->idx
* 4);
668 ring
->next_rptr_gpu_addr
= rdev
->wb
.gpu_addr
+ index
;
669 ring
->next_rptr_cpu_addr
= &rdev
->wb
.wb
[index
/4];
671 if (radeon_debugfs_ring_init(rdev
, ring
)) {
672 DRM_ERROR("Failed to register debugfs file for rings !\n");
674 radeon_ring_lockup_update(rdev
, ring
);
679 * radeon_ring_fini - tear down the driver ring struct.
681 * @rdev: radeon_device pointer
682 * @ring: radeon_ring structure holding ring information
684 * Tear down the driver information for the selected ring (all asics).
686 void radeon_ring_fini(struct radeon_device
*rdev
, struct radeon_ring
*ring
)
689 struct radeon_bo
*ring_obj
;
691 mutex_lock(&rdev
->ring_lock
);
692 ring_obj
= ring
->ring_obj
;
695 ring
->ring_obj
= NULL
;
696 mutex_unlock(&rdev
->ring_lock
);
699 r
= radeon_bo_reserve(ring_obj
, false);
700 if (likely(r
== 0)) {
701 radeon_bo_kunmap(ring_obj
);
702 radeon_bo_unpin(ring_obj
);
703 radeon_bo_unreserve(ring_obj
);
705 radeon_bo_unref(&ring_obj
);
712 #if defined(CONFIG_DEBUG_FS)
714 static int radeon_debugfs_ring_info(struct seq_file
*m
, void *data
)
716 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
717 struct drm_device
*dev
= node
->minor
->dev
;
718 struct radeon_device
*rdev
= dev
->dev_private
;
719 int ridx
= *(int*)node
->info_ent
->data
;
720 struct radeon_ring
*ring
= &rdev
->ring
[ridx
];
722 uint32_t rptr
, wptr
, rptr_next
;
723 unsigned count
, i
, j
;
725 radeon_ring_free_size(rdev
, ring
);
726 count
= (ring
->ring_size
/ 4) - ring
->ring_free_dw
;
728 wptr
= radeon_ring_get_wptr(rdev
, ring
);
729 seq_printf(m
, "wptr: 0x%08x [%5d]\n",
732 rptr
= radeon_ring_get_rptr(rdev
, ring
);
733 seq_printf(m
, "rptr: 0x%08x [%5d]\n",
736 if (ring
->rptr_save_reg
) {
737 rptr_next
= RREG32(ring
->rptr_save_reg
);
738 seq_printf(m
, "rptr next(0x%04x): 0x%08x [%5d]\n",
739 ring
->rptr_save_reg
, rptr_next
, rptr_next
);
743 seq_printf(m
, "driver's copy of the wptr: 0x%08x [%5d]\n",
744 ring
->wptr
, ring
->wptr
);
745 seq_printf(m
, "last semaphore signal addr : 0x%016llx\n",
746 ring
->last_semaphore_signal_addr
);
747 seq_printf(m
, "last semaphore wait addr : 0x%016llx\n",
748 ring
->last_semaphore_wait_addr
);
749 seq_printf(m
, "%u free dwords in ring\n", ring
->ring_free_dw
);
750 seq_printf(m
, "%u dwords in ring\n", count
);
755 /* print 8 dw before current rptr as often it's the last executed
756 * packet that is the root issue
758 i
= (rptr
+ ring
->ptr_mask
+ 1 - 32) & ring
->ptr_mask
;
759 for (j
= 0; j
<= (count
+ 32); j
++) {
760 seq_printf(m
, "r[%5d]=0x%08x", i
, ring
->ring
[i
]);
766 i
= (i
+ 1) & ring
->ptr_mask
;
771 static int radeon_gfx_index
= RADEON_RING_TYPE_GFX_INDEX
;
772 static int cayman_cp1_index
= CAYMAN_RING_TYPE_CP1_INDEX
;
773 static int cayman_cp2_index
= CAYMAN_RING_TYPE_CP2_INDEX
;
774 static int radeon_dma1_index
= R600_RING_TYPE_DMA_INDEX
;
775 static int radeon_dma2_index
= CAYMAN_RING_TYPE_DMA1_INDEX
;
776 static int r600_uvd_index
= R600_RING_TYPE_UVD_INDEX
;
777 static int si_vce1_index
= TN_RING_TYPE_VCE1_INDEX
;
778 static int si_vce2_index
= TN_RING_TYPE_VCE2_INDEX
;
780 static struct drm_info_list radeon_debugfs_ring_info_list
[] = {
781 {"radeon_ring_gfx", radeon_debugfs_ring_info
, 0, &radeon_gfx_index
},
782 {"radeon_ring_cp1", radeon_debugfs_ring_info
, 0, &cayman_cp1_index
},
783 {"radeon_ring_cp2", radeon_debugfs_ring_info
, 0, &cayman_cp2_index
},
784 {"radeon_ring_dma1", radeon_debugfs_ring_info
, 0, &radeon_dma1_index
},
785 {"radeon_ring_dma2", radeon_debugfs_ring_info
, 0, &radeon_dma2_index
},
786 {"radeon_ring_uvd", radeon_debugfs_ring_info
, 0, &r600_uvd_index
},
787 {"radeon_ring_vce1", radeon_debugfs_ring_info
, 0, &si_vce1_index
},
788 {"radeon_ring_vce2", radeon_debugfs_ring_info
, 0, &si_vce2_index
},
791 static int radeon_debugfs_sa_info(struct seq_file
*m
, void *data
)
793 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
794 struct drm_device
*dev
= node
->minor
->dev
;
795 struct radeon_device
*rdev
= dev
->dev_private
;
797 radeon_sa_bo_dump_debug_info(&rdev
->ring_tmp_bo
, m
);
803 static struct drm_info_list radeon_debugfs_sa_list
[] = {
804 {"radeon_sa_info", &radeon_debugfs_sa_info
, 0, NULL
},
809 static int radeon_debugfs_ring_init(struct radeon_device
*rdev
, struct radeon_ring
*ring
)
811 #if defined(CONFIG_DEBUG_FS)
813 for (i
= 0; i
< ARRAY_SIZE(radeon_debugfs_ring_info_list
); ++i
) {
814 struct drm_info_list
*info
= &radeon_debugfs_ring_info_list
[i
];
815 int ridx
= *(int*)radeon_debugfs_ring_info_list
[i
].data
;
818 if (&rdev
->ring
[ridx
] != ring
)
821 r
= radeon_debugfs_add_files(rdev
, info
, 1);
829 static int radeon_debugfs_sa_init(struct radeon_device
*rdev
)
831 #if defined(CONFIG_DEBUG_FS)
832 return radeon_debugfs_add_files(rdev
, radeon_debugfs_sa_list
, 1);