drivers/gpu/drm/radeon/radeon_share.h

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #ifndef __RADEON_SHARE_H__
  29 #define __RADEON_SHARE_H__
  30
  31 /* Common */
  32 struct radeon_device;
  33 struct radeon_cs_parser;
  34 int radeon_clocks_init(struct radeon_device *rdev);
  35 void radeon_clocks_fini(struct radeon_device *rdev);
  36 void radeon_scratch_init(struct radeon_device *rdev);
  37 void radeon_surface_init(struct radeon_device *rdev);
  38 int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
  39
  40
  41 /* R100, RV100, RS100, RV200, RS200, R200, RV250, RS300, RV280 */
  42 void r100_vram_init_sizes(struct radeon_device *rdev);
  43
  44
  45 /* R300, R350, RV350, RV380 */
  46 struct r300_asic {
  47         const unsigned  *reg_safe_bm;
  48         unsigned        reg_safe_bm_size;
  49 };
  50
  51
  52 /* RS690, RS740 */
  53 void rs690_line_buffer_adjust(struct radeon_device *rdev,
  54                               struct drm_display_mode *mode1,
  55                               struct drm_display_mode *mode2);
  56
  57
  58 /* RV515 */
  59 void rv515_bandwidth_avivo_update(struct radeon_device *rdev);
  60
  61
  62 /* R600, RV610, RV630, RV620, RV635, RV670, RS780, RS880 */
  63 bool r600_card_posted(struct radeon_device *rdev);
  64 void r600_cp_stop(struct radeon_device *rdev);
  65 void r600_ring_init(struct radeon_device *rdev, unsigned ring_size);
  66 int r600_cp_resume(struct radeon_device *rdev);
  67 int r600_count_pipe_bits(uint32_t val);
  68 int r600_gart_clear_page(struct radeon_device *rdev, int i);
  69 int r600_mc_wait_for_idle(struct radeon_device *rdev);
  70 void r600_pcie_gart_tlb_flush(struct radeon_device *rdev);
  71 int r600_ib_test(struct radeon_device *rdev);
  72 int r600_ring_test(struct radeon_device *rdev);
  73 int r600_wb_init(struct radeon_device *rdev);
  74 void r600_wb_fini(struct radeon_device *rdev);
  75 void r600_scratch_init(struct radeon_device *rdev);
  76 int r600_blit_init(struct radeon_device *rdev);
  77 void r600_blit_fini(struct radeon_device *rdev);
  78 int r600_cp_init_microcode(struct radeon_device *rdev);
  79 struct r600_asic {
  80         unsigned max_pipes;
  81         unsigned max_tile_pipes;
  82         unsigned max_simds;
  83         unsigned max_backends;
  84         unsigned max_gprs;
  85         unsigned max_threads;
  86         unsigned max_stack_entries;
  87         unsigned max_hw_contexts;
  88         unsigned max_gs_threads;
  89         unsigned sx_max_export_size;
  90         unsigned sx_max_export_pos_size;
  91         unsigned sx_max_export_smx_size;
  92         unsigned sq_num_cf_insts;
  93 };
  94
  95 /* RV770, RV7300, RV710 */
  96 struct rv770_asic {
  97         unsigned max_pipes;
  98         unsigned max_tile_pipes;
  99         unsigned max_simds;
 100         unsigned max_backends;
 101         unsigned max_gprs;
 102         unsigned max_threads;
 103         unsigned max_stack_entries;
 104         unsigned max_hw_contexts;
 105         unsigned max_gs_threads;
 106         unsigned sx_max_export_size;
 107         unsigned sx_max_export_pos_size;
 108         unsigned sx_max_export_smx_size;
 109         unsigned sq_num_cf_insts;
 110         unsigned sx_num_of_sets;
 111         unsigned sc_prim_fifo_size;
 112         unsigned sc_hiz_tile_fifo_size;
 113         unsigned sc_earlyz_tile_fifo_fize;
 114 };
 115
 116 #endif