drivers/gpu/drm/radeon/radeon_uvd.c

   1 /*
   2  * Copyright 2011 Advanced Micro Devices, Inc.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26 /*
  27  * Authors:
  28  *    Christian König <deathsimple@vodafone.de>
  29  */
  30
  31 #include <linux/firmware.h>
  32 #include <linux/module.h>
  33 #include <drm/drmP.h>
  34 #include <drm/drm.h>
  35
  36 #include "radeon.h"
  37 #include "r600d.h"
  38
  39 /* 1 second timeout */
  40 #define UVD_IDLE_TIMEOUT_MS     1000
  41
  42 /* Firmware Names */
  43 #define FIRMWARE_R600           "radeon/R600_uvd.bin"
  44 #define FIRMWARE_RS780          "radeon/RS780_uvd.bin"
  45 #define FIRMWARE_RV770          "radeon/RV770_uvd.bin"
  46 #define FIRMWARE_RV710          "radeon/RV710_uvd.bin"
  47 #define FIRMWARE_CYPRESS        "radeon/CYPRESS_uvd.bin"
  48 #define FIRMWARE_SUMO           "radeon/SUMO_uvd.bin"
  49 #define FIRMWARE_TAHITI         "radeon/TAHITI_uvd.bin"
  50 #define FIRMWARE_BONAIRE        "radeon/BONAIRE_uvd.bin"
  51
  52 MODULE_FIRMWARE(FIRMWARE_R600);
  53 MODULE_FIRMWARE(FIRMWARE_RS780);
  54 MODULE_FIRMWARE(FIRMWARE_RV770);
  55 MODULE_FIRMWARE(FIRMWARE_RV710);
  56 MODULE_FIRMWARE(FIRMWARE_CYPRESS);
  57 MODULE_FIRMWARE(FIRMWARE_SUMO);
  58 MODULE_FIRMWARE(FIRMWARE_TAHITI);
  59 MODULE_FIRMWARE(FIRMWARE_BONAIRE);
  60
  61 static void radeon_uvd_idle_work_handler(struct work_struct *work);
  62
  63 int radeon_uvd_init(struct radeon_device *rdev)
  64 {
  65         unsigned long bo_size;
  66         const char *fw_name;
  67         int i, r;
  68
  69         INIT_DELAYED_WORK(&rdev->uvd.idle_work, radeon_uvd_idle_work_handler);
  70
  71         switch (rdev->family) {
  72         case CHIP_RV610:
  73         case CHIP_RV630:
  74         case CHIP_RV670:
  75         case CHIP_RV620:
  76         case CHIP_RV635:
  77                 fw_name = FIRMWARE_R600;
  78                 break;
  79
  80         case CHIP_RS780:
  81         case CHIP_RS880:
  82                 fw_name = FIRMWARE_RS780;
  83                 break;
  84
  85         case CHIP_RV770:
  86                 fw_name = FIRMWARE_RV770;
  87                 break;
  88
  89         case CHIP_RV710:
  90         case CHIP_RV730:
  91         case CHIP_RV740:
  92                 fw_name = FIRMWARE_RV710;
  93                 break;
  94
  95         case CHIP_CYPRESS:
  96         case CHIP_HEMLOCK:
  97         case CHIP_JUNIPER:
  98         case CHIP_REDWOOD:
  99         case CHIP_CEDAR:
 100                 fw_name = FIRMWARE_CYPRESS;
 101                 break;
 102
 103         case CHIP_SUMO:
 104         case CHIP_SUMO2:
 105         case CHIP_PALM:
 106         case CHIP_CAYMAN:
 107         case CHIP_BARTS:
 108         case CHIP_TURKS:
 109         case CHIP_CAICOS:
 110                 fw_name = FIRMWARE_SUMO;
 111                 break;
 112
 113         case CHIP_TAHITI:
 114         case CHIP_VERDE:
 115         case CHIP_PITCAIRN:
 116         case CHIP_ARUBA:
 117         case CHIP_OLAND:
 118                 fw_name = FIRMWARE_TAHITI;
 119                 break;
 120
 121         case CHIP_BONAIRE:
 122         case CHIP_KABINI:
 123         case CHIP_KAVERI:
 124         case CHIP_HAWAII:
 125         case CHIP_MULLINS:
 126                 fw_name = FIRMWARE_BONAIRE;
 127                 break;
 128
 129         default:
 130                 return -EINVAL;
 131         }
 132
 133         r = request_firmware(&rdev->uvd_fw, fw_name, rdev->dev);
 134         if (r) {
 135                 dev_err(rdev->dev, "radeon_uvd: Can't load firmware \"%s\"\n",
 136                         fw_name);
 137                 return r;
 138         }
 139
 140         bo_size = RADEON_GPU_PAGE_ALIGN(rdev->uvd_fw->size + 8) +
 141                   RADEON_UVD_STACK_SIZE + RADEON_UVD_HEAP_SIZE +
 142                   RADEON_GPU_PAGE_SIZE;
 143         r = radeon_bo_create(rdev, bo_size, PAGE_SIZE, true,
 144                              RADEON_GEM_DOMAIN_VRAM, 0, NULL, &rdev->uvd.vcpu_bo);
 145         if (r) {
 146                 dev_err(rdev->dev, "(%d) failed to allocate UVD bo\n", r);
 147                 return r;
 148         }
 149
 150         r = radeon_bo_reserve(rdev->uvd.vcpu_bo, false);
 151         if (r) {
 152                 radeon_bo_unref(&rdev->uvd.vcpu_bo);
 153                 dev_err(rdev->dev, "(%d) failed to reserve UVD bo\n", r);
 154                 return r;
 155         }
 156
 157         r = radeon_bo_pin(rdev->uvd.vcpu_bo, RADEON_GEM_DOMAIN_VRAM,
 158                           &rdev->uvd.gpu_addr);
 159         if (r) {
 160                 radeon_bo_unreserve(rdev->uvd.vcpu_bo);
 161                 radeon_bo_unref(&rdev->uvd.vcpu_bo);
 162                 dev_err(rdev->dev, "(%d) UVD bo pin failed\n", r);
 163                 return r;
 164         }
 165
 166         r = radeon_bo_kmap(rdev->uvd.vcpu_bo, &rdev->uvd.cpu_addr);
 167         if (r) {
 168                 dev_err(rdev->dev, "(%d) UVD map failed\n", r);
 169                 return r;
 170         }
 171
 172         radeon_bo_unreserve(rdev->uvd.vcpu_bo);
 173
 174         for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) {
 175                 atomic_set(&rdev->uvd.handles[i], 0);
 176                 rdev->uvd.filp[i] = NULL;
 177                 rdev->uvd.img_size[i] = 0;
 178         }
 179
 180         return 0;
 181 }
 182
 183 void radeon_uvd_fini(struct radeon_device *rdev)
 184 {
 185         int r;
 186
 187         if (rdev->uvd.vcpu_bo == NULL)
 188                 return;
 189
 190         r = radeon_bo_reserve(rdev->uvd.vcpu_bo, false);
 191         if (!r) {
 192                 radeon_bo_kunmap(rdev->uvd.vcpu_bo);
 193                 radeon_bo_unpin(rdev->uvd.vcpu_bo);
 194                 radeon_bo_unreserve(rdev->uvd.vcpu_bo);
 195         }
 196
 197         radeon_bo_unref(&rdev->uvd.vcpu_bo);
 198
 199         radeon_ring_fini(rdev, &rdev->ring[R600_RING_TYPE_UVD_INDEX]);
 200
 201         release_firmware(rdev->uvd_fw);
 202 }
 203
 204 int radeon_uvd_suspend(struct radeon_device *rdev)
 205 {
 206         unsigned size;
 207         void *ptr;
 208         int i;
 209
 210         if (rdev->uvd.vcpu_bo == NULL)
 211                 return 0;
 212
 213         for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i)
 214                 if (atomic_read(&rdev->uvd.handles[i]))
 215                         break;
 216
 217         if (i == RADEON_MAX_UVD_HANDLES)
 218                 return 0;
 219
 220         size = radeon_bo_size(rdev->uvd.vcpu_bo);
 221         size -= rdev->uvd_fw->size;
 222
 223         ptr = rdev->uvd.cpu_addr;
 224         ptr += rdev->uvd_fw->size;
 225
 226         rdev->uvd.saved_bo = kmalloc(size, GFP_KERNEL);
 227         memcpy(rdev->uvd.saved_bo, ptr, size);
 228
 229         return 0;
 230 }
 231
 232 int radeon_uvd_resume(struct radeon_device *rdev)
 233 {
 234         unsigned size;
 235         void *ptr;
 236
 237         if (rdev->uvd.vcpu_bo == NULL)
 238                 return -EINVAL;
 239
 240         memcpy(rdev->uvd.cpu_addr, rdev->uvd_fw->data, rdev->uvd_fw->size);
 241
 242         size = radeon_bo_size(rdev->uvd.vcpu_bo);
 243         size -= rdev->uvd_fw->size;
 244
 245         ptr = rdev->uvd.cpu_addr;
 246         ptr += rdev->uvd_fw->size;
 247
 248         if (rdev->uvd.saved_bo != NULL) {
 249                 memcpy(ptr, rdev->uvd.saved_bo, size);
 250                 kfree(rdev->uvd.saved_bo);
 251                 rdev->uvd.saved_bo = NULL;
 252         } else
 253                 memset(ptr, 0, size);
 254
 255         return 0;
 256 }
 257
 258 void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo,
 259                                        uint32_t allowed_domains)
 260 {
 261         int i;
 262
 263         for (i = 0; i < rbo->placement.num_placement; ++i) {
 264                 rbo->placements[i].fpfn = 0 >> PAGE_SHIFT;
 265                 rbo->placements[i].lpfn = (256 * 1024 * 1024) >> PAGE_SHIFT;
 266         }
 267
 268         /* If it must be in VRAM it must be in the first segment as well */
 269         if (allowed_domains == RADEON_GEM_DOMAIN_VRAM)
 270                 return;
 271
 272         /* abort if we already have more than one placement */
 273         if (rbo->placement.num_placement > 1)
 274                 return;
 275
 276         /* add another 256MB segment */
 277         rbo->placements[1] = rbo->placements[0];
 278         rbo->placements[1].fpfn += (256 * 1024 * 1024) >> PAGE_SHIFT;
 279         rbo->placements[1].lpfn += (256 * 1024 * 1024) >> PAGE_SHIFT;
 280         rbo->placement.num_placement++;
 281         rbo->placement.num_busy_placement++;
 282 }
 283
 284 void radeon_uvd_free_handles(struct radeon_device *rdev, struct drm_file *filp)
 285 {
 286         int i, r;
 287         for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) {
 288                 uint32_t handle = atomic_read(&rdev->uvd.handles[i]);
 289                 if (handle != 0 && rdev->uvd.filp[i] == filp) {
 290                         struct radeon_fence *fence;
 291
 292                         radeon_uvd_note_usage(rdev);
 293
 294                         r = radeon_uvd_get_destroy_msg(rdev,
 295                                 R600_RING_TYPE_UVD_INDEX, handle, &fence);
 296                         if (r) {
 297                                 DRM_ERROR("Error destroying UVD (%d)!\n", r);
 298                                 continue;
 299                         }
 300
 301                         radeon_fence_wait(fence, false);
 302                         radeon_fence_unref(&fence);
 303
 304                         rdev->uvd.filp[i] = NULL;
 305                         atomic_set(&rdev->uvd.handles[i], 0);
 306                 }
 307         }
 308 }
 309
 310 static int radeon_uvd_cs_msg_decode(uint32_t *msg, unsigned buf_sizes[])
 311 {
 312         unsigned stream_type = msg[4];
 313         unsigned width = msg[6];
 314         unsigned height = msg[7];
 315         unsigned dpb_size = msg[9];
 316         unsigned pitch = msg[28];
 317
 318         unsigned width_in_mb = width / 16;
 319         unsigned height_in_mb = ALIGN(height / 16, 2);
 320
 321         unsigned image_size, tmp, min_dpb_size;
 322
 323         image_size = width * height;
 324         image_size += image_size / 2;
 325         image_size = ALIGN(image_size, 1024);
 326
 327         switch (stream_type) {
 328         case 0: /* H264 */
 329
 330                 /* reference picture buffer */
 331                 min_dpb_size = image_size * 17;
 332
 333                 /* macroblock context buffer */
 334                 min_dpb_size += width_in_mb * height_in_mb * 17 * 192;
 335
 336                 /* IT surface buffer */
 337                 min_dpb_size += width_in_mb * height_in_mb * 32;
 338                 break;
 339
 340         case 1: /* VC1 */
 341
 342                 /* reference picture buffer */
 343                 min_dpb_size = image_size * 3;
 344
 345                 /* CONTEXT_BUFFER */
 346                 min_dpb_size += width_in_mb * height_in_mb * 128;
 347
 348                 /* IT surface buffer */
 349                 min_dpb_size += width_in_mb * 64;
 350
 351                 /* DB surface buffer */
 352                 min_dpb_size += width_in_mb * 128;
 353
 354                 /* BP */
 355                 tmp = max(width_in_mb, height_in_mb);
 356                 min_dpb_size += ALIGN(tmp * 7 * 16, 64);
 357                 break;
 358
 359         case 3: /* MPEG2 */
 360
 361                 /* reference picture buffer */
 362                 min_dpb_size = image_size * 3;
 363                 break;
 364
 365         case 4: /* MPEG4 */
 366
 367                 /* reference picture buffer */
 368                 min_dpb_size = image_size * 3;
 369
 370                 /* CM */
 371                 min_dpb_size += width_in_mb * height_in_mb * 64;
 372
 373                 /* IT surface buffer */
 374                 min_dpb_size += ALIGN(width_in_mb * height_in_mb * 32, 64);
 375                 break;
 376
 377         default:
 378                 DRM_ERROR("UVD codec not handled %d!\n", stream_type);
 379                 return -EINVAL;
 380         }
 381
 382         if (width > pitch) {
 383                 DRM_ERROR("Invalid UVD decoding target pitch!\n");
 384                 return -EINVAL;
 385         }
 386
 387         if (dpb_size < min_dpb_size) {
 388                 DRM_ERROR("Invalid dpb_size in UVD message (%d / %d)!\n",
 389                           dpb_size, min_dpb_size);
 390                 return -EINVAL;
 391         }
 392
 393         buf_sizes[0x1] = dpb_size;
 394         buf_sizes[0x2] = image_size;
 395         return 0;
 396 }
 397
 398 static int radeon_uvd_cs_msg(struct radeon_cs_parser *p, struct radeon_bo *bo,
 399                              unsigned offset, unsigned buf_sizes[])
 400 {
 401         int32_t *msg, msg_type, handle;
 402         unsigned img_size = 0;
 403         struct fence *f;
 404         void *ptr;
 405
 406         int i, r;
 407
 408         if (offset & 0x3F) {
 409                 DRM_ERROR("UVD messages must be 64 byte aligned!\n");
 410                 return -EINVAL;
 411         }
 412
 413         f = reservation_object_get_excl(bo->tbo.resv);
 414         if (f) {
 415                 r = radeon_fence_wait((struct radeon_fence *)f, false);
 416                 if (r) {
 417                         DRM_ERROR("Failed waiting for UVD message (%d)!\n", r);
 418                         return r;
 419                 }
 420         }
 421
 422         r = radeon_bo_kmap(bo, &ptr);
 423         if (r) {
 424                 DRM_ERROR("Failed mapping the UVD message (%d)!\n", r);
 425                 return r;
 426         }
 427
 428         msg = ptr + offset;
 429
 430         msg_type = msg[1];
 431         handle = msg[2];
 432
 433         if (handle == 0) {
 434                 DRM_ERROR("Invalid UVD handle!\n");
 435                 return -EINVAL;
 436         }
 437
 438         if (msg_type == 1) {
 439                 /* it's a decode msg, calc buffer sizes */
 440                 r = radeon_uvd_cs_msg_decode(msg, buf_sizes);
 441                 /* calc image size (width * height) */
 442                 img_size = msg[6] * msg[7];
 443                 radeon_bo_kunmap(bo);
 444                 if (r)
 445                         return r;
 446
 447         } else if (msg_type == 2) {
 448                 /* it's a destroy msg, free the handle */
 449                 for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i)
 450                         atomic_cmpxchg(&p->rdev->uvd.handles[i], handle, 0);
 451                 radeon_bo_kunmap(bo);
 452                 return 0;
 453         } else {
 454                 /* it's a create msg, calc image size (width * height) */
 455                 img_size = msg[7] * msg[8];
 456                 radeon_bo_kunmap(bo);
 457
 458                 if (msg_type != 0) {
 459                         DRM_ERROR("Illegal UVD message type (%d)!\n", msg_type);
 460                         return -EINVAL;
 461                 }
 462
 463                 /* it's a create msg, no special handling needed */
 464         }
 465
 466         /* create or decode, validate the handle */
 467         for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) {
 468                 if (atomic_read(&p->rdev->uvd.handles[i]) == handle)
 469                         return 0;
 470         }
 471
 472         /* handle not found try to alloc a new one */
 473         for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) {
 474                 if (!atomic_cmpxchg(&p->rdev->uvd.handles[i], 0, handle)) {
 475                         p->rdev->uvd.filp[i] = p->filp;
 476                         p->rdev->uvd.img_size[i] = img_size;
 477                         return 0;
 478                 }
 479         }
 480
 481         DRM_ERROR("No more free UVD handles!\n");
 482         return -EINVAL;
 483 }
 484
 485 static int radeon_uvd_cs_reloc(struct radeon_cs_parser *p,
 486                                int data0, int data1,
 487                                unsigned buf_sizes[], bool *has_msg_cmd)
 488 {
 489         struct radeon_cs_chunk *relocs_chunk;
 490         struct radeon_cs_reloc *reloc;
 491         unsigned idx, cmd, offset;
 492         uint64_t start, end;
 493         int r;
 494
 495         relocs_chunk = &p->chunks[p->chunk_relocs_idx];
 496         offset = radeon_get_ib_value(p, data0);
 497         idx = radeon_get_ib_value(p, data1);
 498         if (idx >= relocs_chunk->length_dw) {
 499                 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
 500                           idx, relocs_chunk->length_dw);
 501                 return -EINVAL;
 502         }
 503
 504         reloc = p->relocs_ptr[(idx / 4)];
 505         start = reloc->gpu_offset;
 506         end = start + radeon_bo_size(reloc->robj);
 507         start += offset;
 508
 509         p->ib.ptr[data0] = start & 0xFFFFFFFF;
 510         p->ib.ptr[data1] = start >> 32;
 511
 512         cmd = radeon_get_ib_value(p, p->idx) >> 1;
 513
 514         if (cmd < 0x4) {
 515                 if (end <= start) {
 516                         DRM_ERROR("invalid reloc offset %X!\n", offset);
 517                         return -EINVAL;
 518                 }
 519                 if ((end - start) < buf_sizes[cmd]) {
 520                         DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd,
 521                                   (unsigned)(end - start), buf_sizes[cmd]);
 522                         return -EINVAL;
 523                 }
 524
 525         } else if (cmd != 0x100) {
 526                 DRM_ERROR("invalid UVD command %X!\n", cmd);
 527                 return -EINVAL;
 528         }
 529
 530         if ((start >> 28) != ((end - 1) >> 28)) {
 531                 DRM_ERROR("reloc %LX-%LX crossing 256MB boundary!\n",
 532                           start, end);
 533                 return -EINVAL;
 534         }
 535
 536         /* TODO: is this still necessary on NI+ ? */
 537         if ((cmd == 0 || cmd == 0x3) &&
 538             (start >> 28) != (p->rdev->uvd.gpu_addr >> 28)) {
 539                 DRM_ERROR("msg/fb buffer %LX-%LX out of 256MB segment!\n",
 540                           start, end);
 541                 return -EINVAL;
 542         }
 543
 544         if (cmd == 0) {
 545                 if (*has_msg_cmd) {
 546                         DRM_ERROR("More than one message in a UVD-IB!\n");
 547                         return -EINVAL;
 548                 }
 549                 *has_msg_cmd = true;
 550                 r = radeon_uvd_cs_msg(p, reloc->robj, offset, buf_sizes);
 551                 if (r)
 552                         return r;
 553         } else if (!*has_msg_cmd) {
 554                 DRM_ERROR("Message needed before other commands are send!\n");
 555                 return -EINVAL;
 556         }
 557
 558         return 0;
 559 }
 560
 561 static int radeon_uvd_cs_reg(struct radeon_cs_parser *p,
 562                              struct radeon_cs_packet *pkt,
 563                              int *data0, int *data1,
 564                              unsigned buf_sizes[],
 565                              bool *has_msg_cmd)
 566 {
 567         int i, r;
 568
 569         p->idx++;
 570         for (i = 0; i <= pkt->count; ++i) {
 571                 switch (pkt->reg + i*4) {
 572                 case UVD_GPCOM_VCPU_DATA0:
 573                         *data0 = p->idx;
 574                         break;
 575                 case UVD_GPCOM_VCPU_DATA1:
 576                         *data1 = p->idx;
 577                         break;
 578                 case UVD_GPCOM_VCPU_CMD:
 579                         r = radeon_uvd_cs_reloc(p, *data0, *data1,
 580                                                 buf_sizes, has_msg_cmd);
 581                         if (r)
 582                                 return r;
 583                         break;
 584                 case UVD_ENGINE_CNTL:
 585                         break;
 586                 default:
 587                         DRM_ERROR("Invalid reg 0x%X!\n",
 588                                   pkt->reg + i*4);
 589                         return -EINVAL;
 590                 }
 591                 p->idx++;
 592         }
 593         return 0;
 594 }
 595
 596 int radeon_uvd_cs_parse(struct radeon_cs_parser *p)
 597 {
 598         struct radeon_cs_packet pkt;
 599         int r, data0 = 0, data1 = 0;
 600
 601         /* does the IB has a msg command */
 602         bool has_msg_cmd = false;
 603
 604         /* minimum buffer sizes */
 605         unsigned buf_sizes[] = {
 606                 [0x00000000]    =       2048,
 607                 [0x00000001]    =       32 * 1024 * 1024,
 608                 [0x00000002]    =       2048 * 1152 * 3,
 609                 [0x00000003]    =       2048,
 610         };
 611
 612         if (p->chunks[p->chunk_ib_idx].length_dw % 16) {
 613                 DRM_ERROR("UVD IB length (%d) not 16 dwords aligned!\n",
 614                           p->chunks[p->chunk_ib_idx].length_dw);
 615                 return -EINVAL;
 616         }
 617
 618         if (p->chunk_relocs_idx == -1) {
 619                 DRM_ERROR("No relocation chunk !\n");
 620                 return -EINVAL;
 621         }
 622
 623
 624         do {
 625                 r = radeon_cs_packet_parse(p, &pkt, p->idx);
 626                 if (r)
 627                         return r;
 628                 switch (pkt.type) {
 629                 case RADEON_PACKET_TYPE0:
 630                         r = radeon_uvd_cs_reg(p, &pkt, &data0, &data1,
 631                                               buf_sizes, &has_msg_cmd);
 632                         if (r)
 633                                 return r;
 634                         break;
 635                 case RADEON_PACKET_TYPE2:
 636                         p->idx += pkt.count + 2;
 637                         break;
 638                 default:
 639                         DRM_ERROR("Unknown packet type %d !\n", pkt.type);
 640                         return -EINVAL;
 641                 }
 642         } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
 643
 644         if (!has_msg_cmd) {
 645                 DRM_ERROR("UVD-IBs need a msg command!\n");
 646                 return -EINVAL;
 647         }
 648
 649         return 0;
 650 }
 651
 652 static int radeon_uvd_send_msg(struct radeon_device *rdev,
 653                                int ring, uint64_t addr,
 654                                struct radeon_fence **fence)
 655 {
 656         struct radeon_ib ib;
 657         int i, r;
 658
 659         r = radeon_ib_get(rdev, ring, &ib, NULL, 64);
 660         if (r)
 661                 return r;
 662
 663         ib.ptr[0] = PACKET0(UVD_GPCOM_VCPU_DATA0, 0);
 664         ib.ptr[1] = addr;
 665         ib.ptr[2] = PACKET0(UVD_GPCOM_VCPU_DATA1, 0);
 666         ib.ptr[3] = addr >> 32;
 667         ib.ptr[4] = PACKET0(UVD_GPCOM_VCPU_CMD, 0);
 668         ib.ptr[5] = 0;
 669         for (i = 6; i < 16; ++i)
 670                 ib.ptr[i] = PACKET2(0);
 671         ib.length_dw = 16;
 672
 673         r = radeon_ib_schedule(rdev, &ib, NULL, false);
 674
 675         if (fence)
 676                 *fence = radeon_fence_ref(ib.fence);
 677
 678         radeon_ib_free(rdev, &ib);
 679         return r;
 680 }
 681
 682 /* multiple fence commands without any stream commands in between can
 683    crash the vcpu so just try to emmit a dummy create/destroy msg to
 684    avoid this */
 685 int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring,
 686                               uint32_t handle, struct radeon_fence **fence)
 687 {
 688         /* we use the last page of the vcpu bo for the UVD message */
 689         uint64_t offs = radeon_bo_size(rdev->uvd.vcpu_bo) -
 690                 RADEON_GPU_PAGE_SIZE;
 691
 692         uint32_t *msg = rdev->uvd.cpu_addr + offs;
 693         uint64_t addr = rdev->uvd.gpu_addr + offs;
 694
 695         int r, i;
 696
 697         r = radeon_bo_reserve(rdev->uvd.vcpu_bo, true);
 698         if (r)
 699                 return r;
 700
 701         /* stitch together an UVD create msg */
 702         msg[0] = cpu_to_le32(0x00000de4);
 703         msg[1] = cpu_to_le32(0x00000000);
 704         msg[2] = cpu_to_le32(handle);
 705         msg[3] = cpu_to_le32(0x00000000);
 706         msg[4] = cpu_to_le32(0x00000000);
 707         msg[5] = cpu_to_le32(0x00000000);
 708         msg[6] = cpu_to_le32(0x00000000);
 709         msg[7] = cpu_to_le32(0x00000780);
 710         msg[8] = cpu_to_le32(0x00000440);
 711         msg[9] = cpu_to_le32(0x00000000);
 712         msg[10] = cpu_to_le32(0x01b37000);
 713         for (i = 11; i < 1024; ++i)
 714                 msg[i] = cpu_to_le32(0x0);
 715
 716         r = radeon_uvd_send_msg(rdev, ring, addr, fence);
 717         radeon_bo_unreserve(rdev->uvd.vcpu_bo);
 718         return r;
 719 }
 720
 721 int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring,
 722                                uint32_t handle, struct radeon_fence **fence)
 723 {
 724         /* we use the last page of the vcpu bo for the UVD message */
 725         uint64_t offs = radeon_bo_size(rdev->uvd.vcpu_bo) -
 726                 RADEON_GPU_PAGE_SIZE;
 727
 728         uint32_t *msg = rdev->uvd.cpu_addr + offs;
 729         uint64_t addr = rdev->uvd.gpu_addr + offs;
 730
 731         int r, i;
 732
 733         r = radeon_bo_reserve(rdev->uvd.vcpu_bo, true);
 734         if (r)
 735                 return r;
 736
 737         /* stitch together an UVD destroy msg */
 738         msg[0] = cpu_to_le32(0x00000de4);
 739         msg[1] = cpu_to_le32(0x00000002);
 740         msg[2] = cpu_to_le32(handle);
 741         msg[3] = cpu_to_le32(0x00000000);
 742         for (i = 4; i < 1024; ++i)
 743                 msg[i] = cpu_to_le32(0x0);
 744
 745         r = radeon_uvd_send_msg(rdev, ring, addr, fence);
 746         radeon_bo_unreserve(rdev->uvd.vcpu_bo);
 747         return r;
 748 }
 749
 750 /**
 751  * radeon_uvd_count_handles - count number of open streams
 752  *
 753  * @rdev: radeon_device pointer
 754  * @sd: number of SD streams
 755  * @hd: number of HD streams
 756  *
 757  * Count the number of open SD/HD streams as a hint for power mangement
 758  */
 759 static void radeon_uvd_count_handles(struct radeon_device *rdev,
 760                                      unsigned *sd, unsigned *hd)
 761 {
 762         unsigned i;
 763
 764         *sd = 0;
 765         *hd = 0;
 766
 767         for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) {
 768                 if (!atomic_read(&rdev->uvd.handles[i]))
 769                         continue;
 770
 771                 if (rdev->uvd.img_size[i] >= 720*576)
 772                         ++(*hd);
 773                 else
 774                         ++(*sd);
 775         }
 776 }
 777
 778 static void radeon_uvd_idle_work_handler(struct work_struct *work)
 779 {
 780         struct radeon_device *rdev =
 781                 container_of(work, struct radeon_device, uvd.idle_work.work);
 782
 783         if (radeon_fence_count_emitted(rdev, R600_RING_TYPE_UVD_INDEX) == 0) {
 784                 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
 785                         radeon_uvd_count_handles(rdev, &rdev->pm.dpm.sd,
 786                                                  &rdev->pm.dpm.hd);
 787                         radeon_dpm_enable_uvd(rdev, false);
 788                 } else {
 789                         radeon_set_uvd_clocks(rdev, 0, 0);
 790                 }
 791         } else {
 792                 schedule_delayed_work(&rdev->uvd.idle_work,
 793                                       msecs_to_jiffies(UVD_IDLE_TIMEOUT_MS));
 794         }
 795 }
 796
 797 void radeon_uvd_note_usage(struct radeon_device *rdev)
 798 {
 799         bool streams_changed = false;
 800         bool set_clocks = !cancel_delayed_work_sync(&rdev->uvd.idle_work);
 801         set_clocks &= schedule_delayed_work(&rdev->uvd.idle_work,
 802                                             msecs_to_jiffies(UVD_IDLE_TIMEOUT_MS));
 803
 804         if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
 805                 unsigned hd = 0, sd = 0;
 806                 radeon_uvd_count_handles(rdev, &sd, &hd);
 807                 if ((rdev->pm.dpm.sd != sd) ||
 808                     (rdev->pm.dpm.hd != hd)) {
 809                         rdev->pm.dpm.sd = sd;
 810                         rdev->pm.dpm.hd = hd;
 811                         /* disable this for now */
 812                         /*streams_changed = true;*/
 813                 }
 814         }
 815
 816         if (set_clocks || streams_changed) {
 817                 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
 818                         radeon_dpm_enable_uvd(rdev, true);
 819                 } else {
 820                         radeon_set_uvd_clocks(rdev, 53300, 40000);
 821                 }
 822         }
 823 }
 824
 825 static unsigned radeon_uvd_calc_upll_post_div(unsigned vco_freq,
 826                                               unsigned target_freq,
 827                                               unsigned pd_min,
 828                                               unsigned pd_even)
 829 {
 830         unsigned post_div = vco_freq / target_freq;
 831
 832         /* adjust to post divider minimum value */
 833         if (post_div < pd_min)
 834                 post_div = pd_min;
 835
 836         /* we alway need a frequency less than or equal the target */
 837         if ((vco_freq / post_div) > target_freq)
 838                 post_div += 1;
 839
 840         /* post dividers above a certain value must be even */
 841         if (post_div > pd_even && post_div % 2)
 842                 post_div += 1;
 843
 844         return post_div;
 845 }
 846
 847 /**
 848  * radeon_uvd_calc_upll_dividers - calc UPLL clock dividers
 849  *
 850  * @rdev: radeon_device pointer
 851  * @vclk: wanted VCLK
 852  * @dclk: wanted DCLK
 853  * @vco_min: minimum VCO frequency
 854  * @vco_max: maximum VCO frequency
 855  * @fb_factor: factor to multiply vco freq with
 856  * @fb_mask: limit and bitmask for feedback divider
 857  * @pd_min: post divider minimum
 858  * @pd_max: post divider maximum
 859  * @pd_even: post divider must be even above this value
 860  * @optimal_fb_div: resulting feedback divider
 861  * @optimal_vclk_div: resulting vclk post divider
 862  * @optimal_dclk_div: resulting dclk post divider
 863  *
 864  * Calculate dividers for UVDs UPLL (R6xx-SI, except APUs).
 865  * Returns zero on success -EINVAL on error.
 866  */
 867 int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev,
 868                                   unsigned vclk, unsigned dclk,
 869                                   unsigned vco_min, unsigned vco_max,
 870                                   unsigned fb_factor, unsigned fb_mask,
 871                                   unsigned pd_min, unsigned pd_max,
 872                                   unsigned pd_even,
 873                                   unsigned *optimal_fb_div,
 874                                   unsigned *optimal_vclk_div,
 875                                   unsigned *optimal_dclk_div)
 876 {
 877         unsigned vco_freq, ref_freq = rdev->clock.spll.reference_freq;
 878
 879         /* start off with something large */
 880         unsigned optimal_score = ~0;
 881
 882         /* loop through vco from low to high */
 883         vco_min = max(max(vco_min, vclk), dclk);
 884         for (vco_freq = vco_min; vco_freq <= vco_max; vco_freq += 100) {
 885
 886                 uint64_t fb_div = (uint64_t)vco_freq * fb_factor;
 887                 unsigned vclk_div, dclk_div, score;
 888
 889                 do_div(fb_div, ref_freq);
 890
 891                 /* fb div out of range ? */
 892                 if (fb_div > fb_mask)
 893                         break; /* it can oly get worse */
 894
 895                 fb_div &= fb_mask;
 896
 897                 /* calc vclk divider with current vco freq */
 898                 vclk_div = radeon_uvd_calc_upll_post_div(vco_freq, vclk,
 899                                                          pd_min, pd_even);
 900                 if (vclk_div > pd_max)
 901                         break; /* vco is too big, it has to stop */
 902
 903                 /* calc dclk divider with current vco freq */
 904                 dclk_div = radeon_uvd_calc_upll_post_div(vco_freq, dclk,
 905                                                          pd_min, pd_even);
 906                 if (vclk_div > pd_max)
 907                         break; /* vco is too big, it has to stop */
 908
 909                 /* calc score with current vco freq */
 910                 score = vclk - (vco_freq / vclk_div) + dclk - (vco_freq / dclk_div);
 911
 912                 /* determine if this vco setting is better than current optimal settings */
 913                 if (score < optimal_score) {
 914                         *optimal_fb_div = fb_div;
 915                         *optimal_vclk_div = vclk_div;
 916                         *optimal_dclk_div = dclk_div;
 917                         optimal_score = score;
 918                         if (optimal_score == 0)
 919                                 break; /* it can't get better than this */
 920                 }
 921         }
 922
 923         /* did we found a valid setup ? */
 924         if (optimal_score == ~0)
 925                 return -EINVAL;
 926
 927         return 0;
 928 }
 929
 930 int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev,
 931                                 unsigned cg_upll_func_cntl)
 932 {
 933         unsigned i;
 934
 935         /* make sure UPLL_CTLREQ is deasserted */
 936         WREG32_P(cg_upll_func_cntl, 0, ~UPLL_CTLREQ_MASK);
 937
 938         mdelay(10);
 939
 940         /* assert UPLL_CTLREQ */
 941         WREG32_P(cg_upll_func_cntl, UPLL_CTLREQ_MASK, ~UPLL_CTLREQ_MASK);
 942
 943         /* wait for CTLACK and CTLACK2 to get asserted */
 944         for (i = 0; i < 100; ++i) {
 945                 uint32_t mask = UPLL_CTLACK_MASK | UPLL_CTLACK2_MASK;
 946                 if ((RREG32(cg_upll_func_cntl) & mask) == mask)
 947                         break;
 948                 mdelay(10);
 949         }
 950
 951         /* deassert UPLL_CTLREQ */
 952         WREG32_P(cg_upll_func_cntl, 0, ~UPLL_CTLREQ_MASK);
 953
 954         if (i == 100) {
 955                 DRM_ERROR("Timeout setting UVD clocks!\n");
 956                 return -ETIMEDOUT;
 957         }
 958
 959         return 0;
 960 }