drivers/gpu/drm/radeon/radeon_uvd.c

   1 /*
   2  * Copyright 2011 Advanced Micro Devices, Inc.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26 /*
  27  * Authors:
  28  *    Christian König <deathsimple@vodafone.de>
  29  */
  30
  31 #include <linux/firmware.h>
  32 #include <linux/module.h>
  33 #include <drm/drmP.h>
  34 #include <drm/drm.h>
  35
  36 #include "radeon.h"
  37 #include "r600d.h"
  38
  39 /* 1 second timeout */
  40 #define UVD_IDLE_TIMEOUT_MS     1000
  41
  42 /* Firmware Names */
  43 #define FIRMWARE_RV710          "radeon/RV710_uvd.bin"
  44 #define FIRMWARE_CYPRESS        "radeon/CYPRESS_uvd.bin"
  45 #define FIRMWARE_SUMO           "radeon/SUMO_uvd.bin"
  46 #define FIRMWARE_TAHITI         "radeon/TAHITI_uvd.bin"
  47 #define FIRMWARE_BONAIRE        "radeon/BONAIRE_uvd.bin"
  48
  49 MODULE_FIRMWARE(FIRMWARE_RV710);
  50 MODULE_FIRMWARE(FIRMWARE_CYPRESS);
  51 MODULE_FIRMWARE(FIRMWARE_SUMO);
  52 MODULE_FIRMWARE(FIRMWARE_TAHITI);
  53 MODULE_FIRMWARE(FIRMWARE_BONAIRE);
  54
  55 static void radeon_uvd_idle_work_handler(struct work_struct *work);
  56
  57 int radeon_uvd_init(struct radeon_device *rdev)
  58 {
  59         unsigned long bo_size;
  60         const char *fw_name;
  61         int i, r;
  62
  63         INIT_DELAYED_WORK(&rdev->uvd.idle_work, radeon_uvd_idle_work_handler);
  64
  65         switch (rdev->family) {
  66         case CHIP_RV710:
  67         case CHIP_RV730:
  68         case CHIP_RV740:
  69                 fw_name = FIRMWARE_RV710;
  70                 break;
  71
  72         case CHIP_CYPRESS:
  73         case CHIP_HEMLOCK:
  74         case CHIP_JUNIPER:
  75         case CHIP_REDWOOD:
  76         case CHIP_CEDAR:
  77                 fw_name = FIRMWARE_CYPRESS;
  78                 break;
  79
  80         case CHIP_SUMO:
  81         case CHIP_SUMO2:
  82         case CHIP_PALM:
  83         case CHIP_CAYMAN:
  84         case CHIP_BARTS:
  85         case CHIP_TURKS:
  86         case CHIP_CAICOS:
  87                 fw_name = FIRMWARE_SUMO;
  88                 break;
  89
  90         case CHIP_TAHITI:
  91         case CHIP_VERDE:
  92         case CHIP_PITCAIRN:
  93         case CHIP_ARUBA:
  94                 fw_name = FIRMWARE_TAHITI;
  95                 break;
  96
  97         case CHIP_BONAIRE:
  98         case CHIP_KABINI:
  99         case CHIP_KAVERI:
 100                 fw_name = FIRMWARE_BONAIRE;
 101                 break;
 102
 103         default:
 104                 return -EINVAL;
 105         }
 106
 107         r = request_firmware(&rdev->uvd_fw, fw_name, rdev->dev);
 108         if (r) {
 109                 dev_err(rdev->dev, "radeon_uvd: Can't load firmware \"%s\"\n",
 110                         fw_name);
 111                 return r;
 112         }
 113
 114         bo_size = RADEON_GPU_PAGE_ALIGN(rdev->uvd_fw->size + 8) +
 115                   RADEON_UVD_STACK_SIZE + RADEON_UVD_HEAP_SIZE;
 116         r = radeon_bo_create(rdev, bo_size, PAGE_SIZE, true,
 117                              RADEON_GEM_DOMAIN_VRAM, NULL, &rdev->uvd.vcpu_bo);
 118         if (r) {
 119                 dev_err(rdev->dev, "(%d) failed to allocate UVD bo\n", r);
 120                 return r;
 121         }
 122
 123         r = radeon_bo_reserve(rdev->uvd.vcpu_bo, false);
 124         if (r) {
 125                 radeon_bo_unref(&rdev->uvd.vcpu_bo);
 126                 dev_err(rdev->dev, "(%d) failed to reserve UVD bo\n", r);
 127                 return r;
 128         }
 129
 130         r = radeon_bo_pin(rdev->uvd.vcpu_bo, RADEON_GEM_DOMAIN_VRAM,
 131                           &rdev->uvd.gpu_addr);
 132         if (r) {
 133                 radeon_bo_unreserve(rdev->uvd.vcpu_bo);
 134                 radeon_bo_unref(&rdev->uvd.vcpu_bo);
 135                 dev_err(rdev->dev, "(%d) UVD bo pin failed\n", r);
 136                 return r;
 137         }
 138
 139         r = radeon_bo_kmap(rdev->uvd.vcpu_bo, &rdev->uvd.cpu_addr);
 140         if (r) {
 141                 dev_err(rdev->dev, "(%d) UVD map failed\n", r);
 142                 return r;
 143         }
 144
 145         radeon_bo_unreserve(rdev->uvd.vcpu_bo);
 146
 147         for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) {
 148                 atomic_set(&rdev->uvd.handles[i], 0);
 149                 rdev->uvd.filp[i] = NULL;
 150         }
 151
 152         return 0;
 153 }
 154
 155 void radeon_uvd_fini(struct radeon_device *rdev)
 156 {
 157         int r;
 158
 159         if (rdev->uvd.vcpu_bo == NULL)
 160                 return;
 161
 162         r = radeon_bo_reserve(rdev->uvd.vcpu_bo, false);
 163         if (!r) {
 164                 radeon_bo_kunmap(rdev->uvd.vcpu_bo);
 165                 radeon_bo_unpin(rdev->uvd.vcpu_bo);
 166                 radeon_bo_unreserve(rdev->uvd.vcpu_bo);
 167         }
 168
 169         radeon_bo_unref(&rdev->uvd.vcpu_bo);
 170
 171         release_firmware(rdev->uvd_fw);
 172 }
 173
 174 int radeon_uvd_suspend(struct radeon_device *rdev)
 175 {
 176         unsigned size;
 177         void *ptr;
 178         int i;
 179
 180         if (rdev->uvd.vcpu_bo == NULL)
 181                 return 0;
 182
 183         for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i)
 184                 if (atomic_read(&rdev->uvd.handles[i]))
 185                         break;
 186
 187         if (i == RADEON_MAX_UVD_HANDLES)
 188                 return 0;
 189
 190         size = radeon_bo_size(rdev->uvd.vcpu_bo);
 191         size -= rdev->uvd_fw->size;
 192
 193         ptr = rdev->uvd.cpu_addr;
 194         ptr += rdev->uvd_fw->size;
 195
 196         rdev->uvd.saved_bo = kmalloc(size, GFP_KERNEL);
 197         memcpy(rdev->uvd.saved_bo, ptr, size);
 198
 199         return 0;
 200 }
 201
 202 int radeon_uvd_resume(struct radeon_device *rdev)
 203 {
 204         unsigned size;
 205         void *ptr;
 206
 207         if (rdev->uvd.vcpu_bo == NULL)
 208                 return -EINVAL;
 209
 210         memcpy(rdev->uvd.cpu_addr, rdev->uvd_fw->data, rdev->uvd_fw->size);
 211
 212         size = radeon_bo_size(rdev->uvd.vcpu_bo);
 213         size -= rdev->uvd_fw->size;
 214
 215         ptr = rdev->uvd.cpu_addr;
 216         ptr += rdev->uvd_fw->size;
 217
 218         if (rdev->uvd.saved_bo != NULL) {
 219                 memcpy(ptr, rdev->uvd.saved_bo, size);
 220                 kfree(rdev->uvd.saved_bo);
 221                 rdev->uvd.saved_bo = NULL;
 222         } else
 223                 memset(ptr, 0, size);
 224
 225         return 0;
 226 }
 227
 228 void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo)
 229 {
 230         rbo->placement.fpfn = 0 >> PAGE_SHIFT;
 231         rbo->placement.lpfn = (256 * 1024 * 1024) >> PAGE_SHIFT;
 232 }
 233
 234 void radeon_uvd_free_handles(struct radeon_device *rdev, struct drm_file *filp)
 235 {
 236         int i, r;
 237         for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) {
 238                 uint32_t handle = atomic_read(&rdev->uvd.handles[i]);
 239                 if (handle != 0 && rdev->uvd.filp[i] == filp) {
 240                         struct radeon_fence *fence;
 241
 242                         r = radeon_uvd_get_destroy_msg(rdev,
 243                                 R600_RING_TYPE_UVD_INDEX, handle, &fence);
 244                         if (r) {
 245                                 DRM_ERROR("Error destroying UVD (%d)!\n", r);
 246                                 continue;
 247                         }
 248
 249                         radeon_fence_wait(fence, false);
 250                         radeon_fence_unref(&fence);
 251
 252                         rdev->uvd.filp[i] = NULL;
 253                         atomic_set(&rdev->uvd.handles[i], 0);
 254                 }
 255         }
 256 }
 257
 258 static int radeon_uvd_cs_msg_decode(uint32_t *msg, unsigned buf_sizes[])
 259 {
 260         unsigned stream_type = msg[4];
 261         unsigned width = msg[6];
 262         unsigned height = msg[7];
 263         unsigned dpb_size = msg[9];
 264         unsigned pitch = msg[28];
 265
 266         unsigned width_in_mb = width / 16;
 267         unsigned height_in_mb = ALIGN(height / 16, 2);
 268
 269         unsigned image_size, tmp, min_dpb_size;
 270
 271         image_size = width * height;
 272         image_size += image_size / 2;
 273         image_size = ALIGN(image_size, 1024);
 274
 275         switch (stream_type) {
 276         case 0: /* H264 */
 277
 278                 /* reference picture buffer */
 279                 min_dpb_size = image_size * 17;
 280
 281                 /* macroblock context buffer */
 282                 min_dpb_size += width_in_mb * height_in_mb * 17 * 192;
 283
 284                 /* IT surface buffer */
 285                 min_dpb_size += width_in_mb * height_in_mb * 32;
 286                 break;
 287
 288         case 1: /* VC1 */
 289
 290                 /* reference picture buffer */
 291                 min_dpb_size = image_size * 3;
 292
 293                 /* CONTEXT_BUFFER */
 294                 min_dpb_size += width_in_mb * height_in_mb * 128;
 295
 296                 /* IT surface buffer */
 297                 min_dpb_size += width_in_mb * 64;
 298
 299                 /* DB surface buffer */
 300                 min_dpb_size += width_in_mb * 128;
 301
 302                 /* BP */
 303                 tmp = max(width_in_mb, height_in_mb);
 304                 min_dpb_size += ALIGN(tmp * 7 * 16, 64);
 305                 break;
 306
 307         case 3: /* MPEG2 */
 308
 309                 /* reference picture buffer */
 310                 min_dpb_size = image_size * 3;
 311                 break;
 312
 313         case 4: /* MPEG4 */
 314
 315                 /* reference picture buffer */
 316                 min_dpb_size = image_size * 3;
 317
 318                 /* CM */
 319                 min_dpb_size += width_in_mb * height_in_mb * 64;
 320
 321                 /* IT surface buffer */
 322                 min_dpb_size += ALIGN(width_in_mb * height_in_mb * 32, 64);
 323                 break;
 324
 325         default:
 326                 DRM_ERROR("UVD codec not handled %d!\n", stream_type);
 327                 return -EINVAL;
 328         }
 329
 330         if (width > pitch) {
 331                 DRM_ERROR("Invalid UVD decoding target pitch!\n");
 332                 return -EINVAL;
 333         }
 334
 335         if (dpb_size < min_dpb_size) {
 336                 DRM_ERROR("Invalid dpb_size in UVD message (%d / %d)!\n",
 337                           dpb_size, min_dpb_size);
 338                 return -EINVAL;
 339         }
 340
 341         buf_sizes[0x1] = dpb_size;
 342         buf_sizes[0x2] = image_size;
 343         return 0;
 344 }
 345
 346 static int radeon_uvd_cs_msg(struct radeon_cs_parser *p, struct radeon_bo *bo,
 347                              unsigned offset, unsigned buf_sizes[])
 348 {
 349         int32_t *msg, msg_type, handle;
 350         void *ptr;
 351
 352         int i, r;
 353
 354         if (offset & 0x3F) {
 355                 DRM_ERROR("UVD messages must be 64 byte aligned!\n");
 356                 return -EINVAL;
 357         }
 358
 359         r = radeon_bo_kmap(bo, &ptr);
 360         if (r) {
 361                 DRM_ERROR("Failed mapping the UVD message (%d)!\n", r);
 362                 return r;
 363         }
 364
 365         msg = ptr + offset;
 366
 367         msg_type = msg[1];
 368         handle = msg[2];
 369
 370         if (handle == 0) {
 371                 DRM_ERROR("Invalid UVD handle!\n");
 372                 return -EINVAL;
 373         }
 374
 375         if (msg_type == 1) {
 376                 /* it's a decode msg, calc buffer sizes */
 377                 r = radeon_uvd_cs_msg_decode(msg, buf_sizes);
 378                 radeon_bo_kunmap(bo);
 379                 if (r)
 380                         return r;
 381
 382         } else if (msg_type == 2) {
 383                 /* it's a destroy msg, free the handle */
 384                 for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i)
 385                         atomic_cmpxchg(&p->rdev->uvd.handles[i], handle, 0);
 386                 radeon_bo_kunmap(bo);
 387                 return 0;
 388         } else {
 389                 radeon_bo_kunmap(bo);
 390
 391                 if (msg_type != 0) {
 392                         DRM_ERROR("Illegal UVD message type (%d)!\n", msg_type);
 393                         return -EINVAL;
 394                 }
 395
 396                 /* it's a create msg, no special handling needed */
 397         }
 398
 399         /* create or decode, validate the handle */
 400         for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) {
 401                 if (atomic_read(&p->rdev->uvd.handles[i]) == handle)
 402                         return 0;
 403         }
 404
 405         /* handle not found try to alloc a new one */
 406         for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) {
 407                 if (!atomic_cmpxchg(&p->rdev->uvd.handles[i], 0, handle)) {
 408                         p->rdev->uvd.filp[i] = p->filp;
 409                         return 0;
 410                 }
 411         }
 412
 413         DRM_ERROR("No more free UVD handles!\n");
 414         return -EINVAL;
 415 }
 416
 417 static int radeon_uvd_cs_reloc(struct radeon_cs_parser *p,
 418                                int data0, int data1,
 419                                unsigned buf_sizes[], bool *has_msg_cmd)
 420 {
 421         struct radeon_cs_chunk *relocs_chunk;
 422         struct radeon_cs_reloc *reloc;
 423         unsigned idx, cmd, offset;
 424         uint64_t start, end;
 425         int r;
 426
 427         relocs_chunk = &p->chunks[p->chunk_relocs_idx];
 428         offset = radeon_get_ib_value(p, data0);
 429         idx = radeon_get_ib_value(p, data1);
 430         if (idx >= relocs_chunk->length_dw) {
 431                 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
 432                           idx, relocs_chunk->length_dw);
 433                 return -EINVAL;
 434         }
 435
 436         reloc = p->relocs_ptr[(idx / 4)];
 437         start = reloc->lobj.gpu_offset;
 438         end = start + radeon_bo_size(reloc->robj);
 439         start += offset;
 440
 441         p->ib.ptr[data0] = start & 0xFFFFFFFF;
 442         p->ib.ptr[data1] = start >> 32;
 443
 444         cmd = radeon_get_ib_value(p, p->idx) >> 1;
 445
 446         if (cmd < 0x4) {
 447                 if ((end - start) < buf_sizes[cmd]) {
 448                         DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd,
 449                                   (unsigned)(end - start), buf_sizes[cmd]);
 450                         return -EINVAL;
 451                 }
 452
 453         } else if (cmd != 0x100) {
 454                 DRM_ERROR("invalid UVD command %X!\n", cmd);
 455                 return -EINVAL;
 456         }
 457
 458         if ((start >> 28) != (end >> 28)) {
 459                 DRM_ERROR("reloc %LX-%LX crossing 256MB boundary!\n",
 460                           start, end);
 461                 return -EINVAL;
 462         }
 463
 464         /* TODO: is this still necessary on NI+ ? */
 465         if ((cmd == 0 || cmd == 0x3) &&
 466             (start >> 28) != (p->rdev->uvd.gpu_addr >> 28)) {
 467                 DRM_ERROR("msg/fb buffer %LX-%LX out of 256MB segment!\n",
 468                           start, end);
 469                 return -EINVAL;
 470         }
 471
 472         if (cmd == 0) {
 473                 if (*has_msg_cmd) {
 474                         DRM_ERROR("More than one message in a UVD-IB!\n");
 475                         return -EINVAL;
 476                 }
 477                 *has_msg_cmd = true;
 478                 r = radeon_uvd_cs_msg(p, reloc->robj, offset, buf_sizes);
 479                 if (r)
 480                         return r;
 481         } else if (!*has_msg_cmd) {
 482                 DRM_ERROR("Message needed before other commands are send!\n");
 483                 return -EINVAL;
 484         }
 485
 486         return 0;
 487 }
 488
 489 static int radeon_uvd_cs_reg(struct radeon_cs_parser *p,
 490                              struct radeon_cs_packet *pkt,
 491                              int *data0, int *data1,
 492                              unsigned buf_sizes[],
 493                              bool *has_msg_cmd)
 494 {
 495         int i, r;
 496
 497         p->idx++;
 498         for (i = 0; i <= pkt->count; ++i) {
 499                 switch (pkt->reg + i*4) {
 500                 case UVD_GPCOM_VCPU_DATA0:
 501                         *data0 = p->idx;
 502                         break;
 503                 case UVD_GPCOM_VCPU_DATA1:
 504                         *data1 = p->idx;
 505                         break;
 506                 case UVD_GPCOM_VCPU_CMD:
 507                         r = radeon_uvd_cs_reloc(p, *data0, *data1,
 508                                                 buf_sizes, has_msg_cmd);
 509                         if (r)
 510                                 return r;
 511                         break;
 512                 case UVD_ENGINE_CNTL:
 513                         break;
 514                 default:
 515                         DRM_ERROR("Invalid reg 0x%X!\n",
 516                                   pkt->reg + i*4);
 517                         return -EINVAL;
 518                 }
 519                 p->idx++;
 520         }
 521         return 0;
 522 }
 523
 524 int radeon_uvd_cs_parse(struct radeon_cs_parser *p)
 525 {
 526         struct radeon_cs_packet pkt;
 527         int r, data0 = 0, data1 = 0;
 528
 529         /* does the IB has a msg command */
 530         bool has_msg_cmd = false;
 531
 532         /* minimum buffer sizes */
 533         unsigned buf_sizes[] = {
 534                 [0x00000000]    =       2048,
 535                 [0x00000001]    =       32 * 1024 * 1024,
 536                 [0x00000002]    =       2048 * 1152 * 3,
 537                 [0x00000003]    =       2048,
 538         };
 539
 540         if (p->chunks[p->chunk_ib_idx].length_dw % 16) {
 541                 DRM_ERROR("UVD IB length (%d) not 16 dwords aligned!\n",
 542                           p->chunks[p->chunk_ib_idx].length_dw);
 543                 return -EINVAL;
 544         }
 545
 546         if (p->chunk_relocs_idx == -1) {
 547                 DRM_ERROR("No relocation chunk !\n");
 548                 return -EINVAL;
 549         }
 550
 551
 552         do {
 553                 r = radeon_cs_packet_parse(p, &pkt, p->idx);
 554                 if (r)
 555                         return r;
 556                 switch (pkt.type) {
 557                 case RADEON_PACKET_TYPE0:
 558                         r = radeon_uvd_cs_reg(p, &pkt, &data0, &data1,
 559                                               buf_sizes, &has_msg_cmd);
 560                         if (r)
 561                                 return r;
 562                         break;
 563                 case RADEON_PACKET_TYPE2:
 564                         p->idx += pkt.count + 2;
 565                         break;
 566                 default:
 567                         DRM_ERROR("Unknown packet type %d !\n", pkt.type);
 568                         return -EINVAL;
 569                 }
 570         } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
 571
 572         if (!has_msg_cmd) {
 573                 DRM_ERROR("UVD-IBs need a msg command!\n");
 574                 return -EINVAL;
 575         }
 576
 577         return 0;
 578 }
 579
 580 static int radeon_uvd_send_msg(struct radeon_device *rdev,
 581                                int ring, struct radeon_bo *bo,
 582                                struct radeon_fence **fence)
 583 {
 584         struct ttm_validate_buffer tv;
 585         struct ww_acquire_ctx ticket;
 586         struct list_head head;
 587         struct radeon_ib ib;
 588         uint64_t addr;
 589         int i, r;
 590
 591         memset(&tv, 0, sizeof(tv));
 592         tv.bo = &bo->tbo;
 593
 594         INIT_LIST_HEAD(&head);
 595         list_add(&tv.head, &head);
 596
 597         r = ttm_eu_reserve_buffers(&ticket, &head);
 598         if (r)
 599                 return r;
 600
 601         radeon_ttm_placement_from_domain(bo, RADEON_GEM_DOMAIN_VRAM);
 602         radeon_uvd_force_into_uvd_segment(bo);
 603
 604         r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
 605         if (r)
 606                 goto err;
 607
 608         r = radeon_ib_get(rdev, ring, &ib, NULL, 16);
 609         if (r)
 610                 goto err;
 611
 612         addr = radeon_bo_gpu_offset(bo);
 613         ib.ptr[0] = PACKET0(UVD_GPCOM_VCPU_DATA0, 0);
 614         ib.ptr[1] = addr;
 615         ib.ptr[2] = PACKET0(UVD_GPCOM_VCPU_DATA1, 0);
 616         ib.ptr[3] = addr >> 32;
 617         ib.ptr[4] = PACKET0(UVD_GPCOM_VCPU_CMD, 0);
 618         ib.ptr[5] = 0;
 619         for (i = 6; i < 16; ++i)
 620                 ib.ptr[i] = PACKET2(0);
 621         ib.length_dw = 16;
 622
 623         r = radeon_ib_schedule(rdev, &ib, NULL);
 624         if (r)
 625                 goto err;
 626         ttm_eu_fence_buffer_objects(&ticket, &head, ib.fence);
 627
 628         if (fence)
 629                 *fence = radeon_fence_ref(ib.fence);
 630
 631         radeon_ib_free(rdev, &ib);
 632         radeon_bo_unref(&bo);
 633         return 0;
 634
 635 err:
 636         ttm_eu_backoff_reservation(&ticket, &head);
 637         return r;
 638 }
 639
 640 /* multiple fence commands without any stream commands in between can
 641    crash the vcpu so just try to emmit a dummy create/destroy msg to
 642    avoid this */
 643 int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring,
 644                               uint32_t handle, struct radeon_fence **fence)
 645 {
 646         struct radeon_bo *bo;
 647         uint32_t *msg;
 648         int r, i;
 649
 650         r = radeon_bo_create(rdev, 1024, PAGE_SIZE, true,
 651                              RADEON_GEM_DOMAIN_VRAM, NULL, &bo);
 652         if (r)
 653                 return r;
 654
 655         r = radeon_bo_reserve(bo, false);
 656         if (r) {
 657                 radeon_bo_unref(&bo);
 658                 return r;
 659         }
 660
 661         r = radeon_bo_kmap(bo, (void **)&msg);
 662         if (r) {
 663                 radeon_bo_unreserve(bo);
 664                 radeon_bo_unref(&bo);
 665                 return r;
 666         }
 667
 668         /* stitch together an UVD create msg */
 669         msg[0] = cpu_to_le32(0x00000de4);
 670         msg[1] = cpu_to_le32(0x00000000);
 671         msg[2] = cpu_to_le32(handle);
 672         msg[3] = cpu_to_le32(0x00000000);
 673         msg[4] = cpu_to_le32(0x00000000);
 674         msg[5] = cpu_to_le32(0x00000000);
 675         msg[6] = cpu_to_le32(0x00000000);
 676         msg[7] = cpu_to_le32(0x00000780);
 677         msg[8] = cpu_to_le32(0x00000440);
 678         msg[9] = cpu_to_le32(0x00000000);
 679         msg[10] = cpu_to_le32(0x01b37000);
 680         for (i = 11; i < 1024; ++i)
 681                 msg[i] = cpu_to_le32(0x0);
 682
 683         radeon_bo_kunmap(bo);
 684         radeon_bo_unreserve(bo);
 685
 686         return radeon_uvd_send_msg(rdev, ring, bo, fence);
 687 }
 688
 689 int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring,
 690                                uint32_t handle, struct radeon_fence **fence)
 691 {
 692         struct radeon_bo *bo;
 693         uint32_t *msg;
 694         int r, i;
 695
 696         r = radeon_bo_create(rdev, 1024, PAGE_SIZE, true,
 697                              RADEON_GEM_DOMAIN_VRAM, NULL, &bo);
 698         if (r)
 699                 return r;
 700
 701         r = radeon_bo_reserve(bo, false);
 702         if (r) {
 703                 radeon_bo_unref(&bo);
 704                 return r;
 705         }
 706
 707         r = radeon_bo_kmap(bo, (void **)&msg);
 708         if (r) {
 709                 radeon_bo_unreserve(bo);
 710                 radeon_bo_unref(&bo);
 711                 return r;
 712         }
 713
 714         /* stitch together an UVD destroy msg */
 715         msg[0] = cpu_to_le32(0x00000de4);
 716         msg[1] = cpu_to_le32(0x00000002);
 717         msg[2] = cpu_to_le32(handle);
 718         msg[3] = cpu_to_le32(0x00000000);
 719         for (i = 4; i < 1024; ++i)
 720                 msg[i] = cpu_to_le32(0x0);
 721
 722         radeon_bo_kunmap(bo);
 723         radeon_bo_unreserve(bo);
 724
 725         return radeon_uvd_send_msg(rdev, ring, bo, fence);
 726 }
 727
 728 static void radeon_uvd_idle_work_handler(struct work_struct *work)
 729 {
 730         struct radeon_device *rdev =
 731                 container_of(work, struct radeon_device, uvd.idle_work.work);
 732
 733         if (radeon_fence_count_emitted(rdev, R600_RING_TYPE_UVD_INDEX) == 0) {
 734                 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
 735                         mutex_lock(&rdev->pm.mutex);
 736                         rdev->pm.dpm.uvd_active = false;
 737                         mutex_unlock(&rdev->pm.mutex);
 738                         radeon_pm_compute_clocks(rdev);
 739                 } else {
 740                         radeon_set_uvd_clocks(rdev, 0, 0);
 741                 }
 742         } else {
 743                 schedule_delayed_work(&rdev->uvd.idle_work,
 744                                       msecs_to_jiffies(UVD_IDLE_TIMEOUT_MS));
 745         }
 746 }
 747
 748 void radeon_uvd_note_usage(struct radeon_device *rdev)
 749 {
 750         bool set_clocks = !cancel_delayed_work_sync(&rdev->uvd.idle_work);
 751         set_clocks &= schedule_delayed_work(&rdev->uvd.idle_work,
 752                                             msecs_to_jiffies(UVD_IDLE_TIMEOUT_MS));
 753         if (set_clocks) {
 754                 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
 755                         /* XXX pick SD/HD/MVC */
 756                         radeon_dpm_enable_power_state(rdev, POWER_STATE_TYPE_INTERNAL_UVD);
 757                 } else {
 758                         radeon_set_uvd_clocks(rdev, 53300, 40000);
 759                 }
 760         }
 761 }
 762
 763 static unsigned radeon_uvd_calc_upll_post_div(unsigned vco_freq,
 764                                               unsigned target_freq,
 765                                               unsigned pd_min,
 766                                               unsigned pd_even)
 767 {
 768         unsigned post_div = vco_freq / target_freq;
 769
 770         /* adjust to post divider minimum value */
 771         if (post_div < pd_min)
 772                 post_div = pd_min;
 773
 774         /* we alway need a frequency less than or equal the target */
 775         if ((vco_freq / post_div) > target_freq)
 776                 post_div += 1;
 777
 778         /* post dividers above a certain value must be even */
 779         if (post_div > pd_even && post_div % 2)
 780                 post_div += 1;
 781
 782         return post_div;
 783 }
 784
 785 /**
 786  * radeon_uvd_calc_upll_dividers - calc UPLL clock dividers
 787  *
 788  * @rdev: radeon_device pointer
 789  * @vclk: wanted VCLK
 790  * @dclk: wanted DCLK
 791  * @vco_min: minimum VCO frequency
 792  * @vco_max: maximum VCO frequency
 793  * @fb_factor: factor to multiply vco freq with
 794  * @fb_mask: limit and bitmask for feedback divider
 795  * @pd_min: post divider minimum
 796  * @pd_max: post divider maximum
 797  * @pd_even: post divider must be even above this value
 798  * @optimal_fb_div: resulting feedback divider
 799  * @optimal_vclk_div: resulting vclk post divider
 800  * @optimal_dclk_div: resulting dclk post divider
 801  *
 802  * Calculate dividers for UVDs UPLL (R6xx-SI, except APUs).
 803  * Returns zero on success -EINVAL on error.
 804  */
 805 int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev,
 806                                   unsigned vclk, unsigned dclk,
 807                                   unsigned vco_min, unsigned vco_max,
 808                                   unsigned fb_factor, unsigned fb_mask,
 809                                   unsigned pd_min, unsigned pd_max,
 810                                   unsigned pd_even,
 811                                   unsigned *optimal_fb_div,
 812                                   unsigned *optimal_vclk_div,
 813                                   unsigned *optimal_dclk_div)
 814 {
 815         unsigned vco_freq, ref_freq = rdev->clock.spll.reference_freq;
 816
 817         /* start off with something large */
 818         unsigned optimal_score = ~0;
 819
 820         /* loop through vco from low to high */
 821         vco_min = max(max(vco_min, vclk), dclk);
 822         for (vco_freq = vco_min; vco_freq <= vco_max; vco_freq += 100) {
 823
 824                 uint64_t fb_div = (uint64_t)vco_freq * fb_factor;
 825                 unsigned vclk_div, dclk_div, score;
 826
 827                 do_div(fb_div, ref_freq);
 828
 829                 /* fb div out of range ? */
 830                 if (fb_div > fb_mask)
 831                         break; /* it can oly get worse */
 832
 833                 fb_div &= fb_mask;
 834
 835                 /* calc vclk divider with current vco freq */
 836                 vclk_div = radeon_uvd_calc_upll_post_div(vco_freq, vclk,
 837                                                          pd_min, pd_even);
 838                 if (vclk_div > pd_max)
 839                         break; /* vco is too big, it has to stop */
 840
 841                 /* calc dclk divider with current vco freq */
 842                 dclk_div = radeon_uvd_calc_upll_post_div(vco_freq, dclk,
 843                                                          pd_min, pd_even);
 844                 if (vclk_div > pd_max)
 845                         break; /* vco is too big, it has to stop */
 846
 847                 /* calc score with current vco freq */
 848                 score = vclk - (vco_freq / vclk_div) + dclk - (vco_freq / dclk_div);
 849
 850                 /* determine if this vco setting is better than current optimal settings */
 851                 if (score < optimal_score) {
 852                         *optimal_fb_div = fb_div;
 853                         *optimal_vclk_div = vclk_div;
 854                         *optimal_dclk_div = dclk_div;
 855                         optimal_score = score;
 856                         if (optimal_score == 0)
 857                                 break; /* it can't get better than this */
 858                 }
 859         }
 860
 861         /* did we found a valid setup ? */
 862         if (optimal_score == ~0)
 863                 return -EINVAL;
 864
 865         return 0;
 866 }
 867
 868 int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev,
 869                                 unsigned cg_upll_func_cntl)
 870 {
 871         unsigned i;
 872
 873         /* make sure UPLL_CTLREQ is deasserted */
 874         WREG32_P(cg_upll_func_cntl, 0, ~UPLL_CTLREQ_MASK);
 875
 876         mdelay(10);
 877
 878         /* assert UPLL_CTLREQ */
 879         WREG32_P(cg_upll_func_cntl, UPLL_CTLREQ_MASK, ~UPLL_CTLREQ_MASK);
 880
 881         /* wait for CTLACK and CTLACK2 to get asserted */
 882         for (i = 0; i < 100; ++i) {
 883                 uint32_t mask = UPLL_CTLACK_MASK | UPLL_CTLACK2_MASK;
 884                 if ((RREG32(cg_upll_func_cntl) & mask) == mask)
 885                         break;
 886                 mdelay(10);
 887         }
 888
 889         /* deassert UPLL_CTLREQ */
 890         WREG32_P(cg_upll_func_cntl, 0, ~UPLL_CTLREQ_MASK);
 891
 892         if (i == 100) {
 893                 DRM_ERROR("Timeout setting UVD clocks!\n");
 894                 return -ETIMEDOUT;
 895         }
 896
 897         return 0;
 898 }