2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
29 #include <drm/radeon_drm.h>
31 #include "radeon_trace.h"
35 * GPUVM is similar to the legacy gart on older asics, however
36 * rather than there being a single global gart table
37 * for the entire GPU, there are multiple VM page tables active
38 * at any given time. The VM page tables can contain a mix
39 * vram pages and system memory pages and system memory pages
40 * can be mapped as snooped (cached system pages) or unsnooped
41 * (uncached system pages).
42 * Each VM has an ID associated with it and there is a page table
43 * associated with each VMID. When execting a command buffer,
44 * the kernel tells the the ring what VMID to use for that command
45 * buffer. VMIDs are allocated dynamically as commands are submitted.
46 * The userspace drivers maintain their own address space and the kernel
47 * sets up their pages tables accordingly when they submit their
48 * command buffers and a VMID is assigned.
49 * Cayman/Trinity support up to 8 active VMs at any given time;
54 * radeon_vm_num_pde - return the number of page directory entries
56 * @rdev: radeon_device pointer
58 * Calculate the number of page directory entries (cayman+).
60 static unsigned radeon_vm_num_pdes(struct radeon_device
*rdev
)
62 return rdev
->vm_manager
.max_pfn
>> radeon_vm_block_size
;
66 * radeon_vm_directory_size - returns the size of the page directory in bytes
68 * @rdev: radeon_device pointer
70 * Calculate the size of the page directory in bytes (cayman+).
72 static unsigned radeon_vm_directory_size(struct radeon_device
*rdev
)
74 return RADEON_GPU_PAGE_ALIGN(radeon_vm_num_pdes(rdev
) * 8);
78 * radeon_vm_manager_init - init the vm manager
80 * @rdev: radeon_device pointer
82 * Init the vm manager (cayman+).
83 * Returns 0 for success, error for failure.
85 int radeon_vm_manager_init(struct radeon_device
*rdev
)
89 if (!rdev
->vm_manager
.enabled
) {
90 r
= radeon_asic_vm_init(rdev
);
94 rdev
->vm_manager
.enabled
= true;
100 * radeon_vm_manager_fini - tear down the vm manager
102 * @rdev: radeon_device pointer
104 * Tear down the VM manager (cayman+).
106 void radeon_vm_manager_fini(struct radeon_device
*rdev
)
110 if (!rdev
->vm_manager
.enabled
)
113 for (i
= 0; i
< RADEON_NUM_VM
; ++i
)
114 radeon_fence_unref(&rdev
->vm_manager
.active
[i
]);
115 radeon_asic_vm_fini(rdev
);
116 rdev
->vm_manager
.enabled
= false;
120 * radeon_vm_get_bos - add the vm BOs to a validation list
122 * @vm: vm providing the BOs
123 * @head: head of validation list
125 * Add the page directory to the list of BOs to
126 * validate for command submission (cayman+).
128 struct radeon_bo_list
*radeon_vm_get_bos(struct radeon_device
*rdev
,
129 struct radeon_vm
*vm
,
130 struct list_head
*head
)
132 struct radeon_bo_list
*list
;
135 list
= drm_malloc_ab(vm
->max_pde_used
+ 2,
136 sizeof(struct radeon_bo_list
));
140 /* add the vm page table to the list */
141 list
[0].robj
= vm
->page_directory
;
142 list
[0].prefered_domains
= RADEON_GEM_DOMAIN_VRAM
;
143 list
[0].allowed_domains
= RADEON_GEM_DOMAIN_VRAM
;
144 list
[0].tv
.bo
= &vm
->page_directory
->tbo
;
145 list
[0].tv
.shared
= true;
146 list
[0].tiling_flags
= 0;
147 list_add(&list
[0].tv
.head
, head
);
149 for (i
= 0, idx
= 1; i
<= vm
->max_pde_used
; i
++) {
150 if (!vm
->page_tables
[i
].bo
)
153 list
[idx
].robj
= vm
->page_tables
[i
].bo
;
154 list
[idx
].prefered_domains
= RADEON_GEM_DOMAIN_VRAM
;
155 list
[idx
].allowed_domains
= RADEON_GEM_DOMAIN_VRAM
;
156 list
[idx
].tv
.bo
= &list
[idx
].robj
->tbo
;
157 list
[idx
].tv
.shared
= true;
158 list
[idx
].tiling_flags
= 0;
159 list_add(&list
[idx
++].tv
.head
, head
);
166 * radeon_vm_grab_id - allocate the next free VMID
168 * @rdev: radeon_device pointer
169 * @vm: vm to allocate id for
170 * @ring: ring we want to submit job to
172 * Allocate an id for the vm (cayman+).
173 * Returns the fence we need to sync to (if any).
175 * Global and local mutex must be locked!
177 struct radeon_fence
*radeon_vm_grab_id(struct radeon_device
*rdev
,
178 struct radeon_vm
*vm
, int ring
)
180 struct radeon_fence
*best
[RADEON_NUM_RINGS
] = {};
181 struct radeon_vm_id
*vm_id
= &vm
->ids
[ring
];
183 unsigned choices
[2] = {};
186 /* check if the id is still valid */
187 if (vm_id
->id
&& vm_id
->last_id_use
&&
188 vm_id
->last_id_use
== rdev
->vm_manager
.active
[vm_id
->id
])
191 /* we definately need to flush */
192 vm_id
->pd_gpu_addr
= ~0ll;
194 /* skip over VMID 0, since it is the system VM */
195 for (i
= 1; i
< rdev
->vm_manager
.nvm
; ++i
) {
196 struct radeon_fence
*fence
= rdev
->vm_manager
.active
[i
];
199 /* found a free one */
201 trace_radeon_vm_grab_id(i
, ring
);
205 if (radeon_fence_is_earlier(fence
, best
[fence
->ring
])) {
206 best
[fence
->ring
] = fence
;
207 choices
[fence
->ring
== ring
? 0 : 1] = i
;
211 for (i
= 0; i
< 2; ++i
) {
213 vm_id
->id
= choices
[i
];
214 trace_radeon_vm_grab_id(choices
[i
], ring
);
215 return rdev
->vm_manager
.active
[choices
[i
]];
219 /* should never happen */
225 * radeon_vm_flush - hardware flush the vm
227 * @rdev: radeon_device pointer
228 * @vm: vm we want to flush
229 * @ring: ring to use for flush
230 * @updates: last vm update that is waited for
232 * Flush the vm (cayman+).
234 * Global and local mutex must be locked!
236 void radeon_vm_flush(struct radeon_device
*rdev
,
237 struct radeon_vm
*vm
,
238 int ring
, struct radeon_fence
*updates
)
240 uint64_t pd_addr
= radeon_bo_gpu_offset(vm
->page_directory
);
241 struct radeon_vm_id
*vm_id
= &vm
->ids
[ring
];
243 if (pd_addr
!= vm_id
->pd_gpu_addr
|| !vm_id
->flushed_updates
||
244 radeon_fence_is_earlier(vm_id
->flushed_updates
, updates
)) {
246 trace_radeon_vm_flush(pd_addr
, ring
, vm
->ids
[ring
].id
);
247 radeon_fence_unref(&vm_id
->flushed_updates
);
248 vm_id
->flushed_updates
= radeon_fence_ref(updates
);
249 vm_id
->pd_gpu_addr
= pd_addr
;
250 radeon_ring_vm_flush(rdev
, &rdev
->ring
[ring
],
251 vm_id
->id
, vm_id
->pd_gpu_addr
);
257 * radeon_vm_fence - remember fence for vm
259 * @rdev: radeon_device pointer
260 * @vm: vm we want to fence
261 * @fence: fence to remember
263 * Fence the vm (cayman+).
264 * Set the fence used to protect page table and id.
266 * Global and local mutex must be locked!
268 void radeon_vm_fence(struct radeon_device
*rdev
,
269 struct radeon_vm
*vm
,
270 struct radeon_fence
*fence
)
272 unsigned vm_id
= vm
->ids
[fence
->ring
].id
;
274 radeon_fence_unref(&rdev
->vm_manager
.active
[vm_id
]);
275 rdev
->vm_manager
.active
[vm_id
] = radeon_fence_ref(fence
);
277 radeon_fence_unref(&vm
->ids
[fence
->ring
].last_id_use
);
278 vm
->ids
[fence
->ring
].last_id_use
= radeon_fence_ref(fence
);
282 * radeon_vm_bo_find - find the bo_va for a specific vm & bo
285 * @bo: requested buffer object
287 * Find @bo inside the requested vm (cayman+).
288 * Search inside the @bos vm list for the requested vm
289 * Returns the found bo_va or NULL if none is found
291 * Object has to be reserved!
293 struct radeon_bo_va
*radeon_vm_bo_find(struct radeon_vm
*vm
,
294 struct radeon_bo
*bo
)
296 struct radeon_bo_va
*bo_va
;
298 list_for_each_entry(bo_va
, &bo
->va
, bo_list
) {
299 if (bo_va
->vm
== vm
) {
307 * radeon_vm_bo_add - add a bo to a specific vm
309 * @rdev: radeon_device pointer
311 * @bo: radeon buffer object
313 * Add @bo into the requested vm (cayman+).
314 * Add @bo to the list of bos associated with the vm
315 * Returns newly added bo_va or NULL for failure
317 * Object has to be reserved!
319 struct radeon_bo_va
*radeon_vm_bo_add(struct radeon_device
*rdev
,
320 struct radeon_vm
*vm
,
321 struct radeon_bo
*bo
)
323 struct radeon_bo_va
*bo_va
;
325 bo_va
= kzalloc(sizeof(struct radeon_bo_va
), GFP_KERNEL
);
335 bo_va
->ref_count
= 1;
336 INIT_LIST_HEAD(&bo_va
->bo_list
);
337 INIT_LIST_HEAD(&bo_va
->vm_status
);
339 mutex_lock(&vm
->mutex
);
340 list_add_tail(&bo_va
->bo_list
, &bo
->va
);
341 mutex_unlock(&vm
->mutex
);
347 * radeon_vm_set_pages - helper to call the right asic function
349 * @rdev: radeon_device pointer
350 * @ib: indirect buffer to fill with commands
351 * @pe: addr of the page entry
352 * @addr: dst addr to write into pe
353 * @count: number of page entries to update
354 * @incr: increase next addr by incr bytes
355 * @flags: hw access flags
357 * Traces the parameters and calls the right asic functions
358 * to setup the page table using the DMA.
360 static void radeon_vm_set_pages(struct radeon_device
*rdev
,
361 struct radeon_ib
*ib
,
363 uint64_t addr
, unsigned count
,
364 uint32_t incr
, uint32_t flags
)
366 trace_radeon_vm_set_page(pe
, addr
, count
, incr
, flags
);
368 if ((flags
& R600_PTE_GART_MASK
) == R600_PTE_GART_MASK
) {
369 uint64_t src
= rdev
->gart
.table_addr
+ (addr
>> 12) * 8;
370 radeon_asic_vm_copy_pages(rdev
, ib
, pe
, src
, count
);
372 } else if ((flags
& R600_PTE_SYSTEM
) || (count
< 3)) {
373 radeon_asic_vm_write_pages(rdev
, ib
, pe
, addr
,
377 radeon_asic_vm_set_pages(rdev
, ib
, pe
, addr
,
383 * radeon_vm_clear_bo - initially clear the page dir/table
385 * @rdev: radeon_device pointer
388 static int radeon_vm_clear_bo(struct radeon_device
*rdev
,
389 struct radeon_bo
*bo
)
396 r
= radeon_bo_reserve(bo
, false);
400 r
= ttm_bo_validate(&bo
->tbo
, &bo
->placement
, true, false);
402 goto error_unreserve
;
404 addr
= radeon_bo_gpu_offset(bo
);
405 entries
= radeon_bo_size(bo
) / 8;
407 r
= radeon_ib_get(rdev
, R600_RING_TYPE_DMA_INDEX
, &ib
, NULL
, 256);
409 goto error_unreserve
;
413 radeon_vm_set_pages(rdev
, &ib
, addr
, 0, entries
, 0, 0);
414 radeon_asic_vm_pad_ib(rdev
, &ib
);
415 WARN_ON(ib
.length_dw
> 64);
417 r
= radeon_ib_schedule(rdev
, &ib
, NULL
, false);
421 ib
.fence
->is_vm_update
= true;
422 radeon_bo_fence(bo
, ib
.fence
, false);
425 radeon_ib_free(rdev
, &ib
);
428 radeon_bo_unreserve(bo
);
433 * radeon_vm_bo_set_addr - set bos virtual address inside a vm
435 * @rdev: radeon_device pointer
436 * @bo_va: bo_va to store the address
437 * @soffset: requested offset of the buffer in the VM address space
438 * @flags: attributes of pages (read/write/valid/etc.)
440 * Set offset of @bo_va (cayman+).
441 * Validate and set the offset requested within the vm address space.
442 * Returns 0 for success, error for failure.
444 * Object has to be reserved and gets unreserved by this function!
446 int radeon_vm_bo_set_addr(struct radeon_device
*rdev
,
447 struct radeon_bo_va
*bo_va
,
451 uint64_t size
= radeon_bo_size(bo_va
->bo
);
452 struct radeon_vm
*vm
= bo_va
->vm
;
453 unsigned last_pfn
, pt_idx
;
458 /* make sure object fit at this offset */
459 eoffset
= soffset
+ size
;
460 if (soffset
>= eoffset
) {
464 last_pfn
= eoffset
/ RADEON_GPU_PAGE_SIZE
;
465 if (last_pfn
> rdev
->vm_manager
.max_pfn
) {
466 dev_err(rdev
->dev
, "va above limit (0x%08X > 0x%08X)\n",
467 last_pfn
, rdev
->vm_manager
.max_pfn
);
472 eoffset
= last_pfn
= 0;
475 mutex_lock(&vm
->mutex
);
476 if (bo_va
->it
.start
|| bo_va
->it
.last
) {
478 /* add a clone of the bo_va to clear the old address */
479 struct radeon_bo_va
*tmp
;
480 tmp
= kzalloc(sizeof(struct radeon_bo_va
), GFP_KERNEL
);
482 mutex_unlock(&vm
->mutex
);
485 tmp
->it
.start
= bo_va
->it
.start
;
486 tmp
->it
.last
= bo_va
->it
.last
;
488 tmp
->addr
= bo_va
->addr
;
489 tmp
->bo
= radeon_bo_ref(bo_va
->bo
);
490 spin_lock(&vm
->status_lock
);
491 list_add(&tmp
->vm_status
, &vm
->freed
);
492 spin_unlock(&vm
->status_lock
);
495 interval_tree_remove(&bo_va
->it
, &vm
->va
);
500 soffset
/= RADEON_GPU_PAGE_SIZE
;
501 eoffset
/= RADEON_GPU_PAGE_SIZE
;
502 if (soffset
|| eoffset
) {
503 struct interval_tree_node
*it
;
504 it
= interval_tree_iter_first(&vm
->va
, soffset
, eoffset
- 1);
506 struct radeon_bo_va
*tmp
;
507 tmp
= container_of(it
, struct radeon_bo_va
, it
);
508 /* bo and tmp overlap, invalid offset */
509 dev_err(rdev
->dev
, "bo %p va 0x%010Lx conflict with "
510 "(bo %p 0x%010lx 0x%010lx)\n", bo_va
->bo
,
511 soffset
, tmp
->bo
, tmp
->it
.start
, tmp
->it
.last
);
512 mutex_unlock(&vm
->mutex
);
515 bo_va
->it
.start
= soffset
;
516 bo_va
->it
.last
= eoffset
- 1;
517 interval_tree_insert(&bo_va
->it
, &vm
->va
);
520 bo_va
->flags
= flags
;
523 soffset
>>= radeon_vm_block_size
;
524 eoffset
>>= radeon_vm_block_size
;
526 BUG_ON(eoffset
>= radeon_vm_num_pdes(rdev
));
528 if (eoffset
> vm
->max_pde_used
)
529 vm
->max_pde_used
= eoffset
;
531 radeon_bo_unreserve(bo_va
->bo
);
533 /* walk over the address space and allocate the page tables */
534 for (pt_idx
= soffset
; pt_idx
<= eoffset
; ++pt_idx
) {
535 struct radeon_bo
*pt
;
537 if (vm
->page_tables
[pt_idx
].bo
)
540 /* drop mutex to allocate and clear page table */
541 mutex_unlock(&vm
->mutex
);
543 r
= radeon_bo_create(rdev
, RADEON_VM_PTE_COUNT
* 8,
544 RADEON_GPU_PAGE_SIZE
, true,
545 RADEON_GEM_DOMAIN_VRAM
, 0,
550 r
= radeon_vm_clear_bo(rdev
, pt
);
552 radeon_bo_unref(&pt
);
553 radeon_bo_reserve(bo_va
->bo
, false);
557 /* aquire mutex again */
558 mutex_lock(&vm
->mutex
);
559 if (vm
->page_tables
[pt_idx
].bo
) {
560 /* someone else allocated the pt in the meantime */
561 mutex_unlock(&vm
->mutex
);
562 radeon_bo_unref(&pt
);
563 mutex_lock(&vm
->mutex
);
567 vm
->page_tables
[pt_idx
].addr
= 0;
568 vm
->page_tables
[pt_idx
].bo
= pt
;
571 mutex_unlock(&vm
->mutex
);
576 * radeon_vm_map_gart - get the physical address of a gart page
578 * @rdev: radeon_device pointer
579 * @addr: the unmapped addr
581 * Look up the physical address of the page that the pte resolves
583 * Returns the physical address of the page.
585 uint64_t radeon_vm_map_gart(struct radeon_device
*rdev
, uint64_t addr
)
589 /* page table offset */
590 result
= rdev
->gart
.pages_entry
[addr
>> RADEON_GPU_PAGE_SHIFT
];
591 result
&= ~RADEON_GPU_PAGE_MASK
;
597 * radeon_vm_page_flags - translate page flags to what the hw uses
599 * @flags: flags comming from userspace
601 * Translate the flags the userspace ABI uses to hw flags.
603 static uint32_t radeon_vm_page_flags(uint32_t flags
)
605 uint32_t hw_flags
= 0;
606 hw_flags
|= (flags
& RADEON_VM_PAGE_VALID
) ? R600_PTE_VALID
: 0;
607 hw_flags
|= (flags
& RADEON_VM_PAGE_READABLE
) ? R600_PTE_READABLE
: 0;
608 hw_flags
|= (flags
& RADEON_VM_PAGE_WRITEABLE
) ? R600_PTE_WRITEABLE
: 0;
609 if (flags
& RADEON_VM_PAGE_SYSTEM
) {
610 hw_flags
|= R600_PTE_SYSTEM
;
611 hw_flags
|= (flags
& RADEON_VM_PAGE_SNOOPED
) ? R600_PTE_SNOOPED
: 0;
617 * radeon_vm_update_pdes - make sure that page directory is valid
619 * @rdev: radeon_device pointer
621 * @start: start of GPU address range
622 * @end: end of GPU address range
624 * Allocates new page tables if necessary
625 * and updates the page directory (cayman+).
626 * Returns 0 for success, error for failure.
628 * Global and local mutex must be locked!
630 int radeon_vm_update_page_directory(struct radeon_device
*rdev
,
631 struct radeon_vm
*vm
)
633 struct radeon_bo
*pd
= vm
->page_directory
;
634 uint64_t pd_addr
= radeon_bo_gpu_offset(pd
);
635 uint32_t incr
= RADEON_VM_PTE_COUNT
* 8;
636 uint64_t last_pde
= ~0, last_pt
= ~0;
637 unsigned count
= 0, pt_idx
, ndw
;
644 /* assume the worst case */
645 ndw
+= vm
->max_pde_used
* 6;
647 /* update too big for an IB */
651 r
= radeon_ib_get(rdev
, R600_RING_TYPE_DMA_INDEX
, &ib
, NULL
, ndw
* 4);
656 /* walk over the address space and update the page directory */
657 for (pt_idx
= 0; pt_idx
<= vm
->max_pde_used
; ++pt_idx
) {
658 struct radeon_bo
*bo
= vm
->page_tables
[pt_idx
].bo
;
664 pt
= radeon_bo_gpu_offset(bo
);
665 if (vm
->page_tables
[pt_idx
].addr
== pt
)
667 vm
->page_tables
[pt_idx
].addr
= pt
;
669 pde
= pd_addr
+ pt_idx
* 8;
670 if (((last_pde
+ 8 * count
) != pde
) ||
671 ((last_pt
+ incr
* count
) != pt
)) {
674 radeon_vm_set_pages(rdev
, &ib
, last_pde
,
675 last_pt
, count
, incr
,
688 radeon_vm_set_pages(rdev
, &ib
, last_pde
, last_pt
, count
,
689 incr
, R600_PTE_VALID
);
691 if (ib
.length_dw
!= 0) {
692 radeon_asic_vm_pad_ib(rdev
, &ib
);
694 radeon_sync_resv(rdev
, &ib
.sync
, pd
->tbo
.resv
, true);
695 WARN_ON(ib
.length_dw
> ndw
);
696 r
= radeon_ib_schedule(rdev
, &ib
, NULL
, false);
698 radeon_ib_free(rdev
, &ib
);
701 ib
.fence
->is_vm_update
= true;
702 radeon_bo_fence(pd
, ib
.fence
, false);
704 radeon_ib_free(rdev
, &ib
);
710 * radeon_vm_frag_ptes - add fragment information to PTEs
712 * @rdev: radeon_device pointer
713 * @ib: IB for the update
714 * @pe_start: first PTE to handle
715 * @pe_end: last PTE to handle
716 * @addr: addr those PTEs should point to
717 * @flags: hw mapping flags
719 * Global and local mutex must be locked!
721 static void radeon_vm_frag_ptes(struct radeon_device
*rdev
,
722 struct radeon_ib
*ib
,
723 uint64_t pe_start
, uint64_t pe_end
,
724 uint64_t addr
, uint32_t flags
)
727 * The MC L1 TLB supports variable sized pages, based on a fragment
728 * field in the PTE. When this field is set to a non-zero value, page
729 * granularity is increased from 4KB to (1 << (12 + frag)). The PTE
730 * flags are considered valid for all PTEs within the fragment range
731 * and corresponding mappings are assumed to be physically contiguous.
733 * The L1 TLB can store a single PTE for the whole fragment,
734 * significantly increasing the space available for translation
735 * caching. This leads to large improvements in throughput when the
736 * TLB is under pressure.
738 * The L2 TLB distributes small and large fragments into two
739 * asymmetric partitions. The large fragment cache is significantly
740 * larger. Thus, we try to use large fragments wherever possible.
741 * Userspace can support this by aligning virtual base address and
742 * allocation size to the fragment size.
745 /* NI is optimized for 256KB fragments, SI and newer for 64KB */
746 uint64_t frag_flags
= ((rdev
->family
== CHIP_CAYMAN
) ||
747 (rdev
->family
== CHIP_ARUBA
)) ?
748 R600_PTE_FRAG_256KB
: R600_PTE_FRAG_64KB
;
749 uint64_t frag_align
= ((rdev
->family
== CHIP_CAYMAN
) ||
750 (rdev
->family
== CHIP_ARUBA
)) ? 0x200 : 0x80;
752 uint64_t frag_start
= ALIGN(pe_start
, frag_align
);
753 uint64_t frag_end
= pe_end
& ~(frag_align
- 1);
757 /* system pages are non continuously */
758 if ((flags
& R600_PTE_SYSTEM
) || !(flags
& R600_PTE_VALID
) ||
759 (frag_start
>= frag_end
)) {
761 count
= (pe_end
- pe_start
) / 8;
762 radeon_vm_set_pages(rdev
, ib
, pe_start
, addr
, count
,
763 RADEON_GPU_PAGE_SIZE
, flags
);
767 /* handle the 4K area at the beginning */
768 if (pe_start
!= frag_start
) {
769 count
= (frag_start
- pe_start
) / 8;
770 radeon_vm_set_pages(rdev
, ib
, pe_start
, addr
, count
,
771 RADEON_GPU_PAGE_SIZE
, flags
);
772 addr
+= RADEON_GPU_PAGE_SIZE
* count
;
775 /* handle the area in the middle */
776 count
= (frag_end
- frag_start
) / 8;
777 radeon_vm_set_pages(rdev
, ib
, frag_start
, addr
, count
,
778 RADEON_GPU_PAGE_SIZE
, flags
| frag_flags
);
780 /* handle the 4K area at the end */
781 if (frag_end
!= pe_end
) {
782 addr
+= RADEON_GPU_PAGE_SIZE
* count
;
783 count
= (pe_end
- frag_end
) / 8;
784 radeon_vm_set_pages(rdev
, ib
, frag_end
, addr
, count
,
785 RADEON_GPU_PAGE_SIZE
, flags
);
790 * radeon_vm_update_ptes - make sure that page tables are valid
792 * @rdev: radeon_device pointer
794 * @start: start of GPU address range
795 * @end: end of GPU address range
796 * @dst: destination address to map to
797 * @flags: mapping flags
799 * Update the page tables in the range @start - @end (cayman+).
801 * Global and local mutex must be locked!
803 static int radeon_vm_update_ptes(struct radeon_device
*rdev
,
804 struct radeon_vm
*vm
,
805 struct radeon_ib
*ib
,
806 uint64_t start
, uint64_t end
,
807 uint64_t dst
, uint32_t flags
)
809 uint64_t mask
= RADEON_VM_PTE_COUNT
- 1;
810 uint64_t last_pte
= ~0, last_dst
= ~0;
814 /* walk over the address space and update the page tables */
815 for (addr
= start
; addr
< end
; ) {
816 uint64_t pt_idx
= addr
>> radeon_vm_block_size
;
817 struct radeon_bo
*pt
= vm
->page_tables
[pt_idx
].bo
;
822 radeon_sync_resv(rdev
, &ib
->sync
, pt
->tbo
.resv
, true);
823 r
= reservation_object_reserve_shared(pt
->tbo
.resv
);
827 if ((addr
& ~mask
) == (end
& ~mask
))
830 nptes
= RADEON_VM_PTE_COUNT
- (addr
& mask
);
832 pte
= radeon_bo_gpu_offset(pt
);
833 pte
+= (addr
& mask
) * 8;
835 if ((last_pte
+ 8 * count
) != pte
) {
838 radeon_vm_frag_ptes(rdev
, ib
, last_pte
,
839 last_pte
+ 8 * count
,
851 dst
+= nptes
* RADEON_GPU_PAGE_SIZE
;
855 radeon_vm_frag_ptes(rdev
, ib
, last_pte
,
856 last_pte
+ 8 * count
,
864 * radeon_vm_fence_pts - fence page tables after an update
867 * @start: start of GPU address range
868 * @end: end of GPU address range
869 * @fence: fence to use
871 * Fence the page tables in the range @start - @end (cayman+).
873 * Global and local mutex must be locked!
875 static void radeon_vm_fence_pts(struct radeon_vm
*vm
,
876 uint64_t start
, uint64_t end
,
877 struct radeon_fence
*fence
)
881 start
>>= radeon_vm_block_size
;
882 end
>>= radeon_vm_block_size
;
884 for (i
= start
; i
<= end
; ++i
)
885 radeon_bo_fence(vm
->page_tables
[i
].bo
, fence
, true);
889 * radeon_vm_bo_update - map a bo into the vm page table
891 * @rdev: radeon_device pointer
893 * @bo: radeon buffer object
896 * Fill in the page table entries for @bo (cayman+).
897 * Returns 0 for success, -EINVAL for failure.
899 * Object have to be reserved and mutex must be locked!
901 int radeon_vm_bo_update(struct radeon_device
*rdev
,
902 struct radeon_bo_va
*bo_va
,
903 struct ttm_mem_reg
*mem
)
905 struct radeon_vm
*vm
= bo_va
->vm
;
907 unsigned nptes
, ncmds
, ndw
;
912 if (!bo_va
->it
.start
) {
913 dev_err(rdev
->dev
, "bo %p don't has a mapping in vm %p\n",
918 spin_lock(&vm
->status_lock
);
919 list_del_init(&bo_va
->vm_status
);
920 spin_unlock(&vm
->status_lock
);
922 bo_va
->flags
&= ~RADEON_VM_PAGE_VALID
;
923 bo_va
->flags
&= ~RADEON_VM_PAGE_SYSTEM
;
924 bo_va
->flags
&= ~RADEON_VM_PAGE_SNOOPED
;
925 if (bo_va
->bo
&& radeon_ttm_tt_is_readonly(bo_va
->bo
->tbo
.ttm
))
926 bo_va
->flags
&= ~RADEON_VM_PAGE_WRITEABLE
;
929 addr
= mem
->start
<< PAGE_SHIFT
;
930 if (mem
->mem_type
!= TTM_PL_SYSTEM
) {
931 bo_va
->flags
|= RADEON_VM_PAGE_VALID
;
933 if (mem
->mem_type
== TTM_PL_TT
) {
934 bo_va
->flags
|= RADEON_VM_PAGE_SYSTEM
;
935 if (!(bo_va
->bo
->flags
& (RADEON_GEM_GTT_WC
| RADEON_GEM_GTT_UC
)))
936 bo_va
->flags
|= RADEON_VM_PAGE_SNOOPED
;
939 addr
+= rdev
->vm_manager
.vram_base_offset
;
945 if (addr
== bo_va
->addr
)
949 trace_radeon_vm_bo_update(bo_va
);
951 nptes
= bo_va
->it
.last
- bo_va
->it
.start
+ 1;
953 /* reserve space for one command every (1 << BLOCK_SIZE) entries
954 or 2k dwords (whatever is smaller) */
955 ncmds
= (nptes
>> min(radeon_vm_block_size
, 11)) + 1;
960 flags
= radeon_vm_page_flags(bo_va
->flags
);
961 if ((flags
& R600_PTE_GART_MASK
) == R600_PTE_GART_MASK
) {
962 /* only copy commands needed */
965 } else if (flags
& R600_PTE_SYSTEM
) {
966 /* header for write data commands */
969 /* body of write data command */
973 /* set page commands needed */
976 /* two extra commands for begin/end of fragment */
980 /* update too big for an IB */
984 r
= radeon_ib_get(rdev
, R600_RING_TYPE_DMA_INDEX
, &ib
, NULL
, ndw
* 4);
989 if (!(bo_va
->flags
& RADEON_VM_PAGE_VALID
)) {
992 for (i
= 0; i
< RADEON_NUM_RINGS
; ++i
)
993 radeon_sync_fence(&ib
.sync
, vm
->ids
[i
].last_id_use
);
996 r
= radeon_vm_update_ptes(rdev
, vm
, &ib
, bo_va
->it
.start
,
997 bo_va
->it
.last
+ 1, addr
,
998 radeon_vm_page_flags(bo_va
->flags
));
1000 radeon_ib_free(rdev
, &ib
);
1004 radeon_asic_vm_pad_ib(rdev
, &ib
);
1005 WARN_ON(ib
.length_dw
> ndw
);
1007 r
= radeon_ib_schedule(rdev
, &ib
, NULL
, false);
1009 radeon_ib_free(rdev
, &ib
);
1012 ib
.fence
->is_vm_update
= true;
1013 radeon_vm_fence_pts(vm
, bo_va
->it
.start
, bo_va
->it
.last
+ 1, ib
.fence
);
1014 radeon_fence_unref(&bo_va
->last_pt_update
);
1015 bo_va
->last_pt_update
= radeon_fence_ref(ib
.fence
);
1016 radeon_ib_free(rdev
, &ib
);
1022 * radeon_vm_clear_freed - clear freed BOs in the PT
1024 * @rdev: radeon_device pointer
1027 * Make sure all freed BOs are cleared in the PT.
1028 * Returns 0 for success.
1030 * PTs have to be reserved and mutex must be locked!
1032 int radeon_vm_clear_freed(struct radeon_device
*rdev
,
1033 struct radeon_vm
*vm
)
1035 struct radeon_bo_va
*bo_va
;
1038 spin_lock(&vm
->status_lock
);
1039 while (!list_empty(&vm
->freed
)) {
1040 bo_va
= list_first_entry(&vm
->freed
,
1041 struct radeon_bo_va
, vm_status
);
1042 spin_unlock(&vm
->status_lock
);
1044 r
= radeon_vm_bo_update(rdev
, bo_va
, NULL
);
1045 radeon_bo_unref(&bo_va
->bo
);
1046 radeon_fence_unref(&bo_va
->last_pt_update
);
1051 spin_lock(&vm
->status_lock
);
1053 spin_unlock(&vm
->status_lock
);
1059 * radeon_vm_clear_invalids - clear invalidated BOs in the PT
1061 * @rdev: radeon_device pointer
1064 * Make sure all invalidated BOs are cleared in the PT.
1065 * Returns 0 for success.
1067 * PTs have to be reserved and mutex must be locked!
1069 int radeon_vm_clear_invalids(struct radeon_device
*rdev
,
1070 struct radeon_vm
*vm
)
1072 struct radeon_bo_va
*bo_va
;
1075 spin_lock(&vm
->status_lock
);
1076 while (!list_empty(&vm
->invalidated
)) {
1077 bo_va
= list_first_entry(&vm
->invalidated
,
1078 struct radeon_bo_va
, vm_status
);
1079 spin_unlock(&vm
->status_lock
);
1081 r
= radeon_vm_bo_update(rdev
, bo_va
, NULL
);
1085 spin_lock(&vm
->status_lock
);
1087 spin_unlock(&vm
->status_lock
);
1093 * radeon_vm_bo_rmv - remove a bo to a specific vm
1095 * @rdev: radeon_device pointer
1096 * @bo_va: requested bo_va
1098 * Remove @bo_va->bo from the requested vm (cayman+).
1100 * Object have to be reserved!
1102 void radeon_vm_bo_rmv(struct radeon_device
*rdev
,
1103 struct radeon_bo_va
*bo_va
)
1105 struct radeon_vm
*vm
= bo_va
->vm
;
1107 list_del(&bo_va
->bo_list
);
1109 mutex_lock(&vm
->mutex
);
1110 interval_tree_remove(&bo_va
->it
, &vm
->va
);
1111 spin_lock(&vm
->status_lock
);
1112 list_del(&bo_va
->vm_status
);
1115 bo_va
->bo
= radeon_bo_ref(bo_va
->bo
);
1116 list_add(&bo_va
->vm_status
, &vm
->freed
);
1118 radeon_fence_unref(&bo_va
->last_pt_update
);
1121 spin_unlock(&vm
->status_lock
);
1123 mutex_unlock(&vm
->mutex
);
1127 * radeon_vm_bo_invalidate - mark the bo as invalid
1129 * @rdev: radeon_device pointer
1131 * @bo: radeon buffer object
1133 * Mark @bo as invalid (cayman+).
1135 void radeon_vm_bo_invalidate(struct radeon_device
*rdev
,
1136 struct radeon_bo
*bo
)
1138 struct radeon_bo_va
*bo_va
;
1140 list_for_each_entry(bo_va
, &bo
->va
, bo_list
) {
1142 spin_lock(&bo_va
->vm
->status_lock
);
1143 list_del(&bo_va
->vm_status
);
1144 list_add(&bo_va
->vm_status
, &bo_va
->vm
->invalidated
);
1145 spin_unlock(&bo_va
->vm
->status_lock
);
1151 * radeon_vm_init - initialize a vm instance
1153 * @rdev: radeon_device pointer
1156 * Init @vm fields (cayman+).
1158 int radeon_vm_init(struct radeon_device
*rdev
, struct radeon_vm
*vm
)
1160 const unsigned align
= min(RADEON_VM_PTB_ALIGN_SIZE
,
1161 RADEON_VM_PTE_COUNT
* 8);
1162 unsigned pd_size
, pd_entries
, pts_size
;
1165 vm
->ib_bo_va
= NULL
;
1166 for (i
= 0; i
< RADEON_NUM_RINGS
; ++i
) {
1168 vm
->ids
[i
].flushed_updates
= NULL
;
1169 vm
->ids
[i
].last_id_use
= NULL
;
1171 mutex_init(&vm
->mutex
);
1173 spin_lock_init(&vm
->status_lock
);
1174 INIT_LIST_HEAD(&vm
->invalidated
);
1175 INIT_LIST_HEAD(&vm
->freed
);
1177 pd_size
= radeon_vm_directory_size(rdev
);
1178 pd_entries
= radeon_vm_num_pdes(rdev
);
1180 /* allocate page table array */
1181 pts_size
= pd_entries
* sizeof(struct radeon_vm_pt
);
1182 vm
->page_tables
= kzalloc(pts_size
, GFP_KERNEL
);
1183 if (vm
->page_tables
== NULL
) {
1184 DRM_ERROR("Cannot allocate memory for page table array\n");
1188 r
= radeon_bo_create(rdev
, pd_size
, align
, true,
1189 RADEON_GEM_DOMAIN_VRAM
, 0, NULL
,
1190 NULL
, &vm
->page_directory
);
1194 r
= radeon_vm_clear_bo(rdev
, vm
->page_directory
);
1196 radeon_bo_unref(&vm
->page_directory
);
1197 vm
->page_directory
= NULL
;
1205 * radeon_vm_fini - tear down a vm instance
1207 * @rdev: radeon_device pointer
1210 * Tear down @vm (cayman+).
1211 * Unbind the VM and remove all bos from the vm bo list
1213 void radeon_vm_fini(struct radeon_device
*rdev
, struct radeon_vm
*vm
)
1215 struct radeon_bo_va
*bo_va
, *tmp
;
1218 if (!RB_EMPTY_ROOT(&vm
->va
)) {
1219 dev_err(rdev
->dev
, "still active bo inside vm\n");
1221 rbtree_postorder_for_each_entry_safe(bo_va
, tmp
, &vm
->va
, it
.rb
) {
1222 interval_tree_remove(&bo_va
->it
, &vm
->va
);
1223 r
= radeon_bo_reserve(bo_va
->bo
, false);
1225 list_del_init(&bo_va
->bo_list
);
1226 radeon_bo_unreserve(bo_va
->bo
);
1227 radeon_fence_unref(&bo_va
->last_pt_update
);
1231 list_for_each_entry_safe(bo_va
, tmp
, &vm
->freed
, vm_status
) {
1232 radeon_bo_unref(&bo_va
->bo
);
1233 radeon_fence_unref(&bo_va
->last_pt_update
);
1237 for (i
= 0; i
< radeon_vm_num_pdes(rdev
); i
++)
1238 radeon_bo_unref(&vm
->page_tables
[i
].bo
);
1239 kfree(vm
->page_tables
);
1241 radeon_bo_unref(&vm
->page_directory
);
1243 for (i
= 0; i
< RADEON_NUM_RINGS
; ++i
) {
1244 radeon_fence_unref(&vm
->ids
[i
].flushed_updates
);
1245 radeon_fence_unref(&vm
->ids
[i
].last_id_use
);
1248 mutex_destroy(&vm
->mutex
);
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