2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/seq_file.h>
30 #include "radeon_reg.h"
33 /* rs400,rs480 depends on : */
34 void r100_hdp_reset(struct radeon_device
*rdev
);
35 void r100_mc_disable_clients(struct radeon_device
*rdev
);
36 int r300_mc_wait_for_idle(struct radeon_device
*rdev
);
37 void r420_pipes_init(struct radeon_device
*rdev
);
39 /* This files gather functions specifics to :
42 * Some of these functions might be used by newer ASICs.
44 void rs400_gpu_init(struct radeon_device
*rdev
);
45 int rs400_debugfs_pcie_gart_info_init(struct radeon_device
*rdev
);
51 void rs400_gart_adjust_size(struct radeon_device
*rdev
)
54 switch (rdev
->mc
.gtt_size
/(1024*1024)) {
64 DRM_ERROR("Unable to use IGP GART size %uM\n",
65 rdev
->mc
.gtt_size
>> 20);
66 DRM_ERROR("Valid GART size for IGP are 32M,64M,128M,256M,512M,1G,2G\n");
67 DRM_ERROR("Forcing to 32M GART size\n");
68 rdev
->mc
.gtt_size
= 32 * 1024 * 1024;
71 if (rdev
->family
== CHIP_RS400
|| rdev
->family
== CHIP_RS480
) {
72 /* FIXME: RS400 & RS480 seems to have issue with GART size
73 * if 4G of system memory (needs more testing) */
74 rdev
->mc
.gtt_size
= 32 * 1024 * 1024;
75 DRM_ERROR("Forcing to 32M GART size (because of ASIC bug ?)\n");
79 void rs400_gart_tlb_flush(struct radeon_device
*rdev
)
82 unsigned int timeout
= rdev
->usec_timeout
;
84 WREG32_MC(RS480_GART_CACHE_CNTRL
, RS480_GART_CACHE_INVALIDATE
);
86 tmp
= RREG32_MC(RS480_GART_CACHE_CNTRL
);
87 if ((tmp
& RS480_GART_CACHE_INVALIDATE
) == 0)
91 } while (timeout
> 0);
92 WREG32_MC(RS480_GART_CACHE_CNTRL
, 0);
95 int rs400_gart_enable(struct radeon_device
*rdev
)
101 /* Initialize common gart structure */
102 r
= radeon_gart_init(rdev
);
106 if (rs400_debugfs_pcie_gart_info_init(rdev
)) {
107 DRM_ERROR("Failed to register debugfs file for RS400 GART !\n");
110 tmp
= RREG32_MC(RS690_AIC_CTRL_SCRATCH
);
111 tmp
|= RS690_DIS_OUT_OF_PCI_GART_ACCESS
;
112 WREG32_MC(RS690_AIC_CTRL_SCRATCH
, tmp
);
113 /* Check gart size */
114 switch(rdev
->mc
.gtt_size
/ (1024 * 1024)) {
116 size_reg
= RS480_VA_SIZE_32MB
;
119 size_reg
= RS480_VA_SIZE_64MB
;
122 size_reg
= RS480_VA_SIZE_128MB
;
125 size_reg
= RS480_VA_SIZE_256MB
;
128 size_reg
= RS480_VA_SIZE_512MB
;
131 size_reg
= RS480_VA_SIZE_1GB
;
134 size_reg
= RS480_VA_SIZE_2GB
;
139 if (rdev
->gart
.table
.ram
.ptr
== NULL
) {
140 rdev
->gart
.table_size
= rdev
->gart
.num_gpu_pages
* 4;
141 r
= radeon_gart_table_ram_alloc(rdev
);
146 /* It should be fine to program it to max value */
147 if (rdev
->family
== CHIP_RS690
|| (rdev
->family
== CHIP_RS740
)) {
148 WREG32_MC(RS690_MCCFG_AGP_BASE
, 0xFFFFFFFF);
149 WREG32_MC(RS690_MCCFG_AGP_BASE_2
, 0);
151 WREG32(RADEON_AGP_BASE
, 0xFFFFFFFF);
152 WREG32(RS480_AGP_BASE_2
, 0);
154 tmp
= rdev
->mc
.gtt_location
+ rdev
->mc
.gtt_size
- 1;
155 tmp
= REG_SET(RS690_MC_AGP_TOP
, tmp
>> 16);
156 tmp
|= REG_SET(RS690_MC_AGP_START
, rdev
->mc
.gtt_location
>> 16);
157 if ((rdev
->family
== CHIP_RS690
) || (rdev
->family
== CHIP_RS740
)) {
158 WREG32_MC(RS690_MCCFG_AGP_LOCATION
, tmp
);
159 tmp
= RREG32(RADEON_BUS_CNTL
) & ~RS600_BUS_MASTER_DIS
;
160 WREG32(RADEON_BUS_CNTL
, tmp
);
162 WREG32(RADEON_MC_AGP_LOCATION
, tmp
);
163 tmp
= RREG32(RADEON_BUS_CNTL
) & ~RADEON_BUS_MASTER_DIS
;
164 WREG32(RADEON_BUS_CNTL
, tmp
);
166 /* Table should be in 32bits address space so ignore bits above. */
167 tmp
= (u32
)rdev
->gart
.table_addr
& 0xfffff000;
168 tmp
|= (upper_32_bits(rdev
->gart
.table_addr
) & 0xff) << 4;
170 WREG32_MC(RS480_GART_BASE
, tmp
);
171 /* TODO: more tweaking here */
172 WREG32_MC(RS480_GART_FEATURE_ID
,
174 RS480_GTW_LAC_EN
| RS480_1LEVEL_GART
));
175 /* Disable snooping */
176 WREG32_MC(RS480_AGP_MODE_CNTL
,
177 (1 << RS480_REQ_TYPE_SNOOP_SHIFT
) | RS480_REQ_TYPE_SNOOP_DIS
);
178 /* Disable AGP mode */
179 /* FIXME: according to doc we should set HIDE_MMCFG_BAR=0,
180 * AGPMODE30=0 & AGP30ENHANCED=0 in NB_CNTL */
181 if ((rdev
->family
== CHIP_RS690
) || (rdev
->family
== CHIP_RS740
)) {
182 WREG32_MC(RS480_MC_MISC_CNTL
,
183 (RS480_GART_INDEX_REG_EN
| RS690_BLOCK_GFX_D3_EN
));
185 WREG32_MC(RS480_MC_MISC_CNTL
, RS480_GART_INDEX_REG_EN
);
188 WREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE
, (RS480_GART_EN
| size_reg
));
189 rs400_gart_tlb_flush(rdev
);
190 rdev
->gart
.ready
= true;
194 void rs400_gart_disable(struct radeon_device
*rdev
)
198 tmp
= RREG32_MC(RS690_AIC_CTRL_SCRATCH
);
199 tmp
|= RS690_DIS_OUT_OF_PCI_GART_ACCESS
;
200 WREG32_MC(RS690_AIC_CTRL_SCRATCH
, tmp
);
201 WREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE
, 0);
204 int rs400_gart_set_page(struct radeon_device
*rdev
, int i
, uint64_t addr
)
208 if (i
< 0 || i
> rdev
->gart
.num_gpu_pages
) {
212 entry
= (lower_32_bits(addr
) & PAGE_MASK
) |
213 ((upper_32_bits(addr
) & 0xff) << 4) |
215 entry
= cpu_to_le32(entry
);
216 rdev
->gart
.table
.ram
.ptr
[i
] = entry
;
224 int rs400_mc_init(struct radeon_device
*rdev
)
229 if (r100_debugfs_rbbm_init(rdev
)) {
230 DRM_ERROR("Failed to register debugfs file for RBBM !\n");
233 rs400_gpu_init(rdev
);
234 rs400_gart_disable(rdev
);
235 rdev
->mc
.gtt_location
= rdev
->mc
.vram_size
;
236 rdev
->mc
.gtt_location
+= (rdev
->mc
.gtt_size
- 1);
237 rdev
->mc
.gtt_location
&= ~(rdev
->mc
.gtt_size
- 1);
238 rdev
->mc
.vram_location
= 0xFFFFFFFFUL
;
239 r
= radeon_mc_setup(rdev
);
244 r100_mc_disable_clients(rdev
);
245 if (r300_mc_wait_for_idle(rdev
)) {
246 printk(KERN_WARNING
"Failed to wait MC idle while "
247 "programming pipes. Bad things might happen.\n");
250 tmp
= rdev
->mc
.vram_location
+ rdev
->mc
.vram_size
- 1;
251 tmp
= REG_SET(RADEON_MC_FB_TOP
, tmp
>> 16);
252 tmp
|= REG_SET(RADEON_MC_FB_START
, rdev
->mc
.vram_location
>> 16);
253 WREG32(RADEON_MC_FB_LOCATION
, tmp
);
254 tmp
= RREG32(RADEON_HOST_PATH_CNTL
) | RADEON_HP_LIN_RD_CACHE_DIS
;
255 WREG32(RADEON_HOST_PATH_CNTL
, tmp
| RADEON_HDP_SOFT_RESET
| RADEON_HDP_READ_BUFFER_INVALIDATE
);
256 (void)RREG32(RADEON_HOST_PATH_CNTL
);
257 WREG32(RADEON_HOST_PATH_CNTL
, tmp
);
258 (void)RREG32(RADEON_HOST_PATH_CNTL
);
262 void rs400_mc_fini(struct radeon_device
*rdev
)
264 rs400_gart_disable(rdev
);
265 radeon_gart_table_ram_free(rdev
);
266 radeon_gart_fini(rdev
);
271 * Global GPU functions
273 void rs400_errata(struct radeon_device
*rdev
)
275 rdev
->pll_errata
= 0;
278 void rs400_gpu_init(struct radeon_device
*rdev
)
280 /* FIXME: HDP same place on rs400 ? */
281 r100_hdp_reset(rdev
);
282 /* FIXME: is this correct ? */
283 r420_pipes_init(rdev
);
284 if (r300_mc_wait_for_idle(rdev
)) {
285 printk(KERN_WARNING
"Failed to wait MC idle while "
286 "programming pipes. Bad things might happen.\n");
294 void rs400_vram_info(struct radeon_device
*rdev
)
298 rs400_gart_adjust_size(rdev
);
299 /* DDR for all card after R300 & IGP */
300 rdev
->mc
.vram_is_ddr
= true;
301 rdev
->mc
.vram_width
= 128;
303 /* read NB_TOM to get the amount of ram stolen for the GPU */
304 tom
= RREG32(RADEON_NB_TOM
);
305 rdev
->mc
.vram_size
= (((tom
>> 16) - (tom
& 0xffff) + 1) << 16);
306 WREG32(RADEON_CONFIG_MEMSIZE
, rdev
->mc
.vram_size
);
308 /* Could aper size report 0 ? */
309 rdev
->mc
.aper_base
= drm_get_resource_start(rdev
->ddev
, 0);
310 rdev
->mc
.aper_size
= drm_get_resource_len(rdev
->ddev
, 0);
315 * Indirect registers accessor
317 uint32_t rs400_mc_rreg(struct radeon_device
*rdev
, uint32_t reg
)
321 WREG32(RS480_NB_MC_INDEX
, reg
& 0xff);
322 r
= RREG32(RS480_NB_MC_DATA
);
323 WREG32(RS480_NB_MC_INDEX
, 0xff);
327 void rs400_mc_wreg(struct radeon_device
*rdev
, uint32_t reg
, uint32_t v
)
329 WREG32(RS480_NB_MC_INDEX
, ((reg
) & 0xff) | RS480_NB_MC_IND_WR_EN
);
330 WREG32(RS480_NB_MC_DATA
, (v
));
331 WREG32(RS480_NB_MC_INDEX
, 0xff);
338 #if defined(CONFIG_DEBUG_FS)
339 static int rs400_debugfs_gart_info(struct seq_file
*m
, void *data
)
341 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
342 struct drm_device
*dev
= node
->minor
->dev
;
343 struct radeon_device
*rdev
= dev
->dev_private
;
346 tmp
= RREG32(RADEON_HOST_PATH_CNTL
);
347 seq_printf(m
, "HOST_PATH_CNTL 0x%08x\n", tmp
);
348 tmp
= RREG32(RADEON_BUS_CNTL
);
349 seq_printf(m
, "BUS_CNTL 0x%08x\n", tmp
);
350 tmp
= RREG32_MC(RS690_AIC_CTRL_SCRATCH
);
351 seq_printf(m
, "AIC_CTRL_SCRATCH 0x%08x\n", tmp
);
352 if (rdev
->family
== CHIP_RS690
|| (rdev
->family
== CHIP_RS740
)) {
353 tmp
= RREG32_MC(RS690_MCCFG_AGP_BASE
);
354 seq_printf(m
, "MCCFG_AGP_BASE 0x%08x\n", tmp
);
355 tmp
= RREG32_MC(RS690_MCCFG_AGP_BASE_2
);
356 seq_printf(m
, "MCCFG_AGP_BASE_2 0x%08x\n", tmp
);
357 tmp
= RREG32_MC(RS690_MCCFG_AGP_LOCATION
);
358 seq_printf(m
, "MCCFG_AGP_LOCATION 0x%08x\n", tmp
);
359 tmp
= RREG32_MC(0x100);
360 seq_printf(m
, "MCCFG_FB_LOCATION 0x%08x\n", tmp
);
362 seq_printf(m
, "HDP_FB_LOCATION 0x%08x\n", tmp
);
364 tmp
= RREG32(RADEON_AGP_BASE
);
365 seq_printf(m
, "AGP_BASE 0x%08x\n", tmp
);
366 tmp
= RREG32(RS480_AGP_BASE_2
);
367 seq_printf(m
, "AGP_BASE_2 0x%08x\n", tmp
);
368 tmp
= RREG32(RADEON_MC_AGP_LOCATION
);
369 seq_printf(m
, "MC_AGP_LOCATION 0x%08x\n", tmp
);
371 tmp
= RREG32_MC(RS480_GART_BASE
);
372 seq_printf(m
, "GART_BASE 0x%08x\n", tmp
);
373 tmp
= RREG32_MC(RS480_GART_FEATURE_ID
);
374 seq_printf(m
, "GART_FEATURE_ID 0x%08x\n", tmp
);
375 tmp
= RREG32_MC(RS480_AGP_MODE_CNTL
);
376 seq_printf(m
, "AGP_MODE_CONTROL 0x%08x\n", tmp
);
377 tmp
= RREG32_MC(RS480_MC_MISC_CNTL
);
378 seq_printf(m
, "MC_MISC_CNTL 0x%08x\n", tmp
);
379 tmp
= RREG32_MC(0x5F);
380 seq_printf(m
, "MC_MISC_UMA_CNTL 0x%08x\n", tmp
);
381 tmp
= RREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE
);
382 seq_printf(m
, "AGP_ADDRESS_SPACE_SIZE 0x%08x\n", tmp
);
383 tmp
= RREG32_MC(RS480_GART_CACHE_CNTRL
);
384 seq_printf(m
, "GART_CACHE_CNTRL 0x%08x\n", tmp
);
385 tmp
= RREG32_MC(0x3B);
386 seq_printf(m
, "MC_GART_ERROR_ADDRESS 0x%08x\n", tmp
);
387 tmp
= RREG32_MC(0x3C);
388 seq_printf(m
, "MC_GART_ERROR_ADDRESS_HI 0x%08x\n", tmp
);
389 tmp
= RREG32_MC(0x30);
390 seq_printf(m
, "GART_ERROR_0 0x%08x\n", tmp
);
391 tmp
= RREG32_MC(0x31);
392 seq_printf(m
, "GART_ERROR_1 0x%08x\n", tmp
);
393 tmp
= RREG32_MC(0x32);
394 seq_printf(m
, "GART_ERROR_2 0x%08x\n", tmp
);
395 tmp
= RREG32_MC(0x33);
396 seq_printf(m
, "GART_ERROR_3 0x%08x\n", tmp
);
397 tmp
= RREG32_MC(0x34);
398 seq_printf(m
, "GART_ERROR_4 0x%08x\n", tmp
);
399 tmp
= RREG32_MC(0x35);
400 seq_printf(m
, "GART_ERROR_5 0x%08x\n", tmp
);
401 tmp
= RREG32_MC(0x36);
402 seq_printf(m
, "GART_ERROR_6 0x%08x\n", tmp
);
403 tmp
= RREG32_MC(0x37);
404 seq_printf(m
, "GART_ERROR_7 0x%08x\n", tmp
);
408 static struct drm_info_list rs400_gart_info_list
[] = {
409 {"rs400_gart_info", rs400_debugfs_gart_info
, 0, NULL
},
413 int rs400_debugfs_pcie_gart_info_init(struct radeon_device
*rdev
)
415 #if defined(CONFIG_DEBUG_FS)
416 return radeon_debugfs_add_files(rdev
, rs400_gart_info_list
, 1);