2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 /* RS600 / Radeon X1250/X1270 integrated GPU
30 * This file gather function specific to RS600 which is the IGP of
31 * the X1250/X1270 family supporting intel CPU (while RS690/RS740
32 * is the X1250/X1270 supporting AMD CPU). The display engine are
33 * the avivo one, bios is an atombios, 3D block are the one of the
34 * R4XX family. The GART is different from the RS400 one and is very
35 * close to the one of the R600 family (R600 likely being an evolution
36 * of the RS600 GART block).
43 #include "rs600_reg_safe.h"
45 void rs600_gpu_init(struct radeon_device
*rdev
);
46 int rs600_mc_wait_for_idle(struct radeon_device
*rdev
);
48 int rs600_mc_init(struct radeon_device
*rdev
)
50 /* read back the MC value from the hw */
54 /* Setup GPU memory space */
55 tmp
= RREG32_MC(R_000004_MC_FB_LOCATION
);
56 rdev
->mc
.vram_location
= G_000004_MC_FB_START(tmp
) << 16;
57 rdev
->mc
.gtt_location
= 0xffffffffUL
;
58 r
= radeon_mc_setup(rdev
);
64 /* hpd for digital panel detect/disconnect */
65 bool rs600_hpd_sense(struct radeon_device
*rdev
, enum radeon_hpd_id hpd
)
68 bool connected
= false;
72 tmp
= RREG32(R_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS
);
73 if (G_007D04_DC_HOT_PLUG_DETECT1_SENSE(tmp
))
77 tmp
= RREG32(R_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS
);
78 if (G_007D14_DC_HOT_PLUG_DETECT2_SENSE(tmp
))
87 void rs600_hpd_set_polarity(struct radeon_device
*rdev
,
88 enum radeon_hpd_id hpd
)
91 bool connected
= rs600_hpd_sense(rdev
, hpd
);
95 tmp
= RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL
);
97 tmp
&= ~S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1);
99 tmp
|= S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1);
100 WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL
, tmp
);
103 tmp
= RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL
);
105 tmp
&= ~S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1);
107 tmp
|= S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1);
108 WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL
, tmp
);
115 void rs600_hpd_init(struct radeon_device
*rdev
)
117 struct drm_device
*dev
= rdev
->ddev
;
118 struct drm_connector
*connector
;
120 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
121 struct radeon_connector
*radeon_connector
= to_radeon_connector(connector
);
122 switch (radeon_connector
->hpd
.hpd
) {
124 WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL
,
125 S_007D00_DC_HOT_PLUG_DETECT1_EN(1));
126 rdev
->irq
.hpd
[0] = true;
129 WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL
,
130 S_007D10_DC_HOT_PLUG_DETECT2_EN(1));
131 rdev
->irq
.hpd
[1] = true;
140 void rs600_hpd_fini(struct radeon_device
*rdev
)
142 struct drm_device
*dev
= rdev
->ddev
;
143 struct drm_connector
*connector
;
145 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
146 struct radeon_connector
*radeon_connector
= to_radeon_connector(connector
);
147 switch (radeon_connector
->hpd
.hpd
) {
149 WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL
,
150 S_007D00_DC_HOT_PLUG_DETECT1_EN(0));
151 rdev
->irq
.hpd
[0] = false;
154 WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL
,
155 S_007D10_DC_HOT_PLUG_DETECT2_EN(0));
156 rdev
->irq
.hpd
[1] = false;
167 void rs600_gart_tlb_flush(struct radeon_device
*rdev
)
171 tmp
= RREG32_MC(R_000100_MC_PT0_CNTL
);
172 tmp
&= C_000100_INVALIDATE_ALL_L1_TLBS
& C_000100_INVALIDATE_L2_CACHE
;
173 WREG32_MC(R_000100_MC_PT0_CNTL
, tmp
);
175 tmp
= RREG32_MC(R_000100_MC_PT0_CNTL
);
176 tmp
|= S_000100_INVALIDATE_ALL_L1_TLBS(1) & S_000100_INVALIDATE_L2_CACHE(1);
177 WREG32_MC(R_000100_MC_PT0_CNTL
, tmp
);
179 tmp
= RREG32_MC(R_000100_MC_PT0_CNTL
);
180 tmp
&= C_000100_INVALIDATE_ALL_L1_TLBS
& C_000100_INVALIDATE_L2_CACHE
;
181 WREG32_MC(R_000100_MC_PT0_CNTL
, tmp
);
182 tmp
= RREG32_MC(R_000100_MC_PT0_CNTL
);
185 int rs600_gart_init(struct radeon_device
*rdev
)
189 if (rdev
->gart
.table
.vram
.robj
) {
190 WARN(1, "RS600 GART already initialized.\n");
193 /* Initialize common gart structure */
194 r
= radeon_gart_init(rdev
);
198 rdev
->gart
.table_size
= rdev
->gart
.num_gpu_pages
* 8;
199 return radeon_gart_table_vram_alloc(rdev
);
202 int rs600_gart_enable(struct radeon_device
*rdev
)
207 if (rdev
->gart
.table
.vram
.robj
== NULL
) {
208 dev_err(rdev
->dev
, "No VRAM object for PCIE GART.\n");
211 r
= radeon_gart_table_vram_pin(rdev
);
214 /* Enable bus master */
215 tmp
= RREG32(R_00004C_BUS_CNTL
) & C_00004C_BUS_MASTER_DIS
;
216 WREG32(R_00004C_BUS_CNTL
, tmp
);
217 /* FIXME: setup default page */
218 WREG32_MC(R_000100_MC_PT0_CNTL
,
219 (S_000100_EFFECTIVE_L2_CACHE_SIZE(6) |
220 S_000100_EFFECTIVE_L2_QUEUE_SIZE(6)));
222 for (i
= 0; i
< 19; i
++) {
223 WREG32_MC(R_00016C_MC_PT0_CLIENT0_CNTL
+ i
,
224 S_00016C_ENABLE_TRANSLATION_MODE_OVERRIDE(1) |
225 S_00016C_SYSTEM_ACCESS_MODE_MASK(
226 V_00016C_SYSTEM_ACCESS_MODE_NOT_IN_SYS
) |
227 S_00016C_SYSTEM_APERTURE_UNMAPPED_ACCESS(
228 V_00016C_SYSTEM_APERTURE_UNMAPPED_PASSTHROUGH
) |
229 S_00016C_EFFECTIVE_L1_CACHE_SIZE(3) |
230 S_00016C_ENABLE_FRAGMENT_PROCESSING(1) |
231 S_00016C_EFFECTIVE_L1_QUEUE_SIZE(3));
233 /* enable first context */
234 WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL
,
235 S_000102_ENABLE_PAGE_TABLE(1) |
236 S_000102_PAGE_TABLE_DEPTH(V_000102_PAGE_TABLE_FLAT
));
238 /* disable all other contexts */
239 for (i
= 1; i
< 8; i
++)
240 WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL
+ i
, 0);
242 /* setup the page table */
243 WREG32_MC(R_00012C_MC_PT0_CONTEXT0_FLAT_BASE_ADDR
,
244 rdev
->gart
.table_addr
);
245 WREG32_MC(R_00013C_MC_PT0_CONTEXT0_FLAT_START_ADDR
, rdev
->mc
.gtt_start
);
246 WREG32_MC(R_00014C_MC_PT0_CONTEXT0_FLAT_END_ADDR
, rdev
->mc
.gtt_end
);
247 WREG32_MC(R_00011C_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR
, 0);
249 /* System context maps to VRAM space */
250 WREG32_MC(R_000112_MC_PT0_SYSTEM_APERTURE_LOW_ADDR
, rdev
->mc
.vram_start
);
251 WREG32_MC(R_000114_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR
, rdev
->mc
.vram_end
);
253 /* enable page tables */
254 tmp
= RREG32_MC(R_000100_MC_PT0_CNTL
);
255 WREG32_MC(R_000100_MC_PT0_CNTL
, (tmp
| S_000100_ENABLE_PT(1)));
256 tmp
= RREG32_MC(R_000009_MC_CNTL1
);
257 WREG32_MC(R_000009_MC_CNTL1
, (tmp
| S_000009_ENABLE_PAGE_TABLES(1)));
258 rs600_gart_tlb_flush(rdev
);
259 rdev
->gart
.ready
= true;
263 void rs600_gart_disable(struct radeon_device
*rdev
)
268 /* FIXME: disable out of gart access */
269 WREG32_MC(R_000100_MC_PT0_CNTL
, 0);
270 tmp
= RREG32_MC(R_000009_MC_CNTL1
);
271 WREG32_MC(R_000009_MC_CNTL1
, tmp
& C_000009_ENABLE_PAGE_TABLES
);
272 if (rdev
->gart
.table
.vram
.robj
) {
273 r
= radeon_bo_reserve(rdev
->gart
.table
.vram
.robj
, false);
275 radeon_bo_kunmap(rdev
->gart
.table
.vram
.robj
);
276 radeon_bo_unpin(rdev
->gart
.table
.vram
.robj
);
277 radeon_bo_unreserve(rdev
->gart
.table
.vram
.robj
);
282 void rs600_gart_fini(struct radeon_device
*rdev
)
284 rs600_gart_disable(rdev
);
285 radeon_gart_table_vram_free(rdev
);
286 radeon_gart_fini(rdev
);
289 #define R600_PTE_VALID (1 << 0)
290 #define R600_PTE_SYSTEM (1 << 1)
291 #define R600_PTE_SNOOPED (1 << 2)
292 #define R600_PTE_READABLE (1 << 5)
293 #define R600_PTE_WRITEABLE (1 << 6)
295 int rs600_gart_set_page(struct radeon_device
*rdev
, int i
, uint64_t addr
)
297 void __iomem
*ptr
= (void *)rdev
->gart
.table
.vram
.ptr
;
299 if (i
< 0 || i
> rdev
->gart
.num_gpu_pages
) {
302 addr
= addr
& 0xFFFFFFFFFFFFF000ULL
;
303 addr
|= R600_PTE_VALID
| R600_PTE_SYSTEM
| R600_PTE_SNOOPED
;
304 addr
|= R600_PTE_READABLE
| R600_PTE_WRITEABLE
;
305 writeq(addr
, ((void __iomem
*)ptr
) + (i
* 8));
309 int rs600_irq_set(struct radeon_device
*rdev
)
312 uint32_t mode_int
= 0;
313 u32 hpd1
= RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL
) &
314 ~S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1);
315 u32 hpd2
= RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL
) &
316 ~S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1);
318 if (rdev
->irq
.sw_int
) {
319 tmp
|= S_000040_SW_INT_EN(1);
321 if (rdev
->irq
.crtc_vblank_int
[0]) {
322 mode_int
|= S_006540_D1MODE_VBLANK_INT_MASK(1);
324 if (rdev
->irq
.crtc_vblank_int
[1]) {
325 mode_int
|= S_006540_D2MODE_VBLANK_INT_MASK(1);
327 if (rdev
->irq
.hpd
[0]) {
328 hpd1
|= S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1);
330 if (rdev
->irq
.hpd
[1]) {
331 hpd2
|= S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1);
333 WREG32(R_000040_GEN_INT_CNTL
, tmp
);
334 WREG32(R_006540_DxMODE_INT_MASK
, mode_int
);
335 WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL
, hpd1
);
336 WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL
, hpd2
);
340 static inline uint32_t rs600_irq_ack(struct radeon_device
*rdev
, u32
*r500_disp_int
)
342 uint32_t irqs
= RREG32(R_000044_GEN_INT_STATUS
);
343 uint32_t irq_mask
= ~C_000044_SW_INT
;
346 if (G_000044_DISPLAY_INT_STAT(irqs
)) {
347 *r500_disp_int
= RREG32(R_007EDC_DISP_INTERRUPT_STATUS
);
348 if (G_007EDC_LB_D1_VBLANK_INTERRUPT(*r500_disp_int
)) {
349 WREG32(R_006534_D1MODE_VBLANK_STATUS
,
350 S_006534_D1MODE_VBLANK_ACK(1));
352 if (G_007EDC_LB_D2_VBLANK_INTERRUPT(*r500_disp_int
)) {
353 WREG32(R_006D34_D2MODE_VBLANK_STATUS
,
354 S_006D34_D2MODE_VBLANK_ACK(1));
356 if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(*r500_disp_int
)) {
357 tmp
= RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL
);
358 tmp
|= S_007D08_DC_HOT_PLUG_DETECT1_INT_ACK(1);
359 WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL
, tmp
);
361 if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(*r500_disp_int
)) {
362 tmp
= RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL
);
363 tmp
|= S_007D18_DC_HOT_PLUG_DETECT2_INT_ACK(1);
364 WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL
, tmp
);
371 WREG32(R_000044_GEN_INT_STATUS
, irqs
);
373 return irqs
& irq_mask
;
376 void rs600_irq_disable(struct radeon_device
*rdev
)
380 WREG32(R_000040_GEN_INT_CNTL
, 0);
381 WREG32(R_006540_DxMODE_INT_MASK
, 0);
382 /* Wait and acknowledge irq */
384 rs600_irq_ack(rdev
, &tmp
);
387 int rs600_irq_process(struct radeon_device
*rdev
)
389 uint32_t status
, msi_rearm
;
390 uint32_t r500_disp_int
;
391 bool queue_hotplug
= false;
393 status
= rs600_irq_ack(rdev
, &r500_disp_int
);
394 if (!status
&& !r500_disp_int
) {
397 while (status
|| r500_disp_int
) {
399 if (G_000044_SW_INT(status
))
400 radeon_fence_process(rdev
);
401 /* Vertical blank interrupts */
402 if (G_007EDC_LB_D1_VBLANK_INTERRUPT(r500_disp_int
))
403 drm_handle_vblank(rdev
->ddev
, 0);
404 if (G_007EDC_LB_D2_VBLANK_INTERRUPT(r500_disp_int
))
405 drm_handle_vblank(rdev
->ddev
, 1);
406 if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(r500_disp_int
)) {
407 queue_hotplug
= true;
410 if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(r500_disp_int
)) {
411 queue_hotplug
= true;
414 status
= rs600_irq_ack(rdev
, &r500_disp_int
);
417 queue_work(rdev
->wq
, &rdev
->hotplug_work
);
418 if (rdev
->msi_enabled
) {
419 switch (rdev
->family
) {
423 msi_rearm
= RREG32(RADEON_BUS_CNTL
) & ~RS600_MSI_REARM
;
424 WREG32(RADEON_BUS_CNTL
, msi_rearm
);
425 WREG32(RADEON_BUS_CNTL
, msi_rearm
| RS600_MSI_REARM
);
428 msi_rearm
= RREG32(RADEON_MSI_REARM_EN
) & ~RV370_MSI_REARM_EN
;
429 WREG32(RADEON_MSI_REARM_EN
, msi_rearm
);
430 WREG32(RADEON_MSI_REARM_EN
, msi_rearm
| RV370_MSI_REARM_EN
);
437 u32
rs600_get_vblank_counter(struct radeon_device
*rdev
, int crtc
)
440 return RREG32(R_0060A4_D1CRTC_STATUS_FRAME_COUNT
);
442 return RREG32(R_0068A4_D2CRTC_STATUS_FRAME_COUNT
);
445 int rs600_mc_wait_for_idle(struct radeon_device
*rdev
)
449 for (i
= 0; i
< rdev
->usec_timeout
; i
++) {
450 if (G_000000_MC_IDLE(RREG32_MC(R_000000_MC_STATUS
)))
457 void rs600_gpu_init(struct radeon_device
*rdev
)
459 r100_hdp_reset(rdev
);
460 r420_pipes_init(rdev
);
461 /* Wait for mc idle */
462 if (rs600_mc_wait_for_idle(rdev
))
463 dev_warn(rdev
->dev
, "Wait MC idle timeout before updating MC.\n");
466 void rs600_vram_info(struct radeon_device
*rdev
)
468 rdev
->mc
.vram_is_ddr
= true;
469 rdev
->mc
.vram_width
= 128;
471 rdev
->mc
.real_vram_size
= RREG32(RADEON_CONFIG_MEMSIZE
);
472 rdev
->mc
.mc_vram_size
= rdev
->mc
.real_vram_size
;
474 rdev
->mc
.aper_base
= drm_get_resource_start(rdev
->ddev
, 0);
475 rdev
->mc
.aper_size
= drm_get_resource_len(rdev
->ddev
, 0);
477 if (rdev
->mc
.mc_vram_size
> rdev
->mc
.aper_size
)
478 rdev
->mc
.mc_vram_size
= rdev
->mc
.aper_size
;
480 if (rdev
->mc
.real_vram_size
> rdev
->mc
.aper_size
)
481 rdev
->mc
.real_vram_size
= rdev
->mc
.aper_size
;
484 void rs600_bandwidth_update(struct radeon_device
*rdev
)
486 /* FIXME: implement, should this be like rs690 ? */
489 uint32_t rs600_mc_rreg(struct radeon_device
*rdev
, uint32_t reg
)
491 WREG32(R_000070_MC_IND_INDEX
, S_000070_MC_IND_ADDR(reg
) |
492 S_000070_MC_IND_CITF_ARB0(1));
493 return RREG32(R_000074_MC_IND_DATA
);
496 void rs600_mc_wreg(struct radeon_device
*rdev
, uint32_t reg
, uint32_t v
)
498 WREG32(R_000070_MC_IND_INDEX
, S_000070_MC_IND_ADDR(reg
) |
499 S_000070_MC_IND_CITF_ARB0(1) | S_000070_MC_IND_WR_EN(1));
500 WREG32(R_000074_MC_IND_DATA
, v
);
503 void rs600_debugfs(struct radeon_device
*rdev
)
505 if (r100_debugfs_rbbm_init(rdev
))
506 DRM_ERROR("Failed to register debugfs file for RBBM !\n");
509 void rs600_set_safe_registers(struct radeon_device
*rdev
)
511 rdev
->config
.r300
.reg_safe_bm
= rs600_reg_safe_bm
;
512 rdev
->config
.r300
.reg_safe_bm_size
= ARRAY_SIZE(rs600_reg_safe_bm
);
515 static void rs600_mc_program(struct radeon_device
*rdev
)
517 struct rv515_mc_save save
;
519 /* Stops all mc clients */
520 rv515_mc_stop(rdev
, &save
);
522 /* Wait for mc idle */
523 if (rs600_mc_wait_for_idle(rdev
))
524 dev_warn(rdev
->dev
, "Wait MC idle timeout before updating MC.\n");
526 /* FIXME: What does AGP means for such chipset ? */
527 WREG32_MC(R_000005_MC_AGP_LOCATION
, 0x0FFFFFFF);
528 WREG32_MC(R_000006_AGP_BASE
, 0);
529 WREG32_MC(R_000007_AGP_BASE_2
, 0);
531 WREG32_MC(R_000004_MC_FB_LOCATION
,
532 S_000004_MC_FB_START(rdev
->mc
.vram_start
>> 16) |
533 S_000004_MC_FB_TOP(rdev
->mc
.vram_end
>> 16));
534 WREG32(R_000134_HDP_FB_LOCATION
,
535 S_000134_HDP_FB_START(rdev
->mc
.vram_start
>> 16));
537 rv515_mc_resume(rdev
, &save
);
540 static int rs600_startup(struct radeon_device
*rdev
)
544 rs600_mc_program(rdev
);
546 rv515_clock_startup(rdev
);
547 /* Initialize GPU configuration (# pipes, ...) */
548 rs600_gpu_init(rdev
);
549 /* Initialize GART (initialize after TTM so we can allocate
550 * memory through TTM but finalize after TTM) */
551 r
= rs600_gart_enable(rdev
);
557 r
= r100_cp_init(rdev
, 1024 * 1024);
559 dev_err(rdev
->dev
, "failled initializing CP (%d).\n", r
);
562 r
= r100_wb_init(rdev
);
564 dev_err(rdev
->dev
, "failled initializing WB (%d).\n", r
);
565 r
= r100_ib_init(rdev
);
567 dev_err(rdev
->dev
, "failled initializing IB (%d).\n", r
);
573 int rs600_resume(struct radeon_device
*rdev
)
575 /* Make sur GART are not working */
576 rs600_gart_disable(rdev
);
577 /* Resume clock before doing reset */
578 rv515_clock_startup(rdev
);
579 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
580 if (radeon_gpu_reset(rdev
)) {
581 dev_warn(rdev
->dev
, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
582 RREG32(R_000E40_RBBM_STATUS
),
583 RREG32(R_0007C0_CP_STAT
));
586 atom_asic_init(rdev
->mode_info
.atom_context
);
587 /* Resume clock after posting */
588 rv515_clock_startup(rdev
);
589 /* Initialize surface registers */
590 radeon_surface_init(rdev
);
591 return rs600_startup(rdev
);
594 int rs600_suspend(struct radeon_device
*rdev
)
596 r100_cp_disable(rdev
);
597 r100_wb_disable(rdev
);
598 rs600_irq_disable(rdev
);
599 rs600_gart_disable(rdev
);
603 void rs600_fini(struct radeon_device
*rdev
)
609 radeon_gem_fini(rdev
);
610 rs600_gart_fini(rdev
);
611 radeon_irq_kms_fini(rdev
);
612 radeon_fence_driver_fini(rdev
);
613 radeon_bo_fini(rdev
);
614 radeon_atombios_fini(rdev
);
619 int rs600_init(struct radeon_device
*rdev
)
624 rv515_vga_render_disable(rdev
);
625 /* Initialize scratch registers */
626 radeon_scratch_init(rdev
);
627 /* Initialize surface registers */
628 radeon_surface_init(rdev
);
630 if (!radeon_get_bios(rdev
)) {
631 if (ASIC_IS_AVIVO(rdev
))
634 if (rdev
->is_atom_bios
) {
635 r
= radeon_atombios_init(rdev
);
639 dev_err(rdev
->dev
, "Expecting atombios for RS600 GPU\n");
642 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
643 if (radeon_gpu_reset(rdev
)) {
645 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
646 RREG32(R_000E40_RBBM_STATUS
),
647 RREG32(R_0007C0_CP_STAT
));
649 /* check if cards are posted or not */
650 if (radeon_boot_test_post_card(rdev
) == false)
653 /* Initialize clocks */
654 radeon_get_clock_info(rdev
->ddev
);
655 /* Initialize power management */
656 radeon_pm_init(rdev
);
657 /* Get vram informations */
658 rs600_vram_info(rdev
);
659 /* Initialize memory controller (also test AGP) */
660 r
= rs600_mc_init(rdev
);
665 r
= radeon_fence_driver_init(rdev
);
668 r
= radeon_irq_kms_init(rdev
);
672 r
= radeon_bo_init(rdev
);
675 r
= rs600_gart_init(rdev
);
678 rs600_set_safe_registers(rdev
);
679 rdev
->accel_working
= true;
680 r
= rs600_startup(rdev
);
682 /* Somethings want wront with the accel init stop accel */
683 dev_err(rdev
->dev
, "Disabling GPU acceleration\n");
688 rs600_gart_fini(rdev
);
689 radeon_irq_kms_fini(rdev
);
690 rdev
->accel_working
= false;