drivers/gpu/drm/radeon/rs600.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 /* RS600 / Radeon X1250/X1270 integrated GPU
  29  *
  30  * This file gather function specific to RS600 which is the IGP of
  31  * the X1250/X1270 family supporting intel CPU (while RS690/RS740
  32  * is the X1250/X1270 supporting AMD CPU). The display engine are
  33  * the avivo one, bios is an atombios, 3D block are the one of the
  34  * R4XX family. The GART is different from the RS400 one and is very
  35  * close to the one of the R600 family (R600 likely being an evolution
  36  * of the RS600 GART block).
  37  */
  38 #include <drm/drmP.h>
  39 #include "radeon.h"
  40 #include "radeon_asic.h"
  41 #include "atom.h"
  42 #include "rs600d.h"
  43
  44 #include "rs600_reg_safe.h"
  45
  46 static void rs600_gpu_init(struct radeon_device *rdev);
  47 int rs600_mc_wait_for_idle(struct radeon_device *rdev);
  48
  49 static const u32 crtc_offsets[2] =
  50 {
  51         0,
  52         AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL
  53 };
  54
  55 static bool avivo_is_in_vblank(struct radeon_device *rdev, int crtc)
  56 {
  57         if (RREG32(AVIVO_D1CRTC_STATUS + crtc_offsets[crtc]) & AVIVO_D1CRTC_V_BLANK)
  58                 return true;
  59         else
  60                 return false;
  61 }
  62
  63 static bool avivo_is_counter_moving(struct radeon_device *rdev, int crtc)
  64 {
  65         u32 pos1, pos2;
  66
  67         pos1 = RREG32(AVIVO_D1CRTC_STATUS_POSITION + crtc_offsets[crtc]);
  68         pos2 = RREG32(AVIVO_D1CRTC_STATUS_POSITION + crtc_offsets[crtc]);
  69
  70         if (pos1 != pos2)
  71                 return true;
  72         else
  73                 return false;
  74 }
  75
  76 /**
  77  * avivo_wait_for_vblank - vblank wait asic callback.
  78  *
  79  * @rdev: radeon_device pointer
  80  * @crtc: crtc to wait for vblank on
  81  *
  82  * Wait for vblank on the requested crtc (r5xx-r7xx).
  83  */
  84 void avivo_wait_for_vblank(struct radeon_device *rdev, int crtc)
  85 {
  86         unsigned i = 0;
  87
  88         if (crtc >= rdev->num_crtc)
  89                 return;
  90
  91         if (!(RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[crtc]) & AVIVO_CRTC_EN))
  92                 return;
  93
  94         /* depending on when we hit vblank, we may be close to active; if so,
  95          * wait for another frame.
  96          */
  97         while (avivo_is_in_vblank(rdev, crtc)) {
  98                 if (i++ % 100 == 0) {
  99                         if (!avivo_is_counter_moving(rdev, crtc))
 100                                 break;
 101                 }
 102         }
 103
 104         while (!avivo_is_in_vblank(rdev, crtc)) {
 105                 if (i++ % 100 == 0) {
 106                         if (!avivo_is_counter_moving(rdev, crtc))
 107                                 break;
 108                 }
 109         }
 110 }
 111
 112 void rs600_pre_page_flip(struct radeon_device *rdev, int crtc)
 113 {
 114         /* enable the pflip int */
 115         radeon_irq_kms_pflip_irq_get(rdev, crtc);
 116 }
 117
 118 void rs600_post_page_flip(struct radeon_device *rdev, int crtc)
 119 {
 120         /* disable the pflip int */
 121         radeon_irq_kms_pflip_irq_put(rdev, crtc);
 122 }
 123
 124 u32 rs600_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
 125 {
 126         struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
 127         u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset);
 128         int i;
 129
 130         /* Lock the graphics update lock */
 131         tmp |= AVIVO_D1GRPH_UPDATE_LOCK;
 132         WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
 133
 134         /* update the scanout addresses */
 135         WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
 136                (u32)crtc_base);
 137         WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
 138                (u32)crtc_base);
 139
 140         /* Wait for update_pending to go high. */
 141         for (i = 0; i < rdev->usec_timeout; i++) {
 142                 if (RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING)
 143                         break;
 144                 udelay(1);
 145         }
 146         DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
 147
 148         /* Unlock the lock, so double-buffering can take place inside vblank */
 149         tmp &= ~AVIVO_D1GRPH_UPDATE_LOCK;
 150         WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
 151
 152         /* Return current update_pending status: */
 153         return RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING;
 154 }
 155
 156 void avivo_program_fmt(struct drm_encoder *encoder)
 157 {
 158         struct drm_device *dev = encoder->dev;
 159         struct radeon_device *rdev = dev->dev_private;
 160         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 161         struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
 162         int bpc = 0;
 163         u32 tmp = 0;
 164         enum radeon_connector_dither dither = RADEON_FMT_DITHER_DISABLE;
 165
 166         if (connector) {
 167                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 168                 bpc = radeon_get_monitor_bpc(connector);
 169                 dither = radeon_connector->dither;
 170         }
 171
 172         /* LVDS FMT is set up by atom */
 173         if (radeon_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
 174                 return;
 175
 176         if (bpc == 0)
 177                 return;
 178
 179         switch (bpc) {
 180         case 6:
 181                 if (dither == RADEON_FMT_DITHER_ENABLE)
 182                         /* XXX sort out optimal dither settings */
 183                         tmp |= AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN;
 184                 else
 185                         tmp |= AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_EN;
 186                 break;
 187         case 8:
 188                 if (dither == RADEON_FMT_DITHER_ENABLE)
 189                         /* XXX sort out optimal dither settings */
 190                         tmp |= (AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN |
 191                                 AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH);
 192                 else
 193                         tmp |= (AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_EN |
 194                                 AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH);
 195                 break;
 196         case 10:
 197         default:
 198                 /* not needed */
 199                 break;
 200         }
 201
 202         switch (radeon_encoder->encoder_id) {
 203         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
 204                 WREG32(AVIVO_TMDSA_BIT_DEPTH_CONTROL, tmp);
 205                 break;
 206         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
 207                 WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, tmp);
 208                 break;
 209         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
 210                 WREG32(AVIVO_DVOA_BIT_DEPTH_CONTROL, tmp);
 211                 break;
 212         case ENCODER_OBJECT_ID_INTERNAL_DDI:
 213                 WREG32(AVIVO_DDIA_BIT_DEPTH_CONTROL, tmp);
 214                 break;
 215         default:
 216                 break;
 217         }
 218 }
 219
 220 void rs600_pm_misc(struct radeon_device *rdev)
 221 {
 222         int requested_index = rdev->pm.requested_power_state_index;
 223         struct radeon_power_state *ps = &rdev->pm.power_state[requested_index];
 224         struct radeon_voltage *voltage = &ps->clock_info[0].voltage;
 225         u32 tmp, dyn_pwrmgt_sclk_length, dyn_sclk_vol_cntl;
 226         u32 hdp_dyn_cntl, /*mc_host_dyn_cntl,*/ dyn_backbias_cntl;
 227
 228         if ((voltage->type == VOLTAGE_GPIO) && (voltage->gpio.valid)) {
 229                 if (ps->misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
 230                         tmp = RREG32(voltage->gpio.reg);
 231                         if (voltage->active_high)
 232                                 tmp |= voltage->gpio.mask;
 233                         else
 234                                 tmp &= ~(voltage->gpio.mask);
 235                         WREG32(voltage->gpio.reg, tmp);
 236                         if (voltage->delay)
 237                                 udelay(voltage->delay);
 238                 } else {
 239                         tmp = RREG32(voltage->gpio.reg);
 240                         if (voltage->active_high)
 241                                 tmp &= ~voltage->gpio.mask;
 242                         else
 243                                 tmp |= voltage->gpio.mask;
 244                         WREG32(voltage->gpio.reg, tmp);
 245                         if (voltage->delay)
 246                                 udelay(voltage->delay);
 247                 }
 248         } else if (voltage->type == VOLTAGE_VDDC)
 249                 radeon_atom_set_voltage(rdev, voltage->vddc_id, SET_VOLTAGE_TYPE_ASIC_VDDC);
 250
 251         dyn_pwrmgt_sclk_length = RREG32_PLL(DYN_PWRMGT_SCLK_LENGTH);
 252         dyn_pwrmgt_sclk_length &= ~REDUCED_POWER_SCLK_HILEN(0xf);
 253         dyn_pwrmgt_sclk_length &= ~REDUCED_POWER_SCLK_LOLEN(0xf);
 254         if (ps->misc & ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN) {
 255                 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2) {
 256                         dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_HILEN(2);
 257                         dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_LOLEN(2);
 258                 } else if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4) {
 259                         dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_HILEN(4);
 260                         dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_LOLEN(4);
 261                 }
 262         } else {
 263                 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_HILEN(1);
 264                 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_LOLEN(1);
 265         }
 266         WREG32_PLL(DYN_PWRMGT_SCLK_LENGTH, dyn_pwrmgt_sclk_length);
 267
 268         dyn_sclk_vol_cntl = RREG32_PLL(DYN_SCLK_VOL_CNTL);
 269         if (ps->misc & ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN) {
 270                 dyn_sclk_vol_cntl |= IO_CG_VOLTAGE_DROP;
 271                 if (voltage->delay) {
 272                         dyn_sclk_vol_cntl |= VOLTAGE_DROP_SYNC;
 273                         dyn_sclk_vol_cntl |= VOLTAGE_DELAY_SEL(voltage->delay);
 274                 } else
 275                         dyn_sclk_vol_cntl &= ~VOLTAGE_DROP_SYNC;
 276         } else
 277                 dyn_sclk_vol_cntl &= ~IO_CG_VOLTAGE_DROP;
 278         WREG32_PLL(DYN_SCLK_VOL_CNTL, dyn_sclk_vol_cntl);
 279
 280         hdp_dyn_cntl = RREG32_PLL(HDP_DYN_CNTL);
 281         if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN)
 282                 hdp_dyn_cntl &= ~HDP_FORCEON;
 283         else
 284                 hdp_dyn_cntl |= HDP_FORCEON;
 285         WREG32_PLL(HDP_DYN_CNTL, hdp_dyn_cntl);
 286 #if 0
 287         /* mc_host_dyn seems to cause hangs from time to time */
 288         mc_host_dyn_cntl = RREG32_PLL(MC_HOST_DYN_CNTL);
 289         if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_MC_HOST_BLOCK_EN)
 290                 mc_host_dyn_cntl &= ~MC_HOST_FORCEON;
 291         else
 292                 mc_host_dyn_cntl |= MC_HOST_FORCEON;
 293         WREG32_PLL(MC_HOST_DYN_CNTL, mc_host_dyn_cntl);
 294 #endif
 295         dyn_backbias_cntl = RREG32_PLL(DYN_BACKBIAS_CNTL);
 296         if (ps->misc & ATOM_PM_MISCINFO2_DYNAMIC_BACK_BIAS_EN)
 297                 dyn_backbias_cntl |= IO_CG_BACKBIAS_EN;
 298         else
 299                 dyn_backbias_cntl &= ~IO_CG_BACKBIAS_EN;
 300         WREG32_PLL(DYN_BACKBIAS_CNTL, dyn_backbias_cntl);
 301
 302         /* set pcie lanes */
 303         if ((rdev->flags & RADEON_IS_PCIE) &&
 304             !(rdev->flags & RADEON_IS_IGP) &&
 305             rdev->asic->pm.set_pcie_lanes &&
 306             (ps->pcie_lanes !=
 307              rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) {
 308                 radeon_set_pcie_lanes(rdev,
 309                                       ps->pcie_lanes);
 310                 DRM_DEBUG("Setting: p: %d\n", ps->pcie_lanes);
 311         }
 312 }
 313
 314 void rs600_pm_prepare(struct radeon_device *rdev)
 315 {
 316         struct drm_device *ddev = rdev->ddev;
 317         struct drm_crtc *crtc;
 318         struct radeon_crtc *radeon_crtc;
 319         u32 tmp;
 320
 321         /* disable any active CRTCs */
 322         list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
 323                 radeon_crtc = to_radeon_crtc(crtc);
 324                 if (radeon_crtc->enabled) {
 325                         tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset);
 326                         tmp |= AVIVO_CRTC_DISP_READ_REQUEST_DISABLE;
 327                         WREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
 328                 }
 329         }
 330 }
 331
 332 void rs600_pm_finish(struct radeon_device *rdev)
 333 {
 334         struct drm_device *ddev = rdev->ddev;
 335         struct drm_crtc *crtc;
 336         struct radeon_crtc *radeon_crtc;
 337         u32 tmp;
 338
 339         /* enable any active CRTCs */
 340         list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
 341                 radeon_crtc = to_radeon_crtc(crtc);
 342                 if (radeon_crtc->enabled) {
 343                         tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset);
 344                         tmp &= ~AVIVO_CRTC_DISP_READ_REQUEST_DISABLE;
 345                         WREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
 346                 }
 347         }
 348 }
 349
 350 /* hpd for digital panel detect/disconnect */
 351 bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
 352 {
 353         u32 tmp;
 354         bool connected = false;
 355
 356         switch (hpd) {
 357         case RADEON_HPD_1:
 358                 tmp = RREG32(R_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS);
 359                 if (G_007D04_DC_HOT_PLUG_DETECT1_SENSE(tmp))
 360                         connected = true;
 361                 break;
 362         case RADEON_HPD_2:
 363                 tmp = RREG32(R_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS);
 364                 if (G_007D14_DC_HOT_PLUG_DETECT2_SENSE(tmp))
 365                         connected = true;
 366                 break;
 367         default:
 368                 break;
 369         }
 370         return connected;
 371 }
 372
 373 void rs600_hpd_set_polarity(struct radeon_device *rdev,
 374                             enum radeon_hpd_id hpd)
 375 {
 376         u32 tmp;
 377         bool connected = rs600_hpd_sense(rdev, hpd);
 378
 379         switch (hpd) {
 380         case RADEON_HPD_1:
 381                 tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL);
 382                 if (connected)
 383                         tmp &= ~S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1);
 384                 else
 385                         tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1);
 386                 WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
 387                 break;
 388         case RADEON_HPD_2:
 389                 tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL);
 390                 if (connected)
 391                         tmp &= ~S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1);
 392                 else
 393                         tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1);
 394                 WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
 395                 break;
 396         default:
 397                 break;
 398         }
 399 }
 400
 401 void rs600_hpd_init(struct radeon_device *rdev)
 402 {
 403         struct drm_device *dev = rdev->ddev;
 404         struct drm_connector *connector;
 405         unsigned enable = 0;
 406
 407         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 408                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 409                 switch (radeon_connector->hpd.hpd) {
 410                 case RADEON_HPD_1:
 411                         WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL,
 412                                S_007D00_DC_HOT_PLUG_DETECT1_EN(1));
 413                         break;
 414                 case RADEON_HPD_2:
 415                         WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL,
 416                                S_007D10_DC_HOT_PLUG_DETECT2_EN(1));
 417                         break;
 418                 default:
 419                         break;
 420                 }
 421                 enable |= 1 << radeon_connector->hpd.hpd;
 422                 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
 423         }
 424         radeon_irq_kms_enable_hpd(rdev, enable);
 425 }
 426
 427 void rs600_hpd_fini(struct radeon_device *rdev)
 428 {
 429         struct drm_device *dev = rdev->ddev;
 430         struct drm_connector *connector;
 431         unsigned disable = 0;
 432
 433         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 434                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 435                 switch (radeon_connector->hpd.hpd) {
 436                 case RADEON_HPD_1:
 437                         WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL,
 438                                S_007D00_DC_HOT_PLUG_DETECT1_EN(0));
 439                         break;
 440                 case RADEON_HPD_2:
 441                         WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL,
 442                                S_007D10_DC_HOT_PLUG_DETECT2_EN(0));
 443                         break;
 444                 default:
 445                         break;
 446                 }
 447                 disable |= 1 << radeon_connector->hpd.hpd;
 448         }
 449         radeon_irq_kms_disable_hpd(rdev, disable);
 450 }
 451
 452 int rs600_asic_reset(struct radeon_device *rdev)
 453 {
 454         struct rv515_mc_save save;
 455         u32 status, tmp;
 456         int ret = 0;
 457
 458         status = RREG32(R_000E40_RBBM_STATUS);
 459         if (!G_000E40_GUI_ACTIVE(status)) {
 460                 return 0;
 461         }
 462         /* Stops all mc clients */
 463         rv515_mc_stop(rdev, &save);
 464         status = RREG32(R_000E40_RBBM_STATUS);
 465         dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
 466         /* stop CP */
 467         WREG32(RADEON_CP_CSQ_CNTL, 0);
 468         tmp = RREG32(RADEON_CP_RB_CNTL);
 469         WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
 470         WREG32(RADEON_CP_RB_RPTR_WR, 0);
 471         WREG32(RADEON_CP_RB_WPTR, 0);
 472         WREG32(RADEON_CP_RB_CNTL, tmp);
 473         pci_save_state(rdev->pdev);
 474         /* disable bus mastering */
 475         pci_clear_master(rdev->pdev);
 476         mdelay(1);
 477         /* reset GA+VAP */
 478         WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_VAP(1) |
 479                                         S_0000F0_SOFT_RESET_GA(1));
 480         RREG32(R_0000F0_RBBM_SOFT_RESET);
 481         mdelay(500);
 482         WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
 483         mdelay(1);
 484         status = RREG32(R_000E40_RBBM_STATUS);
 485         dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
 486         /* reset CP */
 487         WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1));
 488         RREG32(R_0000F0_RBBM_SOFT_RESET);
 489         mdelay(500);
 490         WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
 491         mdelay(1);
 492         status = RREG32(R_000E40_RBBM_STATUS);
 493         dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
 494         /* reset MC */
 495         WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_MC(1));
 496         RREG32(R_0000F0_RBBM_SOFT_RESET);
 497         mdelay(500);
 498         WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
 499         mdelay(1);
 500         status = RREG32(R_000E40_RBBM_STATUS);
 501         dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
 502         /* restore PCI & busmastering */
 503         pci_restore_state(rdev->pdev);
 504         /* Check if GPU is idle */
 505         if (G_000E40_GA_BUSY(status) || G_000E40_VAP_BUSY(status)) {
 506                 dev_err(rdev->dev, "failed to reset GPU\n");
 507                 ret = -1;
 508         } else
 509                 dev_info(rdev->dev, "GPU reset succeed\n");
 510         rv515_mc_resume(rdev, &save);
 511         return ret;
 512 }
 513
 514 /*
 515  * GART.
 516  */
 517 void rs600_gart_tlb_flush(struct radeon_device *rdev)
 518 {
 519         uint32_t tmp;
 520
 521         tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
 522         tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE;
 523         WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
 524
 525         tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
 526         tmp |= S_000100_INVALIDATE_ALL_L1_TLBS(1) | S_000100_INVALIDATE_L2_CACHE(1);
 527         WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
 528
 529         tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
 530         tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE;
 531         WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
 532         tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
 533 }
 534
 535 static int rs600_gart_init(struct radeon_device *rdev)
 536 {
 537         int r;
 538
 539         if (rdev->gart.robj) {
 540                 WARN(1, "RS600 GART already initialized\n");
 541                 return 0;
 542         }
 543         /* Initialize common gart structure */
 544         r = radeon_gart_init(rdev);
 545         if (r) {
 546                 return r;
 547         }
 548         rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
 549         return radeon_gart_table_vram_alloc(rdev);
 550 }
 551
 552 static int rs600_gart_enable(struct radeon_device *rdev)
 553 {
 554         u32 tmp;
 555         int r, i;
 556
 557         if (rdev->gart.robj == NULL) {
 558                 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
 559                 return -EINVAL;
 560         }
 561         r = radeon_gart_table_vram_pin(rdev);
 562         if (r)
 563                 return r;
 564         radeon_gart_restore(rdev);
 565         /* Enable bus master */
 566         tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS;
 567         WREG32(RADEON_BUS_CNTL, tmp);
 568         /* FIXME: setup default page */
 569         WREG32_MC(R_000100_MC_PT0_CNTL,
 570                   (S_000100_EFFECTIVE_L2_CACHE_SIZE(6) |
 571                    S_000100_EFFECTIVE_L2_QUEUE_SIZE(6)));
 572
 573         for (i = 0; i < 19; i++) {
 574                 WREG32_MC(R_00016C_MC_PT0_CLIENT0_CNTL + i,
 575                           S_00016C_ENABLE_TRANSLATION_MODE_OVERRIDE(1) |
 576                           S_00016C_SYSTEM_ACCESS_MODE_MASK(
 577                                   V_00016C_SYSTEM_ACCESS_MODE_NOT_IN_SYS) |
 578                           S_00016C_SYSTEM_APERTURE_UNMAPPED_ACCESS(
 579                                   V_00016C_SYSTEM_APERTURE_UNMAPPED_PASSTHROUGH) |
 580                           S_00016C_EFFECTIVE_L1_CACHE_SIZE(3) |
 581                           S_00016C_ENABLE_FRAGMENT_PROCESSING(1) |
 582                           S_00016C_EFFECTIVE_L1_QUEUE_SIZE(3));
 583         }
 584         /* enable first context */
 585         WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL,
 586                   S_000102_ENABLE_PAGE_TABLE(1) |
 587                   S_000102_PAGE_TABLE_DEPTH(V_000102_PAGE_TABLE_FLAT));
 588
 589         /* disable all other contexts */
 590         for (i = 1; i < 8; i++)
 591                 WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL + i, 0);
 592
 593         /* setup the page table */
 594         WREG32_MC(R_00012C_MC_PT0_CONTEXT0_FLAT_BASE_ADDR,
 595                   rdev->gart.table_addr);
 596         WREG32_MC(R_00013C_MC_PT0_CONTEXT0_FLAT_START_ADDR, rdev->mc.gtt_start);
 597         WREG32_MC(R_00014C_MC_PT0_CONTEXT0_FLAT_END_ADDR, rdev->mc.gtt_end);
 598         WREG32_MC(R_00011C_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR, 0);
 599
 600         /* System context maps to VRAM space */
 601         WREG32_MC(R_000112_MC_PT0_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start);
 602         WREG32_MC(R_000114_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end);
 603
 604         /* enable page tables */
 605         tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
 606         WREG32_MC(R_000100_MC_PT0_CNTL, (tmp | S_000100_ENABLE_PT(1)));
 607         tmp = RREG32_MC(R_000009_MC_CNTL1);
 608         WREG32_MC(R_000009_MC_CNTL1, (tmp | S_000009_ENABLE_PAGE_TABLES(1)));
 609         rs600_gart_tlb_flush(rdev);
 610         DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
 611                  (unsigned)(rdev->mc.gtt_size >> 20),
 612                  (unsigned long long)rdev->gart.table_addr);
 613         rdev->gart.ready = true;
 614         return 0;
 615 }
 616
 617 static void rs600_gart_disable(struct radeon_device *rdev)
 618 {
 619         u32 tmp;
 620
 621         /* FIXME: disable out of gart access */
 622         WREG32_MC(R_000100_MC_PT0_CNTL, 0);
 623         tmp = RREG32_MC(R_000009_MC_CNTL1);
 624         WREG32_MC(R_000009_MC_CNTL1, tmp & C_000009_ENABLE_PAGE_TABLES);
 625         radeon_gart_table_vram_unpin(rdev);
 626 }
 627
 628 static void rs600_gart_fini(struct radeon_device *rdev)
 629 {
 630         radeon_gart_fini(rdev);
 631         rs600_gart_disable(rdev);
 632         radeon_gart_table_vram_free(rdev);
 633 }
 634
 635 #define R600_PTE_VALID     (1 << 0)
 636 #define R600_PTE_SYSTEM    (1 << 1)
 637 #define R600_PTE_SNOOPED   (1 << 2)
 638 #define R600_PTE_READABLE  (1 << 5)
 639 #define R600_PTE_WRITEABLE (1 << 6)
 640
 641 int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
 642 {
 643         void __iomem *ptr = (void *)rdev->gart.ptr;
 644
 645         if (i < 0 || i > rdev->gart.num_gpu_pages) {
 646                 return -EINVAL;
 647         }
 648         addr = addr & 0xFFFFFFFFFFFFF000ULL;
 649         addr |= R600_PTE_VALID | R600_PTE_SYSTEM | R600_PTE_SNOOPED;
 650         addr |= R600_PTE_READABLE | R600_PTE_WRITEABLE;
 651         writeq(addr, ptr + (i * 8));
 652         return 0;
 653 }
 654
 655 int rs600_irq_set(struct radeon_device *rdev)
 656 {
 657         uint32_t tmp = 0;
 658         uint32_t mode_int = 0;
 659         u32 hpd1 = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL) &
 660                 ~S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1);
 661         u32 hpd2 = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL) &
 662                 ~S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1);
 663         u32 hdmi0;
 664         if (ASIC_IS_DCE2(rdev))
 665                 hdmi0 = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL) &
 666                         ~S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(1);
 667         else
 668                 hdmi0 = 0;
 669
 670         if (!rdev->irq.installed) {
 671                 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
 672                 WREG32(R_000040_GEN_INT_CNTL, 0);
 673                 return -EINVAL;
 674         }
 675         if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
 676                 tmp |= S_000040_SW_INT_EN(1);
 677         }
 678         if (rdev->irq.crtc_vblank_int[0] ||
 679             atomic_read(&rdev->irq.pflip[0])) {
 680                 mode_int |= S_006540_D1MODE_VBLANK_INT_MASK(1);
 681         }
 682         if (rdev->irq.crtc_vblank_int[1] ||
 683             atomic_read(&rdev->irq.pflip[1])) {
 684                 mode_int |= S_006540_D2MODE_VBLANK_INT_MASK(1);
 685         }
 686         if (rdev->irq.hpd[0]) {
 687                 hpd1 |= S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1);
 688         }
 689         if (rdev->irq.hpd[1]) {
 690                 hpd2 |= S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1);
 691         }
 692         if (rdev->irq.afmt[0]) {
 693                 hdmi0 |= S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(1);
 694         }
 695         WREG32(R_000040_GEN_INT_CNTL, tmp);
 696         WREG32(R_006540_DxMODE_INT_MASK, mode_int);
 697         WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1);
 698         WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2);
 699         if (ASIC_IS_DCE2(rdev))
 700                 WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, hdmi0);
 701         return 0;
 702 }
 703
 704 static inline u32 rs600_irq_ack(struct radeon_device *rdev)
 705 {
 706         uint32_t irqs = RREG32(R_000044_GEN_INT_STATUS);
 707         uint32_t irq_mask = S_000044_SW_INT(1);
 708         u32 tmp;
 709
 710         if (G_000044_DISPLAY_INT_STAT(irqs)) {
 711                 rdev->irq.stat_regs.r500.disp_int = RREG32(R_007EDC_DISP_INTERRUPT_STATUS);
 712                 if (G_007EDC_LB_D1_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
 713                         WREG32(R_006534_D1MODE_VBLANK_STATUS,
 714                                 S_006534_D1MODE_VBLANK_ACK(1));
 715                 }
 716                 if (G_007EDC_LB_D2_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
 717                         WREG32(R_006D34_D2MODE_VBLANK_STATUS,
 718                                 S_006D34_D2MODE_VBLANK_ACK(1));
 719                 }
 720                 if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
 721                         tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL);
 722                         tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_ACK(1);
 723                         WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
 724                 }
 725                 if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
 726                         tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL);
 727                         tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_ACK(1);
 728                         WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
 729                 }
 730         } else {
 731                 rdev->irq.stat_regs.r500.disp_int = 0;
 732         }
 733
 734         if (ASIC_IS_DCE2(rdev)) {
 735                 rdev->irq.stat_regs.r500.hdmi0_status = RREG32(R_007404_HDMI0_STATUS) &
 736                         S_007404_HDMI0_AZ_FORMAT_WTRIG(1);
 737                 if (G_007404_HDMI0_AZ_FORMAT_WTRIG(rdev->irq.stat_regs.r500.hdmi0_status)) {
 738                         tmp = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL);
 739                         tmp |= S_007408_HDMI0_AZ_FORMAT_WTRIG_ACK(1);
 740                         WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, tmp);
 741                 }
 742         } else
 743                 rdev->irq.stat_regs.r500.hdmi0_status = 0;
 744
 745         if (irqs) {
 746                 WREG32(R_000044_GEN_INT_STATUS, irqs);
 747         }
 748         return irqs & irq_mask;
 749 }
 750
 751 void rs600_irq_disable(struct radeon_device *rdev)
 752 {
 753         u32 hdmi0 = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL) &
 754                 ~S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(1);
 755         WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, hdmi0);
 756         WREG32(R_000040_GEN_INT_CNTL, 0);
 757         WREG32(R_006540_DxMODE_INT_MASK, 0);
 758         /* Wait and acknowledge irq */
 759         mdelay(1);
 760         rs600_irq_ack(rdev);
 761 }
 762
 763 int rs600_irq_process(struct radeon_device *rdev)
 764 {
 765         u32 status, msi_rearm;
 766         bool queue_hotplug = false;
 767         bool queue_hdmi = false;
 768
 769         status = rs600_irq_ack(rdev);
 770         if (!status &&
 771             !rdev->irq.stat_regs.r500.disp_int &&
 772             !rdev->irq.stat_regs.r500.hdmi0_status) {
 773                 return IRQ_NONE;
 774         }
 775         while (status ||
 776                rdev->irq.stat_regs.r500.disp_int ||
 777                rdev->irq.stat_regs.r500.hdmi0_status) {
 778                 /* SW interrupt */
 779                 if (G_000044_SW_INT(status)) {
 780                         radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
 781                 }
 782                 /* Vertical blank interrupts */
 783                 if (G_007EDC_LB_D1_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
 784                         if (rdev->irq.crtc_vblank_int[0]) {
 785                                 drm_handle_vblank(rdev->ddev, 0);
 786                                 rdev->pm.vblank_sync = true;
 787                                 wake_up(&rdev->irq.vblank_queue);
 788                         }
 789                         if (atomic_read(&rdev->irq.pflip[0]))
 790                                 radeon_crtc_handle_flip(rdev, 0);
 791                 }
 792                 if (G_007EDC_LB_D2_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
 793                         if (rdev->irq.crtc_vblank_int[1]) {
 794                                 drm_handle_vblank(rdev->ddev, 1);
 795                                 rdev->pm.vblank_sync = true;
 796                                 wake_up(&rdev->irq.vblank_queue);
 797                         }
 798                         if (atomic_read(&rdev->irq.pflip[1]))
 799                                 radeon_crtc_handle_flip(rdev, 1);
 800                 }
 801                 if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
 802                         queue_hotplug = true;
 803                         DRM_DEBUG("HPD1\n");
 804                 }
 805                 if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
 806                         queue_hotplug = true;
 807                         DRM_DEBUG("HPD2\n");
 808                 }
 809                 if (G_007404_HDMI0_AZ_FORMAT_WTRIG(rdev->irq.stat_regs.r500.hdmi0_status)) {
 810                         queue_hdmi = true;
 811                         DRM_DEBUG("HDMI0\n");
 812                 }
 813                 status = rs600_irq_ack(rdev);
 814         }
 815         if (queue_hotplug)
 816                 schedule_work(&rdev->hotplug_work);
 817         if (queue_hdmi)
 818                 schedule_work(&rdev->audio_work);
 819         if (rdev->msi_enabled) {
 820                 switch (rdev->family) {
 821                 case CHIP_RS600:
 822                 case CHIP_RS690:
 823                 case CHIP_RS740:
 824                         msi_rearm = RREG32(RADEON_BUS_CNTL) & ~RS600_MSI_REARM;
 825                         WREG32(RADEON_BUS_CNTL, msi_rearm);
 826                         WREG32(RADEON_BUS_CNTL, msi_rearm | RS600_MSI_REARM);
 827                         break;
 828                 default:
 829                         WREG32(RADEON_MSI_REARM_EN, RV370_MSI_REARM_EN);
 830                         break;
 831                 }
 832         }
 833         return IRQ_HANDLED;
 834 }
 835
 836 u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc)
 837 {
 838         if (crtc == 0)
 839                 return RREG32(R_0060A4_D1CRTC_STATUS_FRAME_COUNT);
 840         else
 841                 return RREG32(R_0068A4_D2CRTC_STATUS_FRAME_COUNT);
 842 }
 843
 844 int rs600_mc_wait_for_idle(struct radeon_device *rdev)
 845 {
 846         unsigned i;
 847
 848         for (i = 0; i < rdev->usec_timeout; i++) {
 849                 if (G_000000_MC_IDLE(RREG32_MC(R_000000_MC_STATUS)))
 850                         return 0;
 851                 udelay(1);
 852         }
 853         return -1;
 854 }
 855
 856 static void rs600_gpu_init(struct radeon_device *rdev)
 857 {
 858         r420_pipes_init(rdev);
 859         /* Wait for mc idle */
 860         if (rs600_mc_wait_for_idle(rdev))
 861                 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
 862 }
 863
 864 static void rs600_mc_init(struct radeon_device *rdev)
 865 {
 866         u64 base;
 867
 868         rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
 869         rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
 870         rdev->mc.vram_is_ddr = true;
 871         rdev->mc.vram_width = 128;
 872         rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
 873         rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
 874         rdev->mc.visible_vram_size = rdev->mc.aper_size;
 875         rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
 876         base = RREG32_MC(R_000004_MC_FB_LOCATION);
 877         base = G_000004_MC_FB_START(base) << 16;
 878         radeon_vram_location(rdev, &rdev->mc, base);
 879         rdev->mc.gtt_base_align = 0;
 880         radeon_gtt_location(rdev, &rdev->mc);
 881         radeon_update_bandwidth_info(rdev);
 882 }
 883
 884 void rs600_bandwidth_update(struct radeon_device *rdev)
 885 {
 886         struct drm_display_mode *mode0 = NULL;
 887         struct drm_display_mode *mode1 = NULL;
 888         u32 d1mode_priority_a_cnt, d2mode_priority_a_cnt;
 889         /* FIXME: implement full support */
 890
 891         radeon_update_display_priority(rdev);
 892
 893         if (rdev->mode_info.crtcs[0]->base.enabled)
 894                 mode0 = &rdev->mode_info.crtcs[0]->base.mode;
 895         if (rdev->mode_info.crtcs[1]->base.enabled)
 896                 mode1 = &rdev->mode_info.crtcs[1]->base.mode;
 897
 898         rs690_line_buffer_adjust(rdev, mode0, mode1);
 899
 900         if (rdev->disp_priority == 2) {
 901                 d1mode_priority_a_cnt = RREG32(R_006548_D1MODE_PRIORITY_A_CNT);
 902                 d2mode_priority_a_cnt = RREG32(R_006D48_D2MODE_PRIORITY_A_CNT);
 903                 d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1);
 904                 d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1);
 905                 WREG32(R_006548_D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt);
 906                 WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt);
 907                 WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt);
 908                 WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt);
 909         }
 910 }
 911
 912 uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg)
 913 {
 914         unsigned long flags;
 915         u32 r;
 916
 917         spin_lock_irqsave(&rdev->mc_idx_lock, flags);
 918         WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) |
 919                 S_000070_MC_IND_CITF_ARB0(1));
 920         r = RREG32(R_000074_MC_IND_DATA);
 921         spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
 922         return r;
 923 }
 924
 925 void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
 926 {
 927         unsigned long flags;
 928
 929         spin_lock_irqsave(&rdev->mc_idx_lock, flags);
 930         WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) |
 931                 S_000070_MC_IND_CITF_ARB0(1) | S_000070_MC_IND_WR_EN(1));
 932         WREG32(R_000074_MC_IND_DATA, v);
 933         spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
 934 }
 935
 936 static void rs600_debugfs(struct radeon_device *rdev)
 937 {
 938         if (r100_debugfs_rbbm_init(rdev))
 939                 DRM_ERROR("Failed to register debugfs file for RBBM !\n");
 940 }
 941
 942 void rs600_set_safe_registers(struct radeon_device *rdev)
 943 {
 944         rdev->config.r300.reg_safe_bm = rs600_reg_safe_bm;
 945         rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rs600_reg_safe_bm);
 946 }
 947
 948 static void rs600_mc_program(struct radeon_device *rdev)
 949 {
 950         struct rv515_mc_save save;
 951
 952         /* Stops all mc clients */
 953         rv515_mc_stop(rdev, &save);
 954
 955         /* Wait for mc idle */
 956         if (rs600_mc_wait_for_idle(rdev))
 957                 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
 958
 959         /* FIXME: What does AGP means for such chipset ? */
 960         WREG32_MC(R_000005_MC_AGP_LOCATION, 0x0FFFFFFF);
 961         WREG32_MC(R_000006_AGP_BASE, 0);
 962         WREG32_MC(R_000007_AGP_BASE_2, 0);
 963         /* Program MC */
 964         WREG32_MC(R_000004_MC_FB_LOCATION,
 965                         S_000004_MC_FB_START(rdev->mc.vram_start >> 16) |
 966                         S_000004_MC_FB_TOP(rdev->mc.vram_end >> 16));
 967         WREG32(R_000134_HDP_FB_LOCATION,
 968                 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));
 969
 970         rv515_mc_resume(rdev, &save);
 971 }
 972
 973 static int rs600_startup(struct radeon_device *rdev)
 974 {
 975         int r;
 976
 977         rs600_mc_program(rdev);
 978         /* Resume clock */
 979         rv515_clock_startup(rdev);
 980         /* Initialize GPU configuration (# pipes, ...) */
 981         rs600_gpu_init(rdev);
 982         /* Initialize GART (initialize after TTM so we can allocate
 983          * memory through TTM but finalize after TTM) */
 984         r = rs600_gart_enable(rdev);
 985         if (r)
 986                 return r;
 987
 988         /* allocate wb buffer */
 989         r = radeon_wb_init(rdev);
 990         if (r)
 991                 return r;
 992
 993         r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
 994         if (r) {
 995                 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
 996                 return r;
 997         }
 998
 999         /* Enable IRQ */
1000         if (!rdev->irq.installed) {
1001                 r = radeon_irq_kms_init(rdev);
1002                 if (r)
1003                         return r;
1004         }
1005
1006         rs600_irq_set(rdev);
1007         rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
1008         /* 1M ring buffer */
1009         r = r100_cp_init(rdev, 1024 * 1024);
1010         if (r) {
1011                 dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
1012                 return r;
1013         }
1014
1015         r = radeon_ib_pool_init(rdev);
1016         if (r) {
1017                 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
1018                 return r;
1019         }
1020
1021         r = r600_audio_init(rdev);
1022         if (r) {
1023                 dev_err(rdev->dev, "failed initializing audio\n");
1024                 return r;
1025         }
1026
1027         return 0;
1028 }
1029
1030 int rs600_resume(struct radeon_device *rdev)
1031 {
1032         int r;
1033
1034         /* Make sur GART are not working */
1035         rs600_gart_disable(rdev);
1036         /* Resume clock before doing reset */
1037         rv515_clock_startup(rdev);
1038         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
1039         if (radeon_asic_reset(rdev)) {
1040                 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
1041                         RREG32(R_000E40_RBBM_STATUS),
1042                         RREG32(R_0007C0_CP_STAT));
1043         }
1044         /* post */
1045         atom_asic_init(rdev->mode_info.atom_context);
1046         /* Resume clock after posting */
1047         rv515_clock_startup(rdev);
1048         /* Initialize surface registers */
1049         radeon_surface_init(rdev);
1050
1051         rdev->accel_working = true;
1052         r = rs600_startup(rdev);
1053         if (r) {
1054                 rdev->accel_working = false;
1055         }
1056         return r;
1057 }
1058
1059 int rs600_suspend(struct radeon_device *rdev)
1060 {
1061         radeon_pm_suspend(rdev);
1062         r600_audio_fini(rdev);
1063         r100_cp_disable(rdev);
1064         radeon_wb_disable(rdev);
1065         rs600_irq_disable(rdev);
1066         rs600_gart_disable(rdev);
1067         return 0;
1068 }
1069
1070 void rs600_fini(struct radeon_device *rdev)
1071 {
1072         radeon_pm_fini(rdev);
1073         r600_audio_fini(rdev);
1074         r100_cp_fini(rdev);
1075         radeon_wb_fini(rdev);
1076         radeon_ib_pool_fini(rdev);
1077         radeon_gem_fini(rdev);
1078         rs600_gart_fini(rdev);
1079         radeon_irq_kms_fini(rdev);
1080         radeon_fence_driver_fini(rdev);
1081         radeon_bo_fini(rdev);
1082         radeon_atombios_fini(rdev);
1083         kfree(rdev->bios);
1084         rdev->bios = NULL;
1085 }
1086
1087 int rs600_init(struct radeon_device *rdev)
1088 {
1089         int r;
1090
1091         /* Disable VGA */
1092         rv515_vga_render_disable(rdev);
1093         /* Initialize scratch registers */
1094         radeon_scratch_init(rdev);
1095         /* Initialize surface registers */
1096         radeon_surface_init(rdev);
1097         /* restore some register to sane defaults */
1098         r100_restore_sanity(rdev);
1099         /* BIOS */
1100         if (!radeon_get_bios(rdev)) {
1101                 if (ASIC_IS_AVIVO(rdev))
1102                         return -EINVAL;
1103         }
1104         if (rdev->is_atom_bios) {
1105                 r = radeon_atombios_init(rdev);
1106                 if (r)
1107                         return r;
1108         } else {
1109                 dev_err(rdev->dev, "Expecting atombios for RS600 GPU\n");
1110                 return -EINVAL;
1111         }
1112         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
1113         if (radeon_asic_reset(rdev)) {
1114                 dev_warn(rdev->dev,
1115                         "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
1116                         RREG32(R_000E40_RBBM_STATUS),
1117                         RREG32(R_0007C0_CP_STAT));
1118         }
1119         /* check if cards are posted or not */
1120         if (radeon_boot_test_post_card(rdev) == false)
1121                 return -EINVAL;
1122
1123         /* Initialize clocks */
1124         radeon_get_clock_info(rdev->ddev);
1125         /* initialize memory controller */
1126         rs600_mc_init(rdev);
1127         rs600_debugfs(rdev);
1128         /* Fence driver */
1129         r = radeon_fence_driver_init(rdev);
1130         if (r)
1131                 return r;
1132         /* Memory manager */
1133         r = radeon_bo_init(rdev);
1134         if (r)
1135                 return r;
1136         r = rs600_gart_init(rdev);
1137         if (r)
1138                 return r;
1139         rs600_set_safe_registers(rdev);
1140
1141         /* Initialize power management */
1142         radeon_pm_init(rdev);
1143
1144         rdev->accel_working = true;
1145         r = rs600_startup(rdev);
1146         if (r) {
1147                 /* Somethings want wront with the accel init stop accel */
1148                 dev_err(rdev->dev, "Disabling GPU acceleration\n");
1149                 r100_cp_fini(rdev);
1150                 radeon_wb_fini(rdev);
1151                 radeon_ib_pool_fini(rdev);
1152                 rs600_gart_fini(rdev);
1153                 radeon_irq_kms_fini(rdev);
1154                 rdev->accel_working = false;
1155         }
1156         return 0;
1157 }