2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 /* RS600 / Radeon X1250/X1270 integrated GPU
30 * This file gather function specific to RS600 which is the IGP of
31 * the X1250/X1270 family supporting intel CPU (while RS690/RS740
32 * is the X1250/X1270 supporting AMD CPU). The display engine are
33 * the avivo one, bios is an atombios, 3D block are the one of the
34 * R4XX family. The GART is different from the RS400 one and is very
35 * close to the one of the R600 family (R600 likely being an evolution
36 * of the RS600 GART block).
40 #include "radeon_asic.h"
44 #include "rs600_reg_safe.h"
46 void rs600_gpu_init(struct radeon_device
*rdev
);
47 int rs600_mc_wait_for_idle(struct radeon_device
*rdev
);
49 /* hpd for digital panel detect/disconnect */
50 bool rs600_hpd_sense(struct radeon_device
*rdev
, enum radeon_hpd_id hpd
)
53 bool connected
= false;
57 tmp
= RREG32(R_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS
);
58 if (G_007D04_DC_HOT_PLUG_DETECT1_SENSE(tmp
))
62 tmp
= RREG32(R_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS
);
63 if (G_007D14_DC_HOT_PLUG_DETECT2_SENSE(tmp
))
72 void rs600_hpd_set_polarity(struct radeon_device
*rdev
,
73 enum radeon_hpd_id hpd
)
76 bool connected
= rs600_hpd_sense(rdev
, hpd
);
80 tmp
= RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL
);
82 tmp
&= ~S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1);
84 tmp
|= S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1);
85 WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL
, tmp
);
88 tmp
= RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL
);
90 tmp
&= ~S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1);
92 tmp
|= S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1);
93 WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL
, tmp
);
100 void rs600_hpd_init(struct radeon_device
*rdev
)
102 struct drm_device
*dev
= rdev
->ddev
;
103 struct drm_connector
*connector
;
105 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
106 struct radeon_connector
*radeon_connector
= to_radeon_connector(connector
);
107 switch (radeon_connector
->hpd
.hpd
) {
109 WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL
,
110 S_007D00_DC_HOT_PLUG_DETECT1_EN(1));
111 rdev
->irq
.hpd
[0] = true;
114 WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL
,
115 S_007D10_DC_HOT_PLUG_DETECT2_EN(1));
116 rdev
->irq
.hpd
[1] = true;
122 if (rdev
->irq
.installed
)
126 void rs600_hpd_fini(struct radeon_device
*rdev
)
128 struct drm_device
*dev
= rdev
->ddev
;
129 struct drm_connector
*connector
;
131 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
132 struct radeon_connector
*radeon_connector
= to_radeon_connector(connector
);
133 switch (radeon_connector
->hpd
.hpd
) {
135 WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL
,
136 S_007D00_DC_HOT_PLUG_DETECT1_EN(0));
137 rdev
->irq
.hpd
[0] = false;
140 WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL
,
141 S_007D10_DC_HOT_PLUG_DETECT2_EN(0));
142 rdev
->irq
.hpd
[1] = false;
150 void rs600_bm_disable(struct radeon_device
*rdev
)
154 /* disable bus mastering */
155 pci_read_config_word(rdev
->pdev
, 0x4, (u16
*)&tmp
);
156 pci_write_config_word(rdev
->pdev
, 0x4, tmp
& 0xFFFB);
160 int rs600_asic_reset(struct radeon_device
*rdev
)
164 struct rv515_mc_save save
;
166 /* Stops all mc clients */
167 rv515_mc_stop(rdev
, &save
);
168 status
= RREG32(R_000E40_RBBM_STATUS
);
169 if (!G_000E40_GUI_ACTIVE(status
)) {
172 status
= RREG32(R_000E40_RBBM_STATUS
);
173 dev_info(rdev
->dev
, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__
, __LINE__
, status
);
175 WREG32(RADEON_CP_CSQ_CNTL
, 0);
176 tmp
= RREG32(RADEON_CP_RB_CNTL
);
177 WREG32(RADEON_CP_RB_CNTL
, tmp
| RADEON_RB_RPTR_WR_ENA
);
178 WREG32(RADEON_CP_RB_RPTR_WR
, 0);
179 WREG32(RADEON_CP_RB_WPTR
, 0);
180 WREG32(RADEON_CP_RB_CNTL
, tmp
);
181 pci_save_state(rdev
->pdev
);
182 /* disable bus mastering */
183 rs600_bm_disable(rdev
);
185 WREG32(R_0000F0_RBBM_SOFT_RESET
, S_0000F0_SOFT_RESET_VAP(1) |
186 S_0000F0_SOFT_RESET_GA(1));
187 RREG32(R_0000F0_RBBM_SOFT_RESET
);
189 WREG32(R_0000F0_RBBM_SOFT_RESET
, 0);
191 status
= RREG32(R_000E40_RBBM_STATUS
);
192 dev_info(rdev
->dev
, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__
, __LINE__
, status
);
194 WREG32(R_0000F0_RBBM_SOFT_RESET
, S_0000F0_SOFT_RESET_CP(1));
195 RREG32(R_0000F0_RBBM_SOFT_RESET
);
197 WREG32(R_0000F0_RBBM_SOFT_RESET
, 0);
199 status
= RREG32(R_000E40_RBBM_STATUS
);
200 dev_info(rdev
->dev
, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__
, __LINE__
, status
);
202 WREG32(R_0000F0_RBBM_SOFT_RESET
, S_0000F0_SOFT_RESET_MC(1));
203 RREG32(R_0000F0_RBBM_SOFT_RESET
);
205 WREG32(R_0000F0_RBBM_SOFT_RESET
, 0);
207 status
= RREG32(R_000E40_RBBM_STATUS
);
208 dev_info(rdev
->dev
, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__
, __LINE__
, status
);
209 /* restore PCI & busmastering */
210 pci_restore_state(rdev
->pdev
);
211 /* Check if GPU is idle */
212 if (G_000E40_GA_BUSY(status
) || G_000E40_VAP_BUSY(status
)) {
213 dev_err(rdev
->dev
, "failed to reset GPU\n");
214 rdev
->gpu_lockup
= true;
217 rv515_mc_resume(rdev
, &save
);
218 dev_info(rdev
->dev
, "GPU reset succeed\n");
225 void rs600_gart_tlb_flush(struct radeon_device
*rdev
)
229 tmp
= RREG32_MC(R_000100_MC_PT0_CNTL
);
230 tmp
&= C_000100_INVALIDATE_ALL_L1_TLBS
& C_000100_INVALIDATE_L2_CACHE
;
231 WREG32_MC(R_000100_MC_PT0_CNTL
, tmp
);
233 tmp
= RREG32_MC(R_000100_MC_PT0_CNTL
);
234 tmp
|= S_000100_INVALIDATE_ALL_L1_TLBS(1) | S_000100_INVALIDATE_L2_CACHE(1);
235 WREG32_MC(R_000100_MC_PT0_CNTL
, tmp
);
237 tmp
= RREG32_MC(R_000100_MC_PT0_CNTL
);
238 tmp
&= C_000100_INVALIDATE_ALL_L1_TLBS
& C_000100_INVALIDATE_L2_CACHE
;
239 WREG32_MC(R_000100_MC_PT0_CNTL
, tmp
);
240 tmp
= RREG32_MC(R_000100_MC_PT0_CNTL
);
243 int rs600_gart_init(struct radeon_device
*rdev
)
247 if (rdev
->gart
.table
.vram
.robj
) {
248 WARN(1, "RS600 GART already initialized.\n");
251 /* Initialize common gart structure */
252 r
= radeon_gart_init(rdev
);
256 rdev
->gart
.table_size
= rdev
->gart
.num_gpu_pages
* 8;
257 return radeon_gart_table_vram_alloc(rdev
);
260 int rs600_gart_enable(struct radeon_device
*rdev
)
265 if (rdev
->gart
.table
.vram
.robj
== NULL
) {
266 dev_err(rdev
->dev
, "No VRAM object for PCIE GART.\n");
269 r
= radeon_gart_table_vram_pin(rdev
);
272 radeon_gart_restore(rdev
);
273 /* Enable bus master */
274 tmp
= RREG32(R_00004C_BUS_CNTL
) & C_00004C_BUS_MASTER_DIS
;
275 WREG32(R_00004C_BUS_CNTL
, tmp
);
276 /* FIXME: setup default page */
277 WREG32_MC(R_000100_MC_PT0_CNTL
,
278 (S_000100_EFFECTIVE_L2_CACHE_SIZE(6) |
279 S_000100_EFFECTIVE_L2_QUEUE_SIZE(6)));
281 for (i
= 0; i
< 19; i
++) {
282 WREG32_MC(R_00016C_MC_PT0_CLIENT0_CNTL
+ i
,
283 S_00016C_ENABLE_TRANSLATION_MODE_OVERRIDE(1) |
284 S_00016C_SYSTEM_ACCESS_MODE_MASK(
285 V_00016C_SYSTEM_ACCESS_MODE_NOT_IN_SYS
) |
286 S_00016C_SYSTEM_APERTURE_UNMAPPED_ACCESS(
287 V_00016C_SYSTEM_APERTURE_UNMAPPED_PASSTHROUGH
) |
288 S_00016C_EFFECTIVE_L1_CACHE_SIZE(3) |
289 S_00016C_ENABLE_FRAGMENT_PROCESSING(1) |
290 S_00016C_EFFECTIVE_L1_QUEUE_SIZE(3));
292 /* enable first context */
293 WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL
,
294 S_000102_ENABLE_PAGE_TABLE(1) |
295 S_000102_PAGE_TABLE_DEPTH(V_000102_PAGE_TABLE_FLAT
));
297 /* disable all other contexts */
298 for (i
= 1; i
< 8; i
++)
299 WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL
+ i
, 0);
301 /* setup the page table */
302 WREG32_MC(R_00012C_MC_PT0_CONTEXT0_FLAT_BASE_ADDR
,
303 rdev
->gart
.table_addr
);
304 WREG32_MC(R_00013C_MC_PT0_CONTEXT0_FLAT_START_ADDR
, rdev
->mc
.gtt_start
);
305 WREG32_MC(R_00014C_MC_PT0_CONTEXT0_FLAT_END_ADDR
, rdev
->mc
.gtt_end
);
306 WREG32_MC(R_00011C_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR
, 0);
308 /* System context maps to VRAM space */
309 WREG32_MC(R_000112_MC_PT0_SYSTEM_APERTURE_LOW_ADDR
, rdev
->mc
.vram_start
);
310 WREG32_MC(R_000114_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR
, rdev
->mc
.vram_end
);
312 /* enable page tables */
313 tmp
= RREG32_MC(R_000100_MC_PT0_CNTL
);
314 WREG32_MC(R_000100_MC_PT0_CNTL
, (tmp
| S_000100_ENABLE_PT(1)));
315 tmp
= RREG32_MC(R_000009_MC_CNTL1
);
316 WREG32_MC(R_000009_MC_CNTL1
, (tmp
| S_000009_ENABLE_PAGE_TABLES(1)));
317 rs600_gart_tlb_flush(rdev
);
318 rdev
->gart
.ready
= true;
322 void rs600_gart_disable(struct radeon_device
*rdev
)
327 /* FIXME: disable out of gart access */
328 WREG32_MC(R_000100_MC_PT0_CNTL
, 0);
329 tmp
= RREG32_MC(R_000009_MC_CNTL1
);
330 WREG32_MC(R_000009_MC_CNTL1
, tmp
& C_000009_ENABLE_PAGE_TABLES
);
331 if (rdev
->gart
.table
.vram
.robj
) {
332 r
= radeon_bo_reserve(rdev
->gart
.table
.vram
.robj
, false);
334 radeon_bo_kunmap(rdev
->gart
.table
.vram
.robj
);
335 radeon_bo_unpin(rdev
->gart
.table
.vram
.robj
);
336 radeon_bo_unreserve(rdev
->gart
.table
.vram
.robj
);
341 void rs600_gart_fini(struct radeon_device
*rdev
)
343 radeon_gart_fini(rdev
);
344 rs600_gart_disable(rdev
);
345 radeon_gart_table_vram_free(rdev
);
348 #define R600_PTE_VALID (1 << 0)
349 #define R600_PTE_SYSTEM (1 << 1)
350 #define R600_PTE_SNOOPED (1 << 2)
351 #define R600_PTE_READABLE (1 << 5)
352 #define R600_PTE_WRITEABLE (1 << 6)
354 int rs600_gart_set_page(struct radeon_device
*rdev
, int i
, uint64_t addr
)
356 void __iomem
*ptr
= (void *)rdev
->gart
.table
.vram
.ptr
;
358 if (i
< 0 || i
> rdev
->gart
.num_gpu_pages
) {
361 addr
= addr
& 0xFFFFFFFFFFFFF000ULL
;
362 addr
|= R600_PTE_VALID
| R600_PTE_SYSTEM
| R600_PTE_SNOOPED
;
363 addr
|= R600_PTE_READABLE
| R600_PTE_WRITEABLE
;
364 writeq(addr
, ((void __iomem
*)ptr
) + (i
* 8));
368 int rs600_irq_set(struct radeon_device
*rdev
)
371 uint32_t mode_int
= 0;
372 u32 hpd1
= RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL
) &
373 ~S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1);
374 u32 hpd2
= RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL
) &
375 ~S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1);
377 if (!rdev
->irq
.installed
) {
378 WARN(1, "Can't enable IRQ/MSI because no handler is installed.\n");
379 WREG32(R_000040_GEN_INT_CNTL
, 0);
382 if (rdev
->irq
.sw_int
) {
383 tmp
|= S_000040_SW_INT_EN(1);
385 if (rdev
->irq
.gui_idle
) {
386 tmp
|= S_000040_GUI_IDLE(1);
388 if (rdev
->irq
.crtc_vblank_int
[0]) {
389 mode_int
|= S_006540_D1MODE_VBLANK_INT_MASK(1);
391 if (rdev
->irq
.crtc_vblank_int
[1]) {
392 mode_int
|= S_006540_D2MODE_VBLANK_INT_MASK(1);
394 if (rdev
->irq
.hpd
[0]) {
395 hpd1
|= S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1);
397 if (rdev
->irq
.hpd
[1]) {
398 hpd2
|= S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1);
400 WREG32(R_000040_GEN_INT_CNTL
, tmp
);
401 WREG32(R_006540_DxMODE_INT_MASK
, mode_int
);
402 WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL
, hpd1
);
403 WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL
, hpd2
);
407 static inline uint32_t rs600_irq_ack(struct radeon_device
*rdev
, u32
*r500_disp_int
)
409 uint32_t irqs
= RREG32(R_000044_GEN_INT_STATUS
);
410 uint32_t irq_mask
= S_000044_SW_INT(1);
413 /* the interrupt works, but the status bit is permanently asserted */
414 if (rdev
->irq
.gui_idle
&& radeon_gui_idle(rdev
)) {
415 if (!rdev
->irq
.gui_idle_acked
)
416 irq_mask
|= S_000044_GUI_IDLE_STAT(1);
419 if (G_000044_DISPLAY_INT_STAT(irqs
)) {
420 *r500_disp_int
= RREG32(R_007EDC_DISP_INTERRUPT_STATUS
);
421 if (G_007EDC_LB_D1_VBLANK_INTERRUPT(*r500_disp_int
)) {
422 WREG32(R_006534_D1MODE_VBLANK_STATUS
,
423 S_006534_D1MODE_VBLANK_ACK(1));
425 if (G_007EDC_LB_D2_VBLANK_INTERRUPT(*r500_disp_int
)) {
426 WREG32(R_006D34_D2MODE_VBLANK_STATUS
,
427 S_006D34_D2MODE_VBLANK_ACK(1));
429 if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(*r500_disp_int
)) {
430 tmp
= RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL
);
431 tmp
|= S_007D08_DC_HOT_PLUG_DETECT1_INT_ACK(1);
432 WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL
, tmp
);
434 if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(*r500_disp_int
)) {
435 tmp
= RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL
);
436 tmp
|= S_007D18_DC_HOT_PLUG_DETECT2_INT_ACK(1);
437 WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL
, tmp
);
444 WREG32(R_000044_GEN_INT_STATUS
, irqs
);
446 return irqs
& irq_mask
;
449 void rs600_irq_disable(struct radeon_device
*rdev
)
453 WREG32(R_000040_GEN_INT_CNTL
, 0);
454 WREG32(R_006540_DxMODE_INT_MASK
, 0);
455 /* Wait and acknowledge irq */
457 rs600_irq_ack(rdev
, &tmp
);
460 int rs600_irq_process(struct radeon_device
*rdev
)
462 uint32_t status
, msi_rearm
;
463 uint32_t r500_disp_int
;
464 bool queue_hotplug
= false;
466 /* reset gui idle ack. the status bit is broken */
467 rdev
->irq
.gui_idle_acked
= false;
469 status
= rs600_irq_ack(rdev
, &r500_disp_int
);
470 if (!status
&& !r500_disp_int
) {
473 while (status
|| r500_disp_int
) {
475 if (G_000044_SW_INT(status
))
476 radeon_fence_process(rdev
);
478 if (G_000040_GUI_IDLE(status
)) {
479 rdev
->irq
.gui_idle_acked
= true;
480 rdev
->pm
.gui_idle
= true;
481 wake_up(&rdev
->irq
.idle_queue
);
483 /* Vertical blank interrupts */
484 if (G_007EDC_LB_D1_VBLANK_INTERRUPT(r500_disp_int
)) {
485 drm_handle_vblank(rdev
->ddev
, 0);
486 rdev
->pm
.vblank_sync
= true;
487 wake_up(&rdev
->irq
.vblank_queue
);
489 if (G_007EDC_LB_D2_VBLANK_INTERRUPT(r500_disp_int
)) {
490 drm_handle_vblank(rdev
->ddev
, 1);
491 rdev
->pm
.vblank_sync
= true;
492 wake_up(&rdev
->irq
.vblank_queue
);
494 if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(r500_disp_int
)) {
495 queue_hotplug
= true;
498 if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(r500_disp_int
)) {
499 queue_hotplug
= true;
502 status
= rs600_irq_ack(rdev
, &r500_disp_int
);
504 /* reset gui idle ack. the status bit is broken */
505 rdev
->irq
.gui_idle_acked
= false;
507 queue_work(rdev
->wq
, &rdev
->hotplug_work
);
508 if (rdev
->msi_enabled
) {
509 switch (rdev
->family
) {
513 msi_rearm
= RREG32(RADEON_BUS_CNTL
) & ~RS600_MSI_REARM
;
514 WREG32(RADEON_BUS_CNTL
, msi_rearm
);
515 WREG32(RADEON_BUS_CNTL
, msi_rearm
| RS600_MSI_REARM
);
518 msi_rearm
= RREG32(RADEON_MSI_REARM_EN
) & ~RV370_MSI_REARM_EN
;
519 WREG32(RADEON_MSI_REARM_EN
, msi_rearm
);
520 WREG32(RADEON_MSI_REARM_EN
, msi_rearm
| RV370_MSI_REARM_EN
);
527 u32
rs600_get_vblank_counter(struct radeon_device
*rdev
, int crtc
)
530 return RREG32(R_0060A4_D1CRTC_STATUS_FRAME_COUNT
);
532 return RREG32(R_0068A4_D2CRTC_STATUS_FRAME_COUNT
);
535 int rs600_mc_wait_for_idle(struct radeon_device
*rdev
)
539 for (i
= 0; i
< rdev
->usec_timeout
; i
++) {
540 if (G_000000_MC_IDLE(RREG32_MC(R_000000_MC_STATUS
)))
547 void rs600_gpu_init(struct radeon_device
*rdev
)
549 r420_pipes_init(rdev
);
550 /* Wait for mc idle */
551 if (rs600_mc_wait_for_idle(rdev
))
552 dev_warn(rdev
->dev
, "Wait MC idle timeout before updating MC.\n");
555 void rs600_mc_init(struct radeon_device
*rdev
)
559 rdev
->mc
.aper_base
= drm_get_resource_start(rdev
->ddev
, 0);
560 rdev
->mc
.aper_size
= drm_get_resource_len(rdev
->ddev
, 0);
561 rdev
->mc
.vram_is_ddr
= true;
562 rdev
->mc
.vram_width
= 128;
563 rdev
->mc
.real_vram_size
= RREG32(RADEON_CONFIG_MEMSIZE
);
564 rdev
->mc
.mc_vram_size
= rdev
->mc
.real_vram_size
;
565 rdev
->mc
.visible_vram_size
= rdev
->mc
.aper_size
;
566 rdev
->mc
.igp_sideport_enabled
= radeon_atombios_sideport_present(rdev
);
567 base
= RREG32_MC(R_000004_MC_FB_LOCATION
);
568 base
= G_000004_MC_FB_START(base
) << 16;
569 rdev
->mc
.igp_sideport_enabled
= radeon_atombios_sideport_present(rdev
);
570 radeon_vram_location(rdev
, &rdev
->mc
, base
);
571 radeon_gtt_location(rdev
, &rdev
->mc
);
572 radeon_update_bandwidth_info(rdev
);
575 void rs600_bandwidth_update(struct radeon_device
*rdev
)
577 struct drm_display_mode
*mode0
= NULL
;
578 struct drm_display_mode
*mode1
= NULL
;
579 u32 d1mode_priority_a_cnt
, d2mode_priority_a_cnt
;
580 /* FIXME: implement full support */
582 radeon_update_display_priority(rdev
);
584 if (rdev
->mode_info
.crtcs
[0]->base
.enabled
)
585 mode0
= &rdev
->mode_info
.crtcs
[0]->base
.mode
;
586 if (rdev
->mode_info
.crtcs
[1]->base
.enabled
)
587 mode1
= &rdev
->mode_info
.crtcs
[1]->base
.mode
;
589 rs690_line_buffer_adjust(rdev
, mode0
, mode1
);
591 if (rdev
->disp_priority
== 2) {
592 d1mode_priority_a_cnt
= RREG32(R_006548_D1MODE_PRIORITY_A_CNT
);
593 d2mode_priority_a_cnt
= RREG32(R_006D48_D2MODE_PRIORITY_A_CNT
);
594 d1mode_priority_a_cnt
|= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1);
595 d2mode_priority_a_cnt
|= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1);
596 WREG32(R_006548_D1MODE_PRIORITY_A_CNT
, d1mode_priority_a_cnt
);
597 WREG32(R_00654C_D1MODE_PRIORITY_B_CNT
, d1mode_priority_a_cnt
);
598 WREG32(R_006D48_D2MODE_PRIORITY_A_CNT
, d2mode_priority_a_cnt
);
599 WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT
, d2mode_priority_a_cnt
);
603 uint32_t rs600_mc_rreg(struct radeon_device
*rdev
, uint32_t reg
)
605 WREG32(R_000070_MC_IND_INDEX
, S_000070_MC_IND_ADDR(reg
) |
606 S_000070_MC_IND_CITF_ARB0(1));
607 return RREG32(R_000074_MC_IND_DATA
);
610 void rs600_mc_wreg(struct radeon_device
*rdev
, uint32_t reg
, uint32_t v
)
612 WREG32(R_000070_MC_IND_INDEX
, S_000070_MC_IND_ADDR(reg
) |
613 S_000070_MC_IND_CITF_ARB0(1) | S_000070_MC_IND_WR_EN(1));
614 WREG32(R_000074_MC_IND_DATA
, v
);
617 void rs600_debugfs(struct radeon_device
*rdev
)
619 if (r100_debugfs_rbbm_init(rdev
))
620 DRM_ERROR("Failed to register debugfs file for RBBM !\n");
623 void rs600_set_safe_registers(struct radeon_device
*rdev
)
625 rdev
->config
.r300
.reg_safe_bm
= rs600_reg_safe_bm
;
626 rdev
->config
.r300
.reg_safe_bm_size
= ARRAY_SIZE(rs600_reg_safe_bm
);
629 static void rs600_mc_program(struct radeon_device
*rdev
)
631 struct rv515_mc_save save
;
633 /* Stops all mc clients */
634 rv515_mc_stop(rdev
, &save
);
636 /* Wait for mc idle */
637 if (rs600_mc_wait_for_idle(rdev
))
638 dev_warn(rdev
->dev
, "Wait MC idle timeout before updating MC.\n");
640 /* FIXME: What does AGP means for such chipset ? */
641 WREG32_MC(R_000005_MC_AGP_LOCATION
, 0x0FFFFFFF);
642 WREG32_MC(R_000006_AGP_BASE
, 0);
643 WREG32_MC(R_000007_AGP_BASE_2
, 0);
645 WREG32_MC(R_000004_MC_FB_LOCATION
,
646 S_000004_MC_FB_START(rdev
->mc
.vram_start
>> 16) |
647 S_000004_MC_FB_TOP(rdev
->mc
.vram_end
>> 16));
648 WREG32(R_000134_HDP_FB_LOCATION
,
649 S_000134_HDP_FB_START(rdev
->mc
.vram_start
>> 16));
651 rv515_mc_resume(rdev
, &save
);
654 static int rs600_startup(struct radeon_device
*rdev
)
658 rs600_mc_program(rdev
);
660 rv515_clock_startup(rdev
);
661 /* Initialize GPU configuration (# pipes, ...) */
662 rs600_gpu_init(rdev
);
663 /* Initialize GART (initialize after TTM so we can allocate
664 * memory through TTM but finalize after TTM) */
665 r
= rs600_gart_enable(rdev
);
670 rdev
->config
.r300
.hdp_cntl
= RREG32(RADEON_HOST_PATH_CNTL
);
672 r
= r100_cp_init(rdev
, 1024 * 1024);
674 dev_err(rdev
->dev
, "failled initializing CP (%d).\n", r
);
677 r
= r100_wb_init(rdev
);
679 dev_err(rdev
->dev
, "failled initializing WB (%d).\n", r
);
680 r
= r100_ib_init(rdev
);
682 dev_err(rdev
->dev
, "failled initializing IB (%d).\n", r
);
688 int rs600_resume(struct radeon_device
*rdev
)
690 /* Make sur GART are not working */
691 rs600_gart_disable(rdev
);
692 /* Resume clock before doing reset */
693 rv515_clock_startup(rdev
);
694 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
695 if (radeon_asic_reset(rdev
)) {
696 dev_warn(rdev
->dev
, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
697 RREG32(R_000E40_RBBM_STATUS
),
698 RREG32(R_0007C0_CP_STAT
));
701 atom_asic_init(rdev
->mode_info
.atom_context
);
702 /* Resume clock after posting */
703 rv515_clock_startup(rdev
);
704 /* Initialize surface registers */
705 radeon_surface_init(rdev
);
706 return rs600_startup(rdev
);
709 int rs600_suspend(struct radeon_device
*rdev
)
711 r100_cp_disable(rdev
);
712 r100_wb_disable(rdev
);
713 rs600_irq_disable(rdev
);
714 rs600_gart_disable(rdev
);
718 void rs600_fini(struct radeon_device
*rdev
)
720 radeon_pm_fini(rdev
);
724 radeon_gem_fini(rdev
);
725 rs600_gart_fini(rdev
);
726 radeon_irq_kms_fini(rdev
);
727 radeon_fence_driver_fini(rdev
);
728 radeon_bo_fini(rdev
);
729 radeon_atombios_fini(rdev
);
734 int rs600_init(struct radeon_device
*rdev
)
739 rv515_vga_render_disable(rdev
);
740 /* Initialize scratch registers */
741 radeon_scratch_init(rdev
);
742 /* Initialize surface registers */
743 radeon_surface_init(rdev
);
745 if (!radeon_get_bios(rdev
)) {
746 if (ASIC_IS_AVIVO(rdev
))
749 if (rdev
->is_atom_bios
) {
750 r
= radeon_atombios_init(rdev
);
754 dev_err(rdev
->dev
, "Expecting atombios for RS600 GPU\n");
757 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
758 if (radeon_asic_reset(rdev
)) {
760 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
761 RREG32(R_000E40_RBBM_STATUS
),
762 RREG32(R_0007C0_CP_STAT
));
764 /* check if cards are posted or not */
765 if (radeon_boot_test_post_card(rdev
) == false)
768 /* Initialize clocks */
769 radeon_get_clock_info(rdev
->ddev
);
770 /* Initialize power management */
771 radeon_pm_init(rdev
);
772 /* initialize memory controller */
776 r
= radeon_fence_driver_init(rdev
);
779 r
= radeon_irq_kms_init(rdev
);
783 r
= radeon_bo_init(rdev
);
786 r
= rs600_gart_init(rdev
);
789 rs600_set_safe_registers(rdev
);
790 rdev
->accel_working
= true;
791 r
= rs600_startup(rdev
);
793 /* Somethings want wront with the accel init stop accel */
794 dev_err(rdev
->dev
, "Disabling GPU acceleration\n");
798 rs600_gart_fini(rdev
);
799 radeon_irq_kms_fini(rdev
);
800 rdev
->accel_working
= false;