2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
29 #include "radeon_reg.h"
32 /* rs600 depends on : */
33 void r100_hdp_reset(struct radeon_device
*rdev
);
34 int r100_gui_wait_for_idle(struct radeon_device
*rdev
);
35 int r300_mc_wait_for_idle(struct radeon_device
*rdev
);
36 void r420_pipes_init(struct radeon_device
*rdev
);
38 /* This files gather functions specifics to :
41 * Some of these functions might be used by newer ASICs.
43 void rs600_gpu_init(struct radeon_device
*rdev
);
44 int rs600_mc_wait_for_idle(struct radeon_device
*rdev
);
45 void rs600_disable_vga(struct radeon_device
*rdev
);
51 void rs600_gart_tlb_flush(struct radeon_device
*rdev
)
55 tmp
= RREG32_MC(RS600_MC_PT0_CNTL
);
56 tmp
&= ~(RS600_INVALIDATE_ALL_L1_TLBS
| RS600_INVALIDATE_L2_CACHE
);
57 WREG32_MC(RS600_MC_PT0_CNTL
, tmp
);
59 tmp
= RREG32_MC(RS600_MC_PT0_CNTL
);
60 tmp
|= RS600_INVALIDATE_ALL_L1_TLBS
| RS600_INVALIDATE_L2_CACHE
;
61 WREG32_MC(RS600_MC_PT0_CNTL
, tmp
);
63 tmp
= RREG32_MC(RS600_MC_PT0_CNTL
);
64 tmp
&= ~(RS600_INVALIDATE_ALL_L1_TLBS
| RS600_INVALIDATE_L2_CACHE
);
65 WREG32_MC(RS600_MC_PT0_CNTL
, tmp
);
66 tmp
= RREG32_MC(RS600_MC_PT0_CNTL
);
69 int rs600_gart_enable(struct radeon_device
*rdev
)
75 /* Initialize common gart structure */
76 r
= radeon_gart_init(rdev
);
80 rdev
->gart
.table_size
= rdev
->gart
.num_gpu_pages
* 8;
81 r
= radeon_gart_table_vram_alloc(rdev
);
85 /* FIXME: setup default page */
86 WREG32_MC(RS600_MC_PT0_CNTL
,
87 (RS600_EFFECTIVE_L2_CACHE_SIZE(6) |
88 RS600_EFFECTIVE_L2_QUEUE_SIZE(6)));
89 for (i
= 0; i
< 19; i
++) {
90 WREG32_MC(RS600_MC_PT0_CLIENT0_CNTL
+ i
,
91 (RS600_ENABLE_TRANSLATION_MODE_OVERRIDE
|
92 RS600_SYSTEM_ACCESS_MODE_IN_SYS
|
93 RS600_SYSTEM_APERTURE_UNMAPPED_ACCESS_DEFAULT_PAGE
|
94 RS600_EFFECTIVE_L1_CACHE_SIZE(3) |
95 RS600_ENABLE_FRAGMENT_PROCESSING
|
96 RS600_EFFECTIVE_L1_QUEUE_SIZE(3)));
99 /* System context map to GART space */
100 WREG32_MC(RS600_MC_PT0_SYSTEM_APERTURE_LOW_ADDR
, rdev
->mc
.gtt_location
);
101 tmp
= rdev
->mc
.gtt_location
+ rdev
->mc
.gtt_size
- 1;
102 WREG32_MC(RS600_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR
, tmp
);
104 /* enable first context */
105 WREG32_MC(RS600_MC_PT0_CONTEXT0_FLAT_START_ADDR
, rdev
->mc
.gtt_location
);
106 tmp
= rdev
->mc
.gtt_location
+ rdev
->mc
.gtt_size
- 1;
107 WREG32_MC(RS600_MC_PT0_CONTEXT0_FLAT_END_ADDR
, tmp
);
108 WREG32_MC(RS600_MC_PT0_CONTEXT0_CNTL
,
109 (RS600_ENABLE_PAGE_TABLE
| RS600_PAGE_TABLE_TYPE_FLAT
));
110 /* disable all other contexts */
111 for (i
= 1; i
< 8; i
++) {
112 WREG32_MC(RS600_MC_PT0_CONTEXT0_CNTL
+ i
, 0);
115 /* setup the page table */
116 WREG32_MC(RS600_MC_PT0_CONTEXT0_FLAT_BASE_ADDR
,
117 rdev
->gart
.table_addr
);
118 WREG32_MC(RS600_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR
, 0);
120 /* enable page tables */
121 tmp
= RREG32_MC(RS600_MC_PT0_CNTL
);
122 WREG32_MC(RS600_MC_PT0_CNTL
, (tmp
| RS600_ENABLE_PT
));
123 tmp
= RREG32_MC(RS600_MC_CNTL1
);
124 WREG32_MC(RS600_MC_CNTL1
, (tmp
| RS600_ENABLE_PAGE_TABLES
));
125 rs600_gart_tlb_flush(rdev
);
126 rdev
->gart
.ready
= true;
130 void rs600_gart_disable(struct radeon_device
*rdev
)
134 /* FIXME: disable out of gart access */
135 WREG32_MC(RS600_MC_PT0_CNTL
, 0);
136 tmp
= RREG32_MC(RS600_MC_CNTL1
);
137 tmp
&= ~RS600_ENABLE_PAGE_TABLES
;
138 WREG32_MC(RS600_MC_CNTL1
, tmp
);
139 radeon_object_kunmap(rdev
->gart
.table
.vram
.robj
);
140 radeon_object_unpin(rdev
->gart
.table
.vram
.robj
);
143 #define R600_PTE_VALID (1 << 0)
144 #define R600_PTE_SYSTEM (1 << 1)
145 #define R600_PTE_SNOOPED (1 << 2)
146 #define R600_PTE_READABLE (1 << 5)
147 #define R600_PTE_WRITEABLE (1 << 6)
149 int rs600_gart_set_page(struct radeon_device
*rdev
, int i
, uint64_t addr
)
151 void __iomem
*ptr
= (void *)rdev
->gart
.table
.vram
.ptr
;
153 if (i
< 0 || i
> rdev
->gart
.num_gpu_pages
) {
156 addr
= addr
& 0xFFFFFFFFFFFFF000ULL
;
157 addr
|= R600_PTE_VALID
| R600_PTE_SYSTEM
| R600_PTE_SNOOPED
;
158 addr
|= R600_PTE_READABLE
| R600_PTE_WRITEABLE
;
159 writeq(addr
, ((void __iomem
*)ptr
) + (i
* 8));
167 void rs600_mc_disable_clients(struct radeon_device
*rdev
)
171 if (r100_gui_wait_for_idle(rdev
)) {
172 printk(KERN_WARNING
"Failed to wait GUI idle while "
173 "programming pipes. Bad things might happen.\n");
176 tmp
= RREG32(AVIVO_D1VGA_CONTROL
);
177 WREG32(AVIVO_D1VGA_CONTROL
, tmp
& ~AVIVO_DVGA_CONTROL_MODE_ENABLE
);
178 tmp
= RREG32(AVIVO_D2VGA_CONTROL
);
179 WREG32(AVIVO_D2VGA_CONTROL
, tmp
& ~AVIVO_DVGA_CONTROL_MODE_ENABLE
);
181 tmp
= RREG32(AVIVO_D1CRTC_CONTROL
);
182 WREG32(AVIVO_D1CRTC_CONTROL
, tmp
& ~AVIVO_CRTC_EN
);
183 tmp
= RREG32(AVIVO_D2CRTC_CONTROL
);
184 WREG32(AVIVO_D2CRTC_CONTROL
, tmp
& ~AVIVO_CRTC_EN
);
186 /* make sure all previous write got through */
187 tmp
= RREG32(AVIVO_D2CRTC_CONTROL
);
192 int rs600_mc_init(struct radeon_device
*rdev
)
197 if (r100_debugfs_rbbm_init(rdev
)) {
198 DRM_ERROR("Failed to register debugfs file for RBBM !\n");
201 rs600_gpu_init(rdev
);
202 rs600_gart_disable(rdev
);
204 /* Setup GPU memory space */
205 rdev
->mc
.vram_location
= 0xFFFFFFFFUL
;
206 rdev
->mc
.gtt_location
= 0xFFFFFFFFUL
;
207 r
= radeon_mc_setup(rdev
);
212 /* Program GPU memory space */
213 /* Enable bus master */
214 tmp
= RREG32(RADEON_BUS_CNTL
) & ~RS600_BUS_MASTER_DIS
;
215 WREG32(RADEON_BUS_CNTL
, tmp
);
216 /* FIXME: What does AGP means for such chipset ? */
217 WREG32_MC(RS600_MC_AGP_LOCATION
, 0x0FFFFFFF);
218 /* FIXME: are this AGP reg in indirect MC range ? */
219 WREG32_MC(RS600_MC_AGP_BASE
, 0);
220 WREG32_MC(RS600_MC_AGP_BASE_2
, 0);
221 rs600_mc_disable_clients(rdev
);
222 if (rs600_mc_wait_for_idle(rdev
)) {
223 printk(KERN_WARNING
"Failed to wait MC idle while "
224 "programming pipes. Bad things might happen.\n");
226 tmp
= rdev
->mc
.vram_location
+ rdev
->mc
.mc_vram_size
- 1;
227 tmp
= REG_SET(RS600_MC_FB_TOP
, tmp
>> 16);
228 tmp
|= REG_SET(RS600_MC_FB_START
, rdev
->mc
.vram_location
>> 16);
229 WREG32_MC(RS600_MC_FB_LOCATION
, tmp
);
230 WREG32(RS690_HDP_FB_LOCATION
, rdev
->mc
.vram_location
>> 16);
234 void rs600_mc_fini(struct radeon_device
*rdev
)
236 rs600_gart_disable(rdev
);
237 radeon_gart_table_vram_free(rdev
);
238 radeon_gart_fini(rdev
);
245 int rs600_irq_set(struct radeon_device
*rdev
)
248 uint32_t mode_int
= 0;
250 if (rdev
->irq
.sw_int
) {
251 tmp
|= RADEON_SW_INT_ENABLE
;
253 if (rdev
->irq
.crtc_vblank_int
[0]) {
254 tmp
|= AVIVO_DISPLAY_INT_STATUS
;
255 mode_int
|= AVIVO_D1MODE_INT_MASK
;
257 if (rdev
->irq
.crtc_vblank_int
[1]) {
258 tmp
|= AVIVO_DISPLAY_INT_STATUS
;
259 mode_int
|= AVIVO_D2MODE_INT_MASK
;
261 WREG32(RADEON_GEN_INT_CNTL
, tmp
);
262 WREG32(AVIVO_DxMODE_INT_MASK
, mode_int
);
266 static inline uint32_t rs600_irq_ack(struct radeon_device
*rdev
, u32
*r500_disp_int
)
268 uint32_t irqs
= RREG32(RADEON_GEN_INT_STATUS
);
269 uint32_t irq_mask
= RADEON_SW_INT_TEST
;
271 if (irqs
& AVIVO_DISPLAY_INT_STATUS
) {
272 *r500_disp_int
= RREG32(AVIVO_DISP_INTERRUPT_STATUS
);
273 if (*r500_disp_int
& AVIVO_D1_VBLANK_INTERRUPT
) {
274 WREG32(AVIVO_D1MODE_VBLANK_STATUS
, AVIVO_VBLANK_ACK
);
276 if (*r500_disp_int
& AVIVO_D2_VBLANK_INTERRUPT
) {
277 WREG32(AVIVO_D2MODE_VBLANK_STATUS
, AVIVO_VBLANK_ACK
);
284 WREG32(RADEON_GEN_INT_STATUS
, irqs
);
286 return irqs
& irq_mask
;
289 int rs600_irq_process(struct radeon_device
*rdev
)
292 uint32_t r500_disp_int
;
294 status
= rs600_irq_ack(rdev
, &r500_disp_int
);
295 if (!status
&& !r500_disp_int
) {
298 while (status
|| r500_disp_int
) {
300 if (status
& RADEON_SW_INT_TEST
) {
301 radeon_fence_process(rdev
);
303 /* Vertical blank interrupts */
304 if (r500_disp_int
& AVIVO_D1_VBLANK_INTERRUPT
) {
305 drm_handle_vblank(rdev
->ddev
, 0);
307 if (r500_disp_int
& AVIVO_D2_VBLANK_INTERRUPT
) {
308 drm_handle_vblank(rdev
->ddev
, 1);
310 status
= rs600_irq_ack(rdev
, &r500_disp_int
);
315 u32
rs600_get_vblank_counter(struct radeon_device
*rdev
, int crtc
)
318 return RREG32(AVIVO_D1CRTC_FRAME_COUNT
);
320 return RREG32(AVIVO_D2CRTC_FRAME_COUNT
);
325 * Global GPU functions
327 void rs600_disable_vga(struct radeon_device
*rdev
)
336 WREG32(0x308, (1 << 8));
337 WREG32(0x310, rdev
->mc
.vram_location
);
341 int rs600_mc_wait_for_idle(struct radeon_device
*rdev
)
346 for (i
= 0; i
< rdev
->usec_timeout
; i
++) {
348 tmp
= RREG32_MC(RS600_MC_STATUS
);
349 if (tmp
& RS600_MC_STATUS_IDLE
) {
357 void rs600_errata(struct radeon_device
*rdev
)
359 rdev
->pll_errata
= 0;
362 void rs600_gpu_init(struct radeon_device
*rdev
)
364 /* FIXME: HDP same place on rs600 ? */
365 r100_hdp_reset(rdev
);
366 rs600_disable_vga(rdev
);
367 /* FIXME: is this correct ? */
368 r420_pipes_init(rdev
);
369 if (rs600_mc_wait_for_idle(rdev
)) {
370 printk(KERN_WARNING
"Failed to wait MC idle while "
371 "programming pipes. Bad things might happen.\n");
379 void rs600_vram_info(struct radeon_device
*rdev
)
381 /* FIXME: to do or is these values sane ? */
382 rdev
->mc
.vram_is_ddr
= true;
383 rdev
->mc
.vram_width
= 128;
386 void rs600_bandwidth_update(struct radeon_device
*rdev
)
388 /* FIXME: implement, should this be like rs690 ? */
393 * Indirect registers accessor
395 uint32_t rs600_mc_rreg(struct radeon_device
*rdev
, uint32_t reg
)
399 WREG32(RS600_MC_INDEX
,
400 ((reg
& RS600_MC_ADDR_MASK
) | RS600_MC_IND_CITF_ARB0
));
401 r
= RREG32(RS600_MC_DATA
);
405 void rs600_mc_wreg(struct radeon_device
*rdev
, uint32_t reg
, uint32_t v
)
407 WREG32(RS600_MC_INDEX
,
408 RS600_MC_IND_WR_EN
| RS600_MC_IND_CITF_ARB0
|
409 ((reg
) & RS600_MC_ADDR_MASK
));
410 WREG32(RS600_MC_DATA
, v
);