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drm/radeon/kms: fix up rs780/rs880 display watermark calc for dpm
[deliverable/linux.git] / drivers / gpu / drm / radeon / rs690.c
1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28 #include <drm/drmP.h>
29 #include "radeon.h"
30 #include "radeon_asic.h"
31 #include "atom.h"
32 #include "rs690d.h"
33
34 int rs690_mc_wait_for_idle(struct radeon_device *rdev)
35 {
36 unsigned i;
37 uint32_t tmp;
38
39 for (i = 0; i < rdev->usec_timeout; i++) {
40 /* read MC_STATUS */
41 tmp = RREG32_MC(R_000090_MC_SYSTEM_STATUS);
42 if (G_000090_MC_SYSTEM_IDLE(tmp))
43 return 0;
44 udelay(1);
45 }
46 return -1;
47 }
48
49 static void rs690_gpu_init(struct radeon_device *rdev)
50 {
51 /* FIXME: is this correct ? */
52 r420_pipes_init(rdev);
53 if (rs690_mc_wait_for_idle(rdev)) {
54 printk(KERN_WARNING "Failed to wait MC idle while "
55 "programming pipes. Bad things might happen.\n");
56 }
57 }
58
59 union igp_info {
60 struct _ATOM_INTEGRATED_SYSTEM_INFO info;
61 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_v2;
62 };
63
64 void rs690_pm_info(struct radeon_device *rdev)
65 {
66 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
67 union igp_info *info;
68 uint16_t data_offset;
69 uint8_t frev, crev;
70 fixed20_12 tmp;
71
72 if (atom_parse_data_header(rdev->mode_info.atom_context, index, NULL,
73 &frev, &crev, &data_offset)) {
74 info = (union igp_info *)(rdev->mode_info.atom_context->bios + data_offset);
75
76 /* Get various system informations from bios */
77 switch (crev) {
78 case 1:
79 tmp.full = dfixed_const(100);
80 rdev->pm.igp_sideport_mclk.full = dfixed_const(le32_to_cpu(info->info.ulBootUpMemoryClock));
81 rdev->pm.igp_sideport_mclk.full = dfixed_div(rdev->pm.igp_sideport_mclk, tmp);
82 if (le16_to_cpu(info->info.usK8MemoryClock))
83 rdev->pm.igp_system_mclk.full = dfixed_const(le16_to_cpu(info->info.usK8MemoryClock));
84 else if (rdev->clock.default_mclk) {
85 rdev->pm.igp_system_mclk.full = dfixed_const(rdev->clock.default_mclk);
86 rdev->pm.igp_system_mclk.full = dfixed_div(rdev->pm.igp_system_mclk, tmp);
87 } else
88 rdev->pm.igp_system_mclk.full = dfixed_const(400);
89 rdev->pm.igp_ht_link_clk.full = dfixed_const(le16_to_cpu(info->info.usFSBClock));
90 rdev->pm.igp_ht_link_width.full = dfixed_const(info->info.ucHTLinkWidth);
91 break;
92 case 2:
93 tmp.full = dfixed_const(100);
94 rdev->pm.igp_sideport_mclk.full = dfixed_const(le32_to_cpu(info->info_v2.ulBootUpSidePortClock));
95 rdev->pm.igp_sideport_mclk.full = dfixed_div(rdev->pm.igp_sideport_mclk, tmp);
96 if (le32_to_cpu(info->info_v2.ulBootUpUMAClock))
97 rdev->pm.igp_system_mclk.full = dfixed_const(le32_to_cpu(info->info_v2.ulBootUpUMAClock));
98 else if (rdev->clock.default_mclk)
99 rdev->pm.igp_system_mclk.full = dfixed_const(rdev->clock.default_mclk);
100 else
101 rdev->pm.igp_system_mclk.full = dfixed_const(66700);
102 rdev->pm.igp_system_mclk.full = dfixed_div(rdev->pm.igp_system_mclk, tmp);
103 rdev->pm.igp_ht_link_clk.full = dfixed_const(le32_to_cpu(info->info_v2.ulHTLinkFreq));
104 rdev->pm.igp_ht_link_clk.full = dfixed_div(rdev->pm.igp_ht_link_clk, tmp);
105 rdev->pm.igp_ht_link_width.full = dfixed_const(le16_to_cpu(info->info_v2.usMinHTLinkWidth));
106 break;
107 default:
108 /* We assume the slower possible clock ie worst case */
109 rdev->pm.igp_sideport_mclk.full = dfixed_const(200);
110 rdev->pm.igp_system_mclk.full = dfixed_const(200);
111 rdev->pm.igp_ht_link_clk.full = dfixed_const(1000);
112 rdev->pm.igp_ht_link_width.full = dfixed_const(8);
113 DRM_ERROR("No integrated system info for your GPU, using safe default\n");
114 break;
115 }
116 } else {
117 /* We assume the slower possible clock ie worst case */
118 rdev->pm.igp_sideport_mclk.full = dfixed_const(200);
119 rdev->pm.igp_system_mclk.full = dfixed_const(200);
120 rdev->pm.igp_ht_link_clk.full = dfixed_const(1000);
121 rdev->pm.igp_ht_link_width.full = dfixed_const(8);
122 DRM_ERROR("No integrated system info for your GPU, using safe default\n");
123 }
124 /* Compute various bandwidth */
125 /* k8_bandwidth = (memory_clk / 2) * 2 * 8 * 0.5 = memory_clk * 4 */
126 tmp.full = dfixed_const(4);
127 rdev->pm.k8_bandwidth.full = dfixed_mul(rdev->pm.igp_system_mclk, tmp);
128 /* ht_bandwidth = ht_clk * 2 * ht_width / 8 * 0.8
129 * = ht_clk * ht_width / 5
130 */
131 tmp.full = dfixed_const(5);
132 rdev->pm.ht_bandwidth.full = dfixed_mul(rdev->pm.igp_ht_link_clk,
133 rdev->pm.igp_ht_link_width);
134 rdev->pm.ht_bandwidth.full = dfixed_div(rdev->pm.ht_bandwidth, tmp);
135 if (tmp.full < rdev->pm.max_bandwidth.full) {
136 /* HT link is a limiting factor */
137 rdev->pm.max_bandwidth.full = tmp.full;
138 }
139 /* sideport_bandwidth = (sideport_clk / 2) * 2 * 2 * 0.7
140 * = (sideport_clk * 14) / 10
141 */
142 tmp.full = dfixed_const(14);
143 rdev->pm.sideport_bandwidth.full = dfixed_mul(rdev->pm.igp_sideport_mclk, tmp);
144 tmp.full = dfixed_const(10);
145 rdev->pm.sideport_bandwidth.full = dfixed_div(rdev->pm.sideport_bandwidth, tmp);
146 }
147
148 static void rs690_mc_init(struct radeon_device *rdev)
149 {
150 u64 base;
151 uint32_t h_addr, l_addr;
152 unsigned long long k8_addr;
153
154 rs400_gart_adjust_size(rdev);
155 rdev->mc.vram_is_ddr = true;
156 rdev->mc.vram_width = 128;
157 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
158 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
159 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
160 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
161 rdev->mc.visible_vram_size = rdev->mc.aper_size;
162 base = RREG32_MC(R_000100_MCCFG_FB_LOCATION);
163 base = G_000100_MC_FB_START(base) << 16;
164 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
165
166 /* Use K8 direct mapping for fast fb access. */
167 rdev->fastfb_working = false;
168 h_addr = G_00005F_K8_ADDR_EXT(RREG32_MC(R_00005F_MC_MISC_UMA_CNTL));
169 l_addr = RREG32_MC(R_00001E_K8_FB_LOCATION);
170 k8_addr = ((unsigned long long)h_addr) << 32 | l_addr;
171 #if defined(CONFIG_X86_32) && !defined(CONFIG_X86_PAE)
172 if (k8_addr + rdev->mc.visible_vram_size < 0x100000000ULL)
173 #endif
174 {
175 /* FastFB shall be used with UMA memory. Here it is simply disabled when sideport
176 * memory is present.
177 */
178 if (rdev->mc.igp_sideport_enabled == false && radeon_fastfb == 1) {
179 DRM_INFO("Direct mapping: aper base at 0x%llx, replaced by direct mapping base 0x%llx.\n",
180 (unsigned long long)rdev->mc.aper_base, k8_addr);
181 rdev->mc.aper_base = (resource_size_t)k8_addr;
182 rdev->fastfb_working = true;
183 }
184 }
185
186 rs690_pm_info(rdev);
187 radeon_vram_location(rdev, &rdev->mc, base);
188 rdev->mc.gtt_base_align = rdev->mc.gtt_size - 1;
189 radeon_gtt_location(rdev, &rdev->mc);
190 radeon_update_bandwidth_info(rdev);
191 }
192
193 void rs690_line_buffer_adjust(struct radeon_device *rdev,
194 struct drm_display_mode *mode1,
195 struct drm_display_mode *mode2)
196 {
197 u32 tmp;
198
199 /*
200 * Line Buffer Setup
201 * There is a single line buffer shared by both display controllers.
202 * R_006520_DC_LB_MEMORY_SPLIT controls how that line buffer is shared between
203 * the display controllers. The paritioning can either be done
204 * manually or via one of four preset allocations specified in bits 1:0:
205 * 0 - line buffer is divided in half and shared between crtc
206 * 1 - D1 gets 3/4 of the line buffer, D2 gets 1/4
207 * 2 - D1 gets the whole buffer
208 * 3 - D1 gets 1/4 of the line buffer, D2 gets 3/4
209 * Setting bit 2 of R_006520_DC_LB_MEMORY_SPLIT controls switches to manual
210 * allocation mode. In manual allocation mode, D1 always starts at 0,
211 * D1 end/2 is specified in bits 14:4; D2 allocation follows D1.
212 */
213 tmp = RREG32(R_006520_DC_LB_MEMORY_SPLIT) & C_006520_DC_LB_MEMORY_SPLIT;
214 tmp &= ~C_006520_DC_LB_MEMORY_SPLIT_MODE;
215 /* auto */
216 if (mode1 && mode2) {
217 if (mode1->hdisplay > mode2->hdisplay) {
218 if (mode1->hdisplay > 2560)
219 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_3Q_D2_1Q;
220 else
221 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF;
222 } else if (mode2->hdisplay > mode1->hdisplay) {
223 if (mode2->hdisplay > 2560)
224 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q;
225 else
226 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF;
227 } else
228 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF;
229 } else if (mode1) {
230 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_ONLY;
231 } else if (mode2) {
232 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q;
233 }
234 WREG32(R_006520_DC_LB_MEMORY_SPLIT, tmp);
235 }
236
237 struct rs690_watermark {
238 u32 lb_request_fifo_depth;
239 fixed20_12 num_line_pair;
240 fixed20_12 estimated_width;
241 fixed20_12 worst_case_latency;
242 fixed20_12 consumption_rate;
243 fixed20_12 active_time;
244 fixed20_12 dbpp;
245 fixed20_12 priority_mark_max;
246 fixed20_12 priority_mark;
247 fixed20_12 sclk;
248 };
249
250 static void rs690_crtc_bandwidth_compute(struct radeon_device *rdev,
251 struct radeon_crtc *crtc,
252 struct rs690_watermark *wm,
253 bool low)
254 {
255 struct drm_display_mode *mode = &crtc->base.mode;
256 fixed20_12 a, b, c;
257 fixed20_12 pclk, request_fifo_depth, tolerable_latency, estimated_width;
258 fixed20_12 consumption_time, line_time, chunk_time, read_delay_latency;
259 fixed20_12 sclk, core_bandwidth, max_bandwidth;
260 u32 selected_sclk;
261
262 if (!crtc->base.enabled) {
263 /* FIXME: wouldn't it better to set priority mark to maximum */
264 wm->lb_request_fifo_depth = 4;
265 return;
266 }
267
268 if (((rdev->family == CHIP_RS780) || (rdev->family == CHIP_RS880)) &&
269 (rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled)
270 selected_sclk = radeon_dpm_get_sclk(rdev, low);
271 else
272 selected_sclk = rdev->pm.current_sclk;
273
274 /* sclk in Mhz */
275 a.full = dfixed_const(100);
276 sclk.full = dfixed_const(selected_sclk);
277 sclk.full = dfixed_div(sclk, a);
278
279 /* core_bandwidth = sclk(Mhz) * 16 */
280 a.full = dfixed_const(16);
281 core_bandwidth.full = dfixed_div(rdev->pm.sclk, a);
282
283 if (crtc->vsc.full > dfixed_const(2))
284 wm->num_line_pair.full = dfixed_const(2);
285 else
286 wm->num_line_pair.full = dfixed_const(1);
287
288 b.full = dfixed_const(mode->crtc_hdisplay);
289 c.full = dfixed_const(256);
290 a.full = dfixed_div(b, c);
291 request_fifo_depth.full = dfixed_mul(a, wm->num_line_pair);
292 request_fifo_depth.full = dfixed_ceil(request_fifo_depth);
293 if (a.full < dfixed_const(4)) {
294 wm->lb_request_fifo_depth = 4;
295 } else {
296 wm->lb_request_fifo_depth = dfixed_trunc(request_fifo_depth);
297 }
298
299 /* Determine consumption rate
300 * pclk = pixel clock period(ns) = 1000 / (mode.clock / 1000)
301 * vtaps = number of vertical taps,
302 * vsc = vertical scaling ratio, defined as source/destination
303 * hsc = horizontal scaling ration, defined as source/destination
304 */
305 a.full = dfixed_const(mode->clock);
306 b.full = dfixed_const(1000);
307 a.full = dfixed_div(a, b);
308 pclk.full = dfixed_div(b, a);
309 if (crtc->rmx_type != RMX_OFF) {
310 b.full = dfixed_const(2);
311 if (crtc->vsc.full > b.full)
312 b.full = crtc->vsc.full;
313 b.full = dfixed_mul(b, crtc->hsc);
314 c.full = dfixed_const(2);
315 b.full = dfixed_div(b, c);
316 consumption_time.full = dfixed_div(pclk, b);
317 } else {
318 consumption_time.full = pclk.full;
319 }
320 a.full = dfixed_const(1);
321 wm->consumption_rate.full = dfixed_div(a, consumption_time);
322
323
324 /* Determine line time
325 * LineTime = total time for one line of displayhtotal
326 * LineTime = total number of horizontal pixels
327 * pclk = pixel clock period(ns)
328 */
329 a.full = dfixed_const(crtc->base.mode.crtc_htotal);
330 line_time.full = dfixed_mul(a, pclk);
331
332 /* Determine active time
333 * ActiveTime = time of active region of display within one line,
334 * hactive = total number of horizontal active pixels
335 * htotal = total number of horizontal pixels
336 */
337 a.full = dfixed_const(crtc->base.mode.crtc_htotal);
338 b.full = dfixed_const(crtc->base.mode.crtc_hdisplay);
339 wm->active_time.full = dfixed_mul(line_time, b);
340 wm->active_time.full = dfixed_div(wm->active_time, a);
341
342 /* Maximun bandwidth is the minimun bandwidth of all component */
343 max_bandwidth = core_bandwidth;
344 if (rdev->mc.igp_sideport_enabled) {
345 if (max_bandwidth.full > rdev->pm.sideport_bandwidth.full &&
346 rdev->pm.sideport_bandwidth.full)
347 max_bandwidth = rdev->pm.sideport_bandwidth;
348 read_delay_latency.full = dfixed_const(370 * 800 * 1000);
349 read_delay_latency.full = dfixed_div(read_delay_latency,
350 rdev->pm.igp_sideport_mclk);
351 } else {
352 if (max_bandwidth.full > rdev->pm.k8_bandwidth.full &&
353 rdev->pm.k8_bandwidth.full)
354 max_bandwidth = rdev->pm.k8_bandwidth;
355 if (max_bandwidth.full > rdev->pm.ht_bandwidth.full &&
356 rdev->pm.ht_bandwidth.full)
357 max_bandwidth = rdev->pm.ht_bandwidth;
358 read_delay_latency.full = dfixed_const(5000);
359 }
360
361 /* sclk = system clocks(ns) = 1000 / max_bandwidth / 16 */
362 a.full = dfixed_const(16);
363 sclk.full = dfixed_mul(max_bandwidth, a);
364 a.full = dfixed_const(1000);
365 sclk.full = dfixed_div(a, sclk);
366 /* Determine chunk time
367 * ChunkTime = the time it takes the DCP to send one chunk of data
368 * to the LB which consists of pipeline delay and inter chunk gap
369 * sclk = system clock(ns)
370 */
371 a.full = dfixed_const(256 * 13);
372 chunk_time.full = dfixed_mul(sclk, a);
373 a.full = dfixed_const(10);
374 chunk_time.full = dfixed_div(chunk_time, a);
375
376 /* Determine the worst case latency
377 * NumLinePair = Number of line pairs to request(1=2 lines, 2=4 lines)
378 * WorstCaseLatency = worst case time from urgent to when the MC starts
379 * to return data
380 * READ_DELAY_IDLE_MAX = constant of 1us
381 * ChunkTime = time it takes the DCP to send one chunk of data to the LB
382 * which consists of pipeline delay and inter chunk gap
383 */
384 if (dfixed_trunc(wm->num_line_pair) > 1) {
385 a.full = dfixed_const(3);
386 wm->worst_case_latency.full = dfixed_mul(a, chunk_time);
387 wm->worst_case_latency.full += read_delay_latency.full;
388 } else {
389 a.full = dfixed_const(2);
390 wm->worst_case_latency.full = dfixed_mul(a, chunk_time);
391 wm->worst_case_latency.full += read_delay_latency.full;
392 }
393
394 /* Determine the tolerable latency
395 * TolerableLatency = Any given request has only 1 line time
396 * for the data to be returned
397 * LBRequestFifoDepth = Number of chunk requests the LB can
398 * put into the request FIFO for a display
399 * LineTime = total time for one line of display
400 * ChunkTime = the time it takes the DCP to send one chunk
401 * of data to the LB which consists of
402 * pipeline delay and inter chunk gap
403 */
404 if ((2+wm->lb_request_fifo_depth) >= dfixed_trunc(request_fifo_depth)) {
405 tolerable_latency.full = line_time.full;
406 } else {
407 tolerable_latency.full = dfixed_const(wm->lb_request_fifo_depth - 2);
408 tolerable_latency.full = request_fifo_depth.full - tolerable_latency.full;
409 tolerable_latency.full = dfixed_mul(tolerable_latency, chunk_time);
410 tolerable_latency.full = line_time.full - tolerable_latency.full;
411 }
412 /* We assume worst case 32bits (4 bytes) */
413 wm->dbpp.full = dfixed_const(4 * 8);
414
415 /* Determine the maximum priority mark
416 * width = viewport width in pixels
417 */
418 a.full = dfixed_const(16);
419 wm->priority_mark_max.full = dfixed_const(crtc->base.mode.crtc_hdisplay);
420 wm->priority_mark_max.full = dfixed_div(wm->priority_mark_max, a);
421 wm->priority_mark_max.full = dfixed_ceil(wm->priority_mark_max);
422
423 /* Determine estimated width */
424 estimated_width.full = tolerable_latency.full - wm->worst_case_latency.full;
425 estimated_width.full = dfixed_div(estimated_width, consumption_time);
426 if (dfixed_trunc(estimated_width) > crtc->base.mode.crtc_hdisplay) {
427 wm->priority_mark.full = dfixed_const(10);
428 } else {
429 a.full = dfixed_const(16);
430 wm->priority_mark.full = dfixed_div(estimated_width, a);
431 wm->priority_mark.full = dfixed_ceil(wm->priority_mark);
432 wm->priority_mark.full = wm->priority_mark_max.full - wm->priority_mark.full;
433 }
434 }
435
436 static void rs690_compute_mode_priority(struct radeon_device *rdev,
437 struct rs690_watermark *wm0,
438 struct rs690_watermark *wm1,
439 struct drm_display_mode *mode0,
440 struct drm_display_mode *mode1,
441 u32 *d1mode_priority_a_cnt,
442 u32 *d2mode_priority_a_cnt)
443 {
444 fixed20_12 priority_mark02, priority_mark12, fill_rate;
445 fixed20_12 a, b;
446
447 *d1mode_priority_a_cnt = S_006548_D1MODE_PRIORITY_A_OFF(1);
448 *d2mode_priority_a_cnt = S_006548_D1MODE_PRIORITY_A_OFF(1);
449
450 if (mode0 && mode1) {
451 if (dfixed_trunc(wm0->dbpp) > 64)
452 a.full = dfixed_mul(wm0->dbpp, wm0->num_line_pair);
453 else
454 a.full = wm0->num_line_pair.full;
455 if (dfixed_trunc(wm1->dbpp) > 64)
456 b.full = dfixed_mul(wm1->dbpp, wm1->num_line_pair);
457 else
458 b.full = wm1->num_line_pair.full;
459 a.full += b.full;
460 fill_rate.full = dfixed_div(wm0->sclk, a);
461 if (wm0->consumption_rate.full > fill_rate.full) {
462 b.full = wm0->consumption_rate.full - fill_rate.full;
463 b.full = dfixed_mul(b, wm0->active_time);
464 a.full = dfixed_mul(wm0->worst_case_latency,
465 wm0->consumption_rate);
466 a.full = a.full + b.full;
467 b.full = dfixed_const(16 * 1000);
468 priority_mark02.full = dfixed_div(a, b);
469 } else {
470 a.full = dfixed_mul(wm0->worst_case_latency,
471 wm0->consumption_rate);
472 b.full = dfixed_const(16 * 1000);
473 priority_mark02.full = dfixed_div(a, b);
474 }
475 if (wm1->consumption_rate.full > fill_rate.full) {
476 b.full = wm1->consumption_rate.full - fill_rate.full;
477 b.full = dfixed_mul(b, wm1->active_time);
478 a.full = dfixed_mul(wm1->worst_case_latency,
479 wm1->consumption_rate);
480 a.full = a.full + b.full;
481 b.full = dfixed_const(16 * 1000);
482 priority_mark12.full = dfixed_div(a, b);
483 } else {
484 a.full = dfixed_mul(wm1->worst_case_latency,
485 wm1->consumption_rate);
486 b.full = dfixed_const(16 * 1000);
487 priority_mark12.full = dfixed_div(a, b);
488 }
489 if (wm0->priority_mark.full > priority_mark02.full)
490 priority_mark02.full = wm0->priority_mark.full;
491 if (dfixed_trunc(priority_mark02) < 0)
492 priority_mark02.full = 0;
493 if (wm0->priority_mark_max.full > priority_mark02.full)
494 priority_mark02.full = wm0->priority_mark_max.full;
495 if (wm1->priority_mark.full > priority_mark12.full)
496 priority_mark12.full = wm1->priority_mark.full;
497 if (dfixed_trunc(priority_mark12) < 0)
498 priority_mark12.full = 0;
499 if (wm1->priority_mark_max.full > priority_mark12.full)
500 priority_mark12.full = wm1->priority_mark_max.full;
501 *d1mode_priority_a_cnt = dfixed_trunc(priority_mark02);
502 *d2mode_priority_a_cnt = dfixed_trunc(priority_mark12);
503 if (rdev->disp_priority == 2) {
504 *d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1);
505 *d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1);
506 }
507 } else if (mode0) {
508 if (dfixed_trunc(wm0->dbpp) > 64)
509 a.full = dfixed_mul(wm0->dbpp, wm0->num_line_pair);
510 else
511 a.full = wm0->num_line_pair.full;
512 fill_rate.full = dfixed_div(wm0->sclk, a);
513 if (wm0->consumption_rate.full > fill_rate.full) {
514 b.full = wm0->consumption_rate.full - fill_rate.full;
515 b.full = dfixed_mul(b, wm0->active_time);
516 a.full = dfixed_mul(wm0->worst_case_latency,
517 wm0->consumption_rate);
518 a.full = a.full + b.full;
519 b.full = dfixed_const(16 * 1000);
520 priority_mark02.full = dfixed_div(a, b);
521 } else {
522 a.full = dfixed_mul(wm0->worst_case_latency,
523 wm0->consumption_rate);
524 b.full = dfixed_const(16 * 1000);
525 priority_mark02.full = dfixed_div(a, b);
526 }
527 if (wm0->priority_mark.full > priority_mark02.full)
528 priority_mark02.full = wm0->priority_mark.full;
529 if (dfixed_trunc(priority_mark02) < 0)
530 priority_mark02.full = 0;
531 if (wm0->priority_mark_max.full > priority_mark02.full)
532 priority_mark02.full = wm0->priority_mark_max.full;
533 *d1mode_priority_a_cnt = dfixed_trunc(priority_mark02);
534 if (rdev->disp_priority == 2)
535 *d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1);
536 } else if (mode1) {
537 if (dfixed_trunc(wm1->dbpp) > 64)
538 a.full = dfixed_mul(wm1->dbpp, wm1->num_line_pair);
539 else
540 a.full = wm1->num_line_pair.full;
541 fill_rate.full = dfixed_div(wm1->sclk, a);
542 if (wm1->consumption_rate.full > fill_rate.full) {
543 b.full = wm1->consumption_rate.full - fill_rate.full;
544 b.full = dfixed_mul(b, wm1->active_time);
545 a.full = dfixed_mul(wm1->worst_case_latency,
546 wm1->consumption_rate);
547 a.full = a.full + b.full;
548 b.full = dfixed_const(16 * 1000);
549 priority_mark12.full = dfixed_div(a, b);
550 } else {
551 a.full = dfixed_mul(wm1->worst_case_latency,
552 wm1->consumption_rate);
553 b.full = dfixed_const(16 * 1000);
554 priority_mark12.full = dfixed_div(a, b);
555 }
556 if (wm1->priority_mark.full > priority_mark12.full)
557 priority_mark12.full = wm1->priority_mark.full;
558 if (dfixed_trunc(priority_mark12) < 0)
559 priority_mark12.full = 0;
560 if (wm1->priority_mark_max.full > priority_mark12.full)
561 priority_mark12.full = wm1->priority_mark_max.full;
562 *d2mode_priority_a_cnt = dfixed_trunc(priority_mark12);
563 if (rdev->disp_priority == 2)
564 *d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1);
565 }
566 }
567
568 void rs690_bandwidth_update(struct radeon_device *rdev)
569 {
570 struct drm_display_mode *mode0 = NULL;
571 struct drm_display_mode *mode1 = NULL;
572 struct rs690_watermark wm0_high, wm0_low;
573 struct rs690_watermark wm1_high, wm1_low;
574 u32 tmp;
575 u32 d1mode_priority_a_cnt, d1mode_priority_b_cnt;
576 u32 d2mode_priority_a_cnt, d2mode_priority_b_cnt;
577
578 radeon_update_display_priority(rdev);
579
580 if (rdev->mode_info.crtcs[0]->base.enabled)
581 mode0 = &rdev->mode_info.crtcs[0]->base.mode;
582 if (rdev->mode_info.crtcs[1]->base.enabled)
583 mode1 = &rdev->mode_info.crtcs[1]->base.mode;
584 /*
585 * Set display0/1 priority up in the memory controller for
586 * modes if the user specifies HIGH for displaypriority
587 * option.
588 */
589 if ((rdev->disp_priority == 2) &&
590 ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740))) {
591 tmp = RREG32_MC(R_000104_MC_INIT_MISC_LAT_TIMER);
592 tmp &= C_000104_MC_DISP0R_INIT_LAT;
593 tmp &= C_000104_MC_DISP1R_INIT_LAT;
594 if (mode0)
595 tmp |= S_000104_MC_DISP0R_INIT_LAT(1);
596 if (mode1)
597 tmp |= S_000104_MC_DISP1R_INIT_LAT(1);
598 WREG32_MC(R_000104_MC_INIT_MISC_LAT_TIMER, tmp);
599 }
600 rs690_line_buffer_adjust(rdev, mode0, mode1);
601
602 if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740))
603 WREG32(R_006C9C_DCP_CONTROL, 0);
604 if ((rdev->family == CHIP_RS780) || (rdev->family == CHIP_RS880))
605 WREG32(R_006C9C_DCP_CONTROL, 2);
606
607 rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0_high, false);
608 rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1_high, false);
609
610 rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0_low, true);
611 rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1_low, true);
612
613 tmp = (wm0_high.lb_request_fifo_depth - 1);
614 tmp |= (wm1_high.lb_request_fifo_depth - 1) << 16;
615 WREG32(R_006D58_LB_MAX_REQ_OUTSTANDING, tmp);
616
617 rs690_compute_mode_priority(rdev,
618 &wm0_high, &wm1_high,
619 mode0, mode1,
620 &d1mode_priority_a_cnt, &d2mode_priority_a_cnt);
621 rs690_compute_mode_priority(rdev,
622 &wm0_low, &wm1_low,
623 mode0, mode1,
624 &d1mode_priority_b_cnt, &d2mode_priority_b_cnt);
625
626 WREG32(R_006548_D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt);
627 WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, d1mode_priority_b_cnt);
628 WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt);
629 WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, d2mode_priority_b_cnt);
630 }
631
632 uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg)
633 {
634 uint32_t r;
635
636 WREG32(R_000078_MC_INDEX, S_000078_MC_IND_ADDR(reg));
637 r = RREG32(R_00007C_MC_DATA);
638 WREG32(R_000078_MC_INDEX, ~C_000078_MC_IND_ADDR);
639 return r;
640 }
641
642 void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
643 {
644 WREG32(R_000078_MC_INDEX, S_000078_MC_IND_ADDR(reg) |
645 S_000078_MC_IND_WR_EN(1));
646 WREG32(R_00007C_MC_DATA, v);
647 WREG32(R_000078_MC_INDEX, 0x7F);
648 }
649
650 static void rs690_mc_program(struct radeon_device *rdev)
651 {
652 struct rv515_mc_save save;
653
654 /* Stops all mc clients */
655 rv515_mc_stop(rdev, &save);
656
657 /* Wait for mc idle */
658 if (rs690_mc_wait_for_idle(rdev))
659 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
660 /* Program MC, should be a 32bits limited address space */
661 WREG32_MC(R_000100_MCCFG_FB_LOCATION,
662 S_000100_MC_FB_START(rdev->mc.vram_start >> 16) |
663 S_000100_MC_FB_TOP(rdev->mc.vram_end >> 16));
664 WREG32(R_000134_HDP_FB_LOCATION,
665 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));
666
667 rv515_mc_resume(rdev, &save);
668 }
669
670 static int rs690_startup(struct radeon_device *rdev)
671 {
672 int r;
673
674 rs690_mc_program(rdev);
675 /* Resume clock */
676 rv515_clock_startup(rdev);
677 /* Initialize GPU configuration (# pipes, ...) */
678 rs690_gpu_init(rdev);
679 /* Initialize GART (initialize after TTM so we can allocate
680 * memory through TTM but finalize after TTM) */
681 r = rs400_gart_enable(rdev);
682 if (r)
683 return r;
684
685 /* allocate wb buffer */
686 r = radeon_wb_init(rdev);
687 if (r)
688 return r;
689
690 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
691 if (r) {
692 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
693 return r;
694 }
695
696 /* Enable IRQ */
697 if (!rdev->irq.installed) {
698 r = radeon_irq_kms_init(rdev);
699 if (r)
700 return r;
701 }
702
703 rs600_irq_set(rdev);
704 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
705 /* 1M ring buffer */
706 r = r100_cp_init(rdev, 1024 * 1024);
707 if (r) {
708 dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
709 return r;
710 }
711
712 r = radeon_ib_pool_init(rdev);
713 if (r) {
714 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
715 return r;
716 }
717
718 r = r600_audio_init(rdev);
719 if (r) {
720 dev_err(rdev->dev, "failed initializing audio\n");
721 return r;
722 }
723
724 return 0;
725 }
726
727 int rs690_resume(struct radeon_device *rdev)
728 {
729 int r;
730
731 /* Make sur GART are not working */
732 rs400_gart_disable(rdev);
733 /* Resume clock before doing reset */
734 rv515_clock_startup(rdev);
735 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
736 if (radeon_asic_reset(rdev)) {
737 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
738 RREG32(R_000E40_RBBM_STATUS),
739 RREG32(R_0007C0_CP_STAT));
740 }
741 /* post */
742 atom_asic_init(rdev->mode_info.atom_context);
743 /* Resume clock after posting */
744 rv515_clock_startup(rdev);
745 /* Initialize surface registers */
746 radeon_surface_init(rdev);
747
748 rdev->accel_working = true;
749 r = rs690_startup(rdev);
750 if (r) {
751 rdev->accel_working = false;
752 }
753 return r;
754 }
755
756 int rs690_suspend(struct radeon_device *rdev)
757 {
758 r600_audio_fini(rdev);
759 r100_cp_disable(rdev);
760 radeon_wb_disable(rdev);
761 rs600_irq_disable(rdev);
762 rs400_gart_disable(rdev);
763 return 0;
764 }
765
766 void rs690_fini(struct radeon_device *rdev)
767 {
768 r600_audio_fini(rdev);
769 r100_cp_fini(rdev);
770 radeon_wb_fini(rdev);
771 radeon_ib_pool_fini(rdev);
772 radeon_gem_fini(rdev);
773 rs400_gart_fini(rdev);
774 radeon_irq_kms_fini(rdev);
775 radeon_fence_driver_fini(rdev);
776 radeon_bo_fini(rdev);
777 radeon_atombios_fini(rdev);
778 kfree(rdev->bios);
779 rdev->bios = NULL;
780 }
781
782 int rs690_init(struct radeon_device *rdev)
783 {
784 int r;
785
786 /* Disable VGA */
787 rv515_vga_render_disable(rdev);
788 /* Initialize scratch registers */
789 radeon_scratch_init(rdev);
790 /* Initialize surface registers */
791 radeon_surface_init(rdev);
792 /* restore some register to sane defaults */
793 r100_restore_sanity(rdev);
794 /* TODO: disable VGA need to use VGA request */
795 /* BIOS*/
796 if (!radeon_get_bios(rdev)) {
797 if (ASIC_IS_AVIVO(rdev))
798 return -EINVAL;
799 }
800 if (rdev->is_atom_bios) {
801 r = radeon_atombios_init(rdev);
802 if (r)
803 return r;
804 } else {
805 dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n");
806 return -EINVAL;
807 }
808 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
809 if (radeon_asic_reset(rdev)) {
810 dev_warn(rdev->dev,
811 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
812 RREG32(R_000E40_RBBM_STATUS),
813 RREG32(R_0007C0_CP_STAT));
814 }
815 /* check if cards are posted or not */
816 if (radeon_boot_test_post_card(rdev) == false)
817 return -EINVAL;
818
819 /* Initialize clocks */
820 radeon_get_clock_info(rdev->ddev);
821 /* initialize memory controller */
822 rs690_mc_init(rdev);
823 rv515_debugfs(rdev);
824 /* Fence driver */
825 r = radeon_fence_driver_init(rdev);
826 if (r)
827 return r;
828 /* Memory manager */
829 r = radeon_bo_init(rdev);
830 if (r)
831 return r;
832 r = rs400_gart_init(rdev);
833 if (r)
834 return r;
835 rs600_set_safe_registers(rdev);
836
837 rdev->accel_working = true;
838 r = rs690_startup(rdev);
839 if (r) {
840 /* Somethings want wront with the accel init stop accel */
841 dev_err(rdev->dev, "Disabling GPU acceleration\n");
842 r100_cp_fini(rdev);
843 radeon_wb_fini(rdev);
844 radeon_ib_pool_fini(rdev);
845 rs400_gart_fini(rdev);
846 radeon_irq_kms_fini(rdev);
847 rdev->accel_working = false;
848 }
849 return 0;
850 }
Linux kernel - Deliverables
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