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drm/radeon/kms: clear confusion in GART init/deinit path
[deliverable/linux.git] / drivers / gpu / drm / radeon / rv515.c
1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28 #include <linux/seq_file.h>
29 #include "drmP.h"
30 #include "rv515d.h"
31 #include "radeon.h"
32
33 #include "rv515_reg_safe.h"
34 /* rv515 depends on : */
35 void r100_hdp_reset(struct radeon_device *rdev);
36 int r100_cp_reset(struct radeon_device *rdev);
37 int r100_rb2d_reset(struct radeon_device *rdev);
38 int r100_gui_wait_for_idle(struct radeon_device *rdev);
39 int r100_cp_init(struct radeon_device *rdev, unsigned ring_size);
40 void r420_pipes_init(struct radeon_device *rdev);
41 void rs600_mc_disable_clients(struct radeon_device *rdev);
42 void rs600_disable_vga(struct radeon_device *rdev);
43
44 /* This files gather functions specifics to:
45 * rv515
46 *
47 * Some of these functions might be used by newer ASICs.
48 */
49 int rv515_debugfs_pipes_info_init(struct radeon_device *rdev);
50 int rv515_debugfs_ga_info_init(struct radeon_device *rdev);
51 void rv515_gpu_init(struct radeon_device *rdev);
52 int rv515_mc_wait_for_idle(struct radeon_device *rdev);
53
54
55 /*
56 * MC
57 */
58 int rv515_mc_init(struct radeon_device *rdev)
59 {
60 uint32_t tmp;
61 int r;
62
63 if (r100_debugfs_rbbm_init(rdev)) {
64 DRM_ERROR("Failed to register debugfs file for RBBM !\n");
65 }
66 if (rv515_debugfs_pipes_info_init(rdev)) {
67 DRM_ERROR("Failed to register debugfs file for pipes !\n");
68 }
69 if (rv515_debugfs_ga_info_init(rdev)) {
70 DRM_ERROR("Failed to register debugfs file for pipes !\n");
71 }
72
73 rv515_gpu_init(rdev);
74 rv370_pcie_gart_disable(rdev);
75
76 /* Setup GPU memory space */
77 rdev->mc.vram_location = 0xFFFFFFFFUL;
78 rdev->mc.gtt_location = 0xFFFFFFFFUL;
79 if (rdev->flags & RADEON_IS_AGP) {
80 r = radeon_agp_init(rdev);
81 if (r) {
82 printk(KERN_WARNING "[drm] Disabling AGP\n");
83 rdev->flags &= ~RADEON_IS_AGP;
84 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
85 } else {
86 rdev->mc.gtt_location = rdev->mc.agp_base;
87 }
88 }
89 r = radeon_mc_setup(rdev);
90 if (r) {
91 return r;
92 }
93
94 /* Program GPU memory space */
95 rs600_mc_disable_clients(rdev);
96 if (rv515_mc_wait_for_idle(rdev)) {
97 printk(KERN_WARNING "Failed to wait MC idle while "
98 "programming pipes. Bad things might happen.\n");
99 }
100 /* Write VRAM size in case we are limiting it */
101 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
102 tmp = REG_SET(MC_FB_START, rdev->mc.vram_location >> 16);
103 WREG32(0x134, tmp);
104 tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1;
105 tmp = REG_SET(MC_FB_TOP, tmp >> 16);
106 tmp |= REG_SET(MC_FB_START, rdev->mc.vram_location >> 16);
107 WREG32_MC(MC_FB_LOCATION, tmp);
108 WREG32(HDP_FB_LOCATION, rdev->mc.vram_location >> 16);
109 WREG32(0x310, rdev->mc.vram_location);
110 if (rdev->flags & RADEON_IS_AGP) {
111 tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
112 tmp = REG_SET(MC_AGP_TOP, tmp >> 16);
113 tmp |= REG_SET(MC_AGP_START, rdev->mc.gtt_location >> 16);
114 WREG32_MC(MC_AGP_LOCATION, tmp);
115 WREG32_MC(MC_AGP_BASE, rdev->mc.agp_base);
116 WREG32_MC(MC_AGP_BASE_2, 0);
117 } else {
118 WREG32_MC(MC_AGP_LOCATION, 0x0FFFFFFF);
119 WREG32_MC(MC_AGP_BASE, 0);
120 WREG32_MC(MC_AGP_BASE_2, 0);
121 }
122 return 0;
123 }
124
125 void rv515_mc_fini(struct radeon_device *rdev)
126 {
127 }
128
129
130 /*
131 * Global GPU functions
132 */
133 void rv515_ring_start(struct radeon_device *rdev)
134 {
135 int r;
136
137 r = radeon_ring_lock(rdev, 64);
138 if (r) {
139 return;
140 }
141 radeon_ring_write(rdev, PACKET0(ISYNC_CNTL, 0));
142 radeon_ring_write(rdev,
143 ISYNC_ANY2D_IDLE3D |
144 ISYNC_ANY3D_IDLE2D |
145 ISYNC_WAIT_IDLEGUI |
146 ISYNC_CPSCRATCH_IDLEGUI);
147 radeon_ring_write(rdev, PACKET0(WAIT_UNTIL, 0));
148 radeon_ring_write(rdev, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN);
149 radeon_ring_write(rdev, PACKET0(0x170C, 0));
150 radeon_ring_write(rdev, 1 << 31);
151 radeon_ring_write(rdev, PACKET0(GB_SELECT, 0));
152 radeon_ring_write(rdev, 0);
153 radeon_ring_write(rdev, PACKET0(GB_ENABLE, 0));
154 radeon_ring_write(rdev, 0);
155 radeon_ring_write(rdev, PACKET0(0x42C8, 0));
156 radeon_ring_write(rdev, (1 << rdev->num_gb_pipes) - 1);
157 radeon_ring_write(rdev, PACKET0(VAP_INDEX_OFFSET, 0));
158 radeon_ring_write(rdev, 0);
159 radeon_ring_write(rdev, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0));
160 radeon_ring_write(rdev, RB3D_DC_FLUSH | RB3D_DC_FREE);
161 radeon_ring_write(rdev, PACKET0(ZB_ZCACHE_CTLSTAT, 0));
162 radeon_ring_write(rdev, ZC_FLUSH | ZC_FREE);
163 radeon_ring_write(rdev, PACKET0(WAIT_UNTIL, 0));
164 radeon_ring_write(rdev, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN);
165 radeon_ring_write(rdev, PACKET0(GB_AA_CONFIG, 0));
166 radeon_ring_write(rdev, 0);
167 radeon_ring_write(rdev, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0));
168 radeon_ring_write(rdev, RB3D_DC_FLUSH | RB3D_DC_FREE);
169 radeon_ring_write(rdev, PACKET0(ZB_ZCACHE_CTLSTAT, 0));
170 radeon_ring_write(rdev, ZC_FLUSH | ZC_FREE);
171 radeon_ring_write(rdev, PACKET0(GB_MSPOS0, 0));
172 radeon_ring_write(rdev,
173 ((6 << MS_X0_SHIFT) |
174 (6 << MS_Y0_SHIFT) |
175 (6 << MS_X1_SHIFT) |
176 (6 << MS_Y1_SHIFT) |
177 (6 << MS_X2_SHIFT) |
178 (6 << MS_Y2_SHIFT) |
179 (6 << MSBD0_Y_SHIFT) |
180 (6 << MSBD0_X_SHIFT)));
181 radeon_ring_write(rdev, PACKET0(GB_MSPOS1, 0));
182 radeon_ring_write(rdev,
183 ((6 << MS_X3_SHIFT) |
184 (6 << MS_Y3_SHIFT) |
185 (6 << MS_X4_SHIFT) |
186 (6 << MS_Y4_SHIFT) |
187 (6 << MS_X5_SHIFT) |
188 (6 << MS_Y5_SHIFT) |
189 (6 << MSBD1_SHIFT)));
190 radeon_ring_write(rdev, PACKET0(GA_ENHANCE, 0));
191 radeon_ring_write(rdev, GA_DEADLOCK_CNTL | GA_FASTSYNC_CNTL);
192 radeon_ring_write(rdev, PACKET0(GA_POLY_MODE, 0));
193 radeon_ring_write(rdev, FRONT_PTYPE_TRIANGE | BACK_PTYPE_TRIANGE);
194 radeon_ring_write(rdev, PACKET0(GA_ROUND_MODE, 0));
195 radeon_ring_write(rdev, GEOMETRY_ROUND_NEAREST | COLOR_ROUND_NEAREST);
196 radeon_ring_write(rdev, PACKET0(0x20C8, 0));
197 radeon_ring_write(rdev, 0);
198 radeon_ring_unlock_commit(rdev);
199 }
200
201 void rv515_errata(struct radeon_device *rdev)
202 {
203 rdev->pll_errata = 0;
204 }
205
206 int rv515_mc_wait_for_idle(struct radeon_device *rdev)
207 {
208 unsigned i;
209 uint32_t tmp;
210
211 for (i = 0; i < rdev->usec_timeout; i++) {
212 /* read MC_STATUS */
213 tmp = RREG32_MC(MC_STATUS);
214 if (tmp & MC_STATUS_IDLE) {
215 return 0;
216 }
217 DRM_UDELAY(1);
218 }
219 return -1;
220 }
221
222 void rv515_gpu_init(struct radeon_device *rdev)
223 {
224 unsigned pipe_select_current, gb_pipe_select, tmp;
225
226 r100_hdp_reset(rdev);
227 r100_rb2d_reset(rdev);
228
229 if (r100_gui_wait_for_idle(rdev)) {
230 printk(KERN_WARNING "Failed to wait GUI idle while "
231 "reseting GPU. Bad things might happen.\n");
232 }
233
234 rs600_disable_vga(rdev);
235
236 r420_pipes_init(rdev);
237 gb_pipe_select = RREG32(0x402C);
238 tmp = RREG32(0x170C);
239 pipe_select_current = (tmp >> 2) & 3;
240 tmp = (1 << pipe_select_current) |
241 (((gb_pipe_select >> 8) & 0xF) << 4);
242 WREG32_PLL(0x000D, tmp);
243 if (r100_gui_wait_for_idle(rdev)) {
244 printk(KERN_WARNING "Failed to wait GUI idle while "
245 "reseting GPU. Bad things might happen.\n");
246 }
247 if (rv515_mc_wait_for_idle(rdev)) {
248 printk(KERN_WARNING "Failed to wait MC idle while "
249 "programming pipes. Bad things might happen.\n");
250 }
251 }
252
253 int rv515_ga_reset(struct radeon_device *rdev)
254 {
255 uint32_t tmp;
256 bool reinit_cp;
257 int i;
258
259 reinit_cp = rdev->cp.ready;
260 rdev->cp.ready = false;
261 for (i = 0; i < rdev->usec_timeout; i++) {
262 WREG32(CP_CSQ_MODE, 0);
263 WREG32(CP_CSQ_CNTL, 0);
264 WREG32(RBBM_SOFT_RESET, 0x32005);
265 (void)RREG32(RBBM_SOFT_RESET);
266 udelay(200);
267 WREG32(RBBM_SOFT_RESET, 0);
268 /* Wait to prevent race in RBBM_STATUS */
269 mdelay(1);
270 tmp = RREG32(RBBM_STATUS);
271 if (tmp & ((1 << 20) | (1 << 26))) {
272 DRM_ERROR("VAP & CP still busy (RBBM_STATUS=0x%08X)\n", tmp);
273 /* GA still busy soft reset it */
274 WREG32(0x429C, 0x200);
275 WREG32(VAP_PVS_STATE_FLUSH_REG, 0);
276 WREG32(0x43E0, 0);
277 WREG32(0x43E4, 0);
278 WREG32(0x24AC, 0);
279 }
280 /* Wait to prevent race in RBBM_STATUS */
281 mdelay(1);
282 tmp = RREG32(RBBM_STATUS);
283 if (!(tmp & ((1 << 20) | (1 << 26)))) {
284 break;
285 }
286 }
287 for (i = 0; i < rdev->usec_timeout; i++) {
288 tmp = RREG32(RBBM_STATUS);
289 if (!(tmp & ((1 << 20) | (1 << 26)))) {
290 DRM_INFO("GA reset succeed (RBBM_STATUS=0x%08X)\n",
291 tmp);
292 DRM_INFO("GA_IDLE=0x%08X\n", RREG32(0x425C));
293 DRM_INFO("RB3D_RESET_STATUS=0x%08X\n", RREG32(0x46f0));
294 DRM_INFO("ISYNC_CNTL=0x%08X\n", RREG32(0x1724));
295 if (reinit_cp) {
296 return r100_cp_init(rdev, rdev->cp.ring_size);
297 }
298 return 0;
299 }
300 DRM_UDELAY(1);
301 }
302 tmp = RREG32(RBBM_STATUS);
303 DRM_ERROR("Failed to reset GA ! (RBBM_STATUS=0x%08X)\n", tmp);
304 return -1;
305 }
306
307 int rv515_gpu_reset(struct radeon_device *rdev)
308 {
309 uint32_t status;
310
311 /* reset order likely matter */
312 status = RREG32(RBBM_STATUS);
313 /* reset HDP */
314 r100_hdp_reset(rdev);
315 /* reset rb2d */
316 if (status & ((1 << 17) | (1 << 18) | (1 << 27))) {
317 r100_rb2d_reset(rdev);
318 }
319 /* reset GA */
320 if (status & ((1 << 20) | (1 << 26))) {
321 rv515_ga_reset(rdev);
322 }
323 /* reset CP */
324 status = RREG32(RBBM_STATUS);
325 if (status & (1 << 16)) {
326 r100_cp_reset(rdev);
327 }
328 /* Check if GPU is idle */
329 status = RREG32(RBBM_STATUS);
330 if (status & (1 << 31)) {
331 DRM_ERROR("Failed to reset GPU (RBBM_STATUS=0x%08X)\n", status);
332 return -1;
333 }
334 DRM_INFO("GPU reset succeed (RBBM_STATUS=0x%08X)\n", status);
335 return 0;
336 }
337
338
339 /*
340 * VRAM info
341 */
342 static void rv515_vram_get_type(struct radeon_device *rdev)
343 {
344 uint32_t tmp;
345
346 rdev->mc.vram_width = 128;
347 rdev->mc.vram_is_ddr = true;
348 tmp = RREG32_MC(RV515_MC_CNTL) & MEM_NUM_CHANNELS_MASK;
349 switch (tmp) {
350 case 0:
351 rdev->mc.vram_width = 64;
352 break;
353 case 1:
354 rdev->mc.vram_width = 128;
355 break;
356 default:
357 rdev->mc.vram_width = 128;
358 break;
359 }
360 }
361
362 void rv515_vram_info(struct radeon_device *rdev)
363 {
364 fixed20_12 a;
365
366 rv515_vram_get_type(rdev);
367
368 r100_vram_init_sizes(rdev);
369 /* FIXME: we should enforce default clock in case GPU is not in
370 * default setup
371 */
372 a.full = rfixed_const(100);
373 rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk);
374 rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a);
375 }
376
377
378 /*
379 * Indirect registers accessor
380 */
381 uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg)
382 {
383 uint32_t r;
384
385 WREG32(MC_IND_INDEX, 0x7f0000 | (reg & 0xffff));
386 r = RREG32(MC_IND_DATA);
387 WREG32(MC_IND_INDEX, 0);
388 return r;
389 }
390
391 void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
392 {
393 WREG32(MC_IND_INDEX, 0xff0000 | ((reg) & 0xffff));
394 WREG32(MC_IND_DATA, (v));
395 WREG32(MC_IND_INDEX, 0);
396 }
397
398 /*
399 * Debugfs info
400 */
401 #if defined(CONFIG_DEBUG_FS)
402 static int rv515_debugfs_pipes_info(struct seq_file *m, void *data)
403 {
404 struct drm_info_node *node = (struct drm_info_node *) m->private;
405 struct drm_device *dev = node->minor->dev;
406 struct radeon_device *rdev = dev->dev_private;
407 uint32_t tmp;
408
409 tmp = RREG32(GB_PIPE_SELECT);
410 seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp);
411 tmp = RREG32(SU_REG_DEST);
412 seq_printf(m, "SU_REG_DEST 0x%08x\n", tmp);
413 tmp = RREG32(GB_TILE_CONFIG);
414 seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp);
415 tmp = RREG32(DST_PIPE_CONFIG);
416 seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp);
417 return 0;
418 }
419
420 static int rv515_debugfs_ga_info(struct seq_file *m, void *data)
421 {
422 struct drm_info_node *node = (struct drm_info_node *) m->private;
423 struct drm_device *dev = node->minor->dev;
424 struct radeon_device *rdev = dev->dev_private;
425 uint32_t tmp;
426
427 tmp = RREG32(0x2140);
428 seq_printf(m, "VAP_CNTL_STATUS 0x%08x\n", tmp);
429 radeon_gpu_reset(rdev);
430 tmp = RREG32(0x425C);
431 seq_printf(m, "GA_IDLE 0x%08x\n", tmp);
432 return 0;
433 }
434
435 static struct drm_info_list rv515_pipes_info_list[] = {
436 {"rv515_pipes_info", rv515_debugfs_pipes_info, 0, NULL},
437 };
438
439 static struct drm_info_list rv515_ga_info_list[] = {
440 {"rv515_ga_info", rv515_debugfs_ga_info, 0, NULL},
441 };
442 #endif
443
444 int rv515_debugfs_pipes_info_init(struct radeon_device *rdev)
445 {
446 #if defined(CONFIG_DEBUG_FS)
447 return radeon_debugfs_add_files(rdev, rv515_pipes_info_list, 1);
448 #else
449 return 0;
450 #endif
451 }
452
453 int rv515_debugfs_ga_info_init(struct radeon_device *rdev)
454 {
455 #if defined(CONFIG_DEBUG_FS)
456 return radeon_debugfs_add_files(rdev, rv515_ga_info_list, 1);
457 #else
458 return 0;
459 #endif
460 }
461
462 /*
463 * Asic initialization
464 */
465 int rv515_init(struct radeon_device *rdev)
466 {
467 rdev->config.r300.reg_safe_bm = rv515_reg_safe_bm;
468 rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rv515_reg_safe_bm);
469 return 0;
470 }
471
472 void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *crtc)
473 {
474 int index_reg = 0x6578 + crtc->crtc_offset;
475 int data_reg = 0x657c + crtc->crtc_offset;
476
477 WREG32(0x659C + crtc->crtc_offset, 0x0);
478 WREG32(0x6594 + crtc->crtc_offset, 0x705);
479 WREG32(0x65A4 + crtc->crtc_offset, 0x10001);
480 WREG32(0x65D8 + crtc->crtc_offset, 0x0);
481 WREG32(0x65B0 + crtc->crtc_offset, 0x0);
482 WREG32(0x65C0 + crtc->crtc_offset, 0x0);
483 WREG32(0x65D4 + crtc->crtc_offset, 0x0);
484 WREG32(index_reg, 0x0);
485 WREG32(data_reg, 0x841880A8);
486 WREG32(index_reg, 0x1);
487 WREG32(data_reg, 0x84208680);
488 WREG32(index_reg, 0x2);
489 WREG32(data_reg, 0xBFF880B0);
490 WREG32(index_reg, 0x100);
491 WREG32(data_reg, 0x83D88088);
492 WREG32(index_reg, 0x101);
493 WREG32(data_reg, 0x84608680);
494 WREG32(index_reg, 0x102);
495 WREG32(data_reg, 0xBFF080D0);
496 WREG32(index_reg, 0x200);
497 WREG32(data_reg, 0x83988068);
498 WREG32(index_reg, 0x201);
499 WREG32(data_reg, 0x84A08680);
500 WREG32(index_reg, 0x202);
501 WREG32(data_reg, 0xBFF080F8);
502 WREG32(index_reg, 0x300);
503 WREG32(data_reg, 0x83588058);
504 WREG32(index_reg, 0x301);
505 WREG32(data_reg, 0x84E08660);
506 WREG32(index_reg, 0x302);
507 WREG32(data_reg, 0xBFF88120);
508 WREG32(index_reg, 0x400);
509 WREG32(data_reg, 0x83188040);
510 WREG32(index_reg, 0x401);
511 WREG32(data_reg, 0x85008660);
512 WREG32(index_reg, 0x402);
513 WREG32(data_reg, 0xBFF88150);
514 WREG32(index_reg, 0x500);
515 WREG32(data_reg, 0x82D88030);
516 WREG32(index_reg, 0x501);
517 WREG32(data_reg, 0x85408640);
518 WREG32(index_reg, 0x502);
519 WREG32(data_reg, 0xBFF88180);
520 WREG32(index_reg, 0x600);
521 WREG32(data_reg, 0x82A08018);
522 WREG32(index_reg, 0x601);
523 WREG32(data_reg, 0x85808620);
524 WREG32(index_reg, 0x602);
525 WREG32(data_reg, 0xBFF081B8);
526 WREG32(index_reg, 0x700);
527 WREG32(data_reg, 0x82608010);
528 WREG32(index_reg, 0x701);
529 WREG32(data_reg, 0x85A08600);
530 WREG32(index_reg, 0x702);
531 WREG32(data_reg, 0x800081F0);
532 WREG32(index_reg, 0x800);
533 WREG32(data_reg, 0x8228BFF8);
534 WREG32(index_reg, 0x801);
535 WREG32(data_reg, 0x85E085E0);
536 WREG32(index_reg, 0x802);
537 WREG32(data_reg, 0xBFF88228);
538 WREG32(index_reg, 0x10000);
539 WREG32(data_reg, 0x82A8BF00);
540 WREG32(index_reg, 0x10001);
541 WREG32(data_reg, 0x82A08CC0);
542 WREG32(index_reg, 0x10002);
543 WREG32(data_reg, 0x8008BEF8);
544 WREG32(index_reg, 0x10100);
545 WREG32(data_reg, 0x81F0BF28);
546 WREG32(index_reg, 0x10101);
547 WREG32(data_reg, 0x83608CA0);
548 WREG32(index_reg, 0x10102);
549 WREG32(data_reg, 0x8018BED0);
550 WREG32(index_reg, 0x10200);
551 WREG32(data_reg, 0x8148BF38);
552 WREG32(index_reg, 0x10201);
553 WREG32(data_reg, 0x84408C80);
554 WREG32(index_reg, 0x10202);
555 WREG32(data_reg, 0x8008BEB8);
556 WREG32(index_reg, 0x10300);
557 WREG32(data_reg, 0x80B0BF78);
558 WREG32(index_reg, 0x10301);
559 WREG32(data_reg, 0x85008C20);
560 WREG32(index_reg, 0x10302);
561 WREG32(data_reg, 0x8020BEA0);
562 WREG32(index_reg, 0x10400);
563 WREG32(data_reg, 0x8028BF90);
564 WREG32(index_reg, 0x10401);
565 WREG32(data_reg, 0x85E08BC0);
566 WREG32(index_reg, 0x10402);
567 WREG32(data_reg, 0x8018BE90);
568 WREG32(index_reg, 0x10500);
569 WREG32(data_reg, 0xBFB8BFB0);
570 WREG32(index_reg, 0x10501);
571 WREG32(data_reg, 0x86C08B40);
572 WREG32(index_reg, 0x10502);
573 WREG32(data_reg, 0x8010BE90);
574 WREG32(index_reg, 0x10600);
575 WREG32(data_reg, 0xBF58BFC8);
576 WREG32(index_reg, 0x10601);
577 WREG32(data_reg, 0x87A08AA0);
578 WREG32(index_reg, 0x10602);
579 WREG32(data_reg, 0x8010BE98);
580 WREG32(index_reg, 0x10700);
581 WREG32(data_reg, 0xBF10BFF0);
582 WREG32(index_reg, 0x10701);
583 WREG32(data_reg, 0x886089E0);
584 WREG32(index_reg, 0x10702);
585 WREG32(data_reg, 0x8018BEB0);
586 WREG32(index_reg, 0x10800);
587 WREG32(data_reg, 0xBED8BFE8);
588 WREG32(index_reg, 0x10801);
589 WREG32(data_reg, 0x89408940);
590 WREG32(index_reg, 0x10802);
591 WREG32(data_reg, 0xBFE8BED8);
592 WREG32(index_reg, 0x20000);
593 WREG32(data_reg, 0x80008000);
594 WREG32(index_reg, 0x20001);
595 WREG32(data_reg, 0x90008000);
596 WREG32(index_reg, 0x20002);
597 WREG32(data_reg, 0x80008000);
598 WREG32(index_reg, 0x20003);
599 WREG32(data_reg, 0x80008000);
600 WREG32(index_reg, 0x20100);
601 WREG32(data_reg, 0x80108000);
602 WREG32(index_reg, 0x20101);
603 WREG32(data_reg, 0x8FE0BF70);
604 WREG32(index_reg, 0x20102);
605 WREG32(data_reg, 0xBFE880C0);
606 WREG32(index_reg, 0x20103);
607 WREG32(data_reg, 0x80008000);
608 WREG32(index_reg, 0x20200);
609 WREG32(data_reg, 0x8018BFF8);
610 WREG32(index_reg, 0x20201);
611 WREG32(data_reg, 0x8F80BF08);
612 WREG32(index_reg, 0x20202);
613 WREG32(data_reg, 0xBFD081A0);
614 WREG32(index_reg, 0x20203);
615 WREG32(data_reg, 0xBFF88000);
616 WREG32(index_reg, 0x20300);
617 WREG32(data_reg, 0x80188000);
618 WREG32(index_reg, 0x20301);
619 WREG32(data_reg, 0x8EE0BEC0);
620 WREG32(index_reg, 0x20302);
621 WREG32(data_reg, 0xBFB082A0);
622 WREG32(index_reg, 0x20303);
623 WREG32(data_reg, 0x80008000);
624 WREG32(index_reg, 0x20400);
625 WREG32(data_reg, 0x80188000);
626 WREG32(index_reg, 0x20401);
627 WREG32(data_reg, 0x8E00BEA0);
628 WREG32(index_reg, 0x20402);
629 WREG32(data_reg, 0xBF8883C0);
630 WREG32(index_reg, 0x20403);
631 WREG32(data_reg, 0x80008000);
632 WREG32(index_reg, 0x20500);
633 WREG32(data_reg, 0x80188000);
634 WREG32(index_reg, 0x20501);
635 WREG32(data_reg, 0x8D00BE90);
636 WREG32(index_reg, 0x20502);
637 WREG32(data_reg, 0xBF588500);
638 WREG32(index_reg, 0x20503);
639 WREG32(data_reg, 0x80008008);
640 WREG32(index_reg, 0x20600);
641 WREG32(data_reg, 0x80188000);
642 WREG32(index_reg, 0x20601);
643 WREG32(data_reg, 0x8BC0BE98);
644 WREG32(index_reg, 0x20602);
645 WREG32(data_reg, 0xBF308660);
646 WREG32(index_reg, 0x20603);
647 WREG32(data_reg, 0x80008008);
648 WREG32(index_reg, 0x20700);
649 WREG32(data_reg, 0x80108000);
650 WREG32(index_reg, 0x20701);
651 WREG32(data_reg, 0x8A80BEB0);
652 WREG32(index_reg, 0x20702);
653 WREG32(data_reg, 0xBF0087C0);
654 WREG32(index_reg, 0x20703);
655 WREG32(data_reg, 0x80008008);
656 WREG32(index_reg, 0x20800);
657 WREG32(data_reg, 0x80108000);
658 WREG32(index_reg, 0x20801);
659 WREG32(data_reg, 0x8920BED0);
660 WREG32(index_reg, 0x20802);
661 WREG32(data_reg, 0xBED08920);
662 WREG32(index_reg, 0x20803);
663 WREG32(data_reg, 0x80008010);
664 WREG32(index_reg, 0x30000);
665 WREG32(data_reg, 0x90008000);
666 WREG32(index_reg, 0x30001);
667 WREG32(data_reg, 0x80008000);
668 WREG32(index_reg, 0x30100);
669 WREG32(data_reg, 0x8FE0BF90);
670 WREG32(index_reg, 0x30101);
671 WREG32(data_reg, 0xBFF880A0);
672 WREG32(index_reg, 0x30200);
673 WREG32(data_reg, 0x8F60BF40);
674 WREG32(index_reg, 0x30201);
675 WREG32(data_reg, 0xBFE88180);
676 WREG32(index_reg, 0x30300);
677 WREG32(data_reg, 0x8EC0BF00);
678 WREG32(index_reg, 0x30301);
679 WREG32(data_reg, 0xBFC88280);
680 WREG32(index_reg, 0x30400);
681 WREG32(data_reg, 0x8DE0BEE0);
682 WREG32(index_reg, 0x30401);
683 WREG32(data_reg, 0xBFA083A0);
684 WREG32(index_reg, 0x30500);
685 WREG32(data_reg, 0x8CE0BED0);
686 WREG32(index_reg, 0x30501);
687 WREG32(data_reg, 0xBF7884E0);
688 WREG32(index_reg, 0x30600);
689 WREG32(data_reg, 0x8BA0BED8);
690 WREG32(index_reg, 0x30601);
691 WREG32(data_reg, 0xBF508640);
692 WREG32(index_reg, 0x30700);
693 WREG32(data_reg, 0x8A60BEE8);
694 WREG32(index_reg, 0x30701);
695 WREG32(data_reg, 0xBF2087A0);
696 WREG32(index_reg, 0x30800);
697 WREG32(data_reg, 0x8900BF00);
698 WREG32(index_reg, 0x30801);
699 WREG32(data_reg, 0xBF008900);
700 }
701
702 struct rv515_watermark {
703 u32 lb_request_fifo_depth;
704 fixed20_12 num_line_pair;
705 fixed20_12 estimated_width;
706 fixed20_12 worst_case_latency;
707 fixed20_12 consumption_rate;
708 fixed20_12 active_time;
709 fixed20_12 dbpp;
710 fixed20_12 priority_mark_max;
711 fixed20_12 priority_mark;
712 fixed20_12 sclk;
713 };
714
715 void rv515_crtc_bandwidth_compute(struct radeon_device *rdev,
716 struct radeon_crtc *crtc,
717 struct rv515_watermark *wm)
718 {
719 struct drm_display_mode *mode = &crtc->base.mode;
720 fixed20_12 a, b, c;
721 fixed20_12 pclk, request_fifo_depth, tolerable_latency, estimated_width;
722 fixed20_12 consumption_time, line_time, chunk_time, read_delay_latency;
723
724 if (!crtc->base.enabled) {
725 /* FIXME: wouldn't it better to set priority mark to maximum */
726 wm->lb_request_fifo_depth = 4;
727 return;
728 }
729
730 if (crtc->vsc.full > rfixed_const(2))
731 wm->num_line_pair.full = rfixed_const(2);
732 else
733 wm->num_line_pair.full = rfixed_const(1);
734
735 b.full = rfixed_const(mode->crtc_hdisplay);
736 c.full = rfixed_const(256);
737 a.full = rfixed_mul(wm->num_line_pair, b);
738 request_fifo_depth.full = rfixed_div(a, c);
739 if (a.full < rfixed_const(4)) {
740 wm->lb_request_fifo_depth = 4;
741 } else {
742 wm->lb_request_fifo_depth = rfixed_trunc(request_fifo_depth);
743 }
744
745 /* Determine consumption rate
746 * pclk = pixel clock period(ns) = 1000 / (mode.clock / 1000)
747 * vtaps = number of vertical taps,
748 * vsc = vertical scaling ratio, defined as source/destination
749 * hsc = horizontal scaling ration, defined as source/destination
750 */
751 a.full = rfixed_const(mode->clock);
752 b.full = rfixed_const(1000);
753 a.full = rfixed_div(a, b);
754 pclk.full = rfixed_div(b, a);
755 if (crtc->rmx_type != RMX_OFF) {
756 b.full = rfixed_const(2);
757 if (crtc->vsc.full > b.full)
758 b.full = crtc->vsc.full;
759 b.full = rfixed_mul(b, crtc->hsc);
760 c.full = rfixed_const(2);
761 b.full = rfixed_div(b, c);
762 consumption_time.full = rfixed_div(pclk, b);
763 } else {
764 consumption_time.full = pclk.full;
765 }
766 a.full = rfixed_const(1);
767 wm->consumption_rate.full = rfixed_div(a, consumption_time);
768
769
770 /* Determine line time
771 * LineTime = total time for one line of displayhtotal
772 * LineTime = total number of horizontal pixels
773 * pclk = pixel clock period(ns)
774 */
775 a.full = rfixed_const(crtc->base.mode.crtc_htotal);
776 line_time.full = rfixed_mul(a, pclk);
777
778 /* Determine active time
779 * ActiveTime = time of active region of display within one line,
780 * hactive = total number of horizontal active pixels
781 * htotal = total number of horizontal pixels
782 */
783 a.full = rfixed_const(crtc->base.mode.crtc_htotal);
784 b.full = rfixed_const(crtc->base.mode.crtc_hdisplay);
785 wm->active_time.full = rfixed_mul(line_time, b);
786 wm->active_time.full = rfixed_div(wm->active_time, a);
787
788 /* Determine chunk time
789 * ChunkTime = the time it takes the DCP to send one chunk of data
790 * to the LB which consists of pipeline delay and inter chunk gap
791 * sclk = system clock(Mhz)
792 */
793 a.full = rfixed_const(600 * 1000);
794 chunk_time.full = rfixed_div(a, rdev->pm.sclk);
795 read_delay_latency.full = rfixed_const(1000);
796
797 /* Determine the worst case latency
798 * NumLinePair = Number of line pairs to request(1=2 lines, 2=4 lines)
799 * WorstCaseLatency = worst case time from urgent to when the MC starts
800 * to return data
801 * READ_DELAY_IDLE_MAX = constant of 1us
802 * ChunkTime = time it takes the DCP to send one chunk of data to the LB
803 * which consists of pipeline delay and inter chunk gap
804 */
805 if (rfixed_trunc(wm->num_line_pair) > 1) {
806 a.full = rfixed_const(3);
807 wm->worst_case_latency.full = rfixed_mul(a, chunk_time);
808 wm->worst_case_latency.full += read_delay_latency.full;
809 } else {
810 wm->worst_case_latency.full = chunk_time.full + read_delay_latency.full;
811 }
812
813 /* Determine the tolerable latency
814 * TolerableLatency = Any given request has only 1 line time
815 * for the data to be returned
816 * LBRequestFifoDepth = Number of chunk requests the LB can
817 * put into the request FIFO for a display
818 * LineTime = total time for one line of display
819 * ChunkTime = the time it takes the DCP to send one chunk
820 * of data to the LB which consists of
821 * pipeline delay and inter chunk gap
822 */
823 if ((2+wm->lb_request_fifo_depth) >= rfixed_trunc(request_fifo_depth)) {
824 tolerable_latency.full = line_time.full;
825 } else {
826 tolerable_latency.full = rfixed_const(wm->lb_request_fifo_depth - 2);
827 tolerable_latency.full = request_fifo_depth.full - tolerable_latency.full;
828 tolerable_latency.full = rfixed_mul(tolerable_latency, chunk_time);
829 tolerable_latency.full = line_time.full - tolerable_latency.full;
830 }
831 /* We assume worst case 32bits (4 bytes) */
832 wm->dbpp.full = rfixed_const(2 * 16);
833
834 /* Determine the maximum priority mark
835 * width = viewport width in pixels
836 */
837 a.full = rfixed_const(16);
838 wm->priority_mark_max.full = rfixed_const(crtc->base.mode.crtc_hdisplay);
839 wm->priority_mark_max.full = rfixed_div(wm->priority_mark_max, a);
840
841 /* Determine estimated width */
842 estimated_width.full = tolerable_latency.full - wm->worst_case_latency.full;
843 estimated_width.full = rfixed_div(estimated_width, consumption_time);
844 if (rfixed_trunc(estimated_width) > crtc->base.mode.crtc_hdisplay) {
845 wm->priority_mark.full = rfixed_const(10);
846 } else {
847 a.full = rfixed_const(16);
848 wm->priority_mark.full = rfixed_div(estimated_width, a);
849 wm->priority_mark.full = wm->priority_mark_max.full - wm->priority_mark.full;
850 }
851 }
852
853 void rv515_bandwidth_avivo_update(struct radeon_device *rdev)
854 {
855 struct drm_display_mode *mode0 = NULL;
856 struct drm_display_mode *mode1 = NULL;
857 struct rv515_watermark wm0;
858 struct rv515_watermark wm1;
859 u32 tmp;
860 fixed20_12 priority_mark02, priority_mark12, fill_rate;
861 fixed20_12 a, b;
862
863 if (rdev->mode_info.crtcs[0]->base.enabled)
864 mode0 = &rdev->mode_info.crtcs[0]->base.mode;
865 if (rdev->mode_info.crtcs[1]->base.enabled)
866 mode1 = &rdev->mode_info.crtcs[1]->base.mode;
867 rs690_line_buffer_adjust(rdev, mode0, mode1);
868
869 rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0);
870 rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1);
871
872 tmp = wm0.lb_request_fifo_depth;
873 tmp |= wm1.lb_request_fifo_depth << 16;
874 WREG32(LB_MAX_REQ_OUTSTANDING, tmp);
875
876 if (mode0 && mode1) {
877 if (rfixed_trunc(wm0.dbpp) > 64)
878 a.full = rfixed_div(wm0.dbpp, wm0.num_line_pair);
879 else
880 a.full = wm0.num_line_pair.full;
881 if (rfixed_trunc(wm1.dbpp) > 64)
882 b.full = rfixed_div(wm1.dbpp, wm1.num_line_pair);
883 else
884 b.full = wm1.num_line_pair.full;
885 a.full += b.full;
886 fill_rate.full = rfixed_div(wm0.sclk, a);
887 if (wm0.consumption_rate.full > fill_rate.full) {
888 b.full = wm0.consumption_rate.full - fill_rate.full;
889 b.full = rfixed_mul(b, wm0.active_time);
890 a.full = rfixed_const(16);
891 b.full = rfixed_div(b, a);
892 a.full = rfixed_mul(wm0.worst_case_latency,
893 wm0.consumption_rate);
894 priority_mark02.full = a.full + b.full;
895 } else {
896 a.full = rfixed_mul(wm0.worst_case_latency,
897 wm0.consumption_rate);
898 b.full = rfixed_const(16 * 1000);
899 priority_mark02.full = rfixed_div(a, b);
900 }
901 if (wm1.consumption_rate.full > fill_rate.full) {
902 b.full = wm1.consumption_rate.full - fill_rate.full;
903 b.full = rfixed_mul(b, wm1.active_time);
904 a.full = rfixed_const(16);
905 b.full = rfixed_div(b, a);
906 a.full = rfixed_mul(wm1.worst_case_latency,
907 wm1.consumption_rate);
908 priority_mark12.full = a.full + b.full;
909 } else {
910 a.full = rfixed_mul(wm1.worst_case_latency,
911 wm1.consumption_rate);
912 b.full = rfixed_const(16 * 1000);
913 priority_mark12.full = rfixed_div(a, b);
914 }
915 if (wm0.priority_mark.full > priority_mark02.full)
916 priority_mark02.full = wm0.priority_mark.full;
917 if (rfixed_trunc(priority_mark02) < 0)
918 priority_mark02.full = 0;
919 if (wm0.priority_mark_max.full > priority_mark02.full)
920 priority_mark02.full = wm0.priority_mark_max.full;
921 if (wm1.priority_mark.full > priority_mark12.full)
922 priority_mark12.full = wm1.priority_mark.full;
923 if (rfixed_trunc(priority_mark12) < 0)
924 priority_mark12.full = 0;
925 if (wm1.priority_mark_max.full > priority_mark12.full)
926 priority_mark12.full = wm1.priority_mark_max.full;
927 WREG32(D1MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark02));
928 WREG32(D1MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark02));
929 WREG32(D2MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark12));
930 WREG32(D2MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark12));
931 } else if (mode0) {
932 if (rfixed_trunc(wm0.dbpp) > 64)
933 a.full = rfixed_div(wm0.dbpp, wm0.num_line_pair);
934 else
935 a.full = wm0.num_line_pair.full;
936 fill_rate.full = rfixed_div(wm0.sclk, a);
937 if (wm0.consumption_rate.full > fill_rate.full) {
938 b.full = wm0.consumption_rate.full - fill_rate.full;
939 b.full = rfixed_mul(b, wm0.active_time);
940 a.full = rfixed_const(16);
941 b.full = rfixed_div(b, a);
942 a.full = rfixed_mul(wm0.worst_case_latency,
943 wm0.consumption_rate);
944 priority_mark02.full = a.full + b.full;
945 } else {
946 a.full = rfixed_mul(wm0.worst_case_latency,
947 wm0.consumption_rate);
948 b.full = rfixed_const(16);
949 priority_mark02.full = rfixed_div(a, b);
950 }
951 if (wm0.priority_mark.full > priority_mark02.full)
952 priority_mark02.full = wm0.priority_mark.full;
953 if (rfixed_trunc(priority_mark02) < 0)
954 priority_mark02.full = 0;
955 if (wm0.priority_mark_max.full > priority_mark02.full)
956 priority_mark02.full = wm0.priority_mark_max.full;
957 WREG32(D1MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark02));
958 WREG32(D1MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark02));
959 WREG32(D2MODE_PRIORITY_A_CNT, MODE_PRIORITY_OFF);
960 WREG32(D2MODE_PRIORITY_B_CNT, MODE_PRIORITY_OFF);
961 } else {
962 if (rfixed_trunc(wm1.dbpp) > 64)
963 a.full = rfixed_div(wm1.dbpp, wm1.num_line_pair);
964 else
965 a.full = wm1.num_line_pair.full;
966 fill_rate.full = rfixed_div(wm1.sclk, a);
967 if (wm1.consumption_rate.full > fill_rate.full) {
968 b.full = wm1.consumption_rate.full - fill_rate.full;
969 b.full = rfixed_mul(b, wm1.active_time);
970 a.full = rfixed_const(16);
971 b.full = rfixed_div(b, a);
972 a.full = rfixed_mul(wm1.worst_case_latency,
973 wm1.consumption_rate);
974 priority_mark12.full = a.full + b.full;
975 } else {
976 a.full = rfixed_mul(wm1.worst_case_latency,
977 wm1.consumption_rate);
978 b.full = rfixed_const(16 * 1000);
979 priority_mark12.full = rfixed_div(a, b);
980 }
981 if (wm1.priority_mark.full > priority_mark12.full)
982 priority_mark12.full = wm1.priority_mark.full;
983 if (rfixed_trunc(priority_mark12) < 0)
984 priority_mark12.full = 0;
985 if (wm1.priority_mark_max.full > priority_mark12.full)
986 priority_mark12.full = wm1.priority_mark_max.full;
987 WREG32(D1MODE_PRIORITY_A_CNT, MODE_PRIORITY_OFF);
988 WREG32(D1MODE_PRIORITY_B_CNT, MODE_PRIORITY_OFF);
989 WREG32(D2MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark12));
990 WREG32(D2MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark12));
991 }
992 }
993
994 void rv515_bandwidth_update(struct radeon_device *rdev)
995 {
996 uint32_t tmp;
997 struct drm_display_mode *mode0 = NULL;
998 struct drm_display_mode *mode1 = NULL;
999
1000 if (rdev->mode_info.crtcs[0]->base.enabled)
1001 mode0 = &rdev->mode_info.crtcs[0]->base.mode;
1002 if (rdev->mode_info.crtcs[1]->base.enabled)
1003 mode1 = &rdev->mode_info.crtcs[1]->base.mode;
1004 /*
1005 * Set display0/1 priority up in the memory controller for
1006 * modes if the user specifies HIGH for displaypriority
1007 * option.
1008 */
1009 if (rdev->disp_priority == 2) {
1010 tmp = RREG32_MC(MC_MISC_LAT_TIMER);
1011 tmp &= ~MC_DISP1R_INIT_LAT_MASK;
1012 tmp &= ~MC_DISP0R_INIT_LAT_MASK;
1013 if (mode1)
1014 tmp |= (1 << MC_DISP1R_INIT_LAT_SHIFT);
1015 if (mode0)
1016 tmp |= (1 << MC_DISP0R_INIT_LAT_SHIFT);
1017 WREG32_MC(MC_MISC_LAT_TIMER, tmp);
1018 }
1019 rv515_bandwidth_avivo_update(rdev);
1020 }
Linux kernel - Deliverables
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