drivers/gpu/drm/radeon/rv6xxd.h

   1 /*
   2  * Copyright 2011 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #ifndef RV6XXD_H
  24 #define RV6XXD_H
  25
  26 /* RV6xx power management */
  27 #define SPLL_CNTL_MODE                                    0x60c
  28 #       define SPLL_DIV_SYNC                              (1 << 5)
  29
  30 #define GENERAL_PWRMGT                                    0x618
  31 #       define GLOBAL_PWRMGT_EN                           (1 << 0)
  32 #       define STATIC_PM_EN                               (1 << 1)
  33 #       define MOBILE_SU                                  (1 << 2)
  34 #       define THERMAL_PROTECTION_DIS                     (1 << 3)
  35 #       define THERMAL_PROTECTION_TYPE                    (1 << 4)
  36 #       define ENABLE_GEN2PCIE                            (1 << 5)
  37 #       define SW_GPIO_INDEX(x)                           ((x) << 6)
  38 #       define SW_GPIO_INDEX_MASK                         (3 << 6)
  39 #       define LOW_VOLT_D2_ACPI                           (1 << 8)
  40 #       define LOW_VOLT_D3_ACPI                           (1 << 9)
  41 #       define VOLT_PWRMGT_EN                             (1 << 10)
  42 #       define BACKBIAS_PAD_EN                            (1 << 16)
  43 #       define BACKBIAS_VALUE                             (1 << 17)
  44 #       define BACKBIAS_DPM_CNTL                          (1 << 18)
  45 #       define DYN_SPREAD_SPECTRUM_EN                     (1 << 21)
  46
  47 #define MCLK_PWRMGT_CNTL                                  0x624
  48 #       define MPLL_PWRMGT_OFF                            (1 << 0)
  49 #       define YCLK_TURNOFF                               (1 << 1)
  50 #       define MPLL_TURNOFF                               (1 << 2)
  51 #       define SU_MCLK_USE_BCLK                           (1 << 3)
  52 #       define DLL_READY                                  (1 << 4)
  53 #       define MC_BUSY                                    (1 << 5)
  54 #       define MC_INT_CNTL                                (1 << 7)
  55 #       define MRDCKA_SLEEP                               (1 << 8)
  56 #       define MRDCKB_SLEEP                               (1 << 9)
  57 #       define MRDCKC_SLEEP                               (1 << 10)
  58 #       define MRDCKD_SLEEP                               (1 << 11)
  59 #       define MRDCKE_SLEEP                               (1 << 12)
  60 #       define MRDCKF_SLEEP                               (1 << 13)
  61 #       define MRDCKG_SLEEP                               (1 << 14)
  62 #       define MRDCKH_SLEEP                               (1 << 15)
  63 #       define MRDCKA_RESET                               (1 << 16)
  64 #       define MRDCKB_RESET                               (1 << 17)
  65 #       define MRDCKC_RESET                               (1 << 18)
  66 #       define MRDCKD_RESET                               (1 << 19)
  67 #       define MRDCKE_RESET                               (1 << 20)
  68 #       define MRDCKF_RESET                               (1 << 21)
  69 #       define MRDCKG_RESET                               (1 << 22)
  70 #       define MRDCKH_RESET                               (1 << 23)
  71 #       define DLL_READY_READ                             (1 << 24)
  72 #       define USE_DISPLAY_GAP                            (1 << 25)
  73 #       define USE_DISPLAY_URGENT_NORMAL                  (1 << 26)
  74 #       define USE_DISPLAY_GAP_CTXSW                      (1 << 27)
  75 #       define MPLL_TURNOFF_D2                            (1 << 28)
  76 #       define USE_DISPLAY_URGENT_CTXSW                   (1 << 29)
  77
  78 #define MPLL_FREQ_LEVEL_0                                 0x6e8
  79 #       define LEVEL0_MPLL_POST_DIV(x)                    ((x) << 0)
  80 #       define LEVEL0_MPLL_POST_DIV_MASK                  (0xff << 0)
  81 #       define LEVEL0_MPLL_FB_DIV(x)                      ((x) << 8)
  82 #       define LEVEL0_MPLL_FB_DIV_MASK                    (0xfff << 8)
  83 #       define LEVEL0_MPLL_REF_DIV(x)                     ((x) << 20)
  84 #       define LEVEL0_MPLL_REF_DIV_MASK                   (0x3f << 20)
  85 #       define LEVEL0_MPLL_DIV_EN                         (1 << 28)
  86 #       define LEVEL0_DLL_BYPASS                          (1 << 29)
  87 #       define LEVEL0_DLL_RESET                           (1 << 30)
  88
  89 #define VID_RT                                            0x6f8
  90 #       define VID_CRT(x)                                 ((x) << 0)
  91 #       define VID_CRT_MASK                               (0x1fff << 0)
  92 #       define VID_CRTU(x)                                ((x) << 13)
  93 #       define VID_CRTU_MASK                              (7 << 13)
  94 #       define SSTU(x)                                    ((x) << 16)
  95 #       define SSTU_MASK                                  (7 << 16)
  96 #       define VID_SWT(x)                                 ((x) << 19)
  97 #       define VID_SWT_MASK                               (0x1f << 19)
  98 #       define BRT(x)                                     ((x) << 24)
  99 #       define BRT_MASK                                   (0xff << 24)
 100
 101 #define TARGET_AND_CURRENT_PROFILE_INDEX                  0x70c
 102 #       define TARGET_PROFILE_INDEX_MASK                  (3 << 0)
 103 #       define TARGET_PROFILE_INDEX_SHIFT                 0
 104 #       define CURRENT_PROFILE_INDEX_MASK                 (3 << 2)
 105 #       define CURRENT_PROFILE_INDEX_SHIFT                2
 106 #       define DYN_PWR_ENTER_INDEX(x)                     ((x) << 4)
 107 #       define DYN_PWR_ENTER_INDEX_MASK                   (3 << 4)
 108 #       define DYN_PWR_ENTER_INDEX_SHIFT                  4
 109 #       define CURR_MCLK_INDEX_MASK                       (3 << 6)
 110 #       define CURR_MCLK_INDEX_SHIFT                      6
 111 #       define CURR_SCLK_INDEX_MASK                       (0x1f << 8)
 112 #       define CURR_SCLK_INDEX_SHIFT                      8
 113 #       define CURR_VID_INDEX_MASK                        (3 << 13)
 114 #       define CURR_VID_INDEX_SHIFT                       13
 115
 116 #define VID_UPPER_GPIO_CNTL                               0x740
 117 #       define CTXSW_UPPER_GPIO_VALUES(x)                 ((x) << 0)
 118 #       define CTXSW_UPPER_GPIO_VALUES_MASK               (7 << 0)
 119 #       define HIGH_UPPER_GPIO_VALUES(x)                  ((x) << 3)
 120 #       define HIGH_UPPER_GPIO_VALUES_MASK                (7 << 3)
 121 #       define MEDIUM_UPPER_GPIO_VALUES(x)                ((x) << 6)
 122 #       define MEDIUM_UPPER_GPIO_VALUES_MASK              (7 << 6)
 123 #       define LOW_UPPER_GPIO_VALUES(x)                   ((x) << 9)
 124 #       define LOW_UPPER_GPIO_VALUES_MASK                 (7 << 9)
 125 #       define CTXSW_BACKBIAS_VALUE                       (1 << 12)
 126 #       define HIGH_BACKBIAS_VALUE                        (1 << 13)
 127 #       define MEDIUM_BACKBIAS_VALUE                      (1 << 14)
 128 #       define LOW_BACKBIAS_VALUE                         (1 << 15)
 129
 130 #define CG_DISPLAY_GAP_CNTL                               0x7dc
 131 #       define DISP1_GAP(x)                               ((x) << 0)
 132 #       define DISP1_GAP_MASK                             (3 << 0)
 133 #       define DISP2_GAP(x)                               ((x) << 2)
 134 #       define DISP2_GAP_MASK                             (3 << 2)
 135 #       define VBI_TIMER_COUNT(x)                         ((x) << 4)
 136 #       define VBI_TIMER_COUNT_MASK                       (0x3fff << 4)
 137 #       define VBI_TIMER_UNIT(x)                          ((x) << 20)
 138 #       define VBI_TIMER_UNIT_MASK                        (7 << 20)
 139 #       define DISP1_GAP_MCHG(x)                          ((x) << 24)
 140 #       define DISP1_GAP_MCHG_MASK                        (3 << 24)
 141 #       define DISP2_GAP_MCHG(x)                          ((x) << 26)
 142 #       define DISP2_GAP_MCHG_MASK                        (3 << 26)
 143
 144 #define CG_THERMAL_CTRL                                   0x7f0
 145 #       define DPM_EVENT_SRC(x)                           ((x) << 0)
 146 #       define DPM_EVENT_SRC_MASK                         (7 << 0)
 147 #       define THERM_INC_CLK                              (1 << 3)
 148 #       define TOFFSET(x)                                 ((x) << 4)
 149 #       define TOFFSET_MASK                               (0xff << 4)
 150 #       define DIG_THERM_DPM(x)                           ((x) << 12)
 151 #       define DIG_THERM_DPM_MASK                         (0xff << 12)
 152 #       define CTF_SEL(x)                                 ((x) << 20)
 153 #       define CTF_SEL_MASK                               (7 << 20)
 154 #       define CTF_PAD_POLARITY                           (1 << 23)
 155 #       define CTF_PAD_EN                                 (1 << 24)
 156
 157 #define CG_SPLL_SPREAD_SPECTRUM_LOW                       0x820
 158 #       define SSEN                                       (1 << 0)
 159 #       define CLKS(x)                                    ((x) << 3)
 160 #       define CLKS_MASK                                  (0xff << 3)
 161 #       define CLKS_SHIFT                                 3
 162 #       define CLKV(x)                                    ((x) << 11)
 163 #       define CLKV_MASK                                  (0x7ff << 11)
 164 #       define CLKV_SHIFT                                 11
 165 #define CG_MPLL_SPREAD_SPECTRUM                           0x830
 166
 167 #define CITF_CNTL                                       0x200c
 168 #       define BLACKOUT_RD                              (1 << 0)
 169 #       define BLACKOUT_WR                              (1 << 1)
 170
 171 #define RAMCFG                                          0x2408
 172 #define         NOOFBANK_SHIFT                                  0
 173 #define         NOOFBANK_MASK                                   0x00000001
 174 #define         NOOFRANK_SHIFT                                  1
 175 #define         NOOFRANK_MASK                                   0x00000002
 176 #define         NOOFROWS_SHIFT                                  2
 177 #define         NOOFROWS_MASK                                   0x0000001C
 178 #define         NOOFCOLS_SHIFT                                  5
 179 #define         NOOFCOLS_MASK                                   0x00000060
 180 #define         CHANSIZE_SHIFT                                  7
 181 #define         CHANSIZE_MASK                                   0x00000080
 182 #define         BURSTLENGTH_SHIFT                               8
 183 #define         BURSTLENGTH_MASK                                0x00000100
 184 #define         CHANSIZE_OVERRIDE                               (1 << 10)
 185
 186 #define SQM_RATIO                                       0x2424
 187 #       define STATE0(x)                                ((x) << 0)
 188 #       define STATE0_MASK                              (0xff << 0)
 189 #       define STATE1(x)                                ((x) << 8)
 190 #       define STATE1_MASK                              (0xff << 8)
 191 #       define STATE2(x)                                ((x) << 16)
 192 #       define STATE2_MASK                              (0xff << 16)
 193 #       define STATE3(x)                                ((x) << 24)
 194 #       define STATE3_MASK                              (0xff << 24)
 195
 196 #define ARB_RFSH_CNTL                                   0x2460
 197 #       define ENABLE                                   (1 << 0)
 198 #define ARB_RFSH_RATE                                   0x2464
 199 #       define POWERMODE0(x)                            ((x) << 0)
 200 #       define POWERMODE0_MASK                          (0xff << 0)
 201 #       define POWERMODE1(x)                            ((x) << 8)
 202 #       define POWERMODE1_MASK                          (0xff << 8)
 203 #       define POWERMODE2(x)                            ((x) << 16)
 204 #       define POWERMODE2_MASK                          (0xff << 16)
 205 #       define POWERMODE3(x)                            ((x) << 24)
 206 #       define POWERMODE3_MASK                          (0xff << 24)
 207
 208 #define MC_SEQ_DRAM                                     0x2608
 209 #       define CKE_DYN                                  (1 << 12)
 210
 211 #define MC_SEQ_CMD                                      0x26c4
 212
 213 #define MC_SEQ_RESERVE_S                                0x2890
 214 #define MC_SEQ_RESERVE_M                                0x2894
 215
 216 #define LVTMA_DATA_SYNCHRONIZATION                      0x7adc
 217 #       define LVTMA_PFREQCHG                           (1 << 8)
 218 #define DCE3_LVTMA_DATA_SYNCHRONIZATION                 0x7f98
 219
 220 /* PCIE indirect regs */
 221 #define PCIE_P_CNTL                                       0x40
 222 #       define P_PLL_PWRDN_IN_L1L23                       (1 << 3)
 223 #       define P_PLL_BUF_PDNB                             (1 << 4)
 224 #       define P_PLL_PDNB                                 (1 << 9)
 225 #       define P_ALLOW_PRX_FRONTEND_SHUTOFF               (1 << 12)
 226 /* PCIE PORT indirect regs */
 227 #define PCIE_LC_CNTL                                      0xa0
 228 #       define LC_L0S_INACTIVITY(x)                       ((x) << 8)
 229 #       define LC_L0S_INACTIVITY_MASK                     (0xf << 8)
 230 #       define LC_L0S_INACTIVITY_SHIFT                    8
 231 #       define LC_L1_INACTIVITY(x)                        ((x) << 12)
 232 #       define LC_L1_INACTIVITY_MASK                      (0xf << 12)
 233 #       define LC_L1_INACTIVITY_SHIFT                     12
 234 #       define LC_PMI_TO_L1_DIS                           (1 << 16)
 235 #       define LC_ASPM_TO_L1_DIS                          (1 << 24)
 236 #define PCIE_LC_SPEED_CNTL                                0xa4
 237 #       define LC_GEN2_EN                                 (1 << 0)
 238 #       define LC_INITIATE_LINK_SPEED_CHANGE              (1 << 7)
 239 #       define LC_CURRENT_DATA_RATE                       (1 << 11)
 240 #       define LC_HW_VOLTAGE_IF_CONTROL(x)                ((x) << 12)
 241 #       define LC_HW_VOLTAGE_IF_CONTROL_MASK              (3 << 12)
 242 #       define LC_HW_VOLTAGE_IF_CONTROL_SHIFT             12
 243 #       define LC_OTHER_SIDE_EVER_SENT_GEN2               (1 << 23)
 244 #       define LC_OTHER_SIDE_SUPPORTS_GEN2                (1 << 24)
 245
 246 #endif