2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/firmware.h>
29 #include <linux/platform_device.h>
32 #include "radeon_drm.h"
37 #define R700_PFP_UCODE_SIZE 848
38 #define R700_PM4_UCODE_SIZE 1360
40 static void rv770_gpu_init(struct radeon_device
*rdev
);
41 void rv770_fini(struct radeon_device
*rdev
);
47 int rv770_pcie_gart_enable(struct radeon_device
*rdev
)
52 if (rdev
->gart
.table
.vram
.robj
== NULL
) {
53 dev_err(rdev
->dev
, "No VRAM object for PCIE GART.\n");
56 r
= radeon_gart_table_vram_pin(rdev
);
59 radeon_gart_restore(rdev
);
61 WREG32(VM_L2_CNTL
, ENABLE_L2_CACHE
| ENABLE_L2_FRAGMENT_PROCESSING
|
62 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE
|
63 EFFECTIVE_L2_QUEUE_SIZE(7));
64 WREG32(VM_L2_CNTL2
, 0);
65 WREG32(VM_L2_CNTL3
, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
66 /* Setup TLB control */
67 tmp
= ENABLE_L1_TLB
| ENABLE_L1_FRAGMENT_PROCESSING
|
68 SYSTEM_ACCESS_MODE_NOT_IN_SYS
|
69 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU
|
70 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
71 WREG32(MC_VM_MD_L1_TLB0_CNTL
, tmp
);
72 WREG32(MC_VM_MD_L1_TLB1_CNTL
, tmp
);
73 WREG32(MC_VM_MD_L1_TLB2_CNTL
, tmp
);
74 WREG32(MC_VM_MB_L1_TLB0_CNTL
, tmp
);
75 WREG32(MC_VM_MB_L1_TLB1_CNTL
, tmp
);
76 WREG32(MC_VM_MB_L1_TLB2_CNTL
, tmp
);
77 WREG32(MC_VM_MB_L1_TLB3_CNTL
, tmp
);
78 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR
, rdev
->mc
.gtt_start
>> 12);
79 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR
, rdev
->mc
.gtt_end
>> 12);
80 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR
, rdev
->gart
.table_addr
>> 12);
81 WREG32(VM_CONTEXT0_CNTL
, ENABLE_CONTEXT
| PAGE_TABLE_DEPTH(0) |
82 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT
);
83 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR
,
84 (u32
)(rdev
->dummy_page
.addr
>> 12));
85 for (i
= 1; i
< 7; i
++)
86 WREG32(VM_CONTEXT0_CNTL
+ (i
* 4), 0);
88 r600_pcie_gart_tlb_flush(rdev
);
89 rdev
->gart
.ready
= true;
93 void rv770_pcie_gart_disable(struct radeon_device
*rdev
)
98 /* Disable all tables */
99 for (i
= 0; i
< 7; i
++)
100 WREG32(VM_CONTEXT0_CNTL
+ (i
* 4), 0);
103 WREG32(VM_L2_CNTL
, ENABLE_L2_FRAGMENT_PROCESSING
|
104 EFFECTIVE_L2_QUEUE_SIZE(7));
105 WREG32(VM_L2_CNTL2
, 0);
106 WREG32(VM_L2_CNTL3
, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
107 /* Setup TLB control */
108 tmp
= EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
109 WREG32(MC_VM_MD_L1_TLB0_CNTL
, tmp
);
110 WREG32(MC_VM_MD_L1_TLB1_CNTL
, tmp
);
111 WREG32(MC_VM_MD_L1_TLB2_CNTL
, tmp
);
112 WREG32(MC_VM_MB_L1_TLB0_CNTL
, tmp
);
113 WREG32(MC_VM_MB_L1_TLB1_CNTL
, tmp
);
114 WREG32(MC_VM_MB_L1_TLB2_CNTL
, tmp
);
115 WREG32(MC_VM_MB_L1_TLB3_CNTL
, tmp
);
116 if (rdev
->gart
.table
.vram
.robj
) {
117 r
= radeon_bo_reserve(rdev
->gart
.table
.vram
.robj
, false);
118 if (likely(r
== 0)) {
119 radeon_bo_kunmap(rdev
->gart
.table
.vram
.robj
);
120 radeon_bo_unpin(rdev
->gart
.table
.vram
.robj
);
121 radeon_bo_unreserve(rdev
->gart
.table
.vram
.robj
);
126 void rv770_pcie_gart_fini(struct radeon_device
*rdev
)
128 rv770_pcie_gart_disable(rdev
);
129 radeon_gart_table_vram_free(rdev
);
130 radeon_gart_fini(rdev
);
134 void rv770_agp_enable(struct radeon_device
*rdev
)
140 WREG32(VM_L2_CNTL
, ENABLE_L2_CACHE
| ENABLE_L2_FRAGMENT_PROCESSING
|
141 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE
|
142 EFFECTIVE_L2_QUEUE_SIZE(7));
143 WREG32(VM_L2_CNTL2
, 0);
144 WREG32(VM_L2_CNTL3
, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
145 /* Setup TLB control */
146 tmp
= ENABLE_L1_TLB
| ENABLE_L1_FRAGMENT_PROCESSING
|
147 SYSTEM_ACCESS_MODE_NOT_IN_SYS
|
148 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU
|
149 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
150 WREG32(MC_VM_MD_L1_TLB0_CNTL
, tmp
);
151 WREG32(MC_VM_MD_L1_TLB1_CNTL
, tmp
);
152 WREG32(MC_VM_MD_L1_TLB2_CNTL
, tmp
);
153 WREG32(MC_VM_MB_L1_TLB0_CNTL
, tmp
);
154 WREG32(MC_VM_MB_L1_TLB1_CNTL
, tmp
);
155 WREG32(MC_VM_MB_L1_TLB2_CNTL
, tmp
);
156 WREG32(MC_VM_MB_L1_TLB3_CNTL
, tmp
);
157 for (i
= 0; i
< 7; i
++)
158 WREG32(VM_CONTEXT0_CNTL
+ (i
* 4), 0);
161 static void rv770_mc_program(struct radeon_device
*rdev
)
163 struct rv515_mc_save save
;
168 for (i
= 0, j
= 0; i
< 32; i
++, j
+= 0x18) {
169 WREG32((0x2c14 + j
), 0x00000000);
170 WREG32((0x2c18 + j
), 0x00000000);
171 WREG32((0x2c1c + j
), 0x00000000);
172 WREG32((0x2c20 + j
), 0x00000000);
173 WREG32((0x2c24 + j
), 0x00000000);
175 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL
, 0);
177 rv515_mc_stop(rdev
, &save
);
178 if (r600_mc_wait_for_idle(rdev
)) {
179 dev_warn(rdev
->dev
, "Wait for MC idle timedout !\n");
181 /* Lockout access through VGA aperture*/
182 WREG32(VGA_HDP_CONTROL
, VGA_MEMORY_DISABLE
);
183 /* Update configuration */
184 if (rdev
->flags
& RADEON_IS_AGP
) {
185 if (rdev
->mc
.vram_start
< rdev
->mc
.gtt_start
) {
186 /* VRAM before AGP */
187 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR
,
188 rdev
->mc
.vram_start
>> 12);
189 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR
,
190 rdev
->mc
.gtt_end
>> 12);
193 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR
,
194 rdev
->mc
.gtt_start
>> 12);
195 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR
,
196 rdev
->mc
.vram_end
>> 12);
199 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR
,
200 rdev
->mc
.vram_start
>> 12);
201 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR
,
202 rdev
->mc
.vram_end
>> 12);
204 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR
, 0);
205 tmp
= ((rdev
->mc
.vram_end
>> 24) & 0xFFFF) << 16;
206 tmp
|= ((rdev
->mc
.vram_start
>> 24) & 0xFFFF);
207 WREG32(MC_VM_FB_LOCATION
, tmp
);
208 WREG32(HDP_NONSURFACE_BASE
, (rdev
->mc
.vram_start
>> 8));
209 WREG32(HDP_NONSURFACE_INFO
, (2 << 7));
210 WREG32(HDP_NONSURFACE_SIZE
, (rdev
->mc
.mc_vram_size
- 1) | 0x3FF);
211 if (rdev
->flags
& RADEON_IS_AGP
) {
212 WREG32(MC_VM_AGP_TOP
, rdev
->mc
.gtt_end
>> 16);
213 WREG32(MC_VM_AGP_BOT
, rdev
->mc
.gtt_start
>> 16);
214 WREG32(MC_VM_AGP_BASE
, rdev
->mc
.agp_base
>> 22);
216 WREG32(MC_VM_AGP_BASE
, 0);
217 WREG32(MC_VM_AGP_TOP
, 0x0FFFFFFF);
218 WREG32(MC_VM_AGP_BOT
, 0x0FFFFFFF);
220 if (r600_mc_wait_for_idle(rdev
)) {
221 dev_warn(rdev
->dev
, "Wait for MC idle timedout !\n");
223 rv515_mc_resume(rdev
, &save
);
224 /* we need to own VRAM, so turn off the VGA renderer here
225 * to stop it overwriting our objects */
226 rv515_vga_render_disable(rdev
);
233 void r700_cp_stop(struct radeon_device
*rdev
)
235 WREG32(CP_ME_CNTL
, (CP_ME_HALT
| CP_PFP_HALT
));
239 static int rv770_cp_load_microcode(struct radeon_device
*rdev
)
241 const __be32
*fw_data
;
244 if (!rdev
->me_fw
|| !rdev
->pfp_fw
)
248 WREG32(CP_RB_CNTL
, RB_NO_UPDATE
| (15 << 8) | (3 << 0));
251 WREG32(GRBM_SOFT_RESET
, SOFT_RESET_CP
);
252 RREG32(GRBM_SOFT_RESET
);
254 WREG32(GRBM_SOFT_RESET
, 0);
256 fw_data
= (const __be32
*)rdev
->pfp_fw
->data
;
257 WREG32(CP_PFP_UCODE_ADDR
, 0);
258 for (i
= 0; i
< R700_PFP_UCODE_SIZE
; i
++)
259 WREG32(CP_PFP_UCODE_DATA
, be32_to_cpup(fw_data
++));
260 WREG32(CP_PFP_UCODE_ADDR
, 0);
262 fw_data
= (const __be32
*)rdev
->me_fw
->data
;
263 WREG32(CP_ME_RAM_WADDR
, 0);
264 for (i
= 0; i
< R700_PM4_UCODE_SIZE
; i
++)
265 WREG32(CP_ME_RAM_DATA
, be32_to_cpup(fw_data
++));
267 WREG32(CP_PFP_UCODE_ADDR
, 0);
268 WREG32(CP_ME_RAM_WADDR
, 0);
269 WREG32(CP_ME_RAM_RADDR
, 0);
277 static u32
r700_get_tile_pipe_to_backend_map(struct radeon_device
*rdev
,
280 u32 backend_disable_mask
)
283 u32 enabled_backends_mask
;
284 u32 enabled_backends_count
;
286 u32 swizzle_pipe
[R7XX_MAX_PIPES
];
289 bool force_no_swizzle
;
291 if (num_tile_pipes
> R7XX_MAX_PIPES
)
292 num_tile_pipes
= R7XX_MAX_PIPES
;
293 if (num_tile_pipes
< 1)
295 if (num_backends
> R7XX_MAX_BACKENDS
)
296 num_backends
= R7XX_MAX_BACKENDS
;
297 if (num_backends
< 1)
300 enabled_backends_mask
= 0;
301 enabled_backends_count
= 0;
302 for (i
= 0; i
< R7XX_MAX_BACKENDS
; ++i
) {
303 if (((backend_disable_mask
>> i
) & 1) == 0) {
304 enabled_backends_mask
|= (1 << i
);
305 ++enabled_backends_count
;
307 if (enabled_backends_count
== num_backends
)
311 if (enabled_backends_count
== 0) {
312 enabled_backends_mask
= 1;
313 enabled_backends_count
= 1;
316 if (enabled_backends_count
!= num_backends
)
317 num_backends
= enabled_backends_count
;
319 switch (rdev
->family
) {
322 force_no_swizzle
= false;
327 force_no_swizzle
= true;
331 memset((uint8_t *)&swizzle_pipe
[0], 0, sizeof(u32
) * R7XX_MAX_PIPES
);
332 switch (num_tile_pipes
) {
341 if (force_no_swizzle
) {
352 if (force_no_swizzle
) {
365 if (force_no_swizzle
) {
380 if (force_no_swizzle
) {
397 if (force_no_swizzle
) {
416 if (force_no_swizzle
) {
439 for (cur_pipe
= 0; cur_pipe
< num_tile_pipes
; ++cur_pipe
) {
440 while (((1 << cur_backend
) & enabled_backends_mask
) == 0)
441 cur_backend
= (cur_backend
+ 1) % R7XX_MAX_BACKENDS
;
443 backend_map
|= (u32
)(((cur_backend
& 3) << (swizzle_pipe
[cur_pipe
] * 2)));
445 cur_backend
= (cur_backend
+ 1) % R7XX_MAX_BACKENDS
;
451 static void rv770_gpu_init(struct radeon_device
*rdev
)
453 int i
, j
, num_qd_pipes
;
458 u32 num_gs_verts_per_thread
;
460 u32 gs_prim_buffer_depth
= 0;
461 u32 sq_ms_fifo_sizes
;
463 u32 sq_thread_resource_mgmt
;
464 u32 hdp_host_path_cntl
;
465 u32 sq_dyn_gpr_size_simd_ab_0
;
467 u32 gb_tiling_config
= 0;
468 u32 cc_rb_backend_disable
= 0;
469 u32 cc_gc_shader_pipe_config
= 0;
473 /* setup chip specs */
474 switch (rdev
->family
) {
476 rdev
->config
.rv770
.max_pipes
= 4;
477 rdev
->config
.rv770
.max_tile_pipes
= 8;
478 rdev
->config
.rv770
.max_simds
= 10;
479 rdev
->config
.rv770
.max_backends
= 4;
480 rdev
->config
.rv770
.max_gprs
= 256;
481 rdev
->config
.rv770
.max_threads
= 248;
482 rdev
->config
.rv770
.max_stack_entries
= 512;
483 rdev
->config
.rv770
.max_hw_contexts
= 8;
484 rdev
->config
.rv770
.max_gs_threads
= 16 * 2;
485 rdev
->config
.rv770
.sx_max_export_size
= 128;
486 rdev
->config
.rv770
.sx_max_export_pos_size
= 16;
487 rdev
->config
.rv770
.sx_max_export_smx_size
= 112;
488 rdev
->config
.rv770
.sq_num_cf_insts
= 2;
490 rdev
->config
.rv770
.sx_num_of_sets
= 7;
491 rdev
->config
.rv770
.sc_prim_fifo_size
= 0xF9;
492 rdev
->config
.rv770
.sc_hiz_tile_fifo_size
= 0x30;
493 rdev
->config
.rv770
.sc_earlyz_tile_fifo_fize
= 0x130;
496 rdev
->config
.rv770
.max_pipes
= 2;
497 rdev
->config
.rv770
.max_tile_pipes
= 4;
498 rdev
->config
.rv770
.max_simds
= 8;
499 rdev
->config
.rv770
.max_backends
= 2;
500 rdev
->config
.rv770
.max_gprs
= 128;
501 rdev
->config
.rv770
.max_threads
= 248;
502 rdev
->config
.rv770
.max_stack_entries
= 256;
503 rdev
->config
.rv770
.max_hw_contexts
= 8;
504 rdev
->config
.rv770
.max_gs_threads
= 16 * 2;
505 rdev
->config
.rv770
.sx_max_export_size
= 256;
506 rdev
->config
.rv770
.sx_max_export_pos_size
= 32;
507 rdev
->config
.rv770
.sx_max_export_smx_size
= 224;
508 rdev
->config
.rv770
.sq_num_cf_insts
= 2;
510 rdev
->config
.rv770
.sx_num_of_sets
= 7;
511 rdev
->config
.rv770
.sc_prim_fifo_size
= 0xf9;
512 rdev
->config
.rv770
.sc_hiz_tile_fifo_size
= 0x30;
513 rdev
->config
.rv770
.sc_earlyz_tile_fifo_fize
= 0x130;
514 if (rdev
->config
.rv770
.sx_max_export_pos_size
> 16) {
515 rdev
->config
.rv770
.sx_max_export_pos_size
-= 16;
516 rdev
->config
.rv770
.sx_max_export_smx_size
+= 16;
520 rdev
->config
.rv770
.max_pipes
= 2;
521 rdev
->config
.rv770
.max_tile_pipes
= 2;
522 rdev
->config
.rv770
.max_simds
= 2;
523 rdev
->config
.rv770
.max_backends
= 1;
524 rdev
->config
.rv770
.max_gprs
= 256;
525 rdev
->config
.rv770
.max_threads
= 192;
526 rdev
->config
.rv770
.max_stack_entries
= 256;
527 rdev
->config
.rv770
.max_hw_contexts
= 4;
528 rdev
->config
.rv770
.max_gs_threads
= 8 * 2;
529 rdev
->config
.rv770
.sx_max_export_size
= 128;
530 rdev
->config
.rv770
.sx_max_export_pos_size
= 16;
531 rdev
->config
.rv770
.sx_max_export_smx_size
= 112;
532 rdev
->config
.rv770
.sq_num_cf_insts
= 1;
534 rdev
->config
.rv770
.sx_num_of_sets
= 7;
535 rdev
->config
.rv770
.sc_prim_fifo_size
= 0x40;
536 rdev
->config
.rv770
.sc_hiz_tile_fifo_size
= 0x30;
537 rdev
->config
.rv770
.sc_earlyz_tile_fifo_fize
= 0x130;
540 rdev
->config
.rv770
.max_pipes
= 4;
541 rdev
->config
.rv770
.max_tile_pipes
= 4;
542 rdev
->config
.rv770
.max_simds
= 8;
543 rdev
->config
.rv770
.max_backends
= 4;
544 rdev
->config
.rv770
.max_gprs
= 256;
545 rdev
->config
.rv770
.max_threads
= 248;
546 rdev
->config
.rv770
.max_stack_entries
= 512;
547 rdev
->config
.rv770
.max_hw_contexts
= 8;
548 rdev
->config
.rv770
.max_gs_threads
= 16 * 2;
549 rdev
->config
.rv770
.sx_max_export_size
= 256;
550 rdev
->config
.rv770
.sx_max_export_pos_size
= 32;
551 rdev
->config
.rv770
.sx_max_export_smx_size
= 224;
552 rdev
->config
.rv770
.sq_num_cf_insts
= 2;
554 rdev
->config
.rv770
.sx_num_of_sets
= 7;
555 rdev
->config
.rv770
.sc_prim_fifo_size
= 0x100;
556 rdev
->config
.rv770
.sc_hiz_tile_fifo_size
= 0x30;
557 rdev
->config
.rv770
.sc_earlyz_tile_fifo_fize
= 0x130;
559 if (rdev
->config
.rv770
.sx_max_export_pos_size
> 16) {
560 rdev
->config
.rv770
.sx_max_export_pos_size
-= 16;
561 rdev
->config
.rv770
.sx_max_export_smx_size
+= 16;
570 for (i
= 0; i
< 32; i
++) {
571 WREG32((0x2c14 + j
), 0x00000000);
572 WREG32((0x2c18 + j
), 0x00000000);
573 WREG32((0x2c1c + j
), 0x00000000);
574 WREG32((0x2c20 + j
), 0x00000000);
575 WREG32((0x2c24 + j
), 0x00000000);
579 WREG32(GRBM_CNTL
, GRBM_READ_TIMEOUT(0xff));
581 /* setup tiling, simd, pipe config */
582 mc_arb_ramcfg
= RREG32(MC_ARB_RAMCFG
);
584 switch (rdev
->config
.rv770
.max_tile_pipes
) {
587 gb_tiling_config
|= PIPE_TILING(0);
590 gb_tiling_config
|= PIPE_TILING(1);
593 gb_tiling_config
|= PIPE_TILING(2);
596 gb_tiling_config
|= PIPE_TILING(3);
599 rdev
->config
.rv770
.tiling_npipes
= rdev
->config
.rv770
.max_tile_pipes
;
601 if (rdev
->family
== CHIP_RV770
)
602 gb_tiling_config
|= BANK_TILING(1);
604 gb_tiling_config
|= BANK_TILING((mc_arb_ramcfg
& NOOFBANK_MASK
) >> NOOFBANK_SHIFT
);
605 rdev
->config
.rv770
.tiling_nbanks
= 4 << ((gb_tiling_config
>> 4) & 0x3);
607 gb_tiling_config
|= GROUP_SIZE(0);
608 rdev
->config
.rv770
.tiling_group_size
= 256;
610 if (((mc_arb_ramcfg
& NOOFROWS_MASK
) >> NOOFROWS_SHIFT
) > 3) {
611 gb_tiling_config
|= ROW_TILING(3);
612 gb_tiling_config
|= SAMPLE_SPLIT(3);
615 ROW_TILING(((mc_arb_ramcfg
& NOOFROWS_MASK
) >> NOOFROWS_SHIFT
));
617 SAMPLE_SPLIT(((mc_arb_ramcfg
& NOOFROWS_MASK
) >> NOOFROWS_SHIFT
));
620 gb_tiling_config
|= BANK_SWAPS(1);
622 cc_rb_backend_disable
= RREG32(CC_RB_BACKEND_DISABLE
) & 0x00ff0000;
623 cc_rb_backend_disable
|=
624 BACKEND_DISABLE((R7XX_MAX_BACKENDS_MASK
<< rdev
->config
.rv770
.max_backends
) & R7XX_MAX_BACKENDS_MASK
);
626 cc_gc_shader_pipe_config
= RREG32(CC_GC_SHADER_PIPE_CONFIG
) & 0xffffff00;
627 cc_gc_shader_pipe_config
|=
628 INACTIVE_QD_PIPES((R7XX_MAX_PIPES_MASK
<< rdev
->config
.rv770
.max_pipes
) & R7XX_MAX_PIPES_MASK
);
629 cc_gc_shader_pipe_config
|=
630 INACTIVE_SIMDS((R7XX_MAX_SIMDS_MASK
<< rdev
->config
.rv770
.max_simds
) & R7XX_MAX_SIMDS_MASK
);
632 if (rdev
->family
== CHIP_RV740
)
635 backend_map
= r700_get_tile_pipe_to_backend_map(rdev
,
636 rdev
->config
.rv770
.max_tile_pipes
,
638 r600_count_pipe_bits((cc_rb_backend_disable
&
639 R7XX_MAX_BACKENDS_MASK
) >> 16)),
640 (cc_rb_backend_disable
>> 16));
641 gb_tiling_config
|= BACKEND_MAP(backend_map
);
644 WREG32(GB_TILING_CONFIG
, gb_tiling_config
);
645 WREG32(DCP_TILING_CONFIG
, (gb_tiling_config
& 0xffff));
646 WREG32(HDP_TILING_CONFIG
, (gb_tiling_config
& 0xffff));
648 WREG32(CC_RB_BACKEND_DISABLE
, cc_rb_backend_disable
);
649 WREG32(CC_GC_SHADER_PIPE_CONFIG
, cc_gc_shader_pipe_config
);
650 WREG32(CC_SYS_RB_BACKEND_DISABLE
, cc_rb_backend_disable
);
652 WREG32(CGTS_SYS_TCC_DISABLE
, 0);
653 WREG32(CGTS_TCC_DISABLE
, 0);
656 R7XX_MAX_PIPES
- r600_count_pipe_bits((cc_gc_shader_pipe_config
& INACTIVE_QD_PIPES_MASK
) >> 8);
657 WREG32(VGT_OUT_DEALLOC_CNTL
, (num_qd_pipes
* 4) & DEALLOC_DIST_MASK
);
658 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL
, ((num_qd_pipes
* 4) - 2) & VTX_REUSE_DEPTH_MASK
);
660 /* set HW defaults for 3D engine */
661 WREG32(CP_QUEUE_THRESHOLDS
, (ROQ_IB1_START(0x16) |
662 ROQ_IB2_START(0x2b)));
664 WREG32(CP_MEQ_THRESHOLDS
, STQ_SPLIT(0x30));
666 ta_aux_cntl
= RREG32(TA_CNTL_AUX
);
667 WREG32(TA_CNTL_AUX
, ta_aux_cntl
| DISABLE_CUBE_ANISO
);
669 sx_debug_1
= RREG32(SX_DEBUG_1
);
670 sx_debug_1
|= ENABLE_NEW_SMX_ADDRESS
;
671 WREG32(SX_DEBUG_1
, sx_debug_1
);
673 smx_dc_ctl0
= RREG32(SMX_DC_CTL0
);
674 smx_dc_ctl0
&= ~CACHE_DEPTH(0x1ff);
675 smx_dc_ctl0
|= CACHE_DEPTH((rdev
->config
.rv770
.sx_num_of_sets
* 64) - 1);
676 WREG32(SMX_DC_CTL0
, smx_dc_ctl0
);
678 if (rdev
->family
!= CHIP_RV740
)
679 WREG32(SMX_EVENT_CTL
, (ES_FLUSH_CTL(4) |
684 db_debug3
= RREG32(DB_DEBUG3
);
685 db_debug3
&= ~DB_CLK_OFF_DELAY(0x1f);
686 switch (rdev
->family
) {
689 db_debug3
|= DB_CLK_OFF_DELAY(0x1f);
694 db_debug3
|= DB_CLK_OFF_DELAY(2);
697 WREG32(DB_DEBUG3
, db_debug3
);
699 if (rdev
->family
!= CHIP_RV770
) {
700 db_debug4
= RREG32(DB_DEBUG4
);
701 db_debug4
|= DISABLE_TILE_COVERED_FOR_PS_ITER
;
702 WREG32(DB_DEBUG4
, db_debug4
);
705 WREG32(SX_EXPORT_BUFFER_SIZES
, (COLOR_BUFFER_SIZE((rdev
->config
.rv770
.sx_max_export_size
/ 4) - 1) |
706 POSITION_BUFFER_SIZE((rdev
->config
.rv770
.sx_max_export_pos_size
/ 4) - 1) |
707 SMX_BUFFER_SIZE((rdev
->config
.rv770
.sx_max_export_smx_size
/ 4) - 1)));
709 WREG32(PA_SC_FIFO_SIZE
, (SC_PRIM_FIFO_SIZE(rdev
->config
.rv770
.sc_prim_fifo_size
) |
710 SC_HIZ_TILE_FIFO_SIZE(rdev
->config
.rv770
.sc_hiz_tile_fifo_size
) |
711 SC_EARLYZ_TILE_FIFO_SIZE(rdev
->config
.rv770
.sc_earlyz_tile_fifo_fize
)));
713 WREG32(PA_SC_MULTI_CHIP_CNTL
, 0);
715 WREG32(VGT_NUM_INSTANCES
, 1);
717 WREG32(SPI_CONFIG_CNTL
, GPR_WRITE_PRIORITY(0));
719 WREG32(SPI_CONFIG_CNTL_1
, VTX_DONE_DELAY(4));
721 WREG32(CP_PERFMON_CNTL
, 0);
723 sq_ms_fifo_sizes
= (CACHE_FIFO_SIZE(16 * rdev
->config
.rv770
.sq_num_cf_insts
) |
724 DONE_FIFO_HIWATER(0xe0) |
725 ALU_UPDATE_FIFO_HIWATER(0x8));
726 switch (rdev
->family
) {
730 sq_ms_fifo_sizes
|= FETCH_FIFO_HIWATER(0x1);
734 sq_ms_fifo_sizes
|= FETCH_FIFO_HIWATER(0x4);
737 WREG32(SQ_MS_FIFO_SIZES
, sq_ms_fifo_sizes
);
739 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
740 * should be adjusted as needed by the 2D/3D drivers. This just sets default values
742 sq_config
= RREG32(SQ_CONFIG
);
743 sq_config
&= ~(PS_PRIO(3) |
747 sq_config
|= (DX9_CONSTS
|
754 if (rdev
->family
== CHIP_RV710
)
755 /* no vertex cache */
756 sq_config
&= ~VC_ENABLE
;
758 WREG32(SQ_CONFIG
, sq_config
);
760 WREG32(SQ_GPR_RESOURCE_MGMT_1
, (NUM_PS_GPRS((rdev
->config
.rv770
.max_gprs
* 24)/64) |
761 NUM_VS_GPRS((rdev
->config
.rv770
.max_gprs
* 24)/64) |
762 NUM_CLAUSE_TEMP_GPRS(((rdev
->config
.rv770
.max_gprs
* 24)/64)/2)));
764 WREG32(SQ_GPR_RESOURCE_MGMT_2
, (NUM_GS_GPRS((rdev
->config
.rv770
.max_gprs
* 7)/64) |
765 NUM_ES_GPRS((rdev
->config
.rv770
.max_gprs
* 7)/64)));
767 sq_thread_resource_mgmt
= (NUM_PS_THREADS((rdev
->config
.rv770
.max_threads
* 4)/8) |
768 NUM_VS_THREADS((rdev
->config
.rv770
.max_threads
* 2)/8) |
769 NUM_ES_THREADS((rdev
->config
.rv770
.max_threads
* 1)/8));
770 if (((rdev
->config
.rv770
.max_threads
* 1) / 8) > rdev
->config
.rv770
.max_gs_threads
)
771 sq_thread_resource_mgmt
|= NUM_GS_THREADS(rdev
->config
.rv770
.max_gs_threads
);
773 sq_thread_resource_mgmt
|= NUM_GS_THREADS((rdev
->config
.rv770
.max_gs_threads
* 1)/8);
774 WREG32(SQ_THREAD_RESOURCE_MGMT
, sq_thread_resource_mgmt
);
776 WREG32(SQ_STACK_RESOURCE_MGMT_1
, (NUM_PS_STACK_ENTRIES((rdev
->config
.rv770
.max_stack_entries
* 1)/4) |
777 NUM_VS_STACK_ENTRIES((rdev
->config
.rv770
.max_stack_entries
* 1)/4)));
779 WREG32(SQ_STACK_RESOURCE_MGMT_2
, (NUM_GS_STACK_ENTRIES((rdev
->config
.rv770
.max_stack_entries
* 1)/4) |
780 NUM_ES_STACK_ENTRIES((rdev
->config
.rv770
.max_stack_entries
* 1)/4)));
782 sq_dyn_gpr_size_simd_ab_0
= (SIMDA_RING0((rdev
->config
.rv770
.max_gprs
* 38)/64) |
783 SIMDA_RING1((rdev
->config
.rv770
.max_gprs
* 38)/64) |
784 SIMDB_RING0((rdev
->config
.rv770
.max_gprs
* 38)/64) |
785 SIMDB_RING1((rdev
->config
.rv770
.max_gprs
* 38)/64));
787 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_0
, sq_dyn_gpr_size_simd_ab_0
);
788 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_1
, sq_dyn_gpr_size_simd_ab_0
);
789 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_2
, sq_dyn_gpr_size_simd_ab_0
);
790 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_3
, sq_dyn_gpr_size_simd_ab_0
);
791 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_4
, sq_dyn_gpr_size_simd_ab_0
);
792 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_5
, sq_dyn_gpr_size_simd_ab_0
);
793 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_6
, sq_dyn_gpr_size_simd_ab_0
);
794 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_7
, sq_dyn_gpr_size_simd_ab_0
);
796 WREG32(PA_SC_FORCE_EOV_MAX_CNTS
, (FORCE_EOV_MAX_CLK_CNT(4095) |
797 FORCE_EOV_MAX_REZ_CNT(255)));
799 if (rdev
->family
== CHIP_RV710
)
800 WREG32(VGT_CACHE_INVALIDATION
, (CACHE_INVALIDATION(TC_ONLY
) |
801 AUTO_INVLD_EN(ES_AND_GS_AUTO
)));
803 WREG32(VGT_CACHE_INVALIDATION
, (CACHE_INVALIDATION(VC_AND_TC
) |
804 AUTO_INVLD_EN(ES_AND_GS_AUTO
)));
806 switch (rdev
->family
) {
810 gs_prim_buffer_depth
= 384;
813 gs_prim_buffer_depth
= 128;
819 num_gs_verts_per_thread
= rdev
->config
.rv770
.max_pipes
* 16;
820 vgt_gs_per_es
= gs_prim_buffer_depth
+ num_gs_verts_per_thread
;
821 /* Max value for this is 256 */
822 if (vgt_gs_per_es
> 256)
825 WREG32(VGT_ES_PER_GS
, 128);
826 WREG32(VGT_GS_PER_ES
, vgt_gs_per_es
);
827 WREG32(VGT_GS_PER_VS
, 2);
829 /* more default values. 2D/3D driver should adjust as needed */
830 WREG32(VGT_GS_VERTEX_REUSE
, 16);
831 WREG32(PA_SC_LINE_STIPPLE_STATE
, 0);
832 WREG32(VGT_STRMOUT_EN
, 0);
834 WREG32(PA_SC_MODE_CNTL
, 0);
835 WREG32(PA_SC_EDGERULE
, 0xaaaaaaaa);
836 WREG32(PA_SC_AA_CONFIG
, 0);
837 WREG32(PA_SC_CLIPRECT_RULE
, 0xffff);
838 WREG32(PA_SC_LINE_STIPPLE
, 0);
839 WREG32(SPI_INPUT_Z
, 0);
840 WREG32(SPI_PS_IN_CONTROL_0
, NUM_INTERP(2));
841 WREG32(CB_COLOR7_FRAG
, 0);
843 /* clear render buffer base addresses */
844 WREG32(CB_COLOR0_BASE
, 0);
845 WREG32(CB_COLOR1_BASE
, 0);
846 WREG32(CB_COLOR2_BASE
, 0);
847 WREG32(CB_COLOR3_BASE
, 0);
848 WREG32(CB_COLOR4_BASE
, 0);
849 WREG32(CB_COLOR5_BASE
, 0);
850 WREG32(CB_COLOR6_BASE
, 0);
851 WREG32(CB_COLOR7_BASE
, 0);
855 hdp_host_path_cntl
= RREG32(HDP_HOST_PATH_CNTL
);
856 WREG32(HDP_HOST_PATH_CNTL
, hdp_host_path_cntl
);
858 WREG32(PA_SC_MULTI_CHIP_CNTL
, 0);
860 WREG32(PA_CL_ENHANCE
, (CLIP_VTX_REORDER_ENA
|
865 int rv770_mc_init(struct radeon_device
*rdev
)
869 int chansize
, numchan
;
871 /* Get VRAM informations */
872 rdev
->mc
.vram_is_ddr
= true;
873 tmp
= RREG32(MC_ARB_RAMCFG
);
874 if (tmp
& CHANSIZE_OVERRIDE
) {
876 } else if (tmp
& CHANSIZE_MASK
) {
881 tmp
= RREG32(MC_SHARED_CHMAP
);
882 switch ((tmp
& NOOFCHAN_MASK
) >> NOOFCHAN_SHIFT
) {
897 rdev
->mc
.vram_width
= numchan
* chansize
;
898 /* Could aper size report 0 ? */
899 rdev
->mc
.aper_base
= drm_get_resource_start(rdev
->ddev
, 0);
900 rdev
->mc
.aper_size
= drm_get_resource_len(rdev
->ddev
, 0);
901 /* Setup GPU memory space */
902 rdev
->mc
.mc_vram_size
= RREG32(CONFIG_MEMSIZE
);
903 rdev
->mc
.real_vram_size
= RREG32(CONFIG_MEMSIZE
);
904 rdev
->mc
.visible_vram_size
= rdev
->mc
.aper_size
;
905 /* FIXME remove this once we support unmappable VRAM */
906 if (rdev
->mc
.mc_vram_size
> rdev
->mc
.aper_size
) {
907 rdev
->mc
.mc_vram_size
= rdev
->mc
.aper_size
;
908 rdev
->mc
.real_vram_size
= rdev
->mc
.aper_size
;
910 r600_vram_gtt_location(rdev
, &rdev
->mc
);
911 /* FIXME: we should enforce default clock in case GPU is not in
914 a
.full
= rfixed_const(100);
915 rdev
->pm
.sclk
.full
= rfixed_const(rdev
->clock
.default_sclk
);
916 rdev
->pm
.sclk
.full
= rfixed_div(rdev
->pm
.sclk
, a
);
920 int rv770_gpu_reset(struct radeon_device
*rdev
)
922 /* FIXME: implement any rv770 specific bits */
923 return r600_gpu_reset(rdev
);
926 static int rv770_startup(struct radeon_device
*rdev
)
930 if (!rdev
->me_fw
|| !rdev
->pfp_fw
|| !rdev
->rlc_fw
) {
931 r
= r600_init_microcode(rdev
);
933 DRM_ERROR("Failed to load firmware!\n");
938 rv770_mc_program(rdev
);
939 if (rdev
->flags
& RADEON_IS_AGP
) {
940 rv770_agp_enable(rdev
);
942 r
= rv770_pcie_gart_enable(rdev
);
946 rv770_gpu_init(rdev
);
947 r
= r600_blit_init(rdev
);
949 r600_blit_fini(rdev
);
950 rdev
->asic
->copy
= NULL
;
951 dev_warn(rdev
->dev
, "failed blitter (%d) falling back to memcpy\n", r
);
953 /* pin copy shader into vram */
954 if (rdev
->r600_blit
.shader_obj
) {
955 r
= radeon_bo_reserve(rdev
->r600_blit
.shader_obj
, false);
956 if (unlikely(r
!= 0))
958 r
= radeon_bo_pin(rdev
->r600_blit
.shader_obj
, RADEON_GEM_DOMAIN_VRAM
,
959 &rdev
->r600_blit
.shader_gpu_addr
);
960 radeon_bo_unreserve(rdev
->r600_blit
.shader_obj
);
962 DRM_ERROR("failed to pin blit object %d\n", r
);
967 r
= r600_irq_init(rdev
);
969 DRM_ERROR("radeon: IH init failed (%d).\n", r
);
970 radeon_irq_kms_fini(rdev
);
975 r
= radeon_ring_init(rdev
, rdev
->cp
.ring_size
);
978 r
= rv770_cp_load_microcode(rdev
);
981 r
= r600_cp_resume(rdev
);
984 /* write back buffer are not vital so don't worry about failure */
985 r600_wb_enable(rdev
);
989 int rv770_resume(struct radeon_device
*rdev
)
993 /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
994 * posting will perform necessary task to bring back GPU into good
998 atom_asic_init(rdev
->mode_info
.atom_context
);
999 /* Initialize clocks */
1000 r
= radeon_clocks_init(rdev
);
1005 r
= rv770_startup(rdev
);
1007 DRM_ERROR("r600 startup failed on resume\n");
1011 r
= r600_ib_test(rdev
);
1013 DRM_ERROR("radeon: failled testing IB (%d).\n", r
);
1020 int rv770_suspend(struct radeon_device
*rdev
)
1024 /* FIXME: we should wait for ring to be empty */
1026 rdev
->cp
.ready
= false;
1027 r600_irq_suspend(rdev
);
1028 r600_wb_disable(rdev
);
1029 rv770_pcie_gart_disable(rdev
);
1030 /* unpin shaders bo */
1031 if (rdev
->r600_blit
.shader_obj
) {
1032 r
= radeon_bo_reserve(rdev
->r600_blit
.shader_obj
, false);
1033 if (likely(r
== 0)) {
1034 radeon_bo_unpin(rdev
->r600_blit
.shader_obj
);
1035 radeon_bo_unreserve(rdev
->r600_blit
.shader_obj
);
1041 /* Plan is to move initialization in that function and use
1042 * helper function so that radeon_device_init pretty much
1043 * do nothing more than calling asic specific function. This
1044 * should also allow to remove a bunch of callback function
1047 int rv770_init(struct radeon_device
*rdev
)
1051 r
= radeon_dummy_page_init(rdev
);
1054 /* This don't do much */
1055 r
= radeon_gem_init(rdev
);
1059 if (!radeon_get_bios(rdev
)) {
1060 if (ASIC_IS_AVIVO(rdev
))
1063 /* Must be an ATOMBIOS */
1064 if (!rdev
->is_atom_bios
) {
1065 dev_err(rdev
->dev
, "Expecting atombios for R600 GPU\n");
1068 r
= radeon_atombios_init(rdev
);
1071 /* Post card if necessary */
1072 if (!r600_card_posted(rdev
)) {
1074 dev_err(rdev
->dev
, "Card not posted and no BIOS - ignoring\n");
1077 DRM_INFO("GPU not posted. posting now...\n");
1078 atom_asic_init(rdev
->mode_info
.atom_context
);
1080 /* Initialize scratch registers */
1081 r600_scratch_init(rdev
);
1082 /* Initialize surface registers */
1083 radeon_surface_init(rdev
);
1084 /* Initialize clocks */
1085 radeon_get_clock_info(rdev
->ddev
);
1086 r
= radeon_clocks_init(rdev
);
1089 /* Initialize power management */
1090 radeon_pm_init(rdev
);
1092 r
= radeon_fence_driver_init(rdev
);
1095 /* initialize AGP */
1096 if (rdev
->flags
& RADEON_IS_AGP
) {
1097 r
= radeon_agp_init(rdev
);
1099 radeon_agp_disable(rdev
);
1101 r
= rv770_mc_init(rdev
);
1104 /* Memory manager */
1105 r
= radeon_bo_init(rdev
);
1109 r
= radeon_irq_kms_init(rdev
);
1113 rdev
->cp
.ring_obj
= NULL
;
1114 r600_ring_init(rdev
, 1024 * 1024);
1116 rdev
->ih
.ring_obj
= NULL
;
1117 r600_ih_ring_init(rdev
, 64 * 1024);
1119 r
= r600_pcie_gart_init(rdev
);
1123 rdev
->accel_working
= true;
1124 r
= rv770_startup(rdev
);
1126 dev_err(rdev
->dev
, "disabling GPU acceleration\n");
1129 r600_irq_fini(rdev
);
1130 radeon_irq_kms_fini(rdev
);
1131 rv770_pcie_gart_fini(rdev
);
1132 rdev
->accel_working
= false;
1134 if (rdev
->accel_working
) {
1135 r
= radeon_ib_pool_init(rdev
);
1137 dev_err(rdev
->dev
, "IB initialization failed (%d).\n", r
);
1138 rdev
->accel_working
= false;
1140 r
= r600_ib_test(rdev
);
1142 dev_err(rdev
->dev
, "IB test failed (%d).\n", r
);
1143 rdev
->accel_working
= false;
1150 void rv770_fini(struct radeon_device
*rdev
)
1152 r600_blit_fini(rdev
);
1155 r600_irq_fini(rdev
);
1156 radeon_irq_kms_fini(rdev
);
1157 rv770_pcie_gart_fini(rdev
);
1158 radeon_gem_fini(rdev
);
1159 radeon_fence_driver_fini(rdev
);
1160 radeon_clocks_fini(rdev
);
1161 radeon_agp_fini(rdev
);
1162 radeon_bo_fini(rdev
);
1163 radeon_atombios_fini(rdev
);
1166 radeon_dummy_page_fini(rdev
);