2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/firmware.h>
29 #include <linux/platform_device.h>
36 #define R700_PFP_UCODE_SIZE 848
37 #define R700_PM4_UCODE_SIZE 1360
39 static void rv770_gpu_init(struct radeon_device
*rdev
);
40 void rv770_fini(struct radeon_device
*rdev
);
46 int rv770_pcie_gart_enable(struct radeon_device
*rdev
)
51 if (rdev
->gart
.table
.vram
.robj
== NULL
) {
52 dev_err(rdev
->dev
, "No VRAM object for PCIE GART.\n");
55 r
= radeon_gart_table_vram_pin(rdev
);
58 for (i
= 0; i
< rdev
->gart
.num_gpu_pages
; i
++)
59 r600_gart_clear_page(rdev
, i
);
61 WREG32(VM_L2_CNTL
, ENABLE_L2_CACHE
| ENABLE_L2_FRAGMENT_PROCESSING
|
62 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE
|
63 EFFECTIVE_L2_QUEUE_SIZE(7));
64 WREG32(VM_L2_CNTL2
, 0);
65 WREG32(VM_L2_CNTL3
, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
66 /* Setup TLB control */
67 tmp
= ENABLE_L1_TLB
| ENABLE_L1_FRAGMENT_PROCESSING
|
68 SYSTEM_ACCESS_MODE_NOT_IN_SYS
|
69 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU
|
70 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
71 WREG32(MC_VM_MD_L1_TLB0_CNTL
, tmp
);
72 WREG32(MC_VM_MD_L1_TLB1_CNTL
, tmp
);
73 WREG32(MC_VM_MD_L1_TLB2_CNTL
, tmp
);
74 WREG32(MC_VM_MB_L1_TLB0_CNTL
, tmp
);
75 WREG32(MC_VM_MB_L1_TLB1_CNTL
, tmp
);
76 WREG32(MC_VM_MB_L1_TLB2_CNTL
, tmp
);
77 WREG32(MC_VM_MB_L1_TLB3_CNTL
, tmp
);
78 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR
, rdev
->mc
.gtt_start
>> 12);
79 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR
, (rdev
->mc
.gtt_end
- 1) >> 12);
80 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR
, rdev
->gart
.table_addr
>> 12);
81 WREG32(VM_CONTEXT0_CNTL
, ENABLE_CONTEXT
| PAGE_TABLE_DEPTH(0) |
82 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT
);
83 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR
,
84 (u32
)(rdev
->dummy_page
.addr
>> 12));
85 for (i
= 1; i
< 7; i
++)
86 WREG32(VM_CONTEXT0_CNTL
+ (i
* 4), 0);
88 r600_pcie_gart_tlb_flush(rdev
);
89 rdev
->gart
.ready
= true;
93 void rv770_pcie_gart_disable(struct radeon_device
*rdev
)
98 /* Disable all tables */
99 for (i
= 0; i
< 7; i
++)
100 WREG32(VM_CONTEXT0_CNTL
+ (i
* 4), 0);
103 WREG32(VM_L2_CNTL
, ENABLE_L2_FRAGMENT_PROCESSING
|
104 EFFECTIVE_L2_QUEUE_SIZE(7));
105 WREG32(VM_L2_CNTL2
, 0);
106 WREG32(VM_L2_CNTL3
, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
107 /* Setup TLB control */
108 tmp
= EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
109 WREG32(MC_VM_MD_L1_TLB0_CNTL
, tmp
);
110 WREG32(MC_VM_MD_L1_TLB1_CNTL
, tmp
);
111 WREG32(MC_VM_MD_L1_TLB2_CNTL
, tmp
);
112 WREG32(MC_VM_MB_L1_TLB0_CNTL
, tmp
);
113 WREG32(MC_VM_MB_L1_TLB1_CNTL
, tmp
);
114 WREG32(MC_VM_MB_L1_TLB2_CNTL
, tmp
);
115 WREG32(MC_VM_MB_L1_TLB3_CNTL
, tmp
);
116 if (rdev
->gart
.table
.vram
.robj
) {
117 radeon_object_kunmap(rdev
->gart
.table
.vram
.robj
);
118 radeon_object_unpin(rdev
->gart
.table
.vram
.robj
);
122 void rv770_pcie_gart_fini(struct radeon_device
*rdev
)
124 rv770_pcie_gart_disable(rdev
);
125 radeon_gart_table_vram_free(rdev
);
126 radeon_gart_fini(rdev
);
133 static void rv770_mc_resume(struct radeon_device
*rdev
)
135 u32 d1vga_control
, d2vga_control
;
136 u32 vga_render_control
, vga_hdp_control
;
137 u32 d1crtc_control
, d2crtc_control
;
138 u32 new_d1grph_primary
, new_d1grph_secondary
;
139 u32 new_d2grph_primary
, new_d2grph_secondary
;
145 for (i
= 0, j
= 0; i
< 32; i
++, j
+= 0x18) {
146 WREG32((0x2c14 + j
), 0x00000000);
147 WREG32((0x2c18 + j
), 0x00000000);
148 WREG32((0x2c1c + j
), 0x00000000);
149 WREG32((0x2c20 + j
), 0x00000000);
150 WREG32((0x2c24 + j
), 0x00000000);
152 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL
, 0);
154 d1vga_control
= RREG32(D1VGA_CONTROL
);
155 d2vga_control
= RREG32(D2VGA_CONTROL
);
156 vga_render_control
= RREG32(VGA_RENDER_CONTROL
);
157 vga_hdp_control
= RREG32(VGA_HDP_CONTROL
);
158 d1crtc_control
= RREG32(D1CRTC_CONTROL
);
159 d2crtc_control
= RREG32(D2CRTC_CONTROL
);
160 old_vram_start
= (u64
)(RREG32(MC_VM_FB_LOCATION
) & 0xFFFF) << 24;
161 new_d1grph_primary
= RREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS
);
162 new_d1grph_secondary
= RREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS
);
163 new_d1grph_primary
+= rdev
->mc
.vram_start
- old_vram_start
;
164 new_d1grph_secondary
+= rdev
->mc
.vram_start
- old_vram_start
;
165 new_d2grph_primary
= RREG32(D2GRPH_PRIMARY_SURFACE_ADDRESS
);
166 new_d2grph_secondary
= RREG32(D2GRPH_SECONDARY_SURFACE_ADDRESS
);
167 new_d2grph_primary
+= rdev
->mc
.vram_start
- old_vram_start
;
168 new_d2grph_secondary
+= rdev
->mc
.vram_start
- old_vram_start
;
171 WREG32(D1VGA_CONTROL
, 0);
172 WREG32(D2VGA_CONTROL
, 0);
173 WREG32(VGA_RENDER_CONTROL
, 0);
174 WREG32(D1CRTC_UPDATE_LOCK
, 1);
175 WREG32(D2CRTC_UPDATE_LOCK
, 1);
176 WREG32(D1CRTC_CONTROL
, 0);
177 WREG32(D2CRTC_CONTROL
, 0);
178 WREG32(D1CRTC_UPDATE_LOCK
, 0);
179 WREG32(D2CRTC_UPDATE_LOCK
, 0);
182 if (r600_mc_wait_for_idle(rdev
)) {
183 printk(KERN_WARNING
"[drm] MC not idle !\n");
186 /* Lockout access through VGA aperture*/
187 WREG32(VGA_HDP_CONTROL
, VGA_MEMORY_DISABLE
);
189 /* Update configuration */
190 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR
, rdev
->mc
.vram_start
>> 12);
191 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR
, (rdev
->mc
.vram_end
- 1) >> 12);
192 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR
, 0);
193 tmp
= (((rdev
->mc
.vram_end
- 1) >> 24) & 0xFFFF) << 16;
194 tmp
|= ((rdev
->mc
.vram_start
>> 24) & 0xFFFF);
195 WREG32(MC_VM_FB_LOCATION
, tmp
);
196 WREG32(HDP_NONSURFACE_BASE
, (rdev
->mc
.vram_start
>> 8));
197 WREG32(HDP_NONSURFACE_INFO
, (2 << 7));
198 WREG32(HDP_NONSURFACE_SIZE
, (rdev
->mc
.mc_vram_size
- 1) | 0x3FF);
199 if (rdev
->flags
& RADEON_IS_AGP
) {
200 WREG32(MC_VM_AGP_TOP
, (rdev
->mc
.gtt_end
- 1) >> 16);
201 WREG32(MC_VM_AGP_BOT
, rdev
->mc
.gtt_start
>> 16);
202 WREG32(MC_VM_AGP_BASE
, rdev
->mc
.agp_base
>> 22);
204 WREG32(MC_VM_AGP_BASE
, 0);
205 WREG32(MC_VM_AGP_TOP
, 0x0FFFFFFF);
206 WREG32(MC_VM_AGP_BOT
, 0x0FFFFFFF);
208 WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS
, new_d1grph_primary
);
209 WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS
, new_d1grph_secondary
);
210 WREG32(D2GRPH_PRIMARY_SURFACE_ADDRESS
, new_d2grph_primary
);
211 WREG32(D2GRPH_SECONDARY_SURFACE_ADDRESS
, new_d2grph_secondary
);
212 WREG32(VGA_MEMORY_BASE_ADDRESS
, rdev
->mc
.vram_start
);
214 /* Unlock host access */
215 WREG32(VGA_HDP_CONTROL
, vga_hdp_control
);
218 if (r600_mc_wait_for_idle(rdev
)) {
219 printk(KERN_WARNING
"[drm] MC not idle !\n");
222 /* Restore video state */
223 WREG32(D1CRTC_UPDATE_LOCK
, 1);
224 WREG32(D2CRTC_UPDATE_LOCK
, 1);
225 WREG32(D1CRTC_CONTROL
, d1crtc_control
);
226 WREG32(D2CRTC_CONTROL
, d2crtc_control
);
227 WREG32(D1CRTC_UPDATE_LOCK
, 0);
228 WREG32(D2CRTC_UPDATE_LOCK
, 0);
229 WREG32(D1VGA_CONTROL
, d1vga_control
);
230 WREG32(D2VGA_CONTROL
, d2vga_control
);
231 WREG32(VGA_RENDER_CONTROL
, vga_render_control
);
238 void r700_cp_stop(struct radeon_device
*rdev
)
240 WREG32(CP_ME_CNTL
, (CP_ME_HALT
| CP_PFP_HALT
));
244 static int rv770_cp_load_microcode(struct radeon_device
*rdev
)
246 const __be32
*fw_data
;
249 if (!rdev
->me_fw
|| !rdev
->pfp_fw
)
253 WREG32(CP_RB_CNTL
, RB_NO_UPDATE
| (15 << 8) | (3 << 0));
256 WREG32(GRBM_SOFT_RESET
, SOFT_RESET_CP
);
257 RREG32(GRBM_SOFT_RESET
);
259 WREG32(GRBM_SOFT_RESET
, 0);
261 fw_data
= (const __be32
*)rdev
->pfp_fw
->data
;
262 WREG32(CP_PFP_UCODE_ADDR
, 0);
263 for (i
= 0; i
< R700_PFP_UCODE_SIZE
; i
++)
264 WREG32(CP_PFP_UCODE_DATA
, be32_to_cpup(fw_data
++));
265 WREG32(CP_PFP_UCODE_ADDR
, 0);
267 fw_data
= (const __be32
*)rdev
->me_fw
->data
;
268 WREG32(CP_ME_RAM_WADDR
, 0);
269 for (i
= 0; i
< R700_PM4_UCODE_SIZE
; i
++)
270 WREG32(CP_ME_RAM_DATA
, be32_to_cpup(fw_data
++));
272 WREG32(CP_PFP_UCODE_ADDR
, 0);
273 WREG32(CP_ME_RAM_WADDR
, 0);
274 WREG32(CP_ME_RAM_RADDR
, 0);
282 static u32
r700_get_tile_pipe_to_backend_map(u32 num_tile_pipes
,
284 u32 backend_disable_mask
)
287 u32 enabled_backends_mask
;
288 u32 enabled_backends_count
;
290 u32 swizzle_pipe
[R7XX_MAX_PIPES
];
294 if (num_tile_pipes
> R7XX_MAX_PIPES
)
295 num_tile_pipes
= R7XX_MAX_PIPES
;
296 if (num_tile_pipes
< 1)
298 if (num_backends
> R7XX_MAX_BACKENDS
)
299 num_backends
= R7XX_MAX_BACKENDS
;
300 if (num_backends
< 1)
303 enabled_backends_mask
= 0;
304 enabled_backends_count
= 0;
305 for (i
= 0; i
< R7XX_MAX_BACKENDS
; ++i
) {
306 if (((backend_disable_mask
>> i
) & 1) == 0) {
307 enabled_backends_mask
|= (1 << i
);
308 ++enabled_backends_count
;
310 if (enabled_backends_count
== num_backends
)
314 if (enabled_backends_count
== 0) {
315 enabled_backends_mask
= 1;
316 enabled_backends_count
= 1;
319 if (enabled_backends_count
!= num_backends
)
320 num_backends
= enabled_backends_count
;
322 memset((uint8_t *)&swizzle_pipe
[0], 0, sizeof(u32
) * R7XX_MAX_PIPES
);
323 switch (num_tile_pipes
) {
379 for (cur_pipe
= 0; cur_pipe
< num_tile_pipes
; ++cur_pipe
) {
380 while (((1 << cur_backend
) & enabled_backends_mask
) == 0)
381 cur_backend
= (cur_backend
+ 1) % R7XX_MAX_BACKENDS
;
383 backend_map
|= (u32
)(((cur_backend
& 3) << (swizzle_pipe
[cur_pipe
] * 2)));
385 cur_backend
= (cur_backend
+ 1) % R7XX_MAX_BACKENDS
;
391 static void rv770_gpu_init(struct radeon_device
*rdev
)
393 int i
, j
, num_qd_pipes
;
396 u32 num_gs_verts_per_thread
;
398 u32 gs_prim_buffer_depth
= 0;
399 u32 sq_ms_fifo_sizes
;
401 u32 sq_thread_resource_mgmt
;
402 u32 hdp_host_path_cntl
;
403 u32 sq_dyn_gpr_size_simd_ab_0
;
405 u32 gb_tiling_config
= 0;
406 u32 cc_rb_backend_disable
= 0;
407 u32 cc_gc_shader_pipe_config
= 0;
411 /* setup chip specs */
412 switch (rdev
->family
) {
414 rdev
->config
.rv770
.max_pipes
= 4;
415 rdev
->config
.rv770
.max_tile_pipes
= 8;
416 rdev
->config
.rv770
.max_simds
= 10;
417 rdev
->config
.rv770
.max_backends
= 4;
418 rdev
->config
.rv770
.max_gprs
= 256;
419 rdev
->config
.rv770
.max_threads
= 248;
420 rdev
->config
.rv770
.max_stack_entries
= 512;
421 rdev
->config
.rv770
.max_hw_contexts
= 8;
422 rdev
->config
.rv770
.max_gs_threads
= 16 * 2;
423 rdev
->config
.rv770
.sx_max_export_size
= 128;
424 rdev
->config
.rv770
.sx_max_export_pos_size
= 16;
425 rdev
->config
.rv770
.sx_max_export_smx_size
= 112;
426 rdev
->config
.rv770
.sq_num_cf_insts
= 2;
428 rdev
->config
.rv770
.sx_num_of_sets
= 7;
429 rdev
->config
.rv770
.sc_prim_fifo_size
= 0xF9;
430 rdev
->config
.rv770
.sc_hiz_tile_fifo_size
= 0x30;
431 rdev
->config
.rv770
.sc_earlyz_tile_fifo_fize
= 0x130;
434 rdev
->config
.rv770
.max_pipes
= 2;
435 rdev
->config
.rv770
.max_tile_pipes
= 4;
436 rdev
->config
.rv770
.max_simds
= 8;
437 rdev
->config
.rv770
.max_backends
= 2;
438 rdev
->config
.rv770
.max_gprs
= 128;
439 rdev
->config
.rv770
.max_threads
= 248;
440 rdev
->config
.rv770
.max_stack_entries
= 256;
441 rdev
->config
.rv770
.max_hw_contexts
= 8;
442 rdev
->config
.rv770
.max_gs_threads
= 16 * 2;
443 rdev
->config
.rv770
.sx_max_export_size
= 256;
444 rdev
->config
.rv770
.sx_max_export_pos_size
= 32;
445 rdev
->config
.rv770
.sx_max_export_smx_size
= 224;
446 rdev
->config
.rv770
.sq_num_cf_insts
= 2;
448 rdev
->config
.rv770
.sx_num_of_sets
= 7;
449 rdev
->config
.rv770
.sc_prim_fifo_size
= 0xf9;
450 rdev
->config
.rv770
.sc_hiz_tile_fifo_size
= 0x30;
451 rdev
->config
.rv770
.sc_earlyz_tile_fifo_fize
= 0x130;
452 if (rdev
->config
.rv770
.sx_max_export_pos_size
> 16) {
453 rdev
->config
.rv770
.sx_max_export_pos_size
-= 16;
454 rdev
->config
.rv770
.sx_max_export_smx_size
+= 16;
458 rdev
->config
.rv770
.max_pipes
= 2;
459 rdev
->config
.rv770
.max_tile_pipes
= 2;
460 rdev
->config
.rv770
.max_simds
= 2;
461 rdev
->config
.rv770
.max_backends
= 1;
462 rdev
->config
.rv770
.max_gprs
= 256;
463 rdev
->config
.rv770
.max_threads
= 192;
464 rdev
->config
.rv770
.max_stack_entries
= 256;
465 rdev
->config
.rv770
.max_hw_contexts
= 4;
466 rdev
->config
.rv770
.max_gs_threads
= 8 * 2;
467 rdev
->config
.rv770
.sx_max_export_size
= 128;
468 rdev
->config
.rv770
.sx_max_export_pos_size
= 16;
469 rdev
->config
.rv770
.sx_max_export_smx_size
= 112;
470 rdev
->config
.rv770
.sq_num_cf_insts
= 1;
472 rdev
->config
.rv770
.sx_num_of_sets
= 7;
473 rdev
->config
.rv770
.sc_prim_fifo_size
= 0x40;
474 rdev
->config
.rv770
.sc_hiz_tile_fifo_size
= 0x30;
475 rdev
->config
.rv770
.sc_earlyz_tile_fifo_fize
= 0x130;
478 rdev
->config
.rv770
.max_pipes
= 4;
479 rdev
->config
.rv770
.max_tile_pipes
= 4;
480 rdev
->config
.rv770
.max_simds
= 8;
481 rdev
->config
.rv770
.max_backends
= 4;
482 rdev
->config
.rv770
.max_gprs
= 256;
483 rdev
->config
.rv770
.max_threads
= 248;
484 rdev
->config
.rv770
.max_stack_entries
= 512;
485 rdev
->config
.rv770
.max_hw_contexts
= 8;
486 rdev
->config
.rv770
.max_gs_threads
= 16 * 2;
487 rdev
->config
.rv770
.sx_max_export_size
= 256;
488 rdev
->config
.rv770
.sx_max_export_pos_size
= 32;
489 rdev
->config
.rv770
.sx_max_export_smx_size
= 224;
490 rdev
->config
.rv770
.sq_num_cf_insts
= 2;
492 rdev
->config
.rv770
.sx_num_of_sets
= 7;
493 rdev
->config
.rv770
.sc_prim_fifo_size
= 0x100;
494 rdev
->config
.rv770
.sc_hiz_tile_fifo_size
= 0x30;
495 rdev
->config
.rv770
.sc_earlyz_tile_fifo_fize
= 0x130;
497 if (rdev
->config
.rv770
.sx_max_export_pos_size
> 16) {
498 rdev
->config
.rv770
.sx_max_export_pos_size
-= 16;
499 rdev
->config
.rv770
.sx_max_export_smx_size
+= 16;
508 for (i
= 0; i
< 32; i
++) {
509 WREG32((0x2c14 + j
), 0x00000000);
510 WREG32((0x2c18 + j
), 0x00000000);
511 WREG32((0x2c1c + j
), 0x00000000);
512 WREG32((0x2c20 + j
), 0x00000000);
513 WREG32((0x2c24 + j
), 0x00000000);
517 WREG32(GRBM_CNTL
, GRBM_READ_TIMEOUT(0xff));
519 /* setup tiling, simd, pipe config */
520 mc_arb_ramcfg
= RREG32(MC_ARB_RAMCFG
);
522 switch (rdev
->config
.rv770
.max_tile_pipes
) {
524 gb_tiling_config
|= PIPE_TILING(0);
527 gb_tiling_config
|= PIPE_TILING(1);
530 gb_tiling_config
|= PIPE_TILING(2);
533 gb_tiling_config
|= PIPE_TILING(3);
539 if (rdev
->family
== CHIP_RV770
)
540 gb_tiling_config
|= BANK_TILING(1);
542 gb_tiling_config
|= BANK_TILING((mc_arb_ramcfg
& NOOFBANK_SHIFT
) >> NOOFBANK_MASK
);
544 gb_tiling_config
|= GROUP_SIZE(0);
546 if (((mc_arb_ramcfg
& NOOFROWS_MASK
) & NOOFROWS_SHIFT
) > 3) {
547 gb_tiling_config
|= ROW_TILING(3);
548 gb_tiling_config
|= SAMPLE_SPLIT(3);
551 ROW_TILING(((mc_arb_ramcfg
& NOOFROWS_MASK
) >> NOOFROWS_SHIFT
));
553 SAMPLE_SPLIT(((mc_arb_ramcfg
& NOOFROWS_MASK
) >> NOOFROWS_SHIFT
));
556 gb_tiling_config
|= BANK_SWAPS(1);
558 backend_map
= r700_get_tile_pipe_to_backend_map(rdev
->config
.rv770
.max_tile_pipes
,
559 rdev
->config
.rv770
.max_backends
,
560 (0xff << rdev
->config
.rv770
.max_backends
) & 0xff);
561 gb_tiling_config
|= BACKEND_MAP(backend_map
);
563 cc_gc_shader_pipe_config
=
564 INACTIVE_QD_PIPES((R7XX_MAX_PIPES_MASK
<< rdev
->config
.rv770
.max_pipes
) & R7XX_MAX_PIPES_MASK
);
565 cc_gc_shader_pipe_config
|=
566 INACTIVE_SIMDS((R7XX_MAX_SIMDS_MASK
<< rdev
->config
.rv770
.max_simds
) & R7XX_MAX_SIMDS_MASK
);
568 cc_rb_backend_disable
=
569 BACKEND_DISABLE((R7XX_MAX_BACKENDS_MASK
<< rdev
->config
.rv770
.max_backends
) & R7XX_MAX_BACKENDS_MASK
);
571 WREG32(GB_TILING_CONFIG
, gb_tiling_config
);
572 WREG32(DCP_TILING_CONFIG
, (gb_tiling_config
& 0xffff));
573 WREG32(HDP_TILING_CONFIG
, (gb_tiling_config
& 0xffff));
575 WREG32(CC_RB_BACKEND_DISABLE
, cc_rb_backend_disable
);
576 WREG32(CC_GC_SHADER_PIPE_CONFIG
, cc_gc_shader_pipe_config
);
577 WREG32(GC_USER_SHADER_PIPE_CONFIG
, cc_gc_shader_pipe_config
);
579 WREG32(CC_SYS_RB_BACKEND_DISABLE
, cc_rb_backend_disable
);
580 WREG32(CGTS_SYS_TCC_DISABLE
, 0);
581 WREG32(CGTS_TCC_DISABLE
, 0);
582 WREG32(CGTS_USER_SYS_TCC_DISABLE
, 0);
583 WREG32(CGTS_USER_TCC_DISABLE
, 0);
586 R7XX_MAX_BACKENDS
- r600_count_pipe_bits(cc_gc_shader_pipe_config
& INACTIVE_QD_PIPES_MASK
);
587 WREG32(VGT_OUT_DEALLOC_CNTL
, (num_qd_pipes
* 4) & DEALLOC_DIST_MASK
);
588 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL
, ((num_qd_pipes
* 4) - 2) & VTX_REUSE_DEPTH_MASK
);
590 /* set HW defaults for 3D engine */
591 WREG32(CP_QUEUE_THRESHOLDS
, (ROQ_IB1_START(0x16) |
592 ROQ_IB2_START(0x2b)));
594 WREG32(CP_MEQ_THRESHOLDS
, STQ_SPLIT(0x30));
596 WREG32(TA_CNTL_AUX
, (DISABLE_CUBE_ANISO
|
601 sx_debug_1
= RREG32(SX_DEBUG_1
);
602 sx_debug_1
|= ENABLE_NEW_SMX_ADDRESS
;
603 WREG32(SX_DEBUG_1
, sx_debug_1
);
605 smx_dc_ctl0
= RREG32(SMX_DC_CTL0
);
606 smx_dc_ctl0
&= ~CACHE_DEPTH(0x1ff);
607 smx_dc_ctl0
|= CACHE_DEPTH((rdev
->config
.rv770
.sx_num_of_sets
* 64) - 1);
608 WREG32(SMX_DC_CTL0
, smx_dc_ctl0
);
610 WREG32(SMX_EVENT_CTL
, (ES_FLUSH_CTL(4) |
615 if (rdev
->family
== CHIP_RV770
)
616 WREG32(DB_DEBUG3
, DB_CLK_OFF_DELAY(0x1f));
618 db_debug4
= RREG32(DB_DEBUG4
);
619 db_debug4
|= DISABLE_TILE_COVERED_FOR_PS_ITER
;
620 WREG32(DB_DEBUG4
, db_debug4
);
623 WREG32(SX_EXPORT_BUFFER_SIZES
, (COLOR_BUFFER_SIZE((rdev
->config
.rv770
.sx_max_export_size
/ 4) - 1) |
624 POSITION_BUFFER_SIZE((rdev
->config
.rv770
.sx_max_export_pos_size
/ 4) - 1) |
625 SMX_BUFFER_SIZE((rdev
->config
.rv770
.sx_max_export_smx_size
/ 4) - 1)));
627 WREG32(PA_SC_FIFO_SIZE
, (SC_PRIM_FIFO_SIZE(rdev
->config
.rv770
.sc_prim_fifo_size
) |
628 SC_HIZ_TILE_FIFO_SIZE(rdev
->config
.rv770
.sc_hiz_tile_fifo_size
) |
629 SC_EARLYZ_TILE_FIFO_SIZE(rdev
->config
.rv770
.sc_earlyz_tile_fifo_fize
)));
631 WREG32(PA_SC_MULTI_CHIP_CNTL
, 0);
633 WREG32(VGT_NUM_INSTANCES
, 1);
635 WREG32(SPI_CONFIG_CNTL
, GPR_WRITE_PRIORITY(0));
637 WREG32(SPI_CONFIG_CNTL_1
, VTX_DONE_DELAY(4));
639 WREG32(CP_PERFMON_CNTL
, 0);
641 sq_ms_fifo_sizes
= (CACHE_FIFO_SIZE(16 * rdev
->config
.rv770
.sq_num_cf_insts
) |
642 DONE_FIFO_HIWATER(0xe0) |
643 ALU_UPDATE_FIFO_HIWATER(0x8));
644 switch (rdev
->family
) {
646 sq_ms_fifo_sizes
|= FETCH_FIFO_HIWATER(0x1);
652 sq_ms_fifo_sizes
|= FETCH_FIFO_HIWATER(0x4);
655 WREG32(SQ_MS_FIFO_SIZES
, sq_ms_fifo_sizes
);
657 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
658 * should be adjusted as needed by the 2D/3D drivers. This just sets default values
660 sq_config
= RREG32(SQ_CONFIG
);
661 sq_config
&= ~(PS_PRIO(3) |
665 sq_config
|= (DX9_CONSTS
|
672 if (rdev
->family
== CHIP_RV710
)
673 /* no vertex cache */
674 sq_config
&= ~VC_ENABLE
;
676 WREG32(SQ_CONFIG
, sq_config
);
678 WREG32(SQ_GPR_RESOURCE_MGMT_1
, (NUM_PS_GPRS((rdev
->config
.rv770
.max_gprs
* 24)/64) |
679 NUM_VS_GPRS((rdev
->config
.rv770
.max_gprs
* 24)/64) |
680 NUM_CLAUSE_TEMP_GPRS(((rdev
->config
.rv770
.max_gprs
* 24)/64)/2)));
682 WREG32(SQ_GPR_RESOURCE_MGMT_2
, (NUM_GS_GPRS((rdev
->config
.rv770
.max_gprs
* 7)/64) |
683 NUM_ES_GPRS((rdev
->config
.rv770
.max_gprs
* 7)/64)));
685 sq_thread_resource_mgmt
= (NUM_PS_THREADS((rdev
->config
.rv770
.max_threads
* 4)/8) |
686 NUM_VS_THREADS((rdev
->config
.rv770
.max_threads
* 2)/8) |
687 NUM_ES_THREADS((rdev
->config
.rv770
.max_threads
* 1)/8));
688 if (((rdev
->config
.rv770
.max_threads
* 1) / 8) > rdev
->config
.rv770
.max_gs_threads
)
689 sq_thread_resource_mgmt
|= NUM_GS_THREADS(rdev
->config
.rv770
.max_gs_threads
);
691 sq_thread_resource_mgmt
|= NUM_GS_THREADS((rdev
->config
.rv770
.max_gs_threads
* 1)/8);
692 WREG32(SQ_THREAD_RESOURCE_MGMT
, sq_thread_resource_mgmt
);
694 WREG32(SQ_STACK_RESOURCE_MGMT_1
, (NUM_PS_STACK_ENTRIES((rdev
->config
.rv770
.max_stack_entries
* 1)/4) |
695 NUM_VS_STACK_ENTRIES((rdev
->config
.rv770
.max_stack_entries
* 1)/4)));
697 WREG32(SQ_STACK_RESOURCE_MGMT_2
, (NUM_GS_STACK_ENTRIES((rdev
->config
.rv770
.max_stack_entries
* 1)/4) |
698 NUM_ES_STACK_ENTRIES((rdev
->config
.rv770
.max_stack_entries
* 1)/4)));
700 sq_dyn_gpr_size_simd_ab_0
= (SIMDA_RING0((rdev
->config
.rv770
.max_gprs
* 38)/64) |
701 SIMDA_RING1((rdev
->config
.rv770
.max_gprs
* 38)/64) |
702 SIMDB_RING0((rdev
->config
.rv770
.max_gprs
* 38)/64) |
703 SIMDB_RING1((rdev
->config
.rv770
.max_gprs
* 38)/64));
705 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_0
, sq_dyn_gpr_size_simd_ab_0
);
706 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_1
, sq_dyn_gpr_size_simd_ab_0
);
707 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_2
, sq_dyn_gpr_size_simd_ab_0
);
708 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_3
, sq_dyn_gpr_size_simd_ab_0
);
709 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_4
, sq_dyn_gpr_size_simd_ab_0
);
710 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_5
, sq_dyn_gpr_size_simd_ab_0
);
711 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_6
, sq_dyn_gpr_size_simd_ab_0
);
712 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_7
, sq_dyn_gpr_size_simd_ab_0
);
714 WREG32(PA_SC_FORCE_EOV_MAX_CNTS
, (FORCE_EOV_MAX_CLK_CNT(4095) |
715 FORCE_EOV_MAX_REZ_CNT(255)));
717 if (rdev
->family
== CHIP_RV710
)
718 WREG32(VGT_CACHE_INVALIDATION
, (CACHE_INVALIDATION(TC_ONLY
) |
719 AUTO_INVLD_EN(ES_AND_GS_AUTO
)));
721 WREG32(VGT_CACHE_INVALIDATION
, (CACHE_INVALIDATION(VC_AND_TC
) |
722 AUTO_INVLD_EN(ES_AND_GS_AUTO
)));
724 switch (rdev
->family
) {
728 gs_prim_buffer_depth
= 384;
731 gs_prim_buffer_depth
= 128;
737 num_gs_verts_per_thread
= rdev
->config
.rv770
.max_pipes
* 16;
738 vgt_gs_per_es
= gs_prim_buffer_depth
+ num_gs_verts_per_thread
;
739 /* Max value for this is 256 */
740 if (vgt_gs_per_es
> 256)
743 WREG32(VGT_ES_PER_GS
, 128);
744 WREG32(VGT_GS_PER_ES
, vgt_gs_per_es
);
745 WREG32(VGT_GS_PER_VS
, 2);
747 /* more default values. 2D/3D driver should adjust as needed */
748 WREG32(VGT_GS_VERTEX_REUSE
, 16);
749 WREG32(PA_SC_LINE_STIPPLE_STATE
, 0);
750 WREG32(VGT_STRMOUT_EN
, 0);
752 WREG32(PA_SC_MODE_CNTL
, 0);
753 WREG32(PA_SC_EDGERULE
, 0xaaaaaaaa);
754 WREG32(PA_SC_AA_CONFIG
, 0);
755 WREG32(PA_SC_CLIPRECT_RULE
, 0xffff);
756 WREG32(PA_SC_LINE_STIPPLE
, 0);
757 WREG32(SPI_INPUT_Z
, 0);
758 WREG32(SPI_PS_IN_CONTROL_0
, NUM_INTERP(2));
759 WREG32(CB_COLOR7_FRAG
, 0);
761 /* clear render buffer base addresses */
762 WREG32(CB_COLOR0_BASE
, 0);
763 WREG32(CB_COLOR1_BASE
, 0);
764 WREG32(CB_COLOR2_BASE
, 0);
765 WREG32(CB_COLOR3_BASE
, 0);
766 WREG32(CB_COLOR4_BASE
, 0);
767 WREG32(CB_COLOR5_BASE
, 0);
768 WREG32(CB_COLOR6_BASE
, 0);
769 WREG32(CB_COLOR7_BASE
, 0);
773 hdp_host_path_cntl
= RREG32(HDP_HOST_PATH_CNTL
);
774 WREG32(HDP_HOST_PATH_CNTL
, hdp_host_path_cntl
);
776 WREG32(PA_SC_MULTI_CHIP_CNTL
, 0);
778 WREG32(PA_CL_ENHANCE
, (CLIP_VTX_REORDER_ENA
|
783 int rv770_mc_init(struct radeon_device
*rdev
)
789 /* Get VRAM informations */
790 /* FIXME: Don't know how to determine vram width, need to check
793 rdev
->mc
.vram_width
= 128;
794 rdev
->mc
.vram_is_ddr
= true;
795 /* Could aper size report 0 ? */
796 rdev
->mc
.aper_base
= drm_get_resource_start(rdev
->ddev
, 0);
797 rdev
->mc
.aper_size
= drm_get_resource_len(rdev
->ddev
, 0);
798 /* Setup GPU memory space */
799 rdev
->mc
.mc_vram_size
= RREG32(CONFIG_MEMSIZE
);
800 rdev
->mc
.real_vram_size
= RREG32(CONFIG_MEMSIZE
);
801 if (rdev
->flags
& RADEON_IS_AGP
) {
802 r
= radeon_agp_init(rdev
);
805 /* gtt_size is setup by radeon_agp_init */
806 rdev
->mc
.gtt_location
= rdev
->mc
.agp_base
;
807 tmp
= 0xFFFFFFFFUL
- rdev
->mc
.agp_base
- rdev
->mc
.gtt_size
;
808 /* Try to put vram before or after AGP because we
809 * we want SYSTEM_APERTURE to cover both VRAM and
810 * AGP so that GPU can catch out of VRAM/AGP access
812 if (rdev
->mc
.gtt_location
> rdev
->mc
.mc_vram_size
) {
813 /* Enought place before */
814 rdev
->mc
.vram_location
= rdev
->mc
.gtt_location
-
815 rdev
->mc
.mc_vram_size
;
816 } else if (tmp
> rdev
->mc
.mc_vram_size
) {
817 /* Enought place after */
818 rdev
->mc
.vram_location
= rdev
->mc
.gtt_location
+
821 /* Try to setup VRAM then AGP might not
822 * not work on some card
824 rdev
->mc
.vram_location
= 0x00000000UL
;
825 rdev
->mc
.gtt_location
= rdev
->mc
.mc_vram_size
;
828 rdev
->mc
.vram_location
= 0x00000000UL
;
829 rdev
->mc
.gtt_location
= rdev
->mc
.mc_vram_size
;
830 rdev
->mc
.gtt_size
= radeon_gart_size
* 1024 * 1024;
832 rdev
->mc
.vram_start
= rdev
->mc
.vram_location
;
833 rdev
->mc
.vram_end
= rdev
->mc
.vram_location
+ rdev
->mc
.mc_vram_size
;
834 rdev
->mc
.gtt_start
= rdev
->mc
.gtt_location
;
835 rdev
->mc
.gtt_end
= rdev
->mc
.gtt_location
+ rdev
->mc
.gtt_size
;
836 /* FIXME: we should enforce default clock in case GPU is not in
839 a
.full
= rfixed_const(100);
840 rdev
->pm
.sclk
.full
= rfixed_const(rdev
->clock
.default_sclk
);
841 rdev
->pm
.sclk
.full
= rfixed_div(rdev
->pm
.sclk
, a
);
844 int rv770_gpu_reset(struct radeon_device
*rdev
)
846 /* FIXME: implement */
850 int rv770_resume(struct radeon_device
*rdev
)
854 rv770_mc_resume(rdev
);
855 r
= rv770_pcie_gart_enable(rdev
);
858 rv770_gpu_init(rdev
);
859 r
= radeon_ring_init(rdev
, rdev
->cp
.ring_size
);
862 r
= rv770_cp_load_microcode(rdev
);
865 r
= r600_cp_resume(rdev
);
868 r
= r600_wb_init(rdev
);
874 int rv770_suspend(struct radeon_device
*rdev
)
876 /* FIXME: we should wait for ring to be empty */
878 rv770_pcie_gart_disable(rdev
);
882 /* Plan is to move initialization in that function and use
883 * helper function so that radeon_device_init pretty much
884 * do nothing more than calling asic specific function. This
885 * should also allow to remove a bunch of callback function
888 int rv770_init(struct radeon_device
*rdev
)
892 rdev
->new_init_path
= true;
893 r
= radeon_dummy_page_init(rdev
);
896 /* This don't do much */
897 r
= radeon_gem_init(rdev
);
901 if (!radeon_get_bios(rdev
)) {
902 if (ASIC_IS_AVIVO(rdev
))
905 /* Must be an ATOMBIOS */
906 if (!rdev
->is_atom_bios
)
908 r
= radeon_atombios_init(rdev
);
911 /* Post card if necessary */
912 if (!r600_card_posted(rdev
) && rdev
->bios
) {
913 DRM_INFO("GPU not posted. posting now...\n");
914 atom_asic_init(rdev
->mode_info
.atom_context
);
916 /* Initialize scratch registers */
917 r600_scratch_init(rdev
);
918 /* Initialize surface registers */
919 radeon_surface_init(rdev
);
920 radeon_get_clock_info(rdev
->ddev
);
921 r
= radeon_clocks_init(rdev
);
925 r
= radeon_fence_driver_init(rdev
);
928 r
= rv770_mc_init(rdev
);
930 if (rdev
->flags
& RADEON_IS_AGP
) {
931 /* Retry with disabling AGP */
933 rdev
->flags
&= ~RADEON_IS_AGP
;
934 return rv770_init(rdev
);
939 r
= radeon_object_init(rdev
);
942 rdev
->cp
.ring_obj
= NULL
;
943 r600_ring_init(rdev
, 1024 * 1024);
945 if (!rdev
->me_fw
|| !rdev
->pfp_fw
) {
946 r
= r600_cp_init_microcode(rdev
);
948 DRM_ERROR("Failed to load firmware!\n");
953 r
= r600_pcie_gart_init(rdev
);
957 rdev
->accel_working
= true;
958 r
= rv770_resume(rdev
);
960 if (rdev
->flags
& RADEON_IS_AGP
) {
961 /* Retry with disabling AGP */
963 rdev
->flags
&= ~RADEON_IS_AGP
;
964 return rv770_init(rdev
);
966 rdev
->accel_working
= false;
968 if (rdev
->accel_working
) {
969 r
= r600_blit_init(rdev
);
971 DRM_ERROR("radeon: failled blitter (%d).\n", r
);
972 rdev
->accel_working
= false;
974 r
= radeon_ib_pool_init(rdev
);
976 DRM_ERROR("radeon: failled initializing IB pool (%d).\n", r
);
977 rdev
->accel_working
= false;
979 r
= radeon_ib_test(rdev
);
981 DRM_ERROR("radeon: failled testing IB (%d).\n", r
);
982 rdev
->accel_working
= false;
988 void rv770_fini(struct radeon_device
*rdev
)
990 r600_blit_fini(rdev
);
991 radeon_ring_fini(rdev
);
992 rv770_pcie_gart_fini(rdev
);
993 radeon_gem_fini(rdev
);
994 radeon_fence_driver_fini(rdev
);
995 radeon_clocks_fini(rdev
);
997 if (rdev
->flags
& RADEON_IS_AGP
)
998 radeon_agp_fini(rdev
);
1000 radeon_object_fini(rdev
);
1001 if (rdev
->is_atom_bios
) {
1002 radeon_atombios_fini(rdev
);
1004 radeon_combios_fini(rdev
);
1008 radeon_dummy_page_fini(rdev
);