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drm/radeon/kms: add dpm support for rv7xx (v4)
[deliverable/linux.git] / drivers / gpu / drm / radeon / rv770_dpm.c
1 /*
2 * Copyright 2011 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Alex Deucher
23 */
24
25 #include "drmP.h"
26 #include "radeon.h"
27 #include "rv770d.h"
28 #include "r600_dpm.h"
29 #include "rv770_dpm.h"
30 #include "atom.h"
31
32 #define MC_CG_ARB_FREQ_F0 0x0a
33 #define MC_CG_ARB_FREQ_F1 0x0b
34 #define MC_CG_ARB_FREQ_F2 0x0c
35 #define MC_CG_ARB_FREQ_F3 0x0d
36
37 #define MC_CG_SEQ_DRAMCONF_S0 0x05
38 #define MC_CG_SEQ_DRAMCONF_S1 0x06
39
40 #define PCIE_BUS_CLK 10000
41 #define TCLK (PCIE_BUS_CLK / 10)
42
43 #define SMC_RAM_END 0xC000
44
45 struct rv7xx_ps *rv770_get_ps(struct radeon_ps *rps)
46 {
47 struct rv7xx_ps *ps = rps->ps_priv;
48
49 return ps;
50 }
51
52 struct rv7xx_power_info *rv770_get_pi(struct radeon_device *rdev)
53 {
54 struct rv7xx_power_info *pi = rdev->pm.dpm.priv;
55
56 return pi;
57 }
58
59 static void rv770_enable_bif_dynamic_pcie_gen2(struct radeon_device *rdev,
60 bool enable)
61 {
62 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
63 u32 tmp;
64
65 tmp = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
66 if (enable) {
67 tmp &= ~LC_HW_VOLTAGE_IF_CONTROL_MASK;
68 tmp |= LC_HW_VOLTAGE_IF_CONTROL(1);
69 tmp |= LC_GEN2_EN_STRAP;
70 } else {
71 if (!pi->boot_in_gen2) {
72 tmp &= ~LC_HW_VOLTAGE_IF_CONTROL_MASK;
73 tmp &= ~LC_GEN2_EN_STRAP;
74 }
75 }
76 if ((tmp & LC_OTHER_SIDE_EVER_SENT_GEN2) ||
77 (tmp & LC_OTHER_SIDE_SUPPORTS_GEN2))
78 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, tmp);
79
80 }
81
82 static void rv770_enable_l0s(struct radeon_device *rdev)
83 {
84 u32 tmp;
85
86 tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL) & ~LC_L0S_INACTIVITY_MASK;
87 tmp |= LC_L0S_INACTIVITY(3);
88 WREG32_PCIE_PORT(PCIE_LC_CNTL, tmp);
89 }
90
91 static void rv770_enable_l1(struct radeon_device *rdev)
92 {
93 u32 tmp;
94
95 tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL);
96 tmp &= ~LC_L1_INACTIVITY_MASK;
97 tmp |= LC_L1_INACTIVITY(4);
98 tmp &= ~LC_PMI_TO_L1_DIS;
99 tmp &= ~LC_ASPM_TO_L1_DIS;
100 WREG32_PCIE_PORT(PCIE_LC_CNTL, tmp);
101 }
102
103 static void rv770_enable_pll_sleep_in_l1(struct radeon_device *rdev)
104 {
105 u32 tmp;
106
107 tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL) & ~LC_L1_INACTIVITY_MASK;
108 tmp |= LC_L1_INACTIVITY(8);
109 WREG32_PCIE_PORT(PCIE_LC_CNTL, tmp);
110
111 /* NOTE, this is a PCIE indirect reg, not PCIE PORT */
112 tmp = RREG32_PCIE(PCIE_P_CNTL);
113 tmp |= P_PLL_PWRDN_IN_L1L23;
114 tmp &= ~P_PLL_BUF_PDNB;
115 tmp &= ~P_PLL_PDNB;
116 tmp |= P_ALLOW_PRX_FRONTEND_SHUTOFF;
117 WREG32_PCIE(PCIE_P_CNTL, tmp);
118 }
119
120 static void rv770_gfx_clock_gating_enable(struct radeon_device *rdev,
121 bool enable)
122 {
123 if (enable)
124 WREG32_P(SCLK_PWRMGT_CNTL, DYN_GFX_CLK_OFF_EN, ~DYN_GFX_CLK_OFF_EN);
125 else {
126 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN);
127 WREG32_P(SCLK_PWRMGT_CNTL, GFX_CLK_FORCE_ON, ~GFX_CLK_FORCE_ON);
128 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~GFX_CLK_FORCE_ON);
129 RREG32(GB_TILING_CONFIG);
130 }
131 }
132
133 static void rv770_mg_clock_gating_enable(struct radeon_device *rdev,
134 bool enable)
135 {
136 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
137
138 if (enable) {
139 u32 mgcg_cgtt_local0;
140
141 if (rdev->family == CHIP_RV770)
142 mgcg_cgtt_local0 = RV770_MGCGTTLOCAL0_DFLT;
143 else
144 mgcg_cgtt_local0 = RV7XX_MGCGTTLOCAL0_DFLT;
145
146 WREG32(CG_CGTT_LOCAL_0, mgcg_cgtt_local0);
147 WREG32(CG_CGTT_LOCAL_1, (RV770_MGCGTTLOCAL1_DFLT & 0xFFFFCFFF));
148
149 if (pi->mgcgtssm)
150 WREG32(CGTS_SM_CTRL_REG, RV770_MGCGCGTSSMCTRL_DFLT);
151 } else {
152 WREG32(CG_CGTT_LOCAL_0, 0xFFFFFFFF);
153 WREG32(CG_CGTT_LOCAL_1, 0xFFFFCFFF);
154 }
155 }
156
157 void rv770_restore_cgcg(struct radeon_device *rdev)
158 {
159 bool dpm_en = false, cg_en = false;
160
161 if (RREG32(GENERAL_PWRMGT) & GLOBAL_PWRMGT_EN)
162 dpm_en = true;
163 if (RREG32(SCLK_PWRMGT_CNTL) & DYN_GFX_CLK_OFF_EN)
164 cg_en = true;
165
166 if (dpm_en && !cg_en)
167 WREG32_P(SCLK_PWRMGT_CNTL, DYN_GFX_CLK_OFF_EN, ~DYN_GFX_CLK_OFF_EN);
168 }
169
170 static void rv770_start_dpm(struct radeon_device *rdev)
171 {
172 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF);
173
174 WREG32_P(MCLK_PWRMGT_CNTL, 0, ~MPLL_PWRMGT_OFF);
175
176 WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN);
177 }
178
179 void rv770_stop_dpm(struct radeon_device *rdev)
180 {
181 PPSMC_Result result;
182
183 result = rv770_send_msg_to_smc(rdev, PPSMC_MSG_TwoLevelsDisabled);
184
185 if (result != PPSMC_Result_OK)
186 DRM_ERROR("Could not force DPM to low.\n");
187
188 WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN);
189
190 WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF);
191
192 WREG32_P(MCLK_PWRMGT_CNTL, MPLL_PWRMGT_OFF, ~MPLL_PWRMGT_OFF);
193 }
194
195 bool rv770_dpm_enabled(struct radeon_device *rdev)
196 {
197 if (RREG32(GENERAL_PWRMGT) & GLOBAL_PWRMGT_EN)
198 return true;
199 else
200 return false;
201 }
202
203 void rv770_enable_thermal_protection(struct radeon_device *rdev,
204 bool enable)
205 {
206 if (enable)
207 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS);
208 else
209 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS);
210 }
211
212 void rv770_enable_acpi_pm(struct radeon_device *rdev)
213 {
214 WREG32_P(GENERAL_PWRMGT, STATIC_PM_EN, ~STATIC_PM_EN);
215 }
216
217 u8 rv770_get_seq_value(struct radeon_device *rdev,
218 struct rv7xx_pl *pl)
219 {
220 return (pl->flags & ATOM_PPLIB_R600_FLAGS_LOWPOWER) ?
221 MC_CG_SEQ_DRAMCONF_S0 : MC_CG_SEQ_DRAMCONF_S1;
222 }
223
224 int rv770_read_smc_soft_register(struct radeon_device *rdev,
225 u16 reg_offset, u32 *value)
226 {
227 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
228
229 return rv770_read_smc_sram_dword(rdev,
230 pi->soft_regs_start + reg_offset,
231 value, pi->sram_end);
232 }
233
234 int rv770_write_smc_soft_register(struct radeon_device *rdev,
235 u16 reg_offset, u32 value)
236 {
237 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
238
239 return rv770_write_smc_sram_dword(rdev,
240 pi->soft_regs_start + reg_offset,
241 value, pi->sram_end);
242 }
243
244 int rv770_populate_smc_t(struct radeon_device *rdev,
245 struct radeon_ps *radeon_state,
246 RV770_SMC_SWSTATE *smc_state)
247 {
248 struct rv7xx_ps *state = rv770_get_ps(radeon_state);
249 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
250 int i;
251 int a_n;
252 int a_d;
253 u8 l[RV770_SMC_PERFORMANCE_LEVELS_PER_SWSTATE];
254 u8 r[RV770_SMC_PERFORMANCE_LEVELS_PER_SWSTATE];
255 u32 a_t;
256
257 l[0] = 0;
258 r[2] = 100;
259
260 a_n = (int)state->medium.sclk * RV770_LMP_DFLT +
261 (int)state->low.sclk * (R600_AH_DFLT - RV770_RLP_DFLT);
262 a_d = (int)state->low.sclk * (100 - (int)RV770_RLP_DFLT) +
263 (int)state->medium.sclk * RV770_LMP_DFLT;
264
265 l[1] = (u8)(RV770_LMP_DFLT - (int)RV770_LMP_DFLT * a_n / a_d);
266 r[0] = (u8)(RV770_RLP_DFLT + (100 - (int)RV770_RLP_DFLT) * a_n / a_d);
267
268 a_n = (int)state->high.sclk * RV770_LHP_DFLT +
269 (int)state->medium.sclk *
270 (R600_AH_DFLT - RV770_RMP_DFLT);
271 a_d = (int)state->medium.sclk * (100 - (int)RV770_RMP_DFLT) +
272 (int)state->high.sclk * RV770_LHP_DFLT;
273
274 l[2] = (u8)(RV770_LHP_DFLT - (int)RV770_LHP_DFLT * a_n / a_d);
275 r[1] = (u8)(RV770_RMP_DFLT + (100 - (int)RV770_RMP_DFLT) * a_n / a_d);
276
277 for (i = 0; i < (RV770_SMC_PERFORMANCE_LEVELS_PER_SWSTATE - 1); i++) {
278 a_t = CG_R(r[i] * pi->bsp / 200) | CG_L(l[i] * pi->bsp / 200);
279 smc_state->levels[i].aT = cpu_to_be32(a_t);
280 }
281
282 a_t = CG_R(r[RV770_SMC_PERFORMANCE_LEVELS_PER_SWSTATE - 1] * pi->pbsp / 200) |
283 CG_L(l[RV770_SMC_PERFORMANCE_LEVELS_PER_SWSTATE - 1] * pi->pbsp / 200);
284
285 smc_state->levels[RV770_SMC_PERFORMANCE_LEVELS_PER_SWSTATE - 1].aT =
286 cpu_to_be32(a_t);
287
288 return 0;
289 }
290
291 int rv770_populate_smc_sp(struct radeon_device *rdev,
292 struct radeon_ps *radeon_state,
293 RV770_SMC_SWSTATE *smc_state)
294 {
295 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
296 int i;
297
298 for (i = 0; i < (RV770_SMC_PERFORMANCE_LEVELS_PER_SWSTATE - 1); i++)
299 smc_state->levels[i].bSP = cpu_to_be32(pi->dsp);
300
301 smc_state->levels[RV770_SMC_PERFORMANCE_LEVELS_PER_SWSTATE - 1].bSP =
302 cpu_to_be32(pi->psp);
303
304 return 0;
305 }
306
307 static void rv770_calculate_fractional_mpll_feedback_divider(u32 memory_clock,
308 u32 reference_clock,
309 bool gddr5,
310 struct atom_clock_dividers *dividers,
311 u32 *clkf,
312 u32 *clkfrac)
313 {
314 u32 post_divider, reference_divider, feedback_divider8;
315 u32 fyclk;
316
317 if (gddr5)
318 fyclk = (memory_clock * 8) / 2;
319 else
320 fyclk = (memory_clock * 4) / 2;
321
322 post_divider = dividers->post_div;
323 reference_divider = dividers->ref_div;
324
325 feedback_divider8 =
326 (8 * fyclk * reference_divider * post_divider) / reference_clock;
327
328 *clkf = feedback_divider8 / 8;
329 *clkfrac = feedback_divider8 % 8;
330 }
331
332 static int rv770_encode_yclk_post_div(u32 postdiv, u32 *encoded_postdiv)
333 {
334 int ret = 0;
335
336 switch (postdiv) {
337 case 1:
338 *encoded_postdiv = 0;
339 break;
340 case 2:
341 *encoded_postdiv = 1;
342 break;
343 case 4:
344 *encoded_postdiv = 2;
345 break;
346 case 8:
347 *encoded_postdiv = 3;
348 break;
349 case 16:
350 *encoded_postdiv = 4;
351 break;
352 default:
353 ret = -EINVAL;
354 break;
355 }
356
357 return ret;
358 }
359
360 u32 rv770_map_clkf_to_ibias(struct radeon_device *rdev, u32 clkf)
361 {
362 if (clkf <= 0x10)
363 return 0x4B;
364 if (clkf <= 0x19)
365 return 0x5B;
366 if (clkf <= 0x21)
367 return 0x2B;
368 if (clkf <= 0x27)
369 return 0x6C;
370 if (clkf <= 0x31)
371 return 0x9D;
372 return 0xC6;
373 }
374
375 static int rv770_populate_mclk_value(struct radeon_device *rdev,
376 u32 engine_clock, u32 memory_clock,
377 RV7XX_SMC_MCLK_VALUE *mclk)
378 {
379 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
380 u8 encoded_reference_dividers[] = { 0, 16, 17, 20, 21 };
381 u32 mpll_ad_func_cntl =
382 pi->clk_regs.rv770.mpll_ad_func_cntl;
383 u32 mpll_ad_func_cntl_2 =
384 pi->clk_regs.rv770.mpll_ad_func_cntl_2;
385 u32 mpll_dq_func_cntl =
386 pi->clk_regs.rv770.mpll_dq_func_cntl;
387 u32 mpll_dq_func_cntl_2 =
388 pi->clk_regs.rv770.mpll_dq_func_cntl_2;
389 u32 mclk_pwrmgt_cntl =
390 pi->clk_regs.rv770.mclk_pwrmgt_cntl;
391 u32 dll_cntl = pi->clk_regs.rv770.dll_cntl;
392 struct atom_clock_dividers dividers;
393 u32 reference_clock = rdev->clock.mpll.reference_freq;
394 u32 clkf, clkfrac;
395 u32 postdiv_yclk;
396 u32 ibias;
397 int ret;
398
399 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_MEMORY_PLL_PARAM,
400 memory_clock, false, &dividers);
401 if (ret)
402 return ret;
403
404 if ((dividers.ref_div < 1) || (dividers.ref_div > 5))
405 return -EINVAL;
406
407 rv770_calculate_fractional_mpll_feedback_divider(memory_clock, reference_clock,
408 pi->mem_gddr5,
409 &dividers, &clkf, &clkfrac);
410
411 ret = rv770_encode_yclk_post_div(dividers.post_div, &postdiv_yclk);
412 if (ret)
413 return ret;
414
415 ibias = rv770_map_clkf_to_ibias(rdev, clkf);
416
417 mpll_ad_func_cntl &= ~(CLKR_MASK |
418 YCLK_POST_DIV_MASK |
419 CLKF_MASK |
420 CLKFRAC_MASK |
421 IBIAS_MASK);
422 mpll_ad_func_cntl |= CLKR(encoded_reference_dividers[dividers.ref_div - 1]);
423 mpll_ad_func_cntl |= YCLK_POST_DIV(postdiv_yclk);
424 mpll_ad_func_cntl |= CLKF(clkf);
425 mpll_ad_func_cntl |= CLKFRAC(clkfrac);
426 mpll_ad_func_cntl |= IBIAS(ibias);
427
428 if (dividers.vco_mode)
429 mpll_ad_func_cntl_2 |= VCO_MODE;
430 else
431 mpll_ad_func_cntl_2 &= ~VCO_MODE;
432
433 if (pi->mem_gddr5) {
434 rv770_calculate_fractional_mpll_feedback_divider(memory_clock,
435 reference_clock,
436 pi->mem_gddr5,
437 &dividers, &clkf, &clkfrac);
438
439 ibias = rv770_map_clkf_to_ibias(rdev, clkf);
440
441 ret = rv770_encode_yclk_post_div(dividers.post_div, &postdiv_yclk);
442 if (ret)
443 return ret;
444
445 mpll_dq_func_cntl &= ~(CLKR_MASK |
446 YCLK_POST_DIV_MASK |
447 CLKF_MASK |
448 CLKFRAC_MASK |
449 IBIAS_MASK);
450 mpll_dq_func_cntl |= CLKR(encoded_reference_dividers[dividers.ref_div - 1]);
451 mpll_dq_func_cntl |= YCLK_POST_DIV(postdiv_yclk);
452 mpll_dq_func_cntl |= CLKF(clkf);
453 mpll_dq_func_cntl |= CLKFRAC(clkfrac);
454 mpll_dq_func_cntl |= IBIAS(ibias);
455
456 if (dividers.vco_mode)
457 mpll_dq_func_cntl_2 |= VCO_MODE;
458 else
459 mpll_dq_func_cntl_2 &= ~VCO_MODE;
460 }
461
462 mclk->mclk770.mclk_value = cpu_to_be32(memory_clock);
463 mclk->mclk770.vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl);
464 mclk->mclk770.vMPLL_AD_FUNC_CNTL_2 = cpu_to_be32(mpll_ad_func_cntl_2);
465 mclk->mclk770.vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl);
466 mclk->mclk770.vMPLL_DQ_FUNC_CNTL_2 = cpu_to_be32(mpll_dq_func_cntl_2);
467 mclk->mclk770.vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl);
468 mclk->mclk770.vDLL_CNTL = cpu_to_be32(dll_cntl);
469
470 return 0;
471 }
472
473 static int rv770_populate_sclk_value(struct radeon_device *rdev,
474 u32 engine_clock,
475 RV770_SMC_SCLK_VALUE *sclk)
476 {
477 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
478 struct atom_clock_dividers dividers;
479 u32 spll_func_cntl =
480 pi->clk_regs.rv770.cg_spll_func_cntl;
481 u32 spll_func_cntl_2 =
482 pi->clk_regs.rv770.cg_spll_func_cntl_2;
483 u32 spll_func_cntl_3 =
484 pi->clk_regs.rv770.cg_spll_func_cntl_3;
485 u32 cg_spll_spread_spectrum =
486 pi->clk_regs.rv770.cg_spll_spread_spectrum;
487 u32 cg_spll_spread_spectrum_2 =
488 pi->clk_regs.rv770.cg_spll_spread_spectrum_2;
489 u64 tmp;
490 u32 reference_clock = rdev->clock.spll.reference_freq;
491 u32 reference_divider, post_divider;
492 u32 fbdiv;
493 int ret;
494
495 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
496 engine_clock, false, &dividers);
497 if (ret)
498 return ret;
499
500 reference_divider = 1 + dividers.ref_div;
501
502 if (dividers.enable_post_div)
503 post_divider = (0x0f & (dividers.post_div >> 4)) + (0x0f & dividers.post_div) + 2;
504 else
505 post_divider = 1;
506
507 tmp = (u64) engine_clock * reference_divider * post_divider * 16384;
508 do_div(tmp, reference_clock);
509 fbdiv = (u32) tmp;
510
511 if (dividers.enable_post_div)
512 spll_func_cntl |= SPLL_DIVEN;
513 else
514 spll_func_cntl &= ~SPLL_DIVEN;
515 spll_func_cntl &= ~(SPLL_HILEN_MASK | SPLL_LOLEN_MASK | SPLL_REF_DIV_MASK);
516 spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div);
517 spll_func_cntl |= SPLL_HILEN((dividers.post_div >> 4) & 0xf);
518 spll_func_cntl |= SPLL_LOLEN(dividers.post_div & 0xf);
519
520 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
521 spll_func_cntl_2 |= SCLK_MUX_SEL(2);
522
523 spll_func_cntl_3 &= ~SPLL_FB_DIV_MASK;
524 spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv);
525 spll_func_cntl_3 |= SPLL_DITHEN;
526
527 if (pi->sclk_ss) {
528 struct radeon_atom_ss ss;
529 u32 vco_freq = engine_clock * post_divider;
530
531 if (radeon_atombios_get_asic_ss_info(rdev, &ss,
532 ASIC_INTERNAL_ENGINE_SS, vco_freq)) {
533 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate);
534 u32 clk_v = ss.percentage * fbdiv / (clk_s * 10000);
535
536 cg_spll_spread_spectrum &= ~CLKS_MASK;
537 cg_spll_spread_spectrum |= CLKS(clk_s);
538 cg_spll_spread_spectrum |= SSEN;
539
540 cg_spll_spread_spectrum_2 &= ~CLKV_MASK;
541 cg_spll_spread_spectrum_2 |= CLKV(clk_v);
542 }
543 }
544
545 sclk->sclk_value = cpu_to_be32(engine_clock);
546 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl);
547 sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(spll_func_cntl_2);
548 sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(spll_func_cntl_3);
549 sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(cg_spll_spread_spectrum);
550 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(cg_spll_spread_spectrum_2);
551
552 return 0;
553 }
554
555 int rv770_populate_vddc_value(struct radeon_device *rdev, u16 vddc,
556 RV770_SMC_VOLTAGE_VALUE *voltage)
557 {
558 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
559 int i;
560
561 if (!pi->voltage_control) {
562 voltage->index = 0;
563 voltage->value = 0;
564 return 0;
565 }
566
567 for (i = 0; i < pi->valid_vddc_entries; i++) {
568 if (vddc <= pi->vddc_table[i].vddc) {
569 voltage->index = pi->vddc_table[i].vddc_index;
570 voltage->value = cpu_to_be16(vddc);
571 break;
572 }
573 }
574
575 if (i == pi->valid_vddc_entries)
576 return -EINVAL;
577
578 return 0;
579 }
580
581 int rv770_populate_mvdd_value(struct radeon_device *rdev, u32 mclk,
582 RV770_SMC_VOLTAGE_VALUE *voltage)
583 {
584 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
585
586 if (!pi->mvdd_control) {
587 voltage->index = MVDD_HIGH_INDEX;
588 voltage->value = cpu_to_be16(MVDD_HIGH_VALUE);
589 return 0;
590 }
591
592 if (mclk <= pi->mvdd_split_frequency) {
593 voltage->index = MVDD_LOW_INDEX;
594 voltage->value = cpu_to_be16(MVDD_LOW_VALUE);
595 } else {
596 voltage->index = MVDD_HIGH_INDEX;
597 voltage->value = cpu_to_be16(MVDD_HIGH_VALUE);
598 }
599
600 return 0;
601 }
602
603 static int rv770_convert_power_level_to_smc(struct radeon_device *rdev,
604 struct rv7xx_pl *pl,
605 RV770_SMC_HW_PERFORMANCE_LEVEL *level,
606 u8 watermark_level)
607 {
608 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
609 int ret;
610
611 level->gen2PCIE = pi->pcie_gen2 ?
612 ((pl->flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2) ? 1 : 0) : 0;
613 level->gen2XSP = (pl->flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2) ? 1 : 0;
614 level->backbias = (pl->flags & ATOM_PPLIB_R600_FLAGS_BACKBIASENABLE) ? 1 : 0;
615 level->displayWatermark = watermark_level;
616
617 if (rdev->family == CHIP_RV740)
618 ret = rv740_populate_sclk_value(rdev, pl->sclk,
619 &level->sclk);
620 else if ((rdev->family == CHIP_RV730) || (rdev->family == CHIP_RV710))
621 ret = rv730_populate_sclk_value(rdev, pl->sclk,
622 &level->sclk);
623 else
624 ret = rv770_populate_sclk_value(rdev, pl->sclk,
625 &level->sclk);
626 if (ret)
627 return ret;
628
629 if (rdev->family == CHIP_RV740) {
630 if (pi->mem_gddr5) {
631 if (pl->mclk <= pi->mclk_strobe_mode_threshold)
632 level->strobeMode =
633 rv740_get_mclk_frequency_ratio(pl->mclk) | 0x10;
634 else
635 level->strobeMode = 0;
636
637 if (pl->mclk > pi->mclk_edc_enable_threshold)
638 level->mcFlags = SMC_MC_EDC_RD_FLAG | SMC_MC_EDC_WR_FLAG;
639 else
640 level->mcFlags = 0;
641 }
642 ret = rv740_populate_mclk_value(rdev, pl->sclk,
643 pl->mclk, &level->mclk);
644 } else if ((rdev->family == CHIP_RV730) || (rdev->family == CHIP_RV710))
645 ret = rv730_populate_mclk_value(rdev, pl->sclk,
646 pl->mclk, &level->mclk);
647 else
648 ret = rv770_populate_mclk_value(rdev, pl->sclk,
649 pl->mclk, &level->mclk);
650 if (ret)
651 return ret;
652
653 ret = rv770_populate_vddc_value(rdev, pl->vddc,
654 &level->vddc);
655 if (ret)
656 return ret;
657
658 ret = rv770_populate_mvdd_value(rdev, pl->mclk, &level->mvdd);
659
660 return ret;
661 }
662
663 static int rv770_convert_power_state_to_smc(struct radeon_device *rdev,
664 struct radeon_ps *radeon_state,
665 RV770_SMC_SWSTATE *smc_state)
666 {
667 struct rv7xx_ps *state = rv770_get_ps(radeon_state);
668 int ret;
669
670 if (!(radeon_state->caps & ATOM_PPLIB_DISALLOW_ON_DC))
671 smc_state->flags |= PPSMC_SWSTATE_FLAG_DC;
672
673 ret = rv770_convert_power_level_to_smc(rdev,
674 &state->low,
675 &smc_state->levels[0],
676 PPSMC_DISPLAY_WATERMARK_LOW);
677 if (ret)
678 return ret;
679
680 ret = rv770_convert_power_level_to_smc(rdev,
681 &state->medium,
682 &smc_state->levels[1],
683 PPSMC_DISPLAY_WATERMARK_LOW);
684 if (ret)
685 return ret;
686
687 ret = rv770_convert_power_level_to_smc(rdev,
688 &state->high,
689 &smc_state->levels[2],
690 PPSMC_DISPLAY_WATERMARK_HIGH);
691 if (ret)
692 return ret;
693
694 smc_state->levels[0].arbValue = MC_CG_ARB_FREQ_F1;
695 smc_state->levels[1].arbValue = MC_CG_ARB_FREQ_F2;
696 smc_state->levels[2].arbValue = MC_CG_ARB_FREQ_F3;
697
698 smc_state->levels[0].seqValue = rv770_get_seq_value(rdev,
699 &state->low);
700 smc_state->levels[1].seqValue = rv770_get_seq_value(rdev,
701 &state->medium);
702 smc_state->levels[2].seqValue = rv770_get_seq_value(rdev,
703 &state->high);
704
705 rv770_populate_smc_sp(rdev, radeon_state, smc_state);
706
707 return rv770_populate_smc_t(rdev, radeon_state, smc_state);
708
709 }
710
711 u32 rv770_calculate_memory_refresh_rate(struct radeon_device *rdev,
712 u32 engine_clock)
713 {
714 u32 dram_rows;
715 u32 dram_refresh_rate;
716 u32 mc_arb_rfsh_rate;
717 u32 tmp;
718
719 tmp = (RREG32(MC_ARB_RAMCFG) & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
720 dram_rows = 1 << (tmp + 10);
721 tmp = RREG32(MC_SEQ_MISC0) & 3;
722 dram_refresh_rate = 1 << (tmp + 3);
723 mc_arb_rfsh_rate = ((engine_clock * 10) * dram_refresh_rate / dram_rows - 32) / 64;
724
725 return mc_arb_rfsh_rate;
726 }
727
728 static void rv770_program_memory_timing_parameters(struct radeon_device *rdev,
729 struct radeon_ps *radeon_state)
730 {
731 struct rv7xx_ps *state = rv770_get_ps(radeon_state);
732 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
733 u32 sqm_ratio;
734 u32 arb_refresh_rate;
735 u32 high_clock;
736
737 if (state->high.sclk < (state->low.sclk * 0xFF / 0x40))
738 high_clock = state->high.sclk;
739 else
740 high_clock = (state->low.sclk * 0xFF / 0x40);
741
742 radeon_atom_set_engine_dram_timings(rdev, high_clock,
743 state->high.mclk);
744
745 sqm_ratio =
746 STATE0(64 * high_clock / pi->boot_sclk) |
747 STATE1(64 * high_clock / state->low.sclk) |
748 STATE2(64 * high_clock / state->medium.sclk) |
749 STATE3(64 * high_clock / state->high.sclk);
750 WREG32(MC_ARB_SQM_RATIO, sqm_ratio);
751
752 arb_refresh_rate =
753 POWERMODE0(rv770_calculate_memory_refresh_rate(rdev, pi->boot_sclk)) |
754 POWERMODE1(rv770_calculate_memory_refresh_rate(rdev, state->low.sclk)) |
755 POWERMODE2(rv770_calculate_memory_refresh_rate(rdev, state->medium.sclk)) |
756 POWERMODE3(rv770_calculate_memory_refresh_rate(rdev, state->high.sclk));
757 WREG32(MC_ARB_RFSH_RATE, arb_refresh_rate);
758 }
759
760 void rv770_enable_backbias(struct radeon_device *rdev,
761 bool enable)
762 {
763 if (enable)
764 WREG32_P(GENERAL_PWRMGT, BACKBIAS_PAD_EN, ~BACKBIAS_PAD_EN);
765 else
766 WREG32_P(GENERAL_PWRMGT, 0, ~(BACKBIAS_VALUE | BACKBIAS_PAD_EN));
767 }
768
769 static void rv770_enable_spread_spectrum(struct radeon_device *rdev,
770 bool enable)
771 {
772 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
773
774 if (enable) {
775 if (pi->sclk_ss)
776 WREG32_P(GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, ~DYN_SPREAD_SPECTRUM_EN);
777
778 if (pi->mclk_ss) {
779 if (rdev->family == CHIP_RV740)
780 rv740_enable_mclk_spread_spectrum(rdev, true);
781 }
782 } else {
783 WREG32_P(CG_SPLL_SPREAD_SPECTRUM, 0, ~SSEN);
784
785 WREG32_P(GENERAL_PWRMGT, 0, ~DYN_SPREAD_SPECTRUM_EN);
786
787 WREG32_P(CG_MPLL_SPREAD_SPECTRUM, 0, ~SSEN);
788
789 if (rdev->family == CHIP_RV740)
790 rv740_enable_mclk_spread_spectrum(rdev, false);
791 }
792 }
793
794 static void rv770_program_mpll_timing_parameters(struct radeon_device *rdev)
795 {
796 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
797
798 if ((rdev->family == CHIP_RV770) && !pi->mem_gddr5) {
799 WREG32(MPLL_TIME,
800 (MPLL_LOCK_TIME(R600_MPLLLOCKTIME_DFLT * pi->ref_div) |
801 MPLL_RESET_TIME(R600_MPLLRESETTIME_DFLT)));
802 }
803 }
804
805 void rv770_setup_bsp(struct radeon_device *rdev)
806 {
807 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
808 u32 xclk = radeon_get_xclk(rdev);
809
810 r600_calculate_u_and_p(pi->asi,
811 xclk,
812 16,
813 &pi->bsp,
814 &pi->bsu);
815
816 r600_calculate_u_and_p(pi->pasi,
817 xclk,
818 16,
819 &pi->pbsp,
820 &pi->pbsu);
821
822 pi->dsp = BSP(pi->bsp) | BSU(pi->bsu);
823 pi->psp = BSP(pi->pbsp) | BSU(pi->pbsu);
824
825 WREG32(CG_BSP, pi->dsp);
826
827 }
828
829 void rv770_program_git(struct radeon_device *rdev)
830 {
831 WREG32_P(CG_GIT, CG_GICST(R600_GICST_DFLT), ~CG_GICST_MASK);
832 }
833
834 void rv770_program_tp(struct radeon_device *rdev)
835 {
836 int i;
837 enum r600_td td = R600_TD_DFLT;
838
839 for (i = 0; i < R600_PM_NUMBER_OF_TC; i++)
840 WREG32(CG_FFCT_0 + (i * 4), (UTC_0(r600_utc[i]) | DTC_0(r600_dtc[i])));
841
842 if (td == R600_TD_AUTO)
843 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL);
844 else
845 WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL);
846 if (td == R600_TD_UP)
847 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE);
848 if (td == R600_TD_DOWN)
849 WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE);
850 }
851
852 void rv770_program_tpp(struct radeon_device *rdev)
853 {
854 WREG32(CG_TPC, R600_TPC_DFLT);
855 }
856
857 void rv770_program_sstp(struct radeon_device *rdev)
858 {
859 WREG32(CG_SSP, (SSTU(R600_SSTU_DFLT) | SST(R600_SST_DFLT)));
860 }
861
862 void rv770_program_engine_speed_parameters(struct radeon_device *rdev)
863 {
864 WREG32_P(SPLL_CNTL_MODE, SPLL_DIV_SYNC, ~SPLL_DIV_SYNC);
865 }
866
867 static void rv770_enable_display_gap(struct radeon_device *rdev)
868 {
869 u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL);
870
871 tmp &= ~(DISP1_GAP_MCHG_MASK | DISP2_GAP_MCHG_MASK);
872 tmp |= (DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE) |
873 DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE));
874 WREG32(CG_DISPLAY_GAP_CNTL, tmp);
875 }
876
877 void rv770_program_vc(struct radeon_device *rdev)
878 {
879 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
880
881 WREG32(CG_FTV, pi->vrc);
882 }
883
884 void rv770_clear_vc(struct radeon_device *rdev)
885 {
886 WREG32(CG_FTV, 0);
887 }
888
889 int rv770_upload_firmware(struct radeon_device *rdev)
890 {
891 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
892 int ret;
893
894 rv770_reset_smc(rdev);
895 rv770_stop_smc_clock(rdev);
896
897 ret = rv770_load_smc_ucode(rdev, pi->sram_end);
898 if (ret)
899 return ret;
900
901 return 0;
902 }
903
904 static int rv770_populate_smc_acpi_state(struct radeon_device *rdev,
905 RV770_SMC_STATETABLE *table)
906 {
907 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
908
909 u32 mpll_ad_func_cntl =
910 pi->clk_regs.rv770.mpll_ad_func_cntl;
911 u32 mpll_ad_func_cntl_2 =
912 pi->clk_regs.rv770.mpll_ad_func_cntl_2;
913 u32 mpll_dq_func_cntl =
914 pi->clk_regs.rv770.mpll_dq_func_cntl;
915 u32 mpll_dq_func_cntl_2 =
916 pi->clk_regs.rv770.mpll_dq_func_cntl_2;
917 u32 spll_func_cntl =
918 pi->clk_regs.rv770.cg_spll_func_cntl;
919 u32 spll_func_cntl_2 =
920 pi->clk_regs.rv770.cg_spll_func_cntl_2;
921 u32 spll_func_cntl_3 =
922 pi->clk_regs.rv770.cg_spll_func_cntl_3;
923 u32 mclk_pwrmgt_cntl;
924 u32 dll_cntl;
925
926 table->ACPIState = table->initialState;
927
928 table->ACPIState.flags &= ~PPSMC_SWSTATE_FLAG_DC;
929
930 if (pi->acpi_vddc) {
931 rv770_populate_vddc_value(rdev, pi->acpi_vddc,
932 &table->ACPIState.levels[0].vddc);
933 if (pi->pcie_gen2) {
934 if (pi->acpi_pcie_gen2)
935 table->ACPIState.levels[0].gen2PCIE = 1;
936 else
937 table->ACPIState.levels[0].gen2PCIE = 0;
938 } else
939 table->ACPIState.levels[0].gen2PCIE = 0;
940 if (pi->acpi_pcie_gen2)
941 table->ACPIState.levels[0].gen2XSP = 1;
942 else
943 table->ACPIState.levels[0].gen2XSP = 0;
944 } else {
945 rv770_populate_vddc_value(rdev, pi->min_vddc_in_table,
946 &table->ACPIState.levels[0].vddc);
947 table->ACPIState.levels[0].gen2PCIE = 0;
948 }
949
950
951 mpll_ad_func_cntl_2 |= BIAS_GEN_PDNB | RESET_EN;
952
953 mpll_dq_func_cntl_2 |= BIAS_GEN_PDNB | RESET_EN;
954
955 mclk_pwrmgt_cntl = (MRDCKA0_RESET |
956 MRDCKA1_RESET |
957 MRDCKB0_RESET |
958 MRDCKB1_RESET |
959 MRDCKC0_RESET |
960 MRDCKC1_RESET |
961 MRDCKD0_RESET |
962 MRDCKD1_RESET);
963
964 dll_cntl = 0xff000000;
965
966 spll_func_cntl |= SPLL_RESET | SPLL_SLEEP | SPLL_BYPASS_EN;
967
968 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
969 spll_func_cntl_2 |= SCLK_MUX_SEL(4);
970
971 table->ACPIState.levels[0].mclk.mclk770.vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl);
972 table->ACPIState.levels[0].mclk.mclk770.vMPLL_AD_FUNC_CNTL_2 = cpu_to_be32(mpll_ad_func_cntl_2);
973 table->ACPIState.levels[0].mclk.mclk770.vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl);
974 table->ACPIState.levels[0].mclk.mclk770.vMPLL_DQ_FUNC_CNTL_2 = cpu_to_be32(mpll_dq_func_cntl_2);
975
976 table->ACPIState.levels[0].mclk.mclk770.vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl);
977 table->ACPIState.levels[0].mclk.mclk770.vDLL_CNTL = cpu_to_be32(dll_cntl);
978
979 table->ACPIState.levels[0].mclk.mclk770.mclk_value = 0;
980
981 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl);
982 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(spll_func_cntl_2);
983 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(spll_func_cntl_3);
984
985 table->ACPIState.levels[0].sclk.sclk_value = 0;
986
987 rv770_populate_mvdd_value(rdev, 0, &table->ACPIState.levels[0].mvdd);
988
989 table->ACPIState.levels[1] = table->ACPIState.levels[0];
990 table->ACPIState.levels[2] = table->ACPIState.levels[0];
991
992 return 0;
993 }
994
995 int rv770_populate_initial_mvdd_value(struct radeon_device *rdev,
996 RV770_SMC_VOLTAGE_VALUE *voltage)
997 {
998 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
999
1000 if ((pi->s0_vid_lower_smio_cntl & pi->mvdd_mask_low) ==
1001 (pi->mvdd_low_smio[MVDD_LOW_INDEX] & pi->mvdd_mask_low) ) {
1002 voltage->index = MVDD_LOW_INDEX;
1003 voltage->value = cpu_to_be16(MVDD_LOW_VALUE);
1004 } else {
1005 voltage->index = MVDD_HIGH_INDEX;
1006 voltage->value = cpu_to_be16(MVDD_HIGH_VALUE);
1007 }
1008
1009 return 0;
1010 }
1011
1012 static int rv770_populate_smc_initial_state(struct radeon_device *rdev,
1013 struct radeon_ps *radeon_state,
1014 RV770_SMC_STATETABLE *table)
1015 {
1016 struct rv7xx_ps *initial_state = rv770_get_ps(radeon_state);
1017 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1018 u32 a_t;
1019
1020 table->initialState.levels[0].mclk.mclk770.vMPLL_AD_FUNC_CNTL =
1021 cpu_to_be32(pi->clk_regs.rv770.mpll_ad_func_cntl);
1022 table->initialState.levels[0].mclk.mclk770.vMPLL_AD_FUNC_CNTL_2 =
1023 cpu_to_be32(pi->clk_regs.rv770.mpll_ad_func_cntl_2);
1024 table->initialState.levels[0].mclk.mclk770.vMPLL_DQ_FUNC_CNTL =
1025 cpu_to_be32(pi->clk_regs.rv770.mpll_dq_func_cntl);
1026 table->initialState.levels[0].mclk.mclk770.vMPLL_DQ_FUNC_CNTL_2 =
1027 cpu_to_be32(pi->clk_regs.rv770.mpll_dq_func_cntl_2);
1028 table->initialState.levels[0].mclk.mclk770.vMCLK_PWRMGT_CNTL =
1029 cpu_to_be32(pi->clk_regs.rv770.mclk_pwrmgt_cntl);
1030 table->initialState.levels[0].mclk.mclk770.vDLL_CNTL =
1031 cpu_to_be32(pi->clk_regs.rv770.dll_cntl);
1032
1033 table->initialState.levels[0].mclk.mclk770.vMPLL_SS =
1034 cpu_to_be32(pi->clk_regs.rv770.mpll_ss1);
1035 table->initialState.levels[0].mclk.mclk770.vMPLL_SS2 =
1036 cpu_to_be32(pi->clk_regs.rv770.mpll_ss2);
1037
1038 table->initialState.levels[0].mclk.mclk770.mclk_value =
1039 cpu_to_be32(initial_state->low.mclk);
1040
1041 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
1042 cpu_to_be32(pi->clk_regs.rv770.cg_spll_func_cntl);
1043 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
1044 cpu_to_be32(pi->clk_regs.rv770.cg_spll_func_cntl_2);
1045 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
1046 cpu_to_be32(pi->clk_regs.rv770.cg_spll_func_cntl_3);
1047 table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM =
1048 cpu_to_be32(pi->clk_regs.rv770.cg_spll_spread_spectrum);
1049 table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM_2 =
1050 cpu_to_be32(pi->clk_regs.rv770.cg_spll_spread_spectrum_2);
1051
1052 table->initialState.levels[0].sclk.sclk_value =
1053 cpu_to_be32(initial_state->low.sclk);
1054
1055 table->initialState.levels[0].arbValue = MC_CG_ARB_FREQ_F0;
1056
1057 table->initialState.levels[0].seqValue =
1058 rv770_get_seq_value(rdev, &initial_state->low);
1059
1060 rv770_populate_vddc_value(rdev,
1061 initial_state->low.vddc,
1062 &table->initialState.levels[0].vddc);
1063 rv770_populate_initial_mvdd_value(rdev,
1064 &table->initialState.levels[0].mvdd);
1065
1066 a_t = CG_R(0xffff) | CG_L(0);
1067 table->initialState.levels[0].aT = cpu_to_be32(a_t);
1068
1069 table->initialState.levels[0].bSP = cpu_to_be32(pi->dsp);
1070
1071 if (pi->boot_in_gen2)
1072 table->initialState.levels[0].gen2PCIE = 1;
1073 else
1074 table->initialState.levels[0].gen2PCIE = 0;
1075 if (initial_state->low.flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2)
1076 table->initialState.levels[0].gen2XSP = 1;
1077 else
1078 table->initialState.levels[0].gen2XSP = 0;
1079
1080 if (rdev->family == CHIP_RV740) {
1081 if (pi->mem_gddr5) {
1082 if (initial_state->low.mclk <= pi->mclk_strobe_mode_threshold)
1083 table->initialState.levels[0].strobeMode =
1084 rv740_get_mclk_frequency_ratio(initial_state->low.mclk) | 0x10;
1085 else
1086 table->initialState.levels[0].strobeMode = 0;
1087
1088 if (initial_state->low.mclk >= pi->mclk_edc_enable_threshold)
1089 table->initialState.levels[0].mcFlags = SMC_MC_EDC_RD_FLAG | SMC_MC_EDC_WR_FLAG;
1090 else
1091 table->initialState.levels[0].mcFlags = 0;
1092 }
1093 }
1094
1095 table->initialState.levels[1] = table->initialState.levels[0];
1096 table->initialState.levels[2] = table->initialState.levels[0];
1097
1098 table->initialState.flags |= PPSMC_SWSTATE_FLAG_DC;
1099
1100 return 0;
1101 }
1102
1103 static int rv770_populate_smc_vddc_table(struct radeon_device *rdev,
1104 RV770_SMC_STATETABLE *table)
1105 {
1106 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1107 int i;
1108
1109 for (i = 0; i < pi->valid_vddc_entries; i++) {
1110 table->highSMIO[pi->vddc_table[i].vddc_index] =
1111 pi->vddc_table[i].high_smio;
1112 table->lowSMIO[pi->vddc_table[i].vddc_index] =
1113 cpu_to_be32(pi->vddc_table[i].low_smio);
1114 }
1115
1116 table->voltageMaskTable.highMask[RV770_SMC_VOLTAGEMASK_VDDC] = 0;
1117 table->voltageMaskTable.lowMask[RV770_SMC_VOLTAGEMASK_VDDC] =
1118 cpu_to_be32(pi->vddc_mask_low);
1119
1120 for (i = 0;
1121 ((i < pi->valid_vddc_entries) &&
1122 (pi->max_vddc_in_table >
1123 pi->vddc_table[i].vddc));
1124 i++);
1125
1126 table->maxVDDCIndexInPPTable =
1127 pi->vddc_table[i].vddc_index;
1128
1129 return 0;
1130 }
1131
1132 static int rv770_populate_smc_mvdd_table(struct radeon_device *rdev,
1133 RV770_SMC_STATETABLE *table)
1134 {
1135 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1136
1137 if (pi->mvdd_control) {
1138 table->lowSMIO[MVDD_HIGH_INDEX] |=
1139 cpu_to_be32(pi->mvdd_low_smio[MVDD_HIGH_INDEX]);
1140 table->lowSMIO[MVDD_LOW_INDEX] |=
1141 cpu_to_be32(pi->mvdd_low_smio[MVDD_LOW_INDEX]);
1142
1143 table->voltageMaskTable.highMask[RV770_SMC_VOLTAGEMASK_MVDD] = 0;
1144 table->voltageMaskTable.lowMask[RV770_SMC_VOLTAGEMASK_MVDD] =
1145 cpu_to_be32(pi->mvdd_mask_low);
1146 }
1147
1148 return 0;
1149 }
1150
1151 static int rv770_init_smc_table(struct radeon_device *rdev)
1152 {
1153 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1154 struct radeon_ps *radeon_boot_state = rdev->pm.dpm.boot_ps;
1155 struct rv7xx_ps *boot_state = rv770_get_ps(radeon_boot_state);
1156 RV770_SMC_STATETABLE *table = &pi->smc_statetable;
1157 int ret;
1158
1159 memset(table, 0, sizeof(RV770_SMC_STATETABLE));
1160
1161 pi->boot_sclk = boot_state->low.sclk;
1162
1163 rv770_populate_smc_vddc_table(rdev, table);
1164 rv770_populate_smc_mvdd_table(rdev, table);
1165
1166 switch (rdev->pm.int_thermal_type) {
1167 case THERMAL_TYPE_RV770:
1168 case THERMAL_TYPE_ADT7473_WITH_INTERNAL:
1169 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_INTERNAL;
1170 break;
1171 case THERMAL_TYPE_NONE:
1172 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_NONE;
1173 break;
1174 case THERMAL_TYPE_EXTERNAL_GPIO:
1175 default:
1176 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL;
1177 break;
1178 }
1179
1180 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC) {
1181 table->systemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
1182
1183 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_DONT_WAIT_FOR_VBLANK_ON_ALERT)
1184 table->extraFlags |= PPSMC_EXTRAFLAGS_AC2DC_DONT_WAIT_FOR_VBLANK;
1185
1186 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_GOTO_BOOT_ON_ALERT)
1187 table->extraFlags |= PPSMC_EXTRAFLAGS_AC2DC_ACTION_GOTOINITIALSTATE;
1188 }
1189
1190 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC)
1191 table->systemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
1192
1193 if (pi->mem_gddr5)
1194 table->systemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
1195
1196 if ((rdev->family == CHIP_RV730) || (rdev->family == CHIP_RV710))
1197 ret = rv730_populate_smc_initial_state(rdev, radeon_boot_state, table);
1198 else
1199 ret = rv770_populate_smc_initial_state(rdev, radeon_boot_state, table);
1200 if (ret)
1201 return ret;
1202
1203 if (rdev->family == CHIP_RV740)
1204 ret = rv740_populate_smc_acpi_state(rdev, table);
1205 else if ((rdev->family == CHIP_RV730) || (rdev->family == CHIP_RV710))
1206 ret = rv730_populate_smc_acpi_state(rdev, table);
1207 else
1208 ret = rv770_populate_smc_acpi_state(rdev, table);
1209 if (ret)
1210 return ret;
1211
1212 table->driverState = table->initialState;
1213
1214 return rv770_copy_bytes_to_smc(rdev,
1215 pi->state_table_start,
1216 (const u8 *)table,
1217 sizeof(RV770_SMC_STATETABLE),
1218 pi->sram_end);
1219 }
1220
1221 static int rv770_construct_vddc_table(struct radeon_device *rdev)
1222 {
1223 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1224 u16 min, max, step;
1225 u32 steps = 0;
1226 u8 vddc_index = 0;
1227 u32 i;
1228
1229 radeon_atom_get_min_voltage(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, &min);
1230 radeon_atom_get_max_voltage(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, &max);
1231 radeon_atom_get_voltage_step(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, &step);
1232
1233 steps = (max - min) / step + 1;
1234
1235 if (steps > MAX_NO_VREG_STEPS)
1236 return -EINVAL;
1237
1238 for (i = 0; i < steps; i++) {
1239 u32 gpio_pins, gpio_mask;
1240
1241 pi->vddc_table[i].vddc = (u16)(min + i * step);
1242 radeon_atom_get_voltage_gpio_settings(rdev,
1243 pi->vddc_table[i].vddc,
1244 SET_VOLTAGE_TYPE_ASIC_VDDC,
1245 &gpio_pins, &gpio_mask);
1246 pi->vddc_table[i].low_smio = gpio_pins & gpio_mask;
1247 pi->vddc_table[i].high_smio = 0;
1248 pi->vddc_mask_low = gpio_mask;
1249 if (i > 0) {
1250 if ((pi->vddc_table[i].low_smio !=
1251 pi->vddc_table[i - 1].low_smio ) ||
1252 (pi->vddc_table[i].high_smio !=
1253 pi->vddc_table[i - 1].high_smio))
1254 vddc_index++;
1255 }
1256 pi->vddc_table[i].vddc_index = vddc_index;
1257 }
1258
1259 pi->valid_vddc_entries = (u8)steps;
1260
1261 return 0;
1262 }
1263
1264 static u32 rv770_get_mclk_split_point(struct atom_memory_info *memory_info)
1265 {
1266 if (memory_info->mem_type == MEM_TYPE_GDDR3)
1267 return 30000;
1268
1269 return 0;
1270 }
1271
1272 static int rv770_get_mvdd_pin_configuration(struct radeon_device *rdev)
1273 {
1274 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1275 u32 gpio_pins, gpio_mask;
1276
1277 radeon_atom_get_voltage_gpio_settings(rdev,
1278 MVDD_HIGH_VALUE, SET_VOLTAGE_TYPE_ASIC_MVDDC,
1279 &gpio_pins, &gpio_mask);
1280 pi->mvdd_mask_low = gpio_mask;
1281 pi->mvdd_low_smio[MVDD_HIGH_INDEX] =
1282 gpio_pins & gpio_mask;
1283
1284 radeon_atom_get_voltage_gpio_settings(rdev,
1285 MVDD_LOW_VALUE, SET_VOLTAGE_TYPE_ASIC_MVDDC,
1286 &gpio_pins, &gpio_mask);
1287 pi->mvdd_low_smio[MVDD_LOW_INDEX] =
1288 gpio_pins & gpio_mask;
1289
1290 return 0;
1291 }
1292
1293 u8 rv770_get_memory_module_index(struct radeon_device *rdev)
1294 {
1295 return (u8) ((RREG32(BIOS_SCRATCH_4) >> 16) & 0xff);
1296 }
1297
1298 static int rv770_get_mvdd_configuration(struct radeon_device *rdev)
1299 {
1300 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1301 u8 memory_module_index;
1302 struct atom_memory_info memory_info;
1303
1304 memory_module_index = rv770_get_memory_module_index(rdev);
1305
1306 if (radeon_atom_get_memory_info(rdev, memory_module_index, &memory_info)) {
1307 pi->mvdd_control = false;
1308 return 0;
1309 }
1310
1311 pi->mvdd_split_frequency =
1312 rv770_get_mclk_split_point(&memory_info);
1313
1314 if (pi->mvdd_split_frequency == 0) {
1315 pi->mvdd_control = false;
1316 return 0;
1317 }
1318
1319 return rv770_get_mvdd_pin_configuration(rdev);
1320 }
1321
1322 void rv770_enable_voltage_control(struct radeon_device *rdev,
1323 bool enable)
1324 {
1325 if (enable)
1326 WREG32_P(GENERAL_PWRMGT, VOLT_PWRMGT_EN, ~VOLT_PWRMGT_EN);
1327 else
1328 WREG32_P(GENERAL_PWRMGT, 0, ~VOLT_PWRMGT_EN);
1329 }
1330
1331 static void rv770_program_display_gap(struct radeon_device *rdev)
1332 {
1333 u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL);
1334
1335 tmp &= ~(DISP1_GAP_MCHG_MASK | DISP2_GAP_MCHG_MASK);
1336 if (RREG32(AVIVO_D1CRTC_CONTROL) & AVIVO_CRTC_EN) {
1337 tmp |= DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK);
1338 tmp |= DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE);
1339 } else if (RREG32(AVIVO_D2CRTC_CONTROL) & AVIVO_CRTC_EN) {
1340 tmp |= DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE);
1341 tmp |= DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK);
1342 } else {
1343 tmp |= DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE);
1344 tmp |= DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE);
1345 }
1346 WREG32(CG_DISPLAY_GAP_CNTL, tmp);
1347 }
1348
1349 static void rv770_enable_dynamic_pcie_gen2(struct radeon_device *rdev,
1350 bool enable)
1351 {
1352 rv770_enable_bif_dynamic_pcie_gen2(rdev, enable);
1353
1354 if (enable)
1355 WREG32_P(GENERAL_PWRMGT, ENABLE_GEN2PCIE, ~ENABLE_GEN2PCIE);
1356 else
1357 WREG32_P(GENERAL_PWRMGT, 0, ~ENABLE_GEN2PCIE);
1358 }
1359
1360 static void r7xx_program_memory_timing_parameters(struct radeon_device *rdev)
1361 {
1362 struct radeon_ps *radeon_new_state = rdev->pm.dpm.requested_ps;
1363
1364 if ((rdev->family == CHIP_RV730) ||
1365 (rdev->family == CHIP_RV710) ||
1366 (rdev->family == CHIP_RV740))
1367 rv730_program_memory_timing_parameters(rdev, radeon_new_state);
1368 else
1369 rv770_program_memory_timing_parameters(rdev, radeon_new_state);
1370 }
1371
1372 static int rv770_upload_sw_state(struct radeon_device *rdev)
1373 {
1374 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1375 struct radeon_ps *radeon_new_state = rdev->pm.dpm.requested_ps;
1376 u16 address = pi->state_table_start +
1377 offsetof(RV770_SMC_STATETABLE, driverState);
1378 RV770_SMC_SWSTATE state = { 0 };
1379 int ret;
1380
1381 ret = rv770_convert_power_state_to_smc(rdev, radeon_new_state, &state);
1382 if (ret)
1383 return ret;
1384
1385 return rv770_copy_bytes_to_smc(rdev, address, (const u8 *)&state,
1386 sizeof(RV770_SMC_SWSTATE),
1387 pi->sram_end);
1388 }
1389
1390 int rv770_halt_smc(struct radeon_device *rdev)
1391 {
1392 if (rv770_send_msg_to_smc(rdev, PPSMC_MSG_Halt) != PPSMC_Result_OK)
1393 return -EINVAL;
1394
1395 if (rv770_wait_for_smc_inactive(rdev) != PPSMC_Result_OK)
1396 return -EINVAL;
1397
1398 return 0;
1399 }
1400
1401 int rv770_resume_smc(struct radeon_device *rdev)
1402 {
1403 if (rv770_send_msg_to_smc(rdev, PPSMC_MSG_Resume) != PPSMC_Result_OK)
1404 return -EINVAL;
1405 return 0;
1406 }
1407
1408 int rv770_set_sw_state(struct radeon_device *rdev)
1409 {
1410 if (rv770_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToSwState) != PPSMC_Result_OK)
1411 return -EINVAL;
1412 return 0;
1413 }
1414
1415 int rv770_set_boot_state(struct radeon_device *rdev)
1416 {
1417 if (rv770_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToInitialState) != PPSMC_Result_OK)
1418 return -EINVAL;
1419 return 0;
1420 }
1421
1422 int rv770_restrict_performance_levels_before_switch(struct radeon_device *rdev)
1423 {
1424 if (rv770_send_msg_to_smc(rdev, (PPSMC_Msg)(PPSMC_MSG_NoForcedLevel)) != PPSMC_Result_OK)
1425 return -EINVAL;
1426
1427 if (rv770_send_msg_to_smc(rdev, (PPSMC_Msg)(PPSMC_MSG_TwoLevelsDisabled)) != PPSMC_Result_OK)
1428 return -EINVAL;
1429
1430 return 0;
1431 }
1432
1433 int rv770_unrestrict_performance_levels_after_switch(struct radeon_device *rdev)
1434 {
1435 if (rv770_send_msg_to_smc(rdev, (PPSMC_Msg)(PPSMC_MSG_NoForcedLevel)) != PPSMC_Result_OK)
1436 return -EINVAL;
1437
1438 if (rv770_send_msg_to_smc(rdev, (PPSMC_Msg)(PPSMC_MSG_ZeroLevelsDisabled)) != PPSMC_Result_OK)
1439 return -EINVAL;
1440
1441 return 0;
1442 }
1443
1444 void r7xx_start_smc(struct radeon_device *rdev)
1445 {
1446 rv770_start_smc(rdev);
1447 rv770_start_smc_clock(rdev);
1448 }
1449
1450
1451 void r7xx_stop_smc(struct radeon_device *rdev)
1452 {
1453 rv770_reset_smc(rdev);
1454 rv770_stop_smc_clock(rdev);
1455 }
1456
1457 static void rv770_read_clock_registers(struct radeon_device *rdev)
1458 {
1459 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1460
1461 pi->clk_regs.rv770.cg_spll_func_cntl =
1462 RREG32(CG_SPLL_FUNC_CNTL);
1463 pi->clk_regs.rv770.cg_spll_func_cntl_2 =
1464 RREG32(CG_SPLL_FUNC_CNTL_2);
1465 pi->clk_regs.rv770.cg_spll_func_cntl_3 =
1466 RREG32(CG_SPLL_FUNC_CNTL_3);
1467 pi->clk_regs.rv770.cg_spll_spread_spectrum =
1468 RREG32(CG_SPLL_SPREAD_SPECTRUM);
1469 pi->clk_regs.rv770.cg_spll_spread_spectrum_2 =
1470 RREG32(CG_SPLL_SPREAD_SPECTRUM_2);
1471 pi->clk_regs.rv770.mpll_ad_func_cntl =
1472 RREG32(MPLL_AD_FUNC_CNTL);
1473 pi->clk_regs.rv770.mpll_ad_func_cntl_2 =
1474 RREG32(MPLL_AD_FUNC_CNTL_2);
1475 pi->clk_regs.rv770.mpll_dq_func_cntl =
1476 RREG32(MPLL_DQ_FUNC_CNTL);
1477 pi->clk_regs.rv770.mpll_dq_func_cntl_2 =
1478 RREG32(MPLL_DQ_FUNC_CNTL_2);
1479 pi->clk_regs.rv770.mclk_pwrmgt_cntl =
1480 RREG32(MCLK_PWRMGT_CNTL);
1481 pi->clk_regs.rv770.dll_cntl = RREG32(DLL_CNTL);
1482 }
1483
1484 static void r7xx_read_clock_registers(struct radeon_device *rdev)
1485 {
1486 if (rdev->family == CHIP_RV740)
1487 rv740_read_clock_registers(rdev);
1488 else if ((rdev->family == CHIP_RV730) || (rdev->family == CHIP_RV710))
1489 rv730_read_clock_registers(rdev);
1490 else
1491 rv770_read_clock_registers(rdev);
1492 }
1493
1494 void rv770_read_voltage_smio_registers(struct radeon_device *rdev)
1495 {
1496 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1497
1498 pi->s0_vid_lower_smio_cntl =
1499 RREG32(S0_VID_LOWER_SMIO_CNTL);
1500 }
1501
1502 void rv770_reset_smio_status(struct radeon_device *rdev)
1503 {
1504 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1505 u32 sw_smio_index, vid_smio_cntl;
1506
1507 sw_smio_index =
1508 (RREG32(GENERAL_PWRMGT) & SW_SMIO_INDEX_MASK) >> SW_SMIO_INDEX_SHIFT;
1509 switch (sw_smio_index) {
1510 case 3:
1511 vid_smio_cntl = RREG32(S3_VID_LOWER_SMIO_CNTL);
1512 break;
1513 case 2:
1514 vid_smio_cntl = RREG32(S2_VID_LOWER_SMIO_CNTL);
1515 break;
1516 case 1:
1517 vid_smio_cntl = RREG32(S1_VID_LOWER_SMIO_CNTL);
1518 break;
1519 case 0:
1520 return;
1521 default:
1522 vid_smio_cntl = pi->s0_vid_lower_smio_cntl;
1523 break;
1524 }
1525
1526 WREG32(S0_VID_LOWER_SMIO_CNTL, vid_smio_cntl);
1527 WREG32_P(GENERAL_PWRMGT, SW_SMIO_INDEX(0), ~SW_SMIO_INDEX_MASK);
1528 }
1529
1530 void rv770_get_memory_type(struct radeon_device *rdev)
1531 {
1532 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1533 u32 tmp;
1534
1535 tmp = RREG32(MC_SEQ_MISC0);
1536
1537 if (((tmp & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT) ==
1538 MC_SEQ_MISC0_GDDR5_VALUE)
1539 pi->mem_gddr5 = true;
1540 else
1541 pi->mem_gddr5 = false;
1542
1543 }
1544
1545 void rv770_get_pcie_gen2_status(struct radeon_device *rdev)
1546 {
1547 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1548 u32 tmp;
1549
1550 tmp = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
1551
1552 if ((tmp & LC_OTHER_SIDE_EVER_SENT_GEN2) &&
1553 (tmp & LC_OTHER_SIDE_SUPPORTS_GEN2))
1554 pi->pcie_gen2 = true;
1555 else
1556 pi->pcie_gen2 = false;
1557
1558 if (pi->pcie_gen2) {
1559 if (tmp & LC_CURRENT_DATA_RATE)
1560 pi->boot_in_gen2 = true;
1561 else
1562 pi->boot_in_gen2 = false;
1563 } else
1564 pi->boot_in_gen2 = false;
1565 }
1566
1567 #if 0
1568 static int rv770_enter_ulp_state(struct radeon_device *rdev)
1569 {
1570 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1571
1572 if (pi->gfx_clock_gating) {
1573 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN);
1574 WREG32_P(SCLK_PWRMGT_CNTL, GFX_CLK_FORCE_ON, ~GFX_CLK_FORCE_ON);
1575 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~GFX_CLK_FORCE_ON);
1576 RREG32(GB_TILING_CONFIG);
1577 }
1578
1579 WREG32_P(SMC_MSG, HOST_SMC_MSG(PPSMC_MSG_SwitchToMinimumPower),
1580 ~HOST_SMC_MSG_MASK);
1581
1582 udelay(7000);
1583
1584 return 0;
1585 }
1586
1587 static int rv770_exit_ulp_state(struct radeon_device *rdev)
1588 {
1589 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1590 int i;
1591
1592 WREG32_P(SMC_MSG, HOST_SMC_MSG(PPSMC_MSG_ResumeFromMinimumPower),
1593 ~HOST_SMC_MSG_MASK);
1594
1595 udelay(7000);
1596
1597 for (i = 0; i < rdev->usec_timeout; i++) {
1598 if (((RREG32(SMC_MSG) & HOST_SMC_RESP_MASK) >> HOST_SMC_RESP_SHIFT) == 1)
1599 break;
1600 udelay(1000);
1601 }
1602
1603 if (pi->gfx_clock_gating)
1604 WREG32_P(SCLK_PWRMGT_CNTL, DYN_GFX_CLK_OFF_EN, ~DYN_GFX_CLK_OFF_EN);
1605
1606 return 0;
1607 }
1608 #endif
1609
1610 static void rv770_get_mclk_odt_threshold(struct radeon_device *rdev)
1611 {
1612 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1613 u8 memory_module_index;
1614 struct atom_memory_info memory_info;
1615
1616 pi->mclk_odt_threshold = 0;
1617
1618 if ((rdev->family == CHIP_RV730) || (rdev->family == CHIP_RV710)) {
1619 memory_module_index = rv770_get_memory_module_index(rdev);
1620
1621 if (radeon_atom_get_memory_info(rdev, memory_module_index, &memory_info))
1622 return;
1623
1624 if (memory_info.mem_type == MEM_TYPE_DDR2 ||
1625 memory_info.mem_type == MEM_TYPE_DDR3)
1626 pi->mclk_odt_threshold = 30000;
1627 }
1628 }
1629
1630 void rv770_get_max_vddc(struct radeon_device *rdev)
1631 {
1632 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1633 u16 vddc;
1634
1635 if (radeon_atom_get_max_vddc(rdev, 0, 0, &vddc))
1636 pi->max_vddc = 0;
1637 else
1638 pi->max_vddc = vddc;
1639 }
1640
1641 void rv770_program_response_times(struct radeon_device *rdev)
1642 {
1643 u32 voltage_response_time, backbias_response_time;
1644 u32 acpi_delay_time, vbi_time_out;
1645 u32 vddc_dly, bb_dly, acpi_dly, vbi_dly;
1646 u32 reference_clock;
1647
1648 voltage_response_time = (u32)rdev->pm.dpm.voltage_response_time;
1649 backbias_response_time = (u32)rdev->pm.dpm.backbias_response_time;
1650
1651 if (voltage_response_time == 0)
1652 voltage_response_time = 1000;
1653
1654 if (backbias_response_time == 0)
1655 backbias_response_time = 1000;
1656
1657 acpi_delay_time = 15000;
1658 vbi_time_out = 100000;
1659
1660 reference_clock = radeon_get_xclk(rdev);
1661
1662 vddc_dly = (voltage_response_time * reference_clock) / 1600;
1663 bb_dly = (backbias_response_time * reference_clock) / 1600;
1664 acpi_dly = (acpi_delay_time * reference_clock) / 1600;
1665 vbi_dly = (vbi_time_out * reference_clock) / 1600;
1666
1667 rv770_write_smc_soft_register(rdev,
1668 RV770_SMC_SOFT_REGISTER_delay_vreg, vddc_dly);
1669 rv770_write_smc_soft_register(rdev,
1670 RV770_SMC_SOFT_REGISTER_delay_bbias, bb_dly);
1671 rv770_write_smc_soft_register(rdev,
1672 RV770_SMC_SOFT_REGISTER_delay_acpi, acpi_dly);
1673 rv770_write_smc_soft_register(rdev,
1674 RV770_SMC_SOFT_REGISTER_mclk_chg_timeout, vbi_dly);
1675 #if 0
1676 /* XXX look up hw revision */
1677 if (WEKIVA_A21)
1678 rv770_write_smc_soft_register(rdev,
1679 RV770_SMC_SOFT_REGISTER_baby_step_timer,
1680 0x10);
1681 #endif
1682 }
1683
1684 static void rv770_program_dcodt_before_state_switch(struct radeon_device *rdev)
1685 {
1686 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1687 struct radeon_ps *radeon_new_state = rdev->pm.dpm.requested_ps;
1688 struct radeon_ps *radeon_current_state = rdev->pm.dpm.current_ps;
1689 struct rv7xx_ps *new_state = rv770_get_ps(radeon_new_state);
1690 struct rv7xx_ps *current_state = rv770_get_ps(radeon_current_state);
1691 bool current_use_dc = false;
1692 bool new_use_dc = false;
1693
1694 if (pi->mclk_odt_threshold == 0)
1695 return;
1696
1697 if (current_state->high.mclk <= pi->mclk_odt_threshold)
1698 current_use_dc = true;
1699
1700 if (new_state->high.mclk <= pi->mclk_odt_threshold)
1701 new_use_dc = true;
1702
1703 if (current_use_dc == new_use_dc)
1704 return;
1705
1706 if (!current_use_dc && new_use_dc)
1707 return;
1708
1709 if ((rdev->family == CHIP_RV730) || (rdev->family == CHIP_RV710))
1710 rv730_program_dcodt(rdev, new_use_dc);
1711 }
1712
1713 static void rv770_program_dcodt_after_state_switch(struct radeon_device *rdev)
1714 {
1715 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1716 struct radeon_ps *radeon_new_state = rdev->pm.dpm.requested_ps;
1717 struct radeon_ps *radeon_current_state = rdev->pm.dpm.current_ps;
1718 struct rv7xx_ps *new_state = rv770_get_ps(radeon_new_state);
1719 struct rv7xx_ps *current_state = rv770_get_ps(radeon_current_state);
1720 bool current_use_dc = false;
1721 bool new_use_dc = false;
1722
1723 if (pi->mclk_odt_threshold == 0)
1724 return;
1725
1726 if (current_state->high.mclk <= pi->mclk_odt_threshold)
1727 current_use_dc = true;
1728
1729 if (new_state->high.mclk <= pi->mclk_odt_threshold)
1730 new_use_dc = true;
1731
1732 if (current_use_dc == new_use_dc)
1733 return;
1734
1735 if (current_use_dc && !new_use_dc)
1736 return;
1737
1738 if ((rdev->family == CHIP_RV730) || (rdev->family == CHIP_RV710))
1739 rv730_program_dcodt(rdev, new_use_dc);
1740 }
1741
1742 static void rv770_retrieve_odt_values(struct radeon_device *rdev)
1743 {
1744 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1745
1746 if (pi->mclk_odt_threshold == 0)
1747 return;
1748
1749 if ((rdev->family == CHIP_RV730) || (rdev->family == CHIP_RV710))
1750 rv730_get_odt_values(rdev);
1751 }
1752
1753 static void rv770_set_dpm_event_sources(struct radeon_device *rdev, u32 sources)
1754 {
1755 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1756 bool want_thermal_protection;
1757 enum radeon_dpm_event_src dpm_event_src;
1758
1759 switch (sources) {
1760 case 0:
1761 default:
1762 want_thermal_protection = false;
1763 break;
1764 case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL):
1765 want_thermal_protection = true;
1766 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGITAL;
1767 break;
1768
1769 case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL):
1770 want_thermal_protection = true;
1771 dpm_event_src = RADEON_DPM_EVENT_SRC_EXTERNAL;
1772 break;
1773
1774 case ((1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL) |
1775 (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL)):
1776 want_thermal_protection = true;
1777 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL;
1778 break;
1779 }
1780
1781 if (want_thermal_protection) {
1782 WREG32_P(CG_THERMAL_CTRL, DPM_EVENT_SRC(dpm_event_src), ~DPM_EVENT_SRC_MASK);
1783 if (pi->thermal_protection)
1784 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS);
1785 } else {
1786 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS);
1787 }
1788 }
1789
1790 void rv770_enable_auto_throttle_source(struct radeon_device *rdev,
1791 enum radeon_dpm_auto_throttle_src source,
1792 bool enable)
1793 {
1794 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1795
1796 if (enable) {
1797 if (!(pi->active_auto_throttle_sources & (1 << source))) {
1798 pi->active_auto_throttle_sources |= 1 << source;
1799 rv770_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);
1800 }
1801 } else {
1802 if (pi->active_auto_throttle_sources & (1 << source)) {
1803 pi->active_auto_throttle_sources &= ~(1 << source);
1804 rv770_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);
1805 }
1806 }
1807 }
1808
1809 static int rv770_set_thermal_temperature_range(struct radeon_device *rdev,
1810 int min_temp, int max_temp)
1811 {
1812 int low_temp = 0 * 1000;
1813 int high_temp = 255 * 1000;
1814
1815 if (low_temp < min_temp)
1816 low_temp = min_temp;
1817 if (high_temp > max_temp)
1818 high_temp = max_temp;
1819 if (high_temp < low_temp) {
1820 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp);
1821 return -EINVAL;
1822 }
1823
1824 WREG32_P(CG_THERMAL_INT, DIG_THERM_INTH(high_temp / 1000), ~DIG_THERM_INTH_MASK);
1825 WREG32_P(CG_THERMAL_INT, DIG_THERM_INTL(low_temp / 1000), ~DIG_THERM_INTL_MASK);
1826 WREG32_P(CG_THERMAL_CTRL, DIG_THERM_DPM(high_temp / 1000), ~DIG_THERM_DPM_MASK);
1827
1828 rdev->pm.dpm.thermal.min_temp = low_temp;
1829 rdev->pm.dpm.thermal.max_temp = high_temp;
1830
1831 return 0;
1832 }
1833
1834 int rv770_dpm_enable(struct radeon_device *rdev)
1835 {
1836 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1837
1838 if (pi->gfx_clock_gating)
1839 rv770_restore_cgcg(rdev);
1840
1841 if (rv770_dpm_enabled(rdev))
1842 return -EINVAL;
1843
1844 if (pi->voltage_control) {
1845 rv770_enable_voltage_control(rdev, true);
1846 rv770_construct_vddc_table(rdev);
1847 }
1848
1849 if (pi->dcodt)
1850 rv770_retrieve_odt_values(rdev);
1851
1852 if (pi->mvdd_control)
1853 rv770_get_mvdd_configuration(rdev);
1854
1855 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_BACKBIAS)
1856 rv770_enable_backbias(rdev, true);
1857
1858 rv770_enable_spread_spectrum(rdev, true);
1859
1860 if (pi->thermal_protection)
1861 rv770_enable_thermal_protection(rdev, true);
1862
1863 rv770_program_mpll_timing_parameters(rdev);
1864 rv770_setup_bsp(rdev);
1865 rv770_program_git(rdev);
1866 rv770_program_tp(rdev);
1867 rv770_program_tpp(rdev);
1868 rv770_program_sstp(rdev);
1869 rv770_program_engine_speed_parameters(rdev);
1870 rv770_enable_display_gap(rdev);
1871 rv770_program_vc(rdev);
1872
1873 if (pi->dynamic_pcie_gen2)
1874 rv770_enable_dynamic_pcie_gen2(rdev, true);
1875
1876 if (rv770_upload_firmware(rdev))
1877 return -EINVAL;
1878 /* get ucode version ? */
1879 if (rv770_init_smc_table(rdev))
1880 return -EINVAL;
1881 rv770_program_response_times(rdev);
1882 r7xx_start_smc(rdev);
1883
1884 if ((rdev->family == CHIP_RV730) || (rdev->family == CHIP_RV710))
1885 rv730_start_dpm(rdev);
1886 else
1887 rv770_start_dpm(rdev);
1888
1889 if (pi->gfx_clock_gating)
1890 rv770_gfx_clock_gating_enable(rdev, true);
1891
1892 if (pi->mg_clock_gating)
1893 rv770_mg_clock_gating_enable(rdev, true);
1894
1895 if (rdev->irq.installed &&
1896 r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) {
1897 PPSMC_Result result;
1898
1899 rv770_set_thermal_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
1900 rdev->irq.dpm_thermal = true;
1901 radeon_irq_set(rdev);
1902 result = rv770_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt);
1903
1904 if (result != PPSMC_Result_OK)
1905 DRM_DEBUG_KMS("Could not enable thermal interrupts.\n");
1906 }
1907
1908 rv770_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true);
1909
1910 return 0;
1911 }
1912
1913 void rv770_dpm_disable(struct radeon_device *rdev)
1914 {
1915 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1916
1917 if (!rv770_dpm_enabled(rdev))
1918 return;
1919
1920 rv770_clear_vc(rdev);
1921
1922 if (pi->thermal_protection)
1923 rv770_enable_thermal_protection(rdev, false);
1924
1925 rv770_enable_spread_spectrum(rdev, false);
1926
1927 if (pi->dynamic_pcie_gen2)
1928 rv770_enable_dynamic_pcie_gen2(rdev, false);
1929
1930 if (rdev->irq.installed &&
1931 r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) {
1932 rdev->irq.dpm_thermal = false;
1933 radeon_irq_set(rdev);
1934 }
1935
1936 if (pi->gfx_clock_gating)
1937 rv770_gfx_clock_gating_enable(rdev, false);
1938
1939 if (pi->mg_clock_gating)
1940 rv770_mg_clock_gating_enable(rdev, false);
1941
1942 if ((rdev->family == CHIP_RV730) || (rdev->family == CHIP_RV710))
1943 rv730_stop_dpm(rdev);
1944 else
1945 rv770_stop_dpm(rdev);
1946
1947 r7xx_stop_smc(rdev);
1948 rv770_reset_smio_status(rdev);
1949 }
1950
1951 int rv770_dpm_set_power_state(struct radeon_device *rdev)
1952 {
1953 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1954
1955 rv770_restrict_performance_levels_before_switch(rdev);
1956 rv770_halt_smc(rdev);
1957 rv770_upload_sw_state(rdev);
1958 r7xx_program_memory_timing_parameters(rdev);
1959 if (pi->dcodt)
1960 rv770_program_dcodt_before_state_switch(rdev);
1961 rv770_resume_smc(rdev);
1962 rv770_set_sw_state(rdev);
1963 if (pi->dcodt)
1964 rv770_program_dcodt_after_state_switch(rdev);
1965 rv770_unrestrict_performance_levels_after_switch(rdev);
1966
1967 return 0;
1968 }
1969
1970 void rv770_dpm_reset_asic(struct radeon_device *rdev)
1971 {
1972 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1973
1974 rv770_restrict_performance_levels_before_switch(rdev);
1975 if (pi->dcodt)
1976 rv770_program_dcodt_before_state_switch(rdev);
1977 rv770_set_boot_state(rdev);
1978 if (pi->dcodt)
1979 rv770_program_dcodt_after_state_switch(rdev);
1980 }
1981
1982 void rv770_dpm_setup_asic(struct radeon_device *rdev)
1983 {
1984 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1985
1986 r7xx_read_clock_registers(rdev);
1987 rv770_read_voltage_smio_registers(rdev);
1988 rv770_get_memory_type(rdev);
1989 if (pi->dcodt)
1990 rv770_get_mclk_odt_threshold(rdev);
1991 rv770_get_pcie_gen2_status(rdev);
1992
1993 rv770_enable_acpi_pm(rdev);
1994
1995 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_ASPM_L0s)
1996 rv770_enable_l0s(rdev);
1997 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_ASPM_L1)
1998 rv770_enable_l1(rdev);
1999 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_TURNOFFPLL_ASPML1)
2000 rv770_enable_pll_sleep_in_l1(rdev);
2001 }
2002
2003 void rv770_dpm_display_configuration_changed(struct radeon_device *rdev)
2004 {
2005 rv770_program_display_gap(rdev);
2006 }
2007
2008 union power_info {
2009 struct _ATOM_POWERPLAY_INFO info;
2010 struct _ATOM_POWERPLAY_INFO_V2 info_2;
2011 struct _ATOM_POWERPLAY_INFO_V3 info_3;
2012 struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
2013 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
2014 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
2015 };
2016
2017 union pplib_clock_info {
2018 struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
2019 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
2020 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
2021 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
2022 };
2023
2024 union pplib_power_state {
2025 struct _ATOM_PPLIB_STATE v1;
2026 struct _ATOM_PPLIB_STATE_V2 v2;
2027 };
2028
2029 static void rv7xx_parse_pplib_non_clock_info(struct radeon_device *rdev,
2030 struct radeon_ps *rps,
2031 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info,
2032 u8 table_rev)
2033 {
2034 rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);
2035 rps->class = le16_to_cpu(non_clock_info->usClassification);
2036 rps->class2 = le16_to_cpu(non_clock_info->usClassification2);
2037
2038 if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {
2039 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
2040 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
2041 } else if (r600_is_uvd_state(rps->class, rps->class2)) {
2042 rps->vclk = RV770_DEFAULT_VCLK_FREQ;
2043 rps->dclk = RV770_DEFAULT_DCLK_FREQ;
2044 } else {
2045 rps->vclk = 0;
2046 rps->dclk = 0;
2047 }
2048
2049 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT)
2050 rdev->pm.dpm.boot_ps = rps;
2051 if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
2052 rdev->pm.dpm.uvd_ps = rps;
2053 }
2054
2055 static void rv7xx_parse_pplib_clock_info(struct radeon_device *rdev,
2056 struct radeon_ps *rps, int index,
2057 union pplib_clock_info *clock_info)
2058 {
2059 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
2060 struct rv7xx_ps *ps = rv770_get_ps(rps);
2061 u32 sclk, mclk;
2062 u16 vddc;
2063 struct rv7xx_pl *pl;
2064
2065 switch (index) {
2066 case 0:
2067 pl = &ps->low;
2068 break;
2069 case 1:
2070 pl = &ps->medium;
2071 break;
2072 case 2:
2073 default:
2074 pl = &ps->high;
2075 break;
2076 }
2077
2078 sclk = le16_to_cpu(clock_info->r600.usEngineClockLow);
2079 sclk |= clock_info->r600.ucEngineClockHigh << 16;
2080 mclk = le16_to_cpu(clock_info->r600.usMemoryClockLow);
2081 mclk |= clock_info->r600.ucMemoryClockHigh << 16;
2082
2083 pl->vddc = le16_to_cpu(clock_info->r600.usVDDC);
2084 pl->flags = le32_to_cpu(clock_info->r600.ulFlags);
2085
2086 pl->mclk = mclk;
2087 pl->sclk = sclk;
2088
2089 /* patch up vddc if necessary */
2090 if (pl->vddc == 0xff01) {
2091 if (radeon_atom_get_max_vddc(rdev, 0, 0, &vddc) == 0)
2092 pl->vddc = vddc;
2093 }
2094
2095 if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) {
2096 pi->acpi_vddc = pl->vddc;
2097 if (ps->low.flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2)
2098 pi->acpi_pcie_gen2 = true;
2099 else
2100 pi->acpi_pcie_gen2 = false;
2101 }
2102
2103 if (pi->min_vddc_in_table > pl->vddc)
2104 pi->min_vddc_in_table = pl->vddc;
2105
2106 if (pi->max_vddc_in_table < pl->vddc)
2107 pi->max_vddc_in_table = pl->vddc;
2108
2109 /* patch up boot state */
2110 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {
2111 u16 vddc, vddci;
2112 radeon_atombios_get_default_voltages(rdev, &vddc, &vddci);
2113 pl->mclk = rdev->clock.default_mclk;
2114 pl->sclk = rdev->clock.default_sclk;
2115 pl->vddc = vddc;
2116 pl->vddci = vddci;
2117 }
2118 }
2119
2120 int rv7xx_parse_power_table(struct radeon_device *rdev)
2121 {
2122 struct radeon_mode_info *mode_info = &rdev->mode_info;
2123 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
2124 union pplib_power_state *power_state;
2125 int i, j;
2126 union pplib_clock_info *clock_info;
2127 union power_info *power_info;
2128 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2129 u16 data_offset;
2130 u8 frev, crev;
2131 struct rv7xx_ps *ps;
2132
2133 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2134 &frev, &crev, &data_offset))
2135 return -EINVAL;
2136 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2137
2138 rdev->pm.dpm.ps = kzalloc(sizeof(struct radeon_ps) *
2139 power_info->pplib.ucNumStates, GFP_KERNEL);
2140 if (!rdev->pm.dpm.ps)
2141 return -ENOMEM;
2142 rdev->pm.dpm.platform_caps = le32_to_cpu(power_info->pplib.ulPlatformCaps);
2143 rdev->pm.dpm.backbias_response_time = le16_to_cpu(power_info->pplib.usBackbiasTime);
2144 rdev->pm.dpm.voltage_response_time = le16_to_cpu(power_info->pplib.usVoltageTime);
2145
2146 for (i = 0; i < power_info->pplib.ucNumStates; i++) {
2147 power_state = (union pplib_power_state *)
2148 (mode_info->atom_context->bios + data_offset +
2149 le16_to_cpu(power_info->pplib.usStateArrayOffset) +
2150 i * power_info->pplib.ucStateEntrySize);
2151 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
2152 (mode_info->atom_context->bios + data_offset +
2153 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset) +
2154 (power_state->v1.ucNonClockStateIndex *
2155 power_info->pplib.ucNonClockSize));
2156 if (power_info->pplib.ucStateEntrySize - 1) {
2157 ps = kzalloc(sizeof(struct rv7xx_ps), GFP_KERNEL);
2158 if (ps == NULL) {
2159 kfree(rdev->pm.dpm.ps);
2160 return -ENOMEM;
2161 }
2162 rdev->pm.dpm.ps[i].ps_priv = ps;
2163 rv7xx_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i],
2164 non_clock_info,
2165 power_info->pplib.ucNonClockSize);
2166 for (j = 0; j < (power_info->pplib.ucStateEntrySize - 1); j++) {
2167 clock_info = (union pplib_clock_info *)
2168 (mode_info->atom_context->bios + data_offset +
2169 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset) +
2170 (power_state->v1.ucClockStateIndices[j] *
2171 power_info->pplib.ucClockInfoSize));
2172 rv7xx_parse_pplib_clock_info(rdev,
2173 &rdev->pm.dpm.ps[i], j,
2174 clock_info);
2175 }
2176 }
2177 }
2178 rdev->pm.dpm.num_ps = power_info->pplib.ucNumStates;
2179 return 0;
2180 }
2181
2182 int rv770_dpm_init(struct radeon_device *rdev)
2183 {
2184 struct rv7xx_power_info *pi;
2185 int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);
2186 uint16_t data_offset, size;
2187 uint8_t frev, crev;
2188 struct atom_clock_dividers dividers;
2189 int ret;
2190
2191 pi = kzalloc(sizeof(struct rv7xx_power_info), GFP_KERNEL);
2192 if (pi == NULL)
2193 return -ENOMEM;
2194 rdev->pm.dpm.priv = pi;
2195
2196 rv770_get_max_vddc(rdev);
2197
2198 pi->acpi_vddc = 0;
2199 pi->min_vddc_in_table = 0;
2200 pi->max_vddc_in_table = 0;
2201
2202 ret = rv7xx_parse_power_table(rdev);
2203 if (ret)
2204 return ret;
2205
2206 if (rdev->pm.dpm.voltage_response_time == 0)
2207 rdev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT;
2208 if (rdev->pm.dpm.backbias_response_time == 0)
2209 rdev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT;
2210
2211 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
2212 0, false, &dividers);
2213 if (ret)
2214 pi->ref_div = dividers.ref_div + 1;
2215 else
2216 pi->ref_div = R600_REFERENCEDIVIDER_DFLT;
2217
2218 pi->mclk_strobe_mode_threshold = 30000;
2219 pi->mclk_edc_enable_threshold = 30000;
2220
2221 pi->voltage_control =
2222 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC);
2223
2224 pi->mvdd_control =
2225 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_MVDDC);
2226
2227 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
2228 &frev, &crev, &data_offset)) {
2229 pi->sclk_ss = true;
2230 pi->mclk_ss = true;
2231 pi->dynamic_ss = true;
2232 } else {
2233 pi->sclk_ss = false;
2234 pi->mclk_ss = false;
2235 pi->dynamic_ss = false;
2236 }
2237
2238 pi->asi = RV770_ASI_DFLT;
2239 pi->pasi = RV770_HASI_DFLT;
2240 pi->vrc = RV770_VRC_DFLT;
2241
2242 pi->power_gating = false;
2243
2244 pi->gfx_clock_gating = true;
2245
2246 pi->mg_clock_gating = true;
2247 pi->mgcgtssm = true;
2248
2249 pi->dynamic_pcie_gen2 = true;
2250
2251 if (pi->gfx_clock_gating &&
2252 (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE))
2253 pi->thermal_protection = true;
2254 else
2255 pi->thermal_protection = false;
2256
2257 pi->display_gap = true;
2258
2259 if (rdev->flags & RADEON_IS_MOBILITY)
2260 pi->dcodt = true;
2261 else
2262 pi->dcodt = false;
2263
2264 pi->ulps = true;
2265
2266 pi->mclk_stutter_mode_threshold = 0;
2267
2268 pi->sram_end = SMC_RAM_END;
2269 pi->state_table_start = RV770_SMC_TABLE_ADDRESS;
2270 pi->soft_regs_start = RV770_SMC_SOFT_REGISTERS_START;
2271
2272 return 0;
2273 }
2274
2275 void rv770_dpm_print_power_state(struct radeon_device *rdev,
2276 struct radeon_ps *rps)
2277 {
2278 struct rv7xx_ps *ps = rv770_get_ps(rps);
2279 struct rv7xx_pl *pl;
2280
2281 r600_dpm_print_class_info(rps->class, rps->class2);
2282 r600_dpm_print_cap_info(rps->caps);
2283 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
2284 if (rdev->family >= CHIP_CEDAR) {
2285 pl = &ps->low;
2286 printk("\t\tpower level 0 sclk: %u mclk: %u vddc: %u vddci: %u\n",
2287 pl->sclk, pl->mclk, pl->vddc, pl->vddci);
2288 pl = &ps->medium;
2289 printk("\t\tpower level 1 sclk: %u mclk: %u vddc: %u vddci: %u\n",
2290 pl->sclk, pl->mclk, pl->vddc, pl->vddci);
2291 pl = &ps->high;
2292 printk("\t\tpower level 2 sclk: %u mclk: %u vddc: %u vddci: %u\n",
2293 pl->sclk, pl->mclk, pl->vddc, pl->vddci);
2294 } else {
2295 pl = &ps->low;
2296 printk("\t\tpower level 0 sclk: %u mclk: %u vddc: %u\n",
2297 pl->sclk, pl->mclk, pl->vddc);
2298 pl = &ps->medium;
2299 printk("\t\tpower level 1 sclk: %u mclk: %u vddc: %u\n",
2300 pl->sclk, pl->mclk, pl->vddc);
2301 pl = &ps->high;
2302 printk("\t\tpower level 2 sclk: %u mclk: %u vddc: %u\n",
2303 pl->sclk, pl->mclk, pl->vddc);
2304 }
2305 r600_dpm_print_ps_status(rdev, rps);
2306 }
2307
2308 void rv770_dpm_fini(struct radeon_device *rdev)
2309 {
2310 int i;
2311
2312 for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
2313 kfree(rdev->pm.dpm.ps[i].ps_priv);
2314 }
2315 kfree(rdev->pm.dpm.ps);
2316 kfree(rdev->pm.dpm.priv);
2317 }
2318
2319 u32 rv770_dpm_get_sclk(struct radeon_device *rdev, bool low)
2320 {
2321 struct rv7xx_ps *requested_state = rv770_get_ps(rdev->pm.dpm.requested_ps);
2322
2323 if (low)
2324 return requested_state->low.sclk;
2325 else
2326 return requested_state->high.sclk;
2327 }
2328
2329 u32 rv770_dpm_get_mclk(struct radeon_device *rdev, bool low)
2330 {
2331 struct rv7xx_ps *requested_state = rv770_get_ps(rdev->pm.dpm.requested_ps);
2332
2333 if (low)
2334 return requested_state->low.mclk;
2335 else
2336 return requested_state->high.mclk;
2337 }
Linux kernel - Deliverables
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