2 * Copyright 2009 Advanced Micro Devices, Inc.
3 * Copyright 2009 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
30 #define R7XX_MAX_SH_GPRS 256
31 #define R7XX_MAX_TEMP_GPRS 16
32 #define R7XX_MAX_SH_THREADS 256
33 #define R7XX_MAX_SH_STACK_ENTRIES 4096
34 #define R7XX_MAX_BACKENDS 8
35 #define R7XX_MAX_BACKENDS_MASK 0xff
36 #define R7XX_MAX_SIMDS 16
37 #define R7XX_MAX_SIMDS_MASK 0xffff
38 #define R7XX_MAX_PIPES 8
39 #define R7XX_MAX_PIPES_MASK 0xff
41 /* discrete uvd clocks */
42 #define CG_UPLL_FUNC_CNTL 0x718
43 # define UPLL_RESET_MASK 0x00000001
44 # define UPLL_SLEEP_MASK 0x00000002
45 # define UPLL_BYPASS_EN_MASK 0x00000004
46 # define UPLL_CTLREQ_MASK 0x00000008
47 # define UPLL_REF_DIV(x) ((x) << 16)
48 # define UPLL_REF_DIV_MASK 0x003F0000
49 # define UPLL_CTLACK_MASK 0x40000000
50 # define UPLL_CTLACK2_MASK 0x80000000
51 #define CG_UPLL_FUNC_CNTL_2 0x71c
52 # define UPLL_SW_HILEN(x) ((x) << 0)
53 # define UPLL_SW_LOLEN(x) ((x) << 4)
54 # define UPLL_SW_HILEN2(x) ((x) << 8)
55 # define UPLL_SW_LOLEN2(x) ((x) << 12)
56 # define UPLL_SW_MASK 0x0000FFFF
57 # define VCLK_SRC_SEL(x) ((x) << 20)
58 # define VCLK_SRC_SEL_MASK 0x01F00000
59 # define DCLK_SRC_SEL(x) ((x) << 25)
60 # define DCLK_SRC_SEL_MASK 0x3E000000
61 #define CG_UPLL_FUNC_CNTL_3 0x720
62 # define UPLL_FB_DIV(x) ((x) << 0)
63 # define UPLL_FB_DIV_MASK 0x01FFFFFF
66 #define CB_COLOR0_BASE 0x28040
67 #define CB_COLOR1_BASE 0x28044
68 #define CB_COLOR2_BASE 0x28048
69 #define CB_COLOR3_BASE 0x2804C
70 #define CB_COLOR4_BASE 0x28050
71 #define CB_COLOR5_BASE 0x28054
72 #define CB_COLOR6_BASE 0x28058
73 #define CB_COLOR7_BASE 0x2805C
74 #define CB_COLOR7_FRAG 0x280FC
76 #define CC_GC_SHADER_PIPE_CONFIG 0x8950
77 #define CC_RB_BACKEND_DISABLE 0x98F4
78 #define BACKEND_DISABLE(x) ((x) << 16)
79 #define CC_SYS_RB_BACKEND_DISABLE 0x3F88
81 #define CGTS_SYS_TCC_DISABLE 0x3F90
82 #define CGTS_TCC_DISABLE 0x9148
83 #define CGTS_USER_SYS_TCC_DISABLE 0x3F94
84 #define CGTS_USER_TCC_DISABLE 0x914C
86 #define CONFIG_MEMSIZE 0x5428
88 #define CP_ME_CNTL 0x86D8
89 #define CP_ME_HALT (1<<28)
90 #define CP_PFP_HALT (1<<26)
91 #define CP_ME_RAM_DATA 0xC160
92 #define CP_ME_RAM_RADDR 0xC158
93 #define CP_ME_RAM_WADDR 0xC15C
94 #define CP_MEQ_THRESHOLDS 0x8764
95 #define STQ_SPLIT(x) ((x) << 0)
96 #define CP_PERFMON_CNTL 0x87FC
97 #define CP_PFP_UCODE_ADDR 0xC150
98 #define CP_PFP_UCODE_DATA 0xC154
99 #define CP_QUEUE_THRESHOLDS 0x8760
100 #define ROQ_IB1_START(x) ((x) << 0)
101 #define ROQ_IB2_START(x) ((x) << 8)
102 #define CP_RB_CNTL 0xC104
103 #define RB_BUFSZ(x) ((x) << 0)
104 #define RB_BLKSZ(x) ((x) << 8)
105 #define RB_NO_UPDATE (1 << 27)
106 #define RB_RPTR_WR_ENA (1 << 31)
107 #define BUF_SWAP_32BIT (2 << 16)
108 #define CP_RB_RPTR 0x8700
109 #define CP_RB_RPTR_ADDR 0xC10C
110 #define CP_RB_RPTR_ADDR_HI 0xC110
111 #define CP_RB_RPTR_WR 0xC108
112 #define CP_RB_WPTR 0xC114
113 #define CP_RB_WPTR_ADDR 0xC118
114 #define CP_RB_WPTR_ADDR_HI 0xC11C
115 #define CP_RB_WPTR_DELAY 0x8704
116 #define CP_SEM_WAIT_TIMER 0x85BC
118 #define DB_DEBUG3 0x98B0
119 #define DB_CLK_OFF_DELAY(x) ((x) << 11)
120 #define DB_DEBUG4 0x9B8C
121 #define DISABLE_TILE_COVERED_FOR_PS_ITER (1 << 6)
123 #define DCP_TILING_CONFIG 0x6CA0
124 #define PIPE_TILING(x) ((x) << 1)
125 #define BANK_TILING(x) ((x) << 4)
126 #define GROUP_SIZE(x) ((x) << 6)
127 #define ROW_TILING(x) ((x) << 8)
128 #define BANK_SWAPS(x) ((x) << 11)
129 #define SAMPLE_SPLIT(x) ((x) << 14)
130 #define BACKEND_MAP(x) ((x) << 16)
132 #define GB_TILING_CONFIG 0x98F0
133 #define PIPE_TILING__SHIFT 1
134 #define PIPE_TILING__MASK 0x0000000e
136 #define DMA_TILING_CONFIG 0x3ec8
137 #define DMA_TILING_CONFIG2 0xd0b8
140 #define UVD_UDEC_TILING_CONFIG 0xef40
141 #define UVD_UDEC_DB_TILING_CONFIG 0xef44
142 #define UVD_UDEC_DBW_TILING_CONFIG 0xef48
144 #define GC_USER_SHADER_PIPE_CONFIG 0x8954
145 #define INACTIVE_QD_PIPES(x) ((x) << 8)
146 #define INACTIVE_QD_PIPES_MASK 0x0000FF00
147 #define INACTIVE_QD_PIPES_SHIFT 8
148 #define INACTIVE_SIMDS(x) ((x) << 16)
149 #define INACTIVE_SIMDS_MASK 0x00FF0000
151 #define GRBM_CNTL 0x8000
152 #define GRBM_READ_TIMEOUT(x) ((x) << 0)
153 #define GRBM_SOFT_RESET 0x8020
154 #define SOFT_RESET_CP (1<<0)
155 #define GRBM_STATUS 0x8010
156 #define CMDFIFO_AVAIL_MASK 0x0000000F
157 #define GUI_ACTIVE (1<<31)
158 #define GRBM_STATUS2 0x8014
160 #define CG_CLKPIN_CNTL 0x660
161 # define MUX_TCLK_TO_XCLK (1 << 8)
162 # define XTALIN_DIVIDE (1 << 9)
164 #define CG_MULT_THERMAL_STATUS 0x740
165 #define ASIC_T(x) ((x) << 16)
166 #define ASIC_T_MASK 0x3FF0000
167 #define ASIC_T_SHIFT 16
169 #define HDP_HOST_PATH_CNTL 0x2C00
170 #define HDP_NONSURFACE_BASE 0x2C04
171 #define HDP_NONSURFACE_INFO 0x2C08
172 #define HDP_NONSURFACE_SIZE 0x2C0C
173 #define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0
174 #define HDP_TILING_CONFIG 0x2F3C
175 #define HDP_DEBUG1 0x2F34
177 #define MC_SHARED_CHMAP 0x2004
178 #define NOOFCHAN_SHIFT 12
179 #define NOOFCHAN_MASK 0x00003000
180 #define MC_SHARED_CHREMAP 0x2008
182 #define MC_ARB_RAMCFG 0x2760
183 #define NOOFBANK_SHIFT 0
184 #define NOOFBANK_MASK 0x00000003
185 #define NOOFRANK_SHIFT 2
186 #define NOOFRANK_MASK 0x00000004
187 #define NOOFROWS_SHIFT 3
188 #define NOOFROWS_MASK 0x00000038
189 #define NOOFCOLS_SHIFT 6
190 #define NOOFCOLS_MASK 0x000000C0
191 #define CHANSIZE_SHIFT 8
192 #define CHANSIZE_MASK 0x00000100
193 #define BURSTLENGTH_SHIFT 9
194 #define BURSTLENGTH_MASK 0x00000200
195 #define CHANSIZE_OVERRIDE (1 << 11)
196 #define MC_VM_AGP_TOP 0x2028
197 #define MC_VM_AGP_BOT 0x202C
198 #define MC_VM_AGP_BASE 0x2030
199 #define MC_VM_FB_LOCATION 0x2024
200 #define MC_VM_MB_L1_TLB0_CNTL 0x2234
201 #define MC_VM_MB_L1_TLB1_CNTL 0x2238
202 #define MC_VM_MB_L1_TLB2_CNTL 0x223C
203 #define MC_VM_MB_L1_TLB3_CNTL 0x2240
204 #define ENABLE_L1_TLB (1 << 0)
205 #define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1)
206 #define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 3)
207 #define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 3)
208 #define SYSTEM_ACCESS_MODE_IN_SYS (2 << 3)
209 #define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 3)
210 #define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5)
211 #define EFFECTIVE_L1_TLB_SIZE(x) ((x)<<15)
212 #define EFFECTIVE_L1_QUEUE_SIZE(x) ((x)<<18)
213 #define MC_VM_MD_L1_TLB0_CNTL 0x2654
214 #define MC_VM_MD_L1_TLB1_CNTL 0x2658
215 #define MC_VM_MD_L1_TLB2_CNTL 0x265C
216 #define MC_VM_MD_L1_TLB3_CNTL 0x2698
217 #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203C
218 #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038
219 #define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034
221 #define PA_CL_ENHANCE 0x8A14
222 #define CLIP_VTX_REORDER_ENA (1 << 0)
223 #define NUM_CLIP_SEQ(x) ((x) << 1)
224 #define PA_SC_AA_CONFIG 0x28C04
225 #define PA_SC_CLIPRECT_RULE 0x2820C
226 #define PA_SC_EDGERULE 0x28230
227 #define PA_SC_FIFO_SIZE 0x8BCC
228 #define SC_PRIM_FIFO_SIZE(x) ((x) << 0)
229 #define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 12)
230 #define PA_SC_FORCE_EOV_MAX_CNTS 0x8B24
231 #define FORCE_EOV_MAX_CLK_CNT(x) ((x)<<0)
232 #define FORCE_EOV_MAX_REZ_CNT(x) ((x)<<16)
233 #define PA_SC_LINE_STIPPLE 0x28A0C
234 #define PA_SC_LINE_STIPPLE_STATE 0x8B10
235 #define PA_SC_MODE_CNTL 0x28A4C
236 #define PA_SC_MULTI_CHIP_CNTL 0x8B20
237 #define SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 20)
239 #define SCRATCH_REG0 0x8500
240 #define SCRATCH_REG1 0x8504
241 #define SCRATCH_REG2 0x8508
242 #define SCRATCH_REG3 0x850C
243 #define SCRATCH_REG4 0x8510
244 #define SCRATCH_REG5 0x8514
245 #define SCRATCH_REG6 0x8518
246 #define SCRATCH_REG7 0x851C
247 #define SCRATCH_UMSK 0x8540
248 #define SCRATCH_ADDR 0x8544
250 #define SMX_SAR_CTL0 0xA008
251 #define SMX_DC_CTL0 0xA020
252 #define USE_HASH_FUNCTION (1 << 0)
253 #define CACHE_DEPTH(x) ((x) << 1)
254 #define FLUSH_ALL_ON_EVENT (1 << 10)
255 #define STALL_ON_EVENT (1 << 11)
256 #define SMX_EVENT_CTL 0xA02C
257 #define ES_FLUSH_CTL(x) ((x) << 0)
258 #define GS_FLUSH_CTL(x) ((x) << 3)
259 #define ACK_FLUSH_CTL(x) ((x) << 6)
260 #define SYNC_FLUSH_CTL (1 << 8)
262 #define SPI_CONFIG_CNTL 0x9100
263 #define GPR_WRITE_PRIORITY(x) ((x) << 0)
264 #define DISABLE_INTERP_1 (1 << 5)
265 #define SPI_CONFIG_CNTL_1 0x913C
266 #define VTX_DONE_DELAY(x) ((x) << 0)
267 #define INTERP_ONE_PRIM_PER_ROW (1 << 4)
268 #define SPI_INPUT_Z 0x286D8
269 #define SPI_PS_IN_CONTROL_0 0x286CC
270 #define NUM_INTERP(x) ((x)<<0)
271 #define POSITION_ENA (1<<8)
272 #define POSITION_CENTROID (1<<9)
273 #define POSITION_ADDR(x) ((x)<<10)
274 #define PARAM_GEN(x) ((x)<<15)
275 #define PARAM_GEN_ADDR(x) ((x)<<19)
276 #define BARYC_SAMPLE_CNTL(x) ((x)<<26)
277 #define PERSP_GRADIENT_ENA (1<<28)
278 #define LINEAR_GRADIENT_ENA (1<<29)
279 #define POSITION_SAMPLE (1<<30)
280 #define BARYC_AT_SAMPLE_ENA (1<<31)
282 #define SQ_CONFIG 0x8C00
283 #define VC_ENABLE (1 << 0)
284 #define EXPORT_SRC_C (1 << 1)
285 #define DX9_CONSTS (1 << 2)
286 #define ALU_INST_PREFER_VECTOR (1 << 3)
287 #define DX10_CLAMP (1 << 4)
288 #define CLAUSE_SEQ_PRIO(x) ((x) << 8)
289 #define PS_PRIO(x) ((x) << 24)
290 #define VS_PRIO(x) ((x) << 26)
291 #define GS_PRIO(x) ((x) << 28)
292 #define SQ_DYN_GPR_SIZE_SIMD_AB_0 0x8DB0
293 #define SIMDA_RING0(x) ((x)<<0)
294 #define SIMDA_RING1(x) ((x)<<8)
295 #define SIMDB_RING0(x) ((x)<<16)
296 #define SIMDB_RING1(x) ((x)<<24)
297 #define SQ_DYN_GPR_SIZE_SIMD_AB_1 0x8DB4
298 #define SQ_DYN_GPR_SIZE_SIMD_AB_2 0x8DB8
299 #define SQ_DYN_GPR_SIZE_SIMD_AB_3 0x8DBC
300 #define SQ_DYN_GPR_SIZE_SIMD_AB_4 0x8DC0
301 #define SQ_DYN_GPR_SIZE_SIMD_AB_5 0x8DC4
302 #define SQ_DYN_GPR_SIZE_SIMD_AB_6 0x8DC8
303 #define SQ_DYN_GPR_SIZE_SIMD_AB_7 0x8DCC
304 #define ES_PRIO(x) ((x) << 30)
305 #define SQ_GPR_RESOURCE_MGMT_1 0x8C04
306 #define NUM_PS_GPRS(x) ((x) << 0)
307 #define NUM_VS_GPRS(x) ((x) << 16)
308 #define DYN_GPR_ENABLE (1 << 27)
309 #define NUM_CLAUSE_TEMP_GPRS(x) ((x) << 28)
310 #define SQ_GPR_RESOURCE_MGMT_2 0x8C08
311 #define NUM_GS_GPRS(x) ((x) << 0)
312 #define NUM_ES_GPRS(x) ((x) << 16)
313 #define SQ_MS_FIFO_SIZES 0x8CF0
314 #define CACHE_FIFO_SIZE(x) ((x) << 0)
315 #define FETCH_FIFO_HIWATER(x) ((x) << 8)
316 #define DONE_FIFO_HIWATER(x) ((x) << 16)
317 #define ALU_UPDATE_FIFO_HIWATER(x) ((x) << 24)
318 #define SQ_STACK_RESOURCE_MGMT_1 0x8C10
319 #define NUM_PS_STACK_ENTRIES(x) ((x) << 0)
320 #define NUM_VS_STACK_ENTRIES(x) ((x) << 16)
321 #define SQ_STACK_RESOURCE_MGMT_2 0x8C14
322 #define NUM_GS_STACK_ENTRIES(x) ((x) << 0)
323 #define NUM_ES_STACK_ENTRIES(x) ((x) << 16)
324 #define SQ_THREAD_RESOURCE_MGMT 0x8C0C
325 #define NUM_PS_THREADS(x) ((x) << 0)
326 #define NUM_VS_THREADS(x) ((x) << 8)
327 #define NUM_GS_THREADS(x) ((x) << 16)
328 #define NUM_ES_THREADS(x) ((x) << 24)
330 #define SX_DEBUG_1 0x9058
331 #define ENABLE_NEW_SMX_ADDRESS (1 << 16)
332 #define SX_EXPORT_BUFFER_SIZES 0x900C
333 #define COLOR_BUFFER_SIZE(x) ((x) << 0)
334 #define POSITION_BUFFER_SIZE(x) ((x) << 8)
335 #define SMX_BUFFER_SIZE(x) ((x) << 16)
336 #define SX_MISC 0x28350
338 #define TA_CNTL_AUX 0x9508
339 #define DISABLE_CUBE_WRAP (1 << 0)
340 #define DISABLE_CUBE_ANISO (1 << 1)
341 #define SYNC_GRADIENT (1 << 24)
342 #define SYNC_WALKER (1 << 25)
343 #define SYNC_ALIGNER (1 << 26)
344 #define BILINEAR_PRECISION_6_BIT (0 << 31)
345 #define BILINEAR_PRECISION_8_BIT (1 << 31)
347 #define TCP_CNTL 0x9610
348 #define TCP_CHAN_STEER 0x9614
350 #define VC_ENHANCE 0x9714
352 #define VGT_CACHE_INVALIDATION 0x88C4
353 #define CACHE_INVALIDATION(x) ((x)<<0)
357 #define AUTO_INVLD_EN(x) ((x) << 6)
361 #define ES_AND_GS_AUTO 3
362 #define VGT_ES_PER_GS 0x88CC
363 #define VGT_GS_PER_ES 0x88C8
364 #define VGT_GS_PER_VS 0x88E8
365 #define VGT_GS_VERTEX_REUSE 0x88D4
366 #define VGT_NUM_INSTANCES 0x8974
367 #define VGT_OUT_DEALLOC_CNTL 0x28C5C
368 #define DEALLOC_DIST_MASK 0x0000007F
369 #define VGT_STRMOUT_EN 0x28AB0
370 #define VGT_VERTEX_REUSE_BLOCK_CNTL 0x28C58
371 #define VTX_REUSE_DEPTH_MASK 0x000000FF
373 #define VM_CONTEXT0_CNTL 0x1410
374 #define ENABLE_CONTEXT (1 << 0)
375 #define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1)
376 #define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4)
377 #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153C
378 #define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157C
379 #define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155C
380 #define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1518
381 #define VM_L2_CNTL 0x1400
382 #define ENABLE_L2_CACHE (1 << 0)
383 #define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1)
384 #define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9)
385 #define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 14)
386 #define VM_L2_CNTL2 0x1404
387 #define INVALIDATE_ALL_L1_TLBS (1 << 0)
388 #define INVALIDATE_L2_CACHE (1 << 1)
389 #define VM_L2_CNTL3 0x1408
390 #define BANK_SELECT(x) ((x) << 0)
391 #define CACHE_UPDATE_MODE(x) ((x) << 6)
392 #define VM_L2_STATUS 0x140C
393 #define L2_BUSY (1 << 0)
395 #define WAIT_UNTIL 0x8040
398 #define DMA_RB_RPTR 0xd008
399 #define DMA_RB_WPTR 0xd00c
401 /* async DMA packets */
402 #define DMA_PACKET(cmd, t, s, n) ((((cmd) & 0xF) << 28) | \
403 (((t) & 0x1) << 23) | \
404 (((s) & 0x1) << 22) | \
405 (((n) & 0xFFFF) << 0))
406 /* async DMA Packet types */
407 #define DMA_PACKET_WRITE 0x2
408 #define DMA_PACKET_COPY 0x3
409 #define DMA_PACKET_INDIRECT_BUFFER 0x4
410 #define DMA_PACKET_SEMAPHORE 0x5
411 #define DMA_PACKET_FENCE 0x6
412 #define DMA_PACKET_TRAP 0x7
413 #define DMA_PACKET_CONSTANT_FILL 0xd
414 #define DMA_PACKET_NOP 0xf
417 #define SRBM_STATUS 0x0E50
420 #define HDMI_CONTROL 0x7400
421 # define HDMI_KEEPOUT_MODE (1 << 0)
422 # define HDMI_PACKET_GEN_VERSION (1 << 4) /* 0 = r6xx compat */
423 # define HDMI_ERROR_ACK (1 << 8)
424 # define HDMI_ERROR_MASK (1 << 9)
425 #define HDMI_STATUS 0x7404
426 # define HDMI_ACTIVE_AVMUTE (1 << 0)
427 # define HDMI_AUDIO_PACKET_ERROR (1 << 16)
428 # define HDMI_VBI_PACKET_ERROR (1 << 20)
429 #define HDMI_AUDIO_PACKET_CONTROL 0x7408
430 # define HDMI_AUDIO_DELAY_EN(x) (((x) & 3) << 4)
431 # define HDMI_AUDIO_PACKETS_PER_LINE(x) (((x) & 0x1f) << 16)
432 #define HDMI_ACR_PACKET_CONTROL 0x740c
433 # define HDMI_ACR_SEND (1 << 0)
434 # define HDMI_ACR_CONT (1 << 1)
435 # define HDMI_ACR_SELECT(x) (((x) & 3) << 4)
436 # define HDMI_ACR_HW 0
437 # define HDMI_ACR_32 1
438 # define HDMI_ACR_44 2
439 # define HDMI_ACR_48 3
440 # define HDMI_ACR_SOURCE (1 << 8) /* 0 - hw; 1 - cts value */
441 # define HDMI_ACR_AUTO_SEND (1 << 12)
442 #define HDMI_VBI_PACKET_CONTROL 0x7410
443 # define HDMI_NULL_SEND (1 << 0)
444 # define HDMI_GC_SEND (1 << 4)
445 # define HDMI_GC_CONT (1 << 5) /* 0 - once; 1 - every frame */
446 #define HDMI_INFOFRAME_CONTROL0 0x7414
447 # define HDMI_AVI_INFO_SEND (1 << 0)
448 # define HDMI_AVI_INFO_CONT (1 << 1)
449 # define HDMI_AUDIO_INFO_SEND (1 << 4)
450 # define HDMI_AUDIO_INFO_CONT (1 << 5)
451 # define HDMI_MPEG_INFO_SEND (1 << 8)
452 # define HDMI_MPEG_INFO_CONT (1 << 9)
453 #define HDMI_INFOFRAME_CONTROL1 0x7418
454 # define HDMI_AVI_INFO_LINE(x) (((x) & 0x3f) << 0)
455 # define HDMI_AUDIO_INFO_LINE(x) (((x) & 0x3f) << 8)
456 # define HDMI_MPEG_INFO_LINE(x) (((x) & 0x3f) << 16)
457 #define HDMI_GENERIC_PACKET_CONTROL 0x741c
458 # define HDMI_GENERIC0_SEND (1 << 0)
459 # define HDMI_GENERIC0_CONT (1 << 1)
460 # define HDMI_GENERIC1_SEND (1 << 4)
461 # define HDMI_GENERIC1_CONT (1 << 5)
462 # define HDMI_GENERIC0_LINE(x) (((x) & 0x3f) << 16)
463 # define HDMI_GENERIC1_LINE(x) (((x) & 0x3f) << 24)
464 #define HDMI_GC 0x7428
465 # define HDMI_GC_AVMUTE (1 << 0)
466 #define AFMT_AUDIO_PACKET_CONTROL2 0x742c
467 # define AFMT_AUDIO_LAYOUT_OVRD (1 << 0)
468 # define AFMT_AUDIO_LAYOUT_SELECT (1 << 1)
469 # define AFMT_60958_CS_SOURCE (1 << 4)
470 # define AFMT_AUDIO_CHANNEL_ENABLE(x) (((x) & 0xff) << 8)
471 # define AFMT_DP_AUDIO_STREAM_ID(x) (((x) & 0xff) << 16)
472 #define AFMT_AVI_INFO0 0x7454
473 # define AFMT_AVI_INFO_CHECKSUM(x) (((x) & 0xff) << 0)
474 # define AFMT_AVI_INFO_S(x) (((x) & 3) << 8)
475 # define AFMT_AVI_INFO_B(x) (((x) & 3) << 10)
476 # define AFMT_AVI_INFO_A(x) (((x) & 1) << 12)
477 # define AFMT_AVI_INFO_Y(x) (((x) & 3) << 13)
478 # define AFMT_AVI_INFO_Y_RGB 0
479 # define AFMT_AVI_INFO_Y_YCBCR422 1
480 # define AFMT_AVI_INFO_Y_YCBCR444 2
481 # define AFMT_AVI_INFO_Y_A_B_S(x) (((x) & 0xff) << 8)
482 # define AFMT_AVI_INFO_R(x) (((x) & 0xf) << 16)
483 # define AFMT_AVI_INFO_M(x) (((x) & 0x3) << 20)
484 # define AFMT_AVI_INFO_C(x) (((x) & 0x3) << 22)
485 # define AFMT_AVI_INFO_C_M_R(x) (((x) & 0xff) << 16)
486 # define AFMT_AVI_INFO_SC(x) (((x) & 0x3) << 24)
487 # define AFMT_AVI_INFO_Q(x) (((x) & 0x3) << 26)
488 # define AFMT_AVI_INFO_EC(x) (((x) & 0x3) << 28)
489 # define AFMT_AVI_INFO_ITC(x) (((x) & 0x1) << 31)
490 # define AFMT_AVI_INFO_ITC_EC_Q_SC(x) (((x) & 0xff) << 24)
491 #define AFMT_AVI_INFO1 0x7458
492 # define AFMT_AVI_INFO_VIC(x) (((x) & 0x7f) << 0) /* don't use avi infoframe v1 */
493 # define AFMT_AVI_INFO_PR(x) (((x) & 0xf) << 8) /* don't use avi infoframe v1 */
494 # define AFMT_AVI_INFO_TOP(x) (((x) & 0xffff) << 16)
495 #define AFMT_AVI_INFO2 0x745c
496 # define AFMT_AVI_INFO_BOTTOM(x) (((x) & 0xffff) << 0)
497 # define AFMT_AVI_INFO_LEFT(x) (((x) & 0xffff) << 16)
498 #define AFMT_AVI_INFO3 0x7460
499 # define AFMT_AVI_INFO_RIGHT(x) (((x) & 0xffff) << 0)
500 # define AFMT_AVI_INFO_VERSION(x) (((x) & 3) << 24)
501 #define AFMT_MPEG_INFO0 0x7464
502 # define AFMT_MPEG_INFO_CHECKSUM(x) (((x) & 0xff) << 0)
503 # define AFMT_MPEG_INFO_MB0(x) (((x) & 0xff) << 8)
504 # define AFMT_MPEG_INFO_MB1(x) (((x) & 0xff) << 16)
505 # define AFMT_MPEG_INFO_MB2(x) (((x) & 0xff) << 24)
506 #define AFMT_MPEG_INFO1 0x7468
507 # define AFMT_MPEG_INFO_MB3(x) (((x) & 0xff) << 0)
508 # define AFMT_MPEG_INFO_MF(x) (((x) & 3) << 8)
509 # define AFMT_MPEG_INFO_FR(x) (((x) & 1) << 12)
510 #define AFMT_GENERIC0_HDR 0x746c
511 #define AFMT_GENERIC0_0 0x7470
512 #define AFMT_GENERIC0_1 0x7474
513 #define AFMT_GENERIC0_2 0x7478
514 #define AFMT_GENERIC0_3 0x747c
515 #define AFMT_GENERIC0_4 0x7480
516 #define AFMT_GENERIC0_5 0x7484
517 #define AFMT_GENERIC0_6 0x7488
518 #define AFMT_GENERIC1_HDR 0x748c
519 #define AFMT_GENERIC1_0 0x7490
520 #define AFMT_GENERIC1_1 0x7494
521 #define AFMT_GENERIC1_2 0x7498
522 #define AFMT_GENERIC1_3 0x749c
523 #define AFMT_GENERIC1_4 0x74a0
524 #define AFMT_GENERIC1_5 0x74a4
525 #define AFMT_GENERIC1_6 0x74a8
526 #define HDMI_ACR_32_0 0x74ac
527 # define HDMI_ACR_CTS_32(x) (((x) & 0xfffff) << 12)
528 #define HDMI_ACR_32_1 0x74b0
529 # define HDMI_ACR_N_32(x) (((x) & 0xfffff) << 0)
530 #define HDMI_ACR_44_0 0x74b4
531 # define HDMI_ACR_CTS_44(x) (((x) & 0xfffff) << 12)
532 #define HDMI_ACR_44_1 0x74b8
533 # define HDMI_ACR_N_44(x) (((x) & 0xfffff) << 0)
534 #define HDMI_ACR_48_0 0x74bc
535 # define HDMI_ACR_CTS_48(x) (((x) & 0xfffff) << 12)
536 #define HDMI_ACR_48_1 0x74c0
537 # define HDMI_ACR_N_48(x) (((x) & 0xfffff) << 0)
538 #define HDMI_ACR_STATUS_0 0x74c4
539 #define HDMI_ACR_STATUS_1 0x74c8
540 #define AFMT_AUDIO_INFO0 0x74cc
541 # define AFMT_AUDIO_INFO_CHECKSUM(x) (((x) & 0xff) << 0)
542 # define AFMT_AUDIO_INFO_CC(x) (((x) & 7) << 8)
543 # define AFMT_AUDIO_INFO_CHECKSUM_OFFSET(x) (((x) & 0xff) << 16)
544 #define AFMT_AUDIO_INFO1 0x74d0
545 # define AFMT_AUDIO_INFO_CA(x) (((x) & 0xff) << 0)
546 # define AFMT_AUDIO_INFO_LSV(x) (((x) & 0xf) << 11)
547 # define AFMT_AUDIO_INFO_DM_INH(x) (((x) & 1) << 15)
548 # define AFMT_AUDIO_INFO_DM_INH_LSV(x) (((x) & 0xff) << 8)
549 #define AFMT_60958_0 0x74d4
550 # define AFMT_60958_CS_A(x) (((x) & 1) << 0)
551 # define AFMT_60958_CS_B(x) (((x) & 1) << 1)
552 # define AFMT_60958_CS_C(x) (((x) & 1) << 2)
553 # define AFMT_60958_CS_D(x) (((x) & 3) << 3)
554 # define AFMT_60958_CS_MODE(x) (((x) & 3) << 6)
555 # define AFMT_60958_CS_CATEGORY_CODE(x) (((x) & 0xff) << 8)
556 # define AFMT_60958_CS_SOURCE_NUMBER(x) (((x) & 0xf) << 16)
557 # define AFMT_60958_CS_CHANNEL_NUMBER_L(x) (((x) & 0xf) << 20)
558 # define AFMT_60958_CS_SAMPLING_FREQUENCY(x) (((x) & 0xf) << 24)
559 # define AFMT_60958_CS_CLOCK_ACCURACY(x) (((x) & 3) << 28)
560 #define AFMT_60958_1 0x74d8
561 # define AFMT_60958_CS_WORD_LENGTH(x) (((x) & 0xf) << 0)
562 # define AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY(x) (((x) & 0xf) << 4)
563 # define AFMT_60958_CS_VALID_L(x) (((x) & 1) << 16)
564 # define AFMT_60958_CS_VALID_R(x) (((x) & 1) << 18)
565 # define AFMT_60958_CS_CHANNEL_NUMBER_R(x) (((x) & 0xf) << 20)
566 #define AFMT_AUDIO_CRC_CONTROL 0x74dc
567 # define AFMT_AUDIO_CRC_EN (1 << 0)
568 #define AFMT_RAMP_CONTROL0 0x74e0
569 # define AFMT_RAMP_MAX_COUNT(x) (((x) & 0xffffff) << 0)
570 # define AFMT_RAMP_DATA_SIGN (1 << 31)
571 #define AFMT_RAMP_CONTROL1 0x74e4
572 # define AFMT_RAMP_MIN_COUNT(x) (((x) & 0xffffff) << 0)
573 # define AFMT_AUDIO_TEST_CH_DISABLE(x) (((x) & 0xff) << 24)
574 #define AFMT_RAMP_CONTROL2 0x74e8
575 # define AFMT_RAMP_INC_COUNT(x) (((x) & 0xffffff) << 0)
576 #define AFMT_RAMP_CONTROL3 0x74ec
577 # define AFMT_RAMP_DEC_COUNT(x) (((x) & 0xffffff) << 0)
578 #define AFMT_60958_2 0x74f0
579 # define AFMT_60958_CS_CHANNEL_NUMBER_2(x) (((x) & 0xf) << 0)
580 # define AFMT_60958_CS_CHANNEL_NUMBER_3(x) (((x) & 0xf) << 4)
581 # define AFMT_60958_CS_CHANNEL_NUMBER_4(x) (((x) & 0xf) << 8)
582 # define AFMT_60958_CS_CHANNEL_NUMBER_5(x) (((x) & 0xf) << 12)
583 # define AFMT_60958_CS_CHANNEL_NUMBER_6(x) (((x) & 0xf) << 16)
584 # define AFMT_60958_CS_CHANNEL_NUMBER_7(x) (((x) & 0xf) << 20)
585 #define AFMT_STATUS 0x7600
586 # define AFMT_AUDIO_ENABLE (1 << 4)
587 # define AFMT_AZ_FORMAT_WTRIG (1 << 28)
588 # define AFMT_AZ_FORMAT_WTRIG_INT (1 << 29)
589 # define AFMT_AZ_AUDIO_ENABLE_CHG (1 << 30)
590 #define AFMT_AUDIO_PACKET_CONTROL 0x7604
591 # define AFMT_AUDIO_SAMPLE_SEND (1 << 0)
592 # define AFMT_AUDIO_TEST_EN (1 << 12)
593 # define AFMT_AUDIO_CHANNEL_SWAP (1 << 24)
594 # define AFMT_60958_CS_UPDATE (1 << 26)
595 # define AFMT_AZ_AUDIO_ENABLE_CHG_MASK (1 << 27)
596 # define AFMT_AZ_FORMAT_WTRIG_MASK (1 << 28)
597 # define AFMT_AZ_FORMAT_WTRIG_ACK (1 << 29)
598 # define AFMT_AZ_AUDIO_ENABLE_CHG_ACK (1 << 30)
599 #define AFMT_VBI_PACKET_CONTROL 0x7608
600 # define AFMT_GENERIC0_UPDATE (1 << 2)
601 #define AFMT_INFOFRAME_CONTROL0 0x760c
602 # define AFMT_AUDIO_INFO_SOURCE (1 << 6) /* 0 - sound block; 1 - hmdi regs */
603 # define AFMT_AUDIO_INFO_UPDATE (1 << 7)
604 # define AFMT_MPEG_INFO_UPDATE (1 << 10)
605 #define AFMT_GENERIC0_7 0x7610
606 /* second instance starts at 0x7800 */
607 #define HDMI_OFFSET0 (0x7400 - 0x7400)
608 #define HDMI_OFFSET1 (0x7800 - 0x7400)
610 /* DCE3.2 ELD audio interface */
611 #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR0 0x71c8 /* LPCM */
612 #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR1 0x71cc /* AC3 */
613 #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR2 0x71d0 /* MPEG1 */
614 #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR3 0x71d4 /* MP3 */
615 #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR4 0x71d8 /* MPEG2 */
616 #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR5 0x71dc /* AAC */
617 #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR6 0x71e0 /* DTS */
618 #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR7 0x71e4 /* ATRAC */
619 #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR8 0x71e8 /* one bit audio - leave at 0 (default) */
620 #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR9 0x71ec /* Dolby Digital */
621 #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR10 0x71f0 /* DTS-HD */
622 #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR11 0x71f4 /* MAT-MLP */
623 #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR12 0x71f8 /* DTS */
624 #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR13 0x71fc /* WMA Pro */
625 # define MAX_CHANNELS(x) (((x) & 0x7) << 0)
626 /* max channels minus one. 7 = 8 channels */
627 # define SUPPORTED_FREQUENCIES(x) (((x) & 0xff) << 8)
628 # define DESCRIPTOR_BYTE_2(x) (((x) & 0xff) << 16)
629 # define SUPPORTED_FREQUENCIES_STEREO(x) (((x) & 0xff) << 24) /* LPCM only */
630 /* SUPPORTED_FREQUENCIES, SUPPORTED_FREQUENCIES_STEREO
640 #define AZ_HOT_PLUG_CONTROL 0x7300
641 # define AZ_FORCE_CODEC_WAKE (1 << 0)
642 # define PIN0_JACK_DETECTION_ENABLE (1 << 4)
643 # define PIN1_JACK_DETECTION_ENABLE (1 << 5)
644 # define PIN2_JACK_DETECTION_ENABLE (1 << 6)
645 # define PIN3_JACK_DETECTION_ENABLE (1 << 7)
646 # define PIN0_UNSOLICITED_RESPONSE_ENABLE (1 << 8)
647 # define PIN1_UNSOLICITED_RESPONSE_ENABLE (1 << 9)
648 # define PIN2_UNSOLICITED_RESPONSE_ENABLE (1 << 10)
649 # define PIN3_UNSOLICITED_RESPONSE_ENABLE (1 << 11)
650 # define CODEC_HOT_PLUG_ENABLE (1 << 12)
651 # define PIN0_AUDIO_ENABLED (1 << 24)
652 # define PIN1_AUDIO_ENABLED (1 << 25)
653 # define PIN2_AUDIO_ENABLED (1 << 26)
654 # define PIN3_AUDIO_ENABLED (1 << 27)
655 # define AUDIO_ENABLED (1 << 31)
658 #define D1GRPH_PRIMARY_SURFACE_ADDRESS 0x6110
659 #define D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x6914
660 #define D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x6114
661 #define D1GRPH_SECONDARY_SURFACE_ADDRESS 0x6118
662 #define D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x691c
663 #define D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x611c
665 /* PCIE link stuff */
666 #define PCIE_LC_TRAINING_CNTL 0xa1 /* PCIE_P */
667 #define PCIE_LC_LINK_WIDTH_CNTL 0xa2 /* PCIE_P */
668 # define LC_LINK_WIDTH_SHIFT 0
669 # define LC_LINK_WIDTH_MASK 0x7
670 # define LC_LINK_WIDTH_X0 0
671 # define LC_LINK_WIDTH_X1 1
672 # define LC_LINK_WIDTH_X2 2
673 # define LC_LINK_WIDTH_X4 3
674 # define LC_LINK_WIDTH_X8 4
675 # define LC_LINK_WIDTH_X16 6
676 # define LC_LINK_WIDTH_RD_SHIFT 4
677 # define LC_LINK_WIDTH_RD_MASK 0x70
678 # define LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7)
679 # define LC_RECONFIG_NOW (1 << 8)
680 # define LC_RENEGOTIATION_SUPPORT (1 << 9)
681 # define LC_RENEGOTIATE_EN (1 << 10)
682 # define LC_SHORT_RECONFIG_EN (1 << 11)
683 # define LC_UPCONFIGURE_SUPPORT (1 << 12)
684 # define LC_UPCONFIGURE_DIS (1 << 13)
685 #define PCIE_LC_SPEED_CNTL 0xa4 /* PCIE_P */
686 # define LC_GEN2_EN_STRAP (1 << 0)
687 # define LC_TARGET_LINK_SPEED_OVERRIDE_EN (1 << 1)
688 # define LC_FORCE_EN_HW_SPEED_CHANGE (1 << 5)
689 # define LC_FORCE_DIS_HW_SPEED_CHANGE (1 << 6)
690 # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK (0x3 << 8)
691 # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT 3
692 # define LC_CURRENT_DATA_RATE (1 << 11)
693 # define LC_VOLTAGE_TIMER_SEL_MASK (0xf << 14)
694 # define LC_CLR_FAILED_SPD_CHANGE_CNT (1 << 21)
695 # define LC_OTHER_SIDE_EVER_SENT_GEN2 (1 << 23)
696 # define LC_OTHER_SIDE_SUPPORTS_GEN2 (1 << 24)
697 #define MM_CFGREGS_CNTL 0x544c
698 # define MM_WR_TO_CFG_EN (1 << 3)
699 #define LINK_CNTL2 0x88 /* F0 */
700 # define TARGET_LINK_SPEED_MASK (0xf << 0)
701 # define SELECTABLE_DEEMPHASIS (1 << 6)
704 #define UVD_LMI_EXT40_ADDR 0xf498
705 #define UVD_VCPU_CHIP_ID 0xf4d4
706 #define UVD_VCPU_CACHE_OFFSET0 0xf4d8
707 #define UVD_VCPU_CACHE_SIZE0 0xf4dc
708 #define UVD_VCPU_CACHE_OFFSET1 0xf4e0
709 #define UVD_VCPU_CACHE_SIZE1 0xf4e4
710 #define UVD_VCPU_CACHE_OFFSET2 0xf4e8
711 #define UVD_VCPU_CACHE_SIZE2 0xf4ec
712 #define UVD_LMI_ADDR_EXT 0xf594
714 #define UVD_RBC_RB_RPTR 0xf690
715 #define UVD_RBC_RB_WPTR 0xf694
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