projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Merge branch 'for-airlied' of git://people.freedesktop.org/~danvet/drm-intel into...
[deliverable/linux.git] / drivers / gpu / drm / radeon / si.c
1 /*
2 * Copyright 2011 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Alex Deucher
23 */
24 #include <linux/firmware.h>
25 #include <linux/platform_device.h>
26 #include <linux/slab.h>
27 #include <linux/module.h>
28 #include "drmP.h"
29 #include "radeon.h"
30 #include "radeon_asic.h"
31 #include "radeon_drm.h"
32 #include "sid.h"
33 #include "atom.h"
34 #include "si_blit_shaders.h"
35
36 #define SI_PFP_UCODE_SIZE 2144
37 #define SI_PM4_UCODE_SIZE 2144
38 #define SI_CE_UCODE_SIZE 2144
39 #define SI_RLC_UCODE_SIZE 2048
40 #define SI_MC_UCODE_SIZE 7769
41
42 MODULE_FIRMWARE("radeon/TAHITI_pfp.bin");
43 MODULE_FIRMWARE("radeon/TAHITI_me.bin");
44 MODULE_FIRMWARE("radeon/TAHITI_ce.bin");
45 MODULE_FIRMWARE("radeon/TAHITI_mc.bin");
46 MODULE_FIRMWARE("radeon/TAHITI_rlc.bin");
47 MODULE_FIRMWARE("radeon/PITCAIRN_pfp.bin");
48 MODULE_FIRMWARE("radeon/PITCAIRN_me.bin");
49 MODULE_FIRMWARE("radeon/PITCAIRN_ce.bin");
50 MODULE_FIRMWARE("radeon/PITCAIRN_mc.bin");
51 MODULE_FIRMWARE("radeon/PITCAIRN_rlc.bin");
52 MODULE_FIRMWARE("radeon/VERDE_pfp.bin");
53 MODULE_FIRMWARE("radeon/VERDE_me.bin");
54 MODULE_FIRMWARE("radeon/VERDE_ce.bin");
55 MODULE_FIRMWARE("radeon/VERDE_mc.bin");
56 MODULE_FIRMWARE("radeon/VERDE_rlc.bin");
57
58 extern int r600_ih_ring_alloc(struct radeon_device *rdev);
59 extern void r600_ih_ring_fini(struct radeon_device *rdev);
60 extern void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev);
61 extern void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save);
62 extern void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save);
63 extern u32 evergreen_get_number_of_dram_channels(struct radeon_device *rdev);
64
65 /* get temperature in millidegrees */
66 int si_get_temp(struct radeon_device *rdev)
67 {
68 u32 temp;
69 int actual_temp = 0;
70
71 temp = (RREG32(CG_MULT_THERMAL_STATUS) & CTF_TEMP_MASK) >>
72 CTF_TEMP_SHIFT;
73
74 if (temp & 0x200)
75 actual_temp = 255;
76 else
77 actual_temp = temp & 0x1ff;
78
79 actual_temp = (actual_temp * 1000);
80
81 return actual_temp;
82 }
83
84 #define TAHITI_IO_MC_REGS_SIZE 36
85
86 static const u32 tahiti_io_mc_regs[TAHITI_IO_MC_REGS_SIZE][2] = {
87 {0x0000006f, 0x03044000},
88 {0x00000070, 0x0480c018},
89 {0x00000071, 0x00000040},
90 {0x00000072, 0x01000000},
91 {0x00000074, 0x000000ff},
92 {0x00000075, 0x00143400},
93 {0x00000076, 0x08ec0800},
94 {0x00000077, 0x040000cc},
95 {0x00000079, 0x00000000},
96 {0x0000007a, 0x21000409},
97 {0x0000007c, 0x00000000},
98 {0x0000007d, 0xe8000000},
99 {0x0000007e, 0x044408a8},
100 {0x0000007f, 0x00000003},
101 {0x00000080, 0x00000000},
102 {0x00000081, 0x01000000},
103 {0x00000082, 0x02000000},
104 {0x00000083, 0x00000000},
105 {0x00000084, 0xe3f3e4f4},
106 {0x00000085, 0x00052024},
107 {0x00000087, 0x00000000},
108 {0x00000088, 0x66036603},
109 {0x00000089, 0x01000000},
110 {0x0000008b, 0x1c0a0000},
111 {0x0000008c, 0xff010000},
112 {0x0000008e, 0xffffefff},
113 {0x0000008f, 0xfff3efff},
114 {0x00000090, 0xfff3efbf},
115 {0x00000094, 0x00101101},
116 {0x00000095, 0x00000fff},
117 {0x00000096, 0x00116fff},
118 {0x00000097, 0x60010000},
119 {0x00000098, 0x10010000},
120 {0x00000099, 0x00006000},
121 {0x0000009a, 0x00001000},
122 {0x0000009f, 0x00a77400}
123 };
124
125 static const u32 pitcairn_io_mc_regs[TAHITI_IO_MC_REGS_SIZE][2] = {
126 {0x0000006f, 0x03044000},
127 {0x00000070, 0x0480c018},
128 {0x00000071, 0x00000040},
129 {0x00000072, 0x01000000},
130 {0x00000074, 0x000000ff},
131 {0x00000075, 0x00143400},
132 {0x00000076, 0x08ec0800},
133 {0x00000077, 0x040000cc},
134 {0x00000079, 0x00000000},
135 {0x0000007a, 0x21000409},
136 {0x0000007c, 0x00000000},
137 {0x0000007d, 0xe8000000},
138 {0x0000007e, 0x044408a8},
139 {0x0000007f, 0x00000003},
140 {0x00000080, 0x00000000},
141 {0x00000081, 0x01000000},
142 {0x00000082, 0x02000000},
143 {0x00000083, 0x00000000},
144 {0x00000084, 0xe3f3e4f4},
145 {0x00000085, 0x00052024},
146 {0x00000087, 0x00000000},
147 {0x00000088, 0x66036603},
148 {0x00000089, 0x01000000},
149 {0x0000008b, 0x1c0a0000},
150 {0x0000008c, 0xff010000},
151 {0x0000008e, 0xffffefff},
152 {0x0000008f, 0xfff3efff},
153 {0x00000090, 0xfff3efbf},
154 {0x00000094, 0x00101101},
155 {0x00000095, 0x00000fff},
156 {0x00000096, 0x00116fff},
157 {0x00000097, 0x60010000},
158 {0x00000098, 0x10010000},
159 {0x00000099, 0x00006000},
160 {0x0000009a, 0x00001000},
161 {0x0000009f, 0x00a47400}
162 };
163
164 static const u32 verde_io_mc_regs[TAHITI_IO_MC_REGS_SIZE][2] = {
165 {0x0000006f, 0x03044000},
166 {0x00000070, 0x0480c018},
167 {0x00000071, 0x00000040},
168 {0x00000072, 0x01000000},
169 {0x00000074, 0x000000ff},
170 {0x00000075, 0x00143400},
171 {0x00000076, 0x08ec0800},
172 {0x00000077, 0x040000cc},
173 {0x00000079, 0x00000000},
174 {0x0000007a, 0x21000409},
175 {0x0000007c, 0x00000000},
176 {0x0000007d, 0xe8000000},
177 {0x0000007e, 0x044408a8},
178 {0x0000007f, 0x00000003},
179 {0x00000080, 0x00000000},
180 {0x00000081, 0x01000000},
181 {0x00000082, 0x02000000},
182 {0x00000083, 0x00000000},
183 {0x00000084, 0xe3f3e4f4},
184 {0x00000085, 0x00052024},
185 {0x00000087, 0x00000000},
186 {0x00000088, 0x66036603},
187 {0x00000089, 0x01000000},
188 {0x0000008b, 0x1c0a0000},
189 {0x0000008c, 0xff010000},
190 {0x0000008e, 0xffffefff},
191 {0x0000008f, 0xfff3efff},
192 {0x00000090, 0xfff3efbf},
193 {0x00000094, 0x00101101},
194 {0x00000095, 0x00000fff},
195 {0x00000096, 0x00116fff},
196 {0x00000097, 0x60010000},
197 {0x00000098, 0x10010000},
198 {0x00000099, 0x00006000},
199 {0x0000009a, 0x00001000},
200 {0x0000009f, 0x00a37400}
201 };
202
203 /* ucode loading */
204 static int si_mc_load_microcode(struct radeon_device *rdev)
205 {
206 const __be32 *fw_data;
207 u32 running, blackout = 0;
208 u32 *io_mc_regs;
209 int i, ucode_size, regs_size;
210
211 if (!rdev->mc_fw)
212 return -EINVAL;
213
214 switch (rdev->family) {
215 case CHIP_TAHITI:
216 io_mc_regs = (u32 *)&tahiti_io_mc_regs;
217 ucode_size = SI_MC_UCODE_SIZE;
218 regs_size = TAHITI_IO_MC_REGS_SIZE;
219 break;
220 case CHIP_PITCAIRN:
221 io_mc_regs = (u32 *)&pitcairn_io_mc_regs;
222 ucode_size = SI_MC_UCODE_SIZE;
223 regs_size = TAHITI_IO_MC_REGS_SIZE;
224 break;
225 case CHIP_VERDE:
226 default:
227 io_mc_regs = (u32 *)&verde_io_mc_regs;
228 ucode_size = SI_MC_UCODE_SIZE;
229 regs_size = TAHITI_IO_MC_REGS_SIZE;
230 break;
231 }
232
233 running = RREG32(MC_SEQ_SUP_CNTL) & RUN_MASK;
234
235 if (running == 0) {
236 if (running) {
237 blackout = RREG32(MC_SHARED_BLACKOUT_CNTL);
238 WREG32(MC_SHARED_BLACKOUT_CNTL, blackout | 1);
239 }
240
241 /* reset the engine and set to writable */
242 WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
243 WREG32(MC_SEQ_SUP_CNTL, 0x00000010);
244
245 /* load mc io regs */
246 for (i = 0; i < regs_size; i++) {
247 WREG32(MC_SEQ_IO_DEBUG_INDEX, io_mc_regs[(i << 1)]);
248 WREG32(MC_SEQ_IO_DEBUG_DATA, io_mc_regs[(i << 1) + 1]);
249 }
250 /* load the MC ucode */
251 fw_data = (const __be32 *)rdev->mc_fw->data;
252 for (i = 0; i < ucode_size; i++)
253 WREG32(MC_SEQ_SUP_PGM, be32_to_cpup(fw_data++));
254
255 /* put the engine back into the active state */
256 WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
257 WREG32(MC_SEQ_SUP_CNTL, 0x00000004);
258 WREG32(MC_SEQ_SUP_CNTL, 0x00000001);
259
260 /* wait for training to complete */
261 for (i = 0; i < rdev->usec_timeout; i++) {
262 if (RREG32(MC_SEQ_TRAIN_WAKEUP_CNTL) & TRAIN_DONE_D0)
263 break;
264 udelay(1);
265 }
266 for (i = 0; i < rdev->usec_timeout; i++) {
267 if (RREG32(MC_SEQ_TRAIN_WAKEUP_CNTL) & TRAIN_DONE_D1)
268 break;
269 udelay(1);
270 }
271
272 if (running)
273 WREG32(MC_SHARED_BLACKOUT_CNTL, blackout);
274 }
275
276 return 0;
277 }
278
279 static int si_init_microcode(struct radeon_device *rdev)
280 {
281 struct platform_device *pdev;
282 const char *chip_name;
283 const char *rlc_chip_name;
284 size_t pfp_req_size, me_req_size, ce_req_size, rlc_req_size, mc_req_size;
285 char fw_name[30];
286 int err;
287
288 DRM_DEBUG("\n");
289
290 pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
291 err = IS_ERR(pdev);
292 if (err) {
293 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
294 return -EINVAL;
295 }
296
297 switch (rdev->family) {
298 case CHIP_TAHITI:
299 chip_name = "TAHITI";
300 rlc_chip_name = "TAHITI";
301 pfp_req_size = SI_PFP_UCODE_SIZE * 4;
302 me_req_size = SI_PM4_UCODE_SIZE * 4;
303 ce_req_size = SI_CE_UCODE_SIZE * 4;
304 rlc_req_size = SI_RLC_UCODE_SIZE * 4;
305 mc_req_size = SI_MC_UCODE_SIZE * 4;
306 break;
307 case CHIP_PITCAIRN:
308 chip_name = "PITCAIRN";
309 rlc_chip_name = "PITCAIRN";
310 pfp_req_size = SI_PFP_UCODE_SIZE * 4;
311 me_req_size = SI_PM4_UCODE_SIZE * 4;
312 ce_req_size = SI_CE_UCODE_SIZE * 4;
313 rlc_req_size = SI_RLC_UCODE_SIZE * 4;
314 mc_req_size = SI_MC_UCODE_SIZE * 4;
315 break;
316 case CHIP_VERDE:
317 chip_name = "VERDE";
318 rlc_chip_name = "VERDE";
319 pfp_req_size = SI_PFP_UCODE_SIZE * 4;
320 me_req_size = SI_PM4_UCODE_SIZE * 4;
321 ce_req_size = SI_CE_UCODE_SIZE * 4;
322 rlc_req_size = SI_RLC_UCODE_SIZE * 4;
323 mc_req_size = SI_MC_UCODE_SIZE * 4;
324 break;
325 default: BUG();
326 }
327
328 DRM_INFO("Loading %s Microcode\n", chip_name);
329
330 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
331 err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev);
332 if (err)
333 goto out;
334 if (rdev->pfp_fw->size != pfp_req_size) {
335 printk(KERN_ERR
336 "si_cp: Bogus length %zu in firmware \"%s\"\n",
337 rdev->pfp_fw->size, fw_name);
338 err = -EINVAL;
339 goto out;
340 }
341
342 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
343 err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
344 if (err)
345 goto out;
346 if (rdev->me_fw->size != me_req_size) {
347 printk(KERN_ERR
348 "si_cp: Bogus length %zu in firmware \"%s\"\n",
349 rdev->me_fw->size, fw_name);
350 err = -EINVAL;
351 }
352
353 snprintf(fw_name, sizeof(fw_name), "radeon/%s_ce.bin", chip_name);
354 err = request_firmware(&rdev->ce_fw, fw_name, &pdev->dev);
355 if (err)
356 goto out;
357 if (rdev->ce_fw->size != ce_req_size) {
358 printk(KERN_ERR
359 "si_cp: Bogus length %zu in firmware \"%s\"\n",
360 rdev->ce_fw->size, fw_name);
361 err = -EINVAL;
362 }
363
364 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name);
365 err = request_firmware(&rdev->rlc_fw, fw_name, &pdev->dev);
366 if (err)
367 goto out;
368 if (rdev->rlc_fw->size != rlc_req_size) {
369 printk(KERN_ERR
370 "si_rlc: Bogus length %zu in firmware \"%s\"\n",
371 rdev->rlc_fw->size, fw_name);
372 err = -EINVAL;
373 }
374
375 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name);
376 err = request_firmware(&rdev->mc_fw, fw_name, &pdev->dev);
377 if (err)
378 goto out;
379 if (rdev->mc_fw->size != mc_req_size) {
380 printk(KERN_ERR
381 "si_mc: Bogus length %zu in firmware \"%s\"\n",
382 rdev->mc_fw->size, fw_name);
383 err = -EINVAL;
384 }
385
386 out:
387 platform_device_unregister(pdev);
388
389 if (err) {
390 if (err != -EINVAL)
391 printk(KERN_ERR
392 "si_cp: Failed to load firmware \"%s\"\n",
393 fw_name);
394 release_firmware(rdev->pfp_fw);
395 rdev->pfp_fw = NULL;
396 release_firmware(rdev->me_fw);
397 rdev->me_fw = NULL;
398 release_firmware(rdev->ce_fw);
399 rdev->ce_fw = NULL;
400 release_firmware(rdev->rlc_fw);
401 rdev->rlc_fw = NULL;
402 release_firmware(rdev->mc_fw);
403 rdev->mc_fw = NULL;
404 }
405 return err;
406 }
407
408 /* watermark setup */
409 static u32 dce6_line_buffer_adjust(struct radeon_device *rdev,
410 struct radeon_crtc *radeon_crtc,
411 struct drm_display_mode *mode,
412 struct drm_display_mode *other_mode)
413 {
414 u32 tmp;
415 /*
416 * Line Buffer Setup
417 * There are 3 line buffers, each one shared by 2 display controllers.
418 * DC_LB_MEMORY_SPLIT controls how that line buffer is shared between
419 * the display controllers. The paritioning is done via one of four
420 * preset allocations specified in bits 21:20:
421 * 0 - half lb
422 * 2 - whole lb, other crtc must be disabled
423 */
424 /* this can get tricky if we have two large displays on a paired group
425 * of crtcs. Ideally for multiple large displays we'd assign them to
426 * non-linked crtcs for maximum line buffer allocation.
427 */
428 if (radeon_crtc->base.enabled && mode) {
429 if (other_mode)
430 tmp = 0; /* 1/2 */
431 else
432 tmp = 2; /* whole */
433 } else
434 tmp = 0;
435
436 WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset,
437 DC_LB_MEMORY_CONFIG(tmp));
438
439 if (radeon_crtc->base.enabled && mode) {
440 switch (tmp) {
441 case 0:
442 default:
443 return 4096 * 2;
444 case 2:
445 return 8192 * 2;
446 }
447 }
448
449 /* controller not enabled, so no lb used */
450 return 0;
451 }
452
453 static u32 si_get_number_of_dram_channels(struct radeon_device *rdev)
454 {
455 u32 tmp = RREG32(MC_SHARED_CHMAP);
456
457 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
458 case 0:
459 default:
460 return 1;
461 case 1:
462 return 2;
463 case 2:
464 return 4;
465 case 3:
466 return 8;
467 case 4:
468 return 3;
469 case 5:
470 return 6;
471 case 6:
472 return 10;
473 case 7:
474 return 12;
475 case 8:
476 return 16;
477 }
478 }
479
480 struct dce6_wm_params {
481 u32 dram_channels; /* number of dram channels */
482 u32 yclk; /* bandwidth per dram data pin in kHz */
483 u32 sclk; /* engine clock in kHz */
484 u32 disp_clk; /* display clock in kHz */
485 u32 src_width; /* viewport width */
486 u32 active_time; /* active display time in ns */
487 u32 blank_time; /* blank time in ns */
488 bool interlaced; /* mode is interlaced */
489 fixed20_12 vsc; /* vertical scale ratio */
490 u32 num_heads; /* number of active crtcs */
491 u32 bytes_per_pixel; /* bytes per pixel display + overlay */
492 u32 lb_size; /* line buffer allocated to pipe */
493 u32 vtaps; /* vertical scaler taps */
494 };
495
496 static u32 dce6_dram_bandwidth(struct dce6_wm_params *wm)
497 {
498 /* Calculate raw DRAM Bandwidth */
499 fixed20_12 dram_efficiency; /* 0.7 */
500 fixed20_12 yclk, dram_channels, bandwidth;
501 fixed20_12 a;
502
503 a.full = dfixed_const(1000);
504 yclk.full = dfixed_const(wm->yclk);
505 yclk.full = dfixed_div(yclk, a);
506 dram_channels.full = dfixed_const(wm->dram_channels * 4);
507 a.full = dfixed_const(10);
508 dram_efficiency.full = dfixed_const(7);
509 dram_efficiency.full = dfixed_div(dram_efficiency, a);
510 bandwidth.full = dfixed_mul(dram_channels, yclk);
511 bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
512
513 return dfixed_trunc(bandwidth);
514 }
515
516 static u32 dce6_dram_bandwidth_for_display(struct dce6_wm_params *wm)
517 {
518 /* Calculate DRAM Bandwidth and the part allocated to display. */
519 fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
520 fixed20_12 yclk, dram_channels, bandwidth;
521 fixed20_12 a;
522
523 a.full = dfixed_const(1000);
524 yclk.full = dfixed_const(wm->yclk);
525 yclk.full = dfixed_div(yclk, a);
526 dram_channels.full = dfixed_const(wm->dram_channels * 4);
527 a.full = dfixed_const(10);
528 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
529 disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
530 bandwidth.full = dfixed_mul(dram_channels, yclk);
531 bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
532
533 return dfixed_trunc(bandwidth);
534 }
535
536 static u32 dce6_data_return_bandwidth(struct dce6_wm_params *wm)
537 {
538 /* Calculate the display Data return Bandwidth */
539 fixed20_12 return_efficiency; /* 0.8 */
540 fixed20_12 sclk, bandwidth;
541 fixed20_12 a;
542
543 a.full = dfixed_const(1000);
544 sclk.full = dfixed_const(wm->sclk);
545 sclk.full = dfixed_div(sclk, a);
546 a.full = dfixed_const(10);
547 return_efficiency.full = dfixed_const(8);
548 return_efficiency.full = dfixed_div(return_efficiency, a);
549 a.full = dfixed_const(32);
550 bandwidth.full = dfixed_mul(a, sclk);
551 bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
552
553 return dfixed_trunc(bandwidth);
554 }
555
556 static u32 dce6_get_dmif_bytes_per_request(struct dce6_wm_params *wm)
557 {
558 return 32;
559 }
560
561 static u32 dce6_dmif_request_bandwidth(struct dce6_wm_params *wm)
562 {
563 /* Calculate the DMIF Request Bandwidth */
564 fixed20_12 disp_clk_request_efficiency; /* 0.8 */
565 fixed20_12 disp_clk, sclk, bandwidth;
566 fixed20_12 a, b1, b2;
567 u32 min_bandwidth;
568
569 a.full = dfixed_const(1000);
570 disp_clk.full = dfixed_const(wm->disp_clk);
571 disp_clk.full = dfixed_div(disp_clk, a);
572 a.full = dfixed_const(dce6_get_dmif_bytes_per_request(wm) / 2);
573 b1.full = dfixed_mul(a, disp_clk);
574
575 a.full = dfixed_const(1000);
576 sclk.full = dfixed_const(wm->sclk);
577 sclk.full = dfixed_div(sclk, a);
578 a.full = dfixed_const(dce6_get_dmif_bytes_per_request(wm));
579 b2.full = dfixed_mul(a, sclk);
580
581 a.full = dfixed_const(10);
582 disp_clk_request_efficiency.full = dfixed_const(8);
583 disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
584
585 min_bandwidth = min(dfixed_trunc(b1), dfixed_trunc(b2));
586
587 a.full = dfixed_const(min_bandwidth);
588 bandwidth.full = dfixed_mul(a, disp_clk_request_efficiency);
589
590 return dfixed_trunc(bandwidth);
591 }
592
593 static u32 dce6_available_bandwidth(struct dce6_wm_params *wm)
594 {
595 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
596 u32 dram_bandwidth = dce6_dram_bandwidth(wm);
597 u32 data_return_bandwidth = dce6_data_return_bandwidth(wm);
598 u32 dmif_req_bandwidth = dce6_dmif_request_bandwidth(wm);
599
600 return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
601 }
602
603 static u32 dce6_average_bandwidth(struct dce6_wm_params *wm)
604 {
605 /* Calculate the display mode Average Bandwidth
606 * DisplayMode should contain the source and destination dimensions,
607 * timing, etc.
608 */
609 fixed20_12 bpp;
610 fixed20_12 line_time;
611 fixed20_12 src_width;
612 fixed20_12 bandwidth;
613 fixed20_12 a;
614
615 a.full = dfixed_const(1000);
616 line_time.full = dfixed_const(wm->active_time + wm->blank_time);
617 line_time.full = dfixed_div(line_time, a);
618 bpp.full = dfixed_const(wm->bytes_per_pixel);
619 src_width.full = dfixed_const(wm->src_width);
620 bandwidth.full = dfixed_mul(src_width, bpp);
621 bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
622 bandwidth.full = dfixed_div(bandwidth, line_time);
623
624 return dfixed_trunc(bandwidth);
625 }
626
627 static u32 dce6_latency_watermark(struct dce6_wm_params *wm)
628 {
629 /* First calcualte the latency in ns */
630 u32 mc_latency = 2000; /* 2000 ns. */
631 u32 available_bandwidth = dce6_available_bandwidth(wm);
632 u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
633 u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
634 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
635 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
636 (wm->num_heads * cursor_line_pair_return_time);
637 u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
638 u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
639 u32 tmp, dmif_size = 12288;
640 fixed20_12 a, b, c;
641
642 if (wm->num_heads == 0)
643 return 0;
644
645 a.full = dfixed_const(2);
646 b.full = dfixed_const(1);
647 if ((wm->vsc.full > a.full) ||
648 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
649 (wm->vtaps >= 5) ||
650 ((wm->vsc.full >= a.full) && wm->interlaced))
651 max_src_lines_per_dst_line = 4;
652 else
653 max_src_lines_per_dst_line = 2;
654
655 a.full = dfixed_const(available_bandwidth);
656 b.full = dfixed_const(wm->num_heads);
657 a.full = dfixed_div(a, b);
658
659 b.full = dfixed_const(mc_latency + 512);
660 c.full = dfixed_const(wm->disp_clk);
661 b.full = dfixed_div(b, c);
662
663 c.full = dfixed_const(dmif_size);
664 b.full = dfixed_div(c, b);
665
666 tmp = min(dfixed_trunc(a), dfixed_trunc(b));
667
668 b.full = dfixed_const(1000);
669 c.full = dfixed_const(wm->disp_clk);
670 b.full = dfixed_div(c, b);
671 c.full = dfixed_const(wm->bytes_per_pixel);
672 b.full = dfixed_mul(b, c);
673
674 lb_fill_bw = min(tmp, dfixed_trunc(b));
675
676 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
677 b.full = dfixed_const(1000);
678 c.full = dfixed_const(lb_fill_bw);
679 b.full = dfixed_div(c, b);
680 a.full = dfixed_div(a, b);
681 line_fill_time = dfixed_trunc(a);
682
683 if (line_fill_time < wm->active_time)
684 return latency;
685 else
686 return latency + (line_fill_time - wm->active_time);
687
688 }
689
690 static bool dce6_average_bandwidth_vs_dram_bandwidth_for_display(struct dce6_wm_params *wm)
691 {
692 if (dce6_average_bandwidth(wm) <=
693 (dce6_dram_bandwidth_for_display(wm) / wm->num_heads))
694 return true;
695 else
696 return false;
697 };
698
699 static bool dce6_average_bandwidth_vs_available_bandwidth(struct dce6_wm_params *wm)
700 {
701 if (dce6_average_bandwidth(wm) <=
702 (dce6_available_bandwidth(wm) / wm->num_heads))
703 return true;
704 else
705 return false;
706 };
707
708 static bool dce6_check_latency_hiding(struct dce6_wm_params *wm)
709 {
710 u32 lb_partitions = wm->lb_size / wm->src_width;
711 u32 line_time = wm->active_time + wm->blank_time;
712 u32 latency_tolerant_lines;
713 u32 latency_hiding;
714 fixed20_12 a;
715
716 a.full = dfixed_const(1);
717 if (wm->vsc.full > a.full)
718 latency_tolerant_lines = 1;
719 else {
720 if (lb_partitions <= (wm->vtaps + 1))
721 latency_tolerant_lines = 1;
722 else
723 latency_tolerant_lines = 2;
724 }
725
726 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
727
728 if (dce6_latency_watermark(wm) <= latency_hiding)
729 return true;
730 else
731 return false;
732 }
733
734 static void dce6_program_watermarks(struct radeon_device *rdev,
735 struct radeon_crtc *radeon_crtc,
736 u32 lb_size, u32 num_heads)
737 {
738 struct drm_display_mode *mode = &radeon_crtc->base.mode;
739 struct dce6_wm_params wm;
740 u32 pixel_period;
741 u32 line_time = 0;
742 u32 latency_watermark_a = 0, latency_watermark_b = 0;
743 u32 priority_a_mark = 0, priority_b_mark = 0;
744 u32 priority_a_cnt = PRIORITY_OFF;
745 u32 priority_b_cnt = PRIORITY_OFF;
746 u32 tmp, arb_control3;
747 fixed20_12 a, b, c;
748
749 if (radeon_crtc->base.enabled && num_heads && mode) {
750 pixel_period = 1000000 / (u32)mode->clock;
751 line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535);
752 priority_a_cnt = 0;
753 priority_b_cnt = 0;
754
755 wm.yclk = rdev->pm.current_mclk * 10;
756 wm.sclk = rdev->pm.current_sclk * 10;
757 wm.disp_clk = mode->clock;
758 wm.src_width = mode->crtc_hdisplay;
759 wm.active_time = mode->crtc_hdisplay * pixel_period;
760 wm.blank_time = line_time - wm.active_time;
761 wm.interlaced = false;
762 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
763 wm.interlaced = true;
764 wm.vsc = radeon_crtc->vsc;
765 wm.vtaps = 1;
766 if (radeon_crtc->rmx_type != RMX_OFF)
767 wm.vtaps = 2;
768 wm.bytes_per_pixel = 4; /* XXX: get this from fb config */
769 wm.lb_size = lb_size;
770 if (rdev->family == CHIP_ARUBA)
771 wm.dram_channels = evergreen_get_number_of_dram_channels(rdev);
772 else
773 wm.dram_channels = si_get_number_of_dram_channels(rdev);
774 wm.num_heads = num_heads;
775
776 /* set for high clocks */
777 latency_watermark_a = min(dce6_latency_watermark(&wm), (u32)65535);
778 /* set for low clocks */
779 /* wm.yclk = low clk; wm.sclk = low clk */
780 latency_watermark_b = min(dce6_latency_watermark(&wm), (u32)65535);
781
782 /* possibly force display priority to high */
783 /* should really do this at mode validation time... */
784 if (!dce6_average_bandwidth_vs_dram_bandwidth_for_display(&wm) ||
785 !dce6_average_bandwidth_vs_available_bandwidth(&wm) ||
786 !dce6_check_latency_hiding(&wm) ||
787 (rdev->disp_priority == 2)) {
788 DRM_DEBUG_KMS("force priority to high\n");
789 priority_a_cnt |= PRIORITY_ALWAYS_ON;
790 priority_b_cnt |= PRIORITY_ALWAYS_ON;
791 }
792
793 a.full = dfixed_const(1000);
794 b.full = dfixed_const(mode->clock);
795 b.full = dfixed_div(b, a);
796 c.full = dfixed_const(latency_watermark_a);
797 c.full = dfixed_mul(c, b);
798 c.full = dfixed_mul(c, radeon_crtc->hsc);
799 c.full = dfixed_div(c, a);
800 a.full = dfixed_const(16);
801 c.full = dfixed_div(c, a);
802 priority_a_mark = dfixed_trunc(c);
803 priority_a_cnt |= priority_a_mark & PRIORITY_MARK_MASK;
804
805 a.full = dfixed_const(1000);
806 b.full = dfixed_const(mode->clock);
807 b.full = dfixed_div(b, a);
808 c.full = dfixed_const(latency_watermark_b);
809 c.full = dfixed_mul(c, b);
810 c.full = dfixed_mul(c, radeon_crtc->hsc);
811 c.full = dfixed_div(c, a);
812 a.full = dfixed_const(16);
813 c.full = dfixed_div(c, a);
814 priority_b_mark = dfixed_trunc(c);
815 priority_b_cnt |= priority_b_mark & PRIORITY_MARK_MASK;
816 }
817
818 /* select wm A */
819 arb_control3 = RREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset);
820 tmp = arb_control3;
821 tmp &= ~LATENCY_WATERMARK_MASK(3);
822 tmp |= LATENCY_WATERMARK_MASK(1);
823 WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, tmp);
824 WREG32(DPG_PIPE_LATENCY_CONTROL + radeon_crtc->crtc_offset,
825 (LATENCY_LOW_WATERMARK(latency_watermark_a) |
826 LATENCY_HIGH_WATERMARK(line_time)));
827 /* select wm B */
828 tmp = RREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset);
829 tmp &= ~LATENCY_WATERMARK_MASK(3);
830 tmp |= LATENCY_WATERMARK_MASK(2);
831 WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, tmp);
832 WREG32(DPG_PIPE_LATENCY_CONTROL + radeon_crtc->crtc_offset,
833 (LATENCY_LOW_WATERMARK(latency_watermark_b) |
834 LATENCY_HIGH_WATERMARK(line_time)));
835 /* restore original selection */
836 WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, arb_control3);
837
838 /* write the priority marks */
839 WREG32(PRIORITY_A_CNT + radeon_crtc->crtc_offset, priority_a_cnt);
840 WREG32(PRIORITY_B_CNT + radeon_crtc->crtc_offset, priority_b_cnt);
841
842 }
843
844 void dce6_bandwidth_update(struct radeon_device *rdev)
845 {
846 struct drm_display_mode *mode0 = NULL;
847 struct drm_display_mode *mode1 = NULL;
848 u32 num_heads = 0, lb_size;
849 int i;
850
851 radeon_update_display_priority(rdev);
852
853 for (i = 0; i < rdev->num_crtc; i++) {
854 if (rdev->mode_info.crtcs[i]->base.enabled)
855 num_heads++;
856 }
857 for (i = 0; i < rdev->num_crtc; i += 2) {
858 mode0 = &rdev->mode_info.crtcs[i]->base.mode;
859 mode1 = &rdev->mode_info.crtcs[i+1]->base.mode;
860 lb_size = dce6_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i], mode0, mode1);
861 dce6_program_watermarks(rdev, rdev->mode_info.crtcs[i], lb_size, num_heads);
862 lb_size = dce6_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i+1], mode1, mode0);
863 dce6_program_watermarks(rdev, rdev->mode_info.crtcs[i+1], lb_size, num_heads);
864 }
865 }
866
867 /*
868 * Core functions
869 */
870 static u32 si_get_tile_pipe_to_backend_map(struct radeon_device *rdev,
871 u32 num_tile_pipes,
872 u32 num_backends_per_asic,
873 u32 *backend_disable_mask_per_asic,
874 u32 num_shader_engines)
875 {
876 u32 backend_map = 0;
877 u32 enabled_backends_mask = 0;
878 u32 enabled_backends_count = 0;
879 u32 num_backends_per_se;
880 u32 cur_pipe;
881 u32 swizzle_pipe[SI_MAX_PIPES];
882 u32 cur_backend = 0;
883 u32 i;
884 bool force_no_swizzle;
885
886 /* force legal values */
887 if (num_tile_pipes < 1)
888 num_tile_pipes = 1;
889 if (num_tile_pipes > rdev->config.si.max_tile_pipes)
890 num_tile_pipes = rdev->config.si.max_tile_pipes;
891 if (num_shader_engines < 1)
892 num_shader_engines = 1;
893 if (num_shader_engines > rdev->config.si.max_shader_engines)
894 num_shader_engines = rdev->config.si.max_shader_engines;
895 if (num_backends_per_asic < num_shader_engines)
896 num_backends_per_asic = num_shader_engines;
897 if (num_backends_per_asic > (rdev->config.si.max_backends_per_se * num_shader_engines))
898 num_backends_per_asic = rdev->config.si.max_backends_per_se * num_shader_engines;
899
900 /* make sure we have the same number of backends per se */
901 num_backends_per_asic = ALIGN(num_backends_per_asic, num_shader_engines);
902 /* set up the number of backends per se */
903 num_backends_per_se = num_backends_per_asic / num_shader_engines;
904 if (num_backends_per_se > rdev->config.si.max_backends_per_se) {
905 num_backends_per_se = rdev->config.si.max_backends_per_se;
906 num_backends_per_asic = num_backends_per_se * num_shader_engines;
907 }
908
909 /* create enable mask and count for enabled backends */
910 for (i = 0; i < SI_MAX_BACKENDS; ++i) {
911 if (((*backend_disable_mask_per_asic >> i) & 1) == 0) {
912 enabled_backends_mask |= (1 << i);
913 ++enabled_backends_count;
914 }
915 if (enabled_backends_count == num_backends_per_asic)
916 break;
917 }
918
919 /* force the backends mask to match the current number of backends */
920 if (enabled_backends_count != num_backends_per_asic) {
921 u32 this_backend_enabled;
922 u32 shader_engine;
923 u32 backend_per_se;
924
925 enabled_backends_mask = 0;
926 enabled_backends_count = 0;
927 *backend_disable_mask_per_asic = SI_MAX_BACKENDS_MASK;
928 for (i = 0; i < SI_MAX_BACKENDS; ++i) {
929 /* calc the current se */
930 shader_engine = i / rdev->config.si.max_backends_per_se;
931 /* calc the backend per se */
932 backend_per_se = i % rdev->config.si.max_backends_per_se;
933 /* default to not enabled */
934 this_backend_enabled = 0;
935 if ((shader_engine < num_shader_engines) &&
936 (backend_per_se < num_backends_per_se))
937 this_backend_enabled = 1;
938 if (this_backend_enabled) {
939 enabled_backends_mask |= (1 << i);
940 *backend_disable_mask_per_asic &= ~(1 << i);
941 ++enabled_backends_count;
942 }
943 }
944 }
945
946
947 memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * SI_MAX_PIPES);
948 switch (rdev->family) {
949 case CHIP_TAHITI:
950 case CHIP_PITCAIRN:
951 case CHIP_VERDE:
952 force_no_swizzle = true;
953 break;
954 default:
955 force_no_swizzle = false;
956 break;
957 }
958 if (force_no_swizzle) {
959 bool last_backend_enabled = false;
960
961 force_no_swizzle = false;
962 for (i = 0; i < SI_MAX_BACKENDS; ++i) {
963 if (((enabled_backends_mask >> i) & 1) == 1) {
964 if (last_backend_enabled)
965 force_no_swizzle = true;
966 last_backend_enabled = true;
967 } else
968 last_backend_enabled = false;
969 }
970 }
971
972 switch (num_tile_pipes) {
973 case 1:
974 case 3:
975 case 5:
976 case 7:
977 DRM_ERROR("odd number of pipes!\n");
978 break;
979 case 2:
980 swizzle_pipe[0] = 0;
981 swizzle_pipe[1] = 1;
982 break;
983 case 4:
984 if (force_no_swizzle) {
985 swizzle_pipe[0] = 0;
986 swizzle_pipe[1] = 1;
987 swizzle_pipe[2] = 2;
988 swizzle_pipe[3] = 3;
989 } else {
990 swizzle_pipe[0] = 0;
991 swizzle_pipe[1] = 2;
992 swizzle_pipe[2] = 1;
993 swizzle_pipe[3] = 3;
994 }
995 break;
996 case 6:
997 if (force_no_swizzle) {
998 swizzle_pipe[0] = 0;
999 swizzle_pipe[1] = 1;
1000 swizzle_pipe[2] = 2;
1001 swizzle_pipe[3] = 3;
1002 swizzle_pipe[4] = 4;
1003 swizzle_pipe[5] = 5;
1004 } else {
1005 swizzle_pipe[0] = 0;
1006 swizzle_pipe[1] = 2;
1007 swizzle_pipe[2] = 4;
1008 swizzle_pipe[3] = 1;
1009 swizzle_pipe[4] = 3;
1010 swizzle_pipe[5] = 5;
1011 }
1012 break;
1013 case 8:
1014 if (force_no_swizzle) {
1015 swizzle_pipe[0] = 0;
1016 swizzle_pipe[1] = 1;
1017 swizzle_pipe[2] = 2;
1018 swizzle_pipe[3] = 3;
1019 swizzle_pipe[4] = 4;
1020 swizzle_pipe[5] = 5;
1021 swizzle_pipe[6] = 6;
1022 swizzle_pipe[7] = 7;
1023 } else {
1024 swizzle_pipe[0] = 0;
1025 swizzle_pipe[1] = 2;
1026 swizzle_pipe[2] = 4;
1027 swizzle_pipe[3] = 6;
1028 swizzle_pipe[4] = 1;
1029 swizzle_pipe[5] = 3;
1030 swizzle_pipe[6] = 5;
1031 swizzle_pipe[7] = 7;
1032 }
1033 break;
1034 }
1035
1036 for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
1037 while (((1 << cur_backend) & enabled_backends_mask) == 0)
1038 cur_backend = (cur_backend + 1) % SI_MAX_BACKENDS;
1039
1040 backend_map |= (((cur_backend & 0xf) << (swizzle_pipe[cur_pipe] * 4)));
1041
1042 cur_backend = (cur_backend + 1) % SI_MAX_BACKENDS;
1043 }
1044
1045 return backend_map;
1046 }
1047
1048 static u32 si_get_disable_mask_per_asic(struct radeon_device *rdev,
1049 u32 disable_mask_per_se,
1050 u32 max_disable_mask_per_se,
1051 u32 num_shader_engines)
1052 {
1053 u32 disable_field_width_per_se = r600_count_pipe_bits(disable_mask_per_se);
1054 u32 disable_mask_per_asic = disable_mask_per_se & max_disable_mask_per_se;
1055
1056 if (num_shader_engines == 1)
1057 return disable_mask_per_asic;
1058 else if (num_shader_engines == 2)
1059 return disable_mask_per_asic | (disable_mask_per_asic << disable_field_width_per_se);
1060 else
1061 return 0xffffffff;
1062 }
1063
1064 static void si_tiling_mode_table_init(struct radeon_device *rdev)
1065 {
1066 const u32 num_tile_mode_states = 32;
1067 u32 reg_offset, gb_tile_moden, split_equal_to_row_size;
1068
1069 switch (rdev->config.si.mem_row_size_in_kb) {
1070 case 1:
1071 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB;
1072 break;
1073 case 2:
1074 default:
1075 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB;
1076 break;
1077 case 4:
1078 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB;
1079 break;
1080 }
1081
1082 if ((rdev->family == CHIP_TAHITI) ||
1083 (rdev->family == CHIP_PITCAIRN)) {
1084 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
1085 switch (reg_offset) {
1086 case 0: /* non-AA compressed depth or any compressed stencil */
1087 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1088 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1089 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1090 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1091 NUM_BANKS(ADDR_SURF_16_BANK) |
1092 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1093 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1094 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1095 break;
1096 case 1: /* 2xAA/4xAA compressed depth only */
1097 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1098 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1099 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1100 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1101 NUM_BANKS(ADDR_SURF_16_BANK) |
1102 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1103 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1104 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1105 break;
1106 case 2: /* 8xAA compressed depth only */
1107 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1108 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1109 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1110 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1111 NUM_BANKS(ADDR_SURF_16_BANK) |
1112 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1113 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1114 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1115 break;
1116 case 3: /* 2xAA/4xAA compressed depth with stencil (for depth buffer) */
1117 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1118 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1119 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1120 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1121 NUM_BANKS(ADDR_SURF_16_BANK) |
1122 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1123 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1124 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1125 break;
1126 case 4: /* Maps w/ a dimension less than the 2D macro-tile dimensions (for mipmapped depth textures) */
1127 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1128 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1129 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1130 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1131 NUM_BANKS(ADDR_SURF_16_BANK) |
1132 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1133 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1134 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1135 break;
1136 case 5: /* Uncompressed 16bpp depth - and stencil buffer allocated with it */
1137 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1138 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1139 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1140 TILE_SPLIT(split_equal_to_row_size) |
1141 NUM_BANKS(ADDR_SURF_16_BANK) |
1142 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1143 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1144 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1145 break;
1146 case 6: /* Uncompressed 32bpp depth - and stencil buffer allocated with it */
1147 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1148 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1149 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1150 TILE_SPLIT(split_equal_to_row_size) |
1151 NUM_BANKS(ADDR_SURF_16_BANK) |
1152 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1153 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1154 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
1155 break;
1156 case 7: /* Uncompressed 8bpp stencil without depth (drivers typically do not use) */
1157 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1158 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1159 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1160 TILE_SPLIT(split_equal_to_row_size) |
1161 NUM_BANKS(ADDR_SURF_16_BANK) |
1162 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1163 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1164 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1165 break;
1166 case 8: /* 1D and 1D Array Surfaces */
1167 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1168 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1169 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1170 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1171 NUM_BANKS(ADDR_SURF_16_BANK) |
1172 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1173 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1174 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1175 break;
1176 case 9: /* Displayable maps. */
1177 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1178 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1179 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1180 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1181 NUM_BANKS(ADDR_SURF_16_BANK) |
1182 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1183 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1184 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1185 break;
1186 case 10: /* Display 8bpp. */
1187 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1188 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1189 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1190 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1191 NUM_BANKS(ADDR_SURF_16_BANK) |
1192 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1193 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1194 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1195 break;
1196 case 11: /* Display 16bpp. */
1197 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1198 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1199 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1200 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1201 NUM_BANKS(ADDR_SURF_16_BANK) |
1202 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1203 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1204 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1205 break;
1206 case 12: /* Display 32bpp. */
1207 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1208 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1209 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1210 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1211 NUM_BANKS(ADDR_SURF_16_BANK) |
1212 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1213 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1214 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
1215 break;
1216 case 13: /* Thin. */
1217 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1218 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1219 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1220 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1221 NUM_BANKS(ADDR_SURF_16_BANK) |
1222 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1223 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1224 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1225 break;
1226 case 14: /* Thin 8 bpp. */
1227 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1228 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1229 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1230 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1231 NUM_BANKS(ADDR_SURF_16_BANK) |
1232 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1233 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1234 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
1235 break;
1236 case 15: /* Thin 16 bpp. */
1237 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1238 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1239 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1240 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1241 NUM_BANKS(ADDR_SURF_16_BANK) |
1242 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1243 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1244 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
1245 break;
1246 case 16: /* Thin 32 bpp. */
1247 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1248 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1249 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1250 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1251 NUM_BANKS(ADDR_SURF_16_BANK) |
1252 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1253 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1254 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
1255 break;
1256 case 17: /* Thin 64 bpp. */
1257 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1258 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1259 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1260 TILE_SPLIT(split_equal_to_row_size) |
1261 NUM_BANKS(ADDR_SURF_16_BANK) |
1262 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1263 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1264 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
1265 break;
1266 case 21: /* 8 bpp PRT. */
1267 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1268 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1269 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1270 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1271 NUM_BANKS(ADDR_SURF_16_BANK) |
1272 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1273 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1274 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1275 break;
1276 case 22: /* 16 bpp PRT */
1277 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1278 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1279 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1280 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1281 NUM_BANKS(ADDR_SURF_16_BANK) |
1282 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1283 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1284 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
1285 break;
1286 case 23: /* 32 bpp PRT */
1287 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1288 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1289 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1290 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1291 NUM_BANKS(ADDR_SURF_16_BANK) |
1292 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1293 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1294 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1295 break;
1296 case 24: /* 64 bpp PRT */
1297 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1298 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1299 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1300 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1301 NUM_BANKS(ADDR_SURF_16_BANK) |
1302 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1303 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1304 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1305 break;
1306 case 25: /* 128 bpp PRT */
1307 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1308 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1309 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1310 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1311 NUM_BANKS(ADDR_SURF_8_BANK) |
1312 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1313 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1314 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
1315 break;
1316 default:
1317 gb_tile_moden = 0;
1318 break;
1319 }
1320 WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);
1321 }
1322 } else if (rdev->family == CHIP_VERDE) {
1323 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
1324 switch (reg_offset) {
1325 case 0: /* non-AA compressed depth or any compressed stencil */
1326 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1327 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1328 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1329 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1330 NUM_BANKS(ADDR_SURF_16_BANK) |
1331 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1332 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1333 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
1334 break;
1335 case 1: /* 2xAA/4xAA compressed depth only */
1336 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1337 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1338 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1339 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1340 NUM_BANKS(ADDR_SURF_16_BANK) |
1341 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1342 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1343 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
1344 break;
1345 case 2: /* 8xAA compressed depth only */
1346 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1347 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1348 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1349 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1350 NUM_BANKS(ADDR_SURF_16_BANK) |
1351 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1352 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1353 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
1354 break;
1355 case 3: /* 2xAA/4xAA compressed depth with stencil (for depth buffer) */
1356 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1357 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1358 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1359 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1360 NUM_BANKS(ADDR_SURF_16_BANK) |
1361 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1362 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1363 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
1364 break;
1365 case 4: /* Maps w/ a dimension less than the 2D macro-tile dimensions (for mipmapped depth textures) */
1366 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1367 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1368 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1369 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1370 NUM_BANKS(ADDR_SURF_16_BANK) |
1371 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1372 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1373 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1374 break;
1375 case 5: /* Uncompressed 16bpp depth - and stencil buffer allocated with it */
1376 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1377 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1378 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1379 TILE_SPLIT(split_equal_to_row_size) |
1380 NUM_BANKS(ADDR_SURF_16_BANK) |
1381 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1382 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1383 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1384 break;
1385 case 6: /* Uncompressed 32bpp depth - and stencil buffer allocated with it */
1386 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1387 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1388 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1389 TILE_SPLIT(split_equal_to_row_size) |
1390 NUM_BANKS(ADDR_SURF_16_BANK) |
1391 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1392 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1393 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1394 break;
1395 case 7: /* Uncompressed 8bpp stencil without depth (drivers typically do not use) */
1396 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1397 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1398 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1399 TILE_SPLIT(split_equal_to_row_size) |
1400 NUM_BANKS(ADDR_SURF_16_BANK) |
1401 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1402 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1403 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
1404 break;
1405 case 8: /* 1D and 1D Array Surfaces */
1406 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1407 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1408 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1409 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1410 NUM_BANKS(ADDR_SURF_16_BANK) |
1411 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1412 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1413 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1414 break;
1415 case 9: /* Displayable maps. */
1416 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1417 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1418 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1419 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1420 NUM_BANKS(ADDR_SURF_16_BANK) |
1421 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1422 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1423 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1424 break;
1425 case 10: /* Display 8bpp. */
1426 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1427 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1428 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1429 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1430 NUM_BANKS(ADDR_SURF_16_BANK) |
1431 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1432 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1433 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
1434 break;
1435 case 11: /* Display 16bpp. */
1436 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1437 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1438 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1439 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1440 NUM_BANKS(ADDR_SURF_16_BANK) |
1441 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1442 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1443 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1444 break;
1445 case 12: /* Display 32bpp. */
1446 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1447 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1448 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1449 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1450 NUM_BANKS(ADDR_SURF_16_BANK) |
1451 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1452 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1453 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1454 break;
1455 case 13: /* Thin. */
1456 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1457 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1458 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1459 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1460 NUM_BANKS(ADDR_SURF_16_BANK) |
1461 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1462 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1463 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1464 break;
1465 case 14: /* Thin 8 bpp. */
1466 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1467 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1468 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1469 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1470 NUM_BANKS(ADDR_SURF_16_BANK) |
1471 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1472 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1473 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1474 break;
1475 case 15: /* Thin 16 bpp. */
1476 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1477 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1478 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1479 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1480 NUM_BANKS(ADDR_SURF_16_BANK) |
1481 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1482 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1483 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1484 break;
1485 case 16: /* Thin 32 bpp. */
1486 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1487 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1488 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1489 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1490 NUM_BANKS(ADDR_SURF_16_BANK) |
1491 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1492 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1493 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1494 break;
1495 case 17: /* Thin 64 bpp. */
1496 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1497 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1498 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1499 TILE_SPLIT(split_equal_to_row_size) |
1500 NUM_BANKS(ADDR_SURF_16_BANK) |
1501 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1502 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1503 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1504 break;
1505 case 21: /* 8 bpp PRT. */
1506 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1507 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1508 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1509 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1510 NUM_BANKS(ADDR_SURF_16_BANK) |
1511 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1512 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1513 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1514 break;
1515 case 22: /* 16 bpp PRT */
1516 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1517 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1518 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1519 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1520 NUM_BANKS(ADDR_SURF_16_BANK) |
1521 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1522 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1523 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
1524 break;
1525 case 23: /* 32 bpp PRT */
1526 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1527 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1528 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1529 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1530 NUM_BANKS(ADDR_SURF_16_BANK) |
1531 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1532 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1533 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1534 break;
1535 case 24: /* 64 bpp PRT */
1536 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1537 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1538 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1539 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1540 NUM_BANKS(ADDR_SURF_16_BANK) |
1541 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1542 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1543 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1544 break;
1545 case 25: /* 128 bpp PRT */
1546 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1547 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1548 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1549 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1550 NUM_BANKS(ADDR_SURF_8_BANK) |
1551 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1552 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1553 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
1554 break;
1555 default:
1556 gb_tile_moden = 0;
1557 break;
1558 }
1559 WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);
1560 }
1561 } else
1562 DRM_ERROR("unknown asic: 0x%x\n", rdev->family);
1563 }
1564
1565 static void si_gpu_init(struct radeon_device *rdev)
1566 {
1567 u32 cc_rb_backend_disable = 0;
1568 u32 cc_gc_shader_array_config;
1569 u32 gb_addr_config = 0;
1570 u32 mc_shared_chmap, mc_arb_ramcfg;
1571 u32 gb_backend_map;
1572 u32 cgts_tcc_disable;
1573 u32 sx_debug_1;
1574 u32 gc_user_shader_array_config;
1575 u32 gc_user_rb_backend_disable;
1576 u32 cgts_user_tcc_disable;
1577 u32 hdp_host_path_cntl;
1578 u32 tmp;
1579 int i, j;
1580
1581 switch (rdev->family) {
1582 case CHIP_TAHITI:
1583 rdev->config.si.max_shader_engines = 2;
1584 rdev->config.si.max_pipes_per_simd = 4;
1585 rdev->config.si.max_tile_pipes = 12;
1586 rdev->config.si.max_simds_per_se = 8;
1587 rdev->config.si.max_backends_per_se = 4;
1588 rdev->config.si.max_texture_channel_caches = 12;
1589 rdev->config.si.max_gprs = 256;
1590 rdev->config.si.max_gs_threads = 32;
1591 rdev->config.si.max_hw_contexts = 8;
1592
1593 rdev->config.si.sc_prim_fifo_size_frontend = 0x20;
1594 rdev->config.si.sc_prim_fifo_size_backend = 0x100;
1595 rdev->config.si.sc_hiz_tile_fifo_size = 0x30;
1596 rdev->config.si.sc_earlyz_tile_fifo_size = 0x130;
1597 break;
1598 case CHIP_PITCAIRN:
1599 rdev->config.si.max_shader_engines = 2;
1600 rdev->config.si.max_pipes_per_simd = 4;
1601 rdev->config.si.max_tile_pipes = 8;
1602 rdev->config.si.max_simds_per_se = 5;
1603 rdev->config.si.max_backends_per_se = 4;
1604 rdev->config.si.max_texture_channel_caches = 8;
1605 rdev->config.si.max_gprs = 256;
1606 rdev->config.si.max_gs_threads = 32;
1607 rdev->config.si.max_hw_contexts = 8;
1608
1609 rdev->config.si.sc_prim_fifo_size_frontend = 0x20;
1610 rdev->config.si.sc_prim_fifo_size_backend = 0x100;
1611 rdev->config.si.sc_hiz_tile_fifo_size = 0x30;
1612 rdev->config.si.sc_earlyz_tile_fifo_size = 0x130;
1613 break;
1614 case CHIP_VERDE:
1615 default:
1616 rdev->config.si.max_shader_engines = 1;
1617 rdev->config.si.max_pipes_per_simd = 4;
1618 rdev->config.si.max_tile_pipes = 4;
1619 rdev->config.si.max_simds_per_se = 2;
1620 rdev->config.si.max_backends_per_se = 4;
1621 rdev->config.si.max_texture_channel_caches = 4;
1622 rdev->config.si.max_gprs = 256;
1623 rdev->config.si.max_gs_threads = 32;
1624 rdev->config.si.max_hw_contexts = 8;
1625
1626 rdev->config.si.sc_prim_fifo_size_frontend = 0x20;
1627 rdev->config.si.sc_prim_fifo_size_backend = 0x40;
1628 rdev->config.si.sc_hiz_tile_fifo_size = 0x30;
1629 rdev->config.si.sc_earlyz_tile_fifo_size = 0x130;
1630 break;
1631 }
1632
1633 /* Initialize HDP */
1634 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1635 WREG32((0x2c14 + j), 0x00000000);
1636 WREG32((0x2c18 + j), 0x00000000);
1637 WREG32((0x2c1c + j), 0x00000000);
1638 WREG32((0x2c20 + j), 0x00000000);
1639 WREG32((0x2c24 + j), 0x00000000);
1640 }
1641
1642 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1643
1644 evergreen_fix_pci_max_read_req_size(rdev);
1645
1646 WREG32(BIF_FB_EN, FB_READ_EN | FB_WRITE_EN);
1647
1648 mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
1649 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
1650
1651 cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE);
1652 cc_gc_shader_array_config = RREG32(CC_GC_SHADER_ARRAY_CONFIG);
1653 cgts_tcc_disable = 0xffff0000;
1654 for (i = 0; i < rdev->config.si.max_texture_channel_caches; i++)
1655 cgts_tcc_disable &= ~(1 << (16 + i));
1656 gc_user_rb_backend_disable = RREG32(GC_USER_RB_BACKEND_DISABLE);
1657 gc_user_shader_array_config = RREG32(GC_USER_SHADER_ARRAY_CONFIG);
1658 cgts_user_tcc_disable = RREG32(CGTS_USER_TCC_DISABLE);
1659
1660 rdev->config.si.num_shader_engines = rdev->config.si.max_shader_engines;
1661 rdev->config.si.num_tile_pipes = rdev->config.si.max_tile_pipes;
1662 tmp = ((~gc_user_rb_backend_disable) & BACKEND_DISABLE_MASK) >> BACKEND_DISABLE_SHIFT;
1663 rdev->config.si.num_backends_per_se = r600_count_pipe_bits(tmp);
1664 tmp = (gc_user_rb_backend_disable & BACKEND_DISABLE_MASK) >> BACKEND_DISABLE_SHIFT;
1665 rdev->config.si.backend_disable_mask_per_asic =
1666 si_get_disable_mask_per_asic(rdev, tmp, SI_MAX_BACKENDS_PER_SE_MASK,
1667 rdev->config.si.num_shader_engines);
1668 rdev->config.si.backend_map =
1669 si_get_tile_pipe_to_backend_map(rdev, rdev->config.si.num_tile_pipes,
1670 rdev->config.si.num_backends_per_se *
1671 rdev->config.si.num_shader_engines,
1672 &rdev->config.si.backend_disable_mask_per_asic,
1673 rdev->config.si.num_shader_engines);
1674 tmp = ((~cgts_user_tcc_disable) & TCC_DISABLE_MASK) >> TCC_DISABLE_SHIFT;
1675 rdev->config.si.num_texture_channel_caches = r600_count_pipe_bits(tmp);
1676 rdev->config.si.mem_max_burst_length_bytes = 256;
1677 tmp = (mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT;
1678 rdev->config.si.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
1679 if (rdev->config.si.mem_row_size_in_kb > 4)
1680 rdev->config.si.mem_row_size_in_kb = 4;
1681 /* XXX use MC settings? */
1682 rdev->config.si.shader_engine_tile_size = 32;
1683 rdev->config.si.num_gpus = 1;
1684 rdev->config.si.multi_gpu_tile_size = 64;
1685
1686 gb_addr_config = 0;
1687 switch (rdev->config.si.num_tile_pipes) {
1688 case 1:
1689 gb_addr_config |= NUM_PIPES(0);
1690 break;
1691 case 2:
1692 gb_addr_config |= NUM_PIPES(1);
1693 break;
1694 case 4:
1695 gb_addr_config |= NUM_PIPES(2);
1696 break;
1697 case 8:
1698 default:
1699 gb_addr_config |= NUM_PIPES(3);
1700 break;
1701 }
1702
1703 tmp = (rdev->config.si.mem_max_burst_length_bytes / 256) - 1;
1704 gb_addr_config |= PIPE_INTERLEAVE_SIZE(tmp);
1705 gb_addr_config |= NUM_SHADER_ENGINES(rdev->config.si.num_shader_engines - 1);
1706 tmp = (rdev->config.si.shader_engine_tile_size / 16) - 1;
1707 gb_addr_config |= SHADER_ENGINE_TILE_SIZE(tmp);
1708 switch (rdev->config.si.num_gpus) {
1709 case 1:
1710 default:
1711 gb_addr_config |= NUM_GPUS(0);
1712 break;
1713 case 2:
1714 gb_addr_config |= NUM_GPUS(1);
1715 break;
1716 case 4:
1717 gb_addr_config |= NUM_GPUS(2);
1718 break;
1719 }
1720 switch (rdev->config.si.multi_gpu_tile_size) {
1721 case 16:
1722 gb_addr_config |= MULTI_GPU_TILE_SIZE(0);
1723 break;
1724 case 32:
1725 default:
1726 gb_addr_config |= MULTI_GPU_TILE_SIZE(1);
1727 break;
1728 case 64:
1729 gb_addr_config |= MULTI_GPU_TILE_SIZE(2);
1730 break;
1731 case 128:
1732 gb_addr_config |= MULTI_GPU_TILE_SIZE(3);
1733 break;
1734 }
1735 switch (rdev->config.si.mem_row_size_in_kb) {
1736 case 1:
1737 default:
1738 gb_addr_config |= ROW_SIZE(0);
1739 break;
1740 case 2:
1741 gb_addr_config |= ROW_SIZE(1);
1742 break;
1743 case 4:
1744 gb_addr_config |= ROW_SIZE(2);
1745 break;
1746 }
1747
1748 tmp = (gb_addr_config & NUM_PIPES_MASK) >> NUM_PIPES_SHIFT;
1749 rdev->config.si.num_tile_pipes = (1 << tmp);
1750 tmp = (gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT;
1751 rdev->config.si.mem_max_burst_length_bytes = (tmp + 1) * 256;
1752 tmp = (gb_addr_config & NUM_SHADER_ENGINES_MASK) >> NUM_SHADER_ENGINES_SHIFT;
1753 rdev->config.si.num_shader_engines = tmp + 1;
1754 tmp = (gb_addr_config & NUM_GPUS_MASK) >> NUM_GPUS_SHIFT;
1755 rdev->config.si.num_gpus = tmp + 1;
1756 tmp = (gb_addr_config & MULTI_GPU_TILE_SIZE_MASK) >> MULTI_GPU_TILE_SIZE_SHIFT;
1757 rdev->config.si.multi_gpu_tile_size = 1 << tmp;
1758 tmp = (gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT;
1759 rdev->config.si.mem_row_size_in_kb = 1 << tmp;
1760
1761 gb_backend_map =
1762 si_get_tile_pipe_to_backend_map(rdev, rdev->config.si.num_tile_pipes,
1763 rdev->config.si.num_backends_per_se *
1764 rdev->config.si.num_shader_engines,
1765 &rdev->config.si.backend_disable_mask_per_asic,
1766 rdev->config.si.num_shader_engines);
1767
1768 /* setup tiling info dword. gb_addr_config is not adequate since it does
1769 * not have bank info, so create a custom tiling dword.
1770 * bits 3:0 num_pipes
1771 * bits 7:4 num_banks
1772 * bits 11:8 group_size
1773 * bits 15:12 row_size
1774 */
1775 rdev->config.si.tile_config = 0;
1776 switch (rdev->config.si.num_tile_pipes) {
1777 case 1:
1778 rdev->config.si.tile_config |= (0 << 0);
1779 break;
1780 case 2:
1781 rdev->config.si.tile_config |= (1 << 0);
1782 break;
1783 case 4:
1784 rdev->config.si.tile_config |= (2 << 0);
1785 break;
1786 case 8:
1787 default:
1788 /* XXX what about 12? */
1789 rdev->config.si.tile_config |= (3 << 0);
1790 break;
1791 }
1792 rdev->config.si.tile_config |=
1793 ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) << 4;
1794 rdev->config.si.tile_config |=
1795 ((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8;
1796 rdev->config.si.tile_config |=
1797 ((gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT) << 12;
1798
1799 rdev->config.si.backend_map = gb_backend_map;
1800 WREG32(GB_ADDR_CONFIG, gb_addr_config);
1801 WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
1802 WREG32(HDP_ADDR_CONFIG, gb_addr_config);
1803
1804 /* primary versions */
1805 WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);
1806 WREG32(CC_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable);
1807 WREG32(CC_GC_SHADER_ARRAY_CONFIG, cc_gc_shader_array_config);
1808
1809 WREG32(CGTS_TCC_DISABLE, cgts_tcc_disable);
1810
1811 /* user versions */
1812 WREG32(GC_USER_RB_BACKEND_DISABLE, cc_rb_backend_disable);
1813 WREG32(GC_USER_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable);
1814 WREG32(GC_USER_SHADER_ARRAY_CONFIG, cc_gc_shader_array_config);
1815
1816 WREG32(CGTS_USER_TCC_DISABLE, cgts_tcc_disable);
1817
1818 si_tiling_mode_table_init(rdev);
1819
1820 /* set HW defaults for 3D engine */
1821 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
1822 ROQ_IB2_START(0x2b)));
1823 WREG32(CP_MEQ_THRESHOLDS, MEQ1_START(0x30) | MEQ2_START(0x60));
1824
1825 sx_debug_1 = RREG32(SX_DEBUG_1);
1826 WREG32(SX_DEBUG_1, sx_debug_1);
1827
1828 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
1829
1830 WREG32(PA_SC_FIFO_SIZE, (SC_FRONTEND_PRIM_FIFO_SIZE(rdev->config.si.sc_prim_fifo_size_frontend) |
1831 SC_BACKEND_PRIM_FIFO_SIZE(rdev->config.si.sc_prim_fifo_size_backend) |
1832 SC_HIZ_TILE_FIFO_SIZE(rdev->config.si.sc_hiz_tile_fifo_size) |
1833 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.si.sc_earlyz_tile_fifo_size)));
1834
1835 WREG32(VGT_NUM_INSTANCES, 1);
1836
1837 WREG32(CP_PERFMON_CNTL, 0);
1838
1839 WREG32(SQ_CONFIG, 0);
1840
1841 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
1842 FORCE_EOV_MAX_REZ_CNT(255)));
1843
1844 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC) |
1845 AUTO_INVLD_EN(ES_AND_GS_AUTO));
1846
1847 WREG32(VGT_GS_VERTEX_REUSE, 16);
1848 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
1849
1850 WREG32(CB_PERFCOUNTER0_SELECT0, 0);
1851 WREG32(CB_PERFCOUNTER0_SELECT1, 0);
1852 WREG32(CB_PERFCOUNTER1_SELECT0, 0);
1853 WREG32(CB_PERFCOUNTER1_SELECT1, 0);
1854 WREG32(CB_PERFCOUNTER2_SELECT0, 0);
1855 WREG32(CB_PERFCOUNTER2_SELECT1, 0);
1856 WREG32(CB_PERFCOUNTER3_SELECT0, 0);
1857 WREG32(CB_PERFCOUNTER3_SELECT1, 0);
1858
1859 tmp = RREG32(HDP_MISC_CNTL);
1860 tmp |= HDP_FLUSH_INVALIDATE_CACHE;
1861 WREG32(HDP_MISC_CNTL, tmp);
1862
1863 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
1864 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
1865
1866 WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
1867
1868 udelay(50);
1869 }
1870
1871 /*
1872 * GPU scratch registers helpers function.
1873 */
1874 static void si_scratch_init(struct radeon_device *rdev)
1875 {
1876 int i;
1877
1878 rdev->scratch.num_reg = 7;
1879 rdev->scratch.reg_base = SCRATCH_REG0;
1880 for (i = 0; i < rdev->scratch.num_reg; i++) {
1881 rdev->scratch.free[i] = true;
1882 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
1883 }
1884 }
1885
1886 void si_fence_ring_emit(struct radeon_device *rdev,
1887 struct radeon_fence *fence)
1888 {
1889 struct radeon_ring *ring = &rdev->ring[fence->ring];
1890 u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
1891
1892 /* flush read cache over gart */
1893 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1894 radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2);
1895 radeon_ring_write(ring, 0);
1896 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
1897 radeon_ring_write(ring, PACKET3_TCL1_ACTION_ENA |
1898 PACKET3_TC_ACTION_ENA |
1899 PACKET3_SH_KCACHE_ACTION_ENA |
1900 PACKET3_SH_ICACHE_ACTION_ENA);
1901 radeon_ring_write(ring, 0xFFFFFFFF);
1902 radeon_ring_write(ring, 0);
1903 radeon_ring_write(ring, 10); /* poll interval */
1904 /* EVENT_WRITE_EOP - flush caches, send int */
1905 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
1906 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5));
1907 radeon_ring_write(ring, addr & 0xffffffff);
1908 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2));
1909 radeon_ring_write(ring, fence->seq);
1910 radeon_ring_write(ring, 0);
1911 }
1912
1913 /*
1914 * IB stuff
1915 */
1916 void si_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
1917 {
1918 struct radeon_ring *ring = &rdev->ring[ib->fence->ring];
1919 u32 header;
1920
1921 if (ib->is_const_ib)
1922 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
1923 else
1924 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
1925
1926 radeon_ring_write(ring, header);
1927 radeon_ring_write(ring,
1928 #ifdef __BIG_ENDIAN
1929 (2 << 0) |
1930 #endif
1931 (ib->gpu_addr & 0xFFFFFFFC));
1932 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
1933 radeon_ring_write(ring, ib->length_dw | (ib->vm_id << 24));
1934
1935 /* flush read cache over gart for this vmid */
1936 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1937 radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2);
1938 radeon_ring_write(ring, ib->vm_id);
1939 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
1940 radeon_ring_write(ring, PACKET3_TCL1_ACTION_ENA |
1941 PACKET3_TC_ACTION_ENA |
1942 PACKET3_SH_KCACHE_ACTION_ENA |
1943 PACKET3_SH_ICACHE_ACTION_ENA);
1944 radeon_ring_write(ring, 0xFFFFFFFF);
1945 radeon_ring_write(ring, 0);
1946 radeon_ring_write(ring, 10); /* poll interval */
1947 }
1948
1949 /*
1950 * CP.
1951 */
1952 static void si_cp_enable(struct radeon_device *rdev, bool enable)
1953 {
1954 if (enable)
1955 WREG32(CP_ME_CNTL, 0);
1956 else {
1957 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
1958 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT));
1959 WREG32(SCRATCH_UMSK, 0);
1960 }
1961 udelay(50);
1962 }
1963
1964 static int si_cp_load_microcode(struct radeon_device *rdev)
1965 {
1966 const __be32 *fw_data;
1967 int i;
1968
1969 if (!rdev->me_fw || !rdev->pfp_fw)
1970 return -EINVAL;
1971
1972 si_cp_enable(rdev, false);
1973
1974 /* PFP */
1975 fw_data = (const __be32 *)rdev->pfp_fw->data;
1976 WREG32(CP_PFP_UCODE_ADDR, 0);
1977 for (i = 0; i < SI_PFP_UCODE_SIZE; i++)
1978 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
1979 WREG32(CP_PFP_UCODE_ADDR, 0);
1980
1981 /* CE */
1982 fw_data = (const __be32 *)rdev->ce_fw->data;
1983 WREG32(CP_CE_UCODE_ADDR, 0);
1984 for (i = 0; i < SI_CE_UCODE_SIZE; i++)
1985 WREG32(CP_CE_UCODE_DATA, be32_to_cpup(fw_data++));
1986 WREG32(CP_CE_UCODE_ADDR, 0);
1987
1988 /* ME */
1989 fw_data = (const __be32 *)rdev->me_fw->data;
1990 WREG32(CP_ME_RAM_WADDR, 0);
1991 for (i = 0; i < SI_PM4_UCODE_SIZE; i++)
1992 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
1993 WREG32(CP_ME_RAM_WADDR, 0);
1994
1995 WREG32(CP_PFP_UCODE_ADDR, 0);
1996 WREG32(CP_CE_UCODE_ADDR, 0);
1997 WREG32(CP_ME_RAM_WADDR, 0);
1998 WREG32(CP_ME_RAM_RADDR, 0);
1999 return 0;
2000 }
2001
2002 static int si_cp_start(struct radeon_device *rdev)
2003 {
2004 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2005 int r, i;
2006
2007 r = radeon_ring_lock(rdev, ring, 7 + 4);
2008 if (r) {
2009 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
2010 return r;
2011 }
2012 /* init the CP */
2013 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
2014 radeon_ring_write(ring, 0x1);
2015 radeon_ring_write(ring, 0x0);
2016 radeon_ring_write(ring, rdev->config.si.max_hw_contexts - 1);
2017 radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
2018 radeon_ring_write(ring, 0);
2019 radeon_ring_write(ring, 0);
2020
2021 /* init the CE partitions */
2022 radeon_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
2023 radeon_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
2024 radeon_ring_write(ring, 0xc000);
2025 radeon_ring_write(ring, 0xe000);
2026 radeon_ring_unlock_commit(rdev, ring);
2027
2028 si_cp_enable(rdev, true);
2029
2030 r = radeon_ring_lock(rdev, ring, si_default_size + 10);
2031 if (r) {
2032 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
2033 return r;
2034 }
2035
2036 /* setup clear context state */
2037 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2038 radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
2039
2040 for (i = 0; i < si_default_size; i++)
2041 radeon_ring_write(ring, si_default_state[i]);
2042
2043 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2044 radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
2045
2046 /* set clear context state */
2047 radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
2048 radeon_ring_write(ring, 0);
2049
2050 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
2051 radeon_ring_write(ring, 0x00000316);
2052 radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
2053 radeon_ring_write(ring, 0x00000010); /* VGT_OUT_DEALLOC_CNTL */
2054
2055 radeon_ring_unlock_commit(rdev, ring);
2056
2057 for (i = RADEON_RING_TYPE_GFX_INDEX; i <= CAYMAN_RING_TYPE_CP2_INDEX; ++i) {
2058 ring = &rdev->ring[i];
2059 r = radeon_ring_lock(rdev, ring, 2);
2060
2061 /* clear the compute context state */
2062 radeon_ring_write(ring, PACKET3_COMPUTE(PACKET3_CLEAR_STATE, 0));
2063 radeon_ring_write(ring, 0);
2064
2065 radeon_ring_unlock_commit(rdev, ring);
2066 }
2067
2068 return 0;
2069 }
2070
2071 static void si_cp_fini(struct radeon_device *rdev)
2072 {
2073 si_cp_enable(rdev, false);
2074 radeon_ring_fini(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
2075 radeon_ring_fini(rdev, &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX]);
2076 radeon_ring_fini(rdev, &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX]);
2077 }
2078
2079 static int si_cp_resume(struct radeon_device *rdev)
2080 {
2081 struct radeon_ring *ring;
2082 u32 tmp;
2083 u32 rb_bufsz;
2084 int r;
2085
2086 /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */
2087 WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP |
2088 SOFT_RESET_PA |
2089 SOFT_RESET_VGT |
2090 SOFT_RESET_SPI |
2091 SOFT_RESET_SX));
2092 RREG32(GRBM_SOFT_RESET);
2093 mdelay(15);
2094 WREG32(GRBM_SOFT_RESET, 0);
2095 RREG32(GRBM_SOFT_RESET);
2096
2097 WREG32(CP_SEM_WAIT_TIMER, 0x0);
2098 WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
2099
2100 /* Set the write pointer delay */
2101 WREG32(CP_RB_WPTR_DELAY, 0);
2102
2103 WREG32(CP_DEBUG, 0);
2104 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
2105
2106 /* ring 0 - compute and gfx */
2107 /* Set ring buffer size */
2108 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2109 rb_bufsz = drm_order(ring->ring_size / 8);
2110 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2111 #ifdef __BIG_ENDIAN
2112 tmp |= BUF_SWAP_32BIT;
2113 #endif
2114 WREG32(CP_RB0_CNTL, tmp);
2115
2116 /* Initialize the ring buffer's read and write pointers */
2117 WREG32(CP_RB0_CNTL, tmp | RB_RPTR_WR_ENA);
2118 ring->wptr = 0;
2119 WREG32(CP_RB0_WPTR, ring->wptr);
2120
2121 /* set the wb address wether it's enabled or not */
2122 WREG32(CP_RB0_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC);
2123 WREG32(CP_RB0_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
2124
2125 if (rdev->wb.enabled)
2126 WREG32(SCRATCH_UMSK, 0xff);
2127 else {
2128 tmp |= RB_NO_UPDATE;
2129 WREG32(SCRATCH_UMSK, 0);
2130 }
2131
2132 mdelay(1);
2133 WREG32(CP_RB0_CNTL, tmp);
2134
2135 WREG32(CP_RB0_BASE, ring->gpu_addr >> 8);
2136
2137 ring->rptr = RREG32(CP_RB0_RPTR);
2138
2139 /* ring1 - compute only */
2140 /* Set ring buffer size */
2141 ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX];
2142 rb_bufsz = drm_order(ring->ring_size / 8);
2143 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2144 #ifdef __BIG_ENDIAN
2145 tmp |= BUF_SWAP_32BIT;
2146 #endif
2147 WREG32(CP_RB1_CNTL, tmp);
2148
2149 /* Initialize the ring buffer's read and write pointers */
2150 WREG32(CP_RB1_CNTL, tmp | RB_RPTR_WR_ENA);
2151 ring->wptr = 0;
2152 WREG32(CP_RB1_WPTR, ring->wptr);
2153
2154 /* set the wb address wether it's enabled or not */
2155 WREG32(CP_RB1_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFFFFFFFC);
2156 WREG32(CP_RB1_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFF);
2157
2158 mdelay(1);
2159 WREG32(CP_RB1_CNTL, tmp);
2160
2161 WREG32(CP_RB1_BASE, ring->gpu_addr >> 8);
2162
2163 ring->rptr = RREG32(CP_RB1_RPTR);
2164
2165 /* ring2 - compute only */
2166 /* Set ring buffer size */
2167 ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX];
2168 rb_bufsz = drm_order(ring->ring_size / 8);
2169 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2170 #ifdef __BIG_ENDIAN
2171 tmp |= BUF_SWAP_32BIT;
2172 #endif
2173 WREG32(CP_RB2_CNTL, tmp);
2174
2175 /* Initialize the ring buffer's read and write pointers */
2176 WREG32(CP_RB2_CNTL, tmp | RB_RPTR_WR_ENA);
2177 ring->wptr = 0;
2178 WREG32(CP_RB2_WPTR, ring->wptr);
2179
2180 /* set the wb address wether it's enabled or not */
2181 WREG32(CP_RB2_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFFFFFFFC);
2182 WREG32(CP_RB2_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFF);
2183
2184 mdelay(1);
2185 WREG32(CP_RB2_CNTL, tmp);
2186
2187 WREG32(CP_RB2_BASE, ring->gpu_addr >> 8);
2188
2189 ring->rptr = RREG32(CP_RB2_RPTR);
2190
2191 /* start the rings */
2192 si_cp_start(rdev);
2193 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = true;
2194 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = true;
2195 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = true;
2196 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
2197 if (r) {
2198 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
2199 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
2200 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
2201 return r;
2202 }
2203 r = radeon_ring_test(rdev, CAYMAN_RING_TYPE_CP1_INDEX, &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX]);
2204 if (r) {
2205 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
2206 }
2207 r = radeon_ring_test(rdev, CAYMAN_RING_TYPE_CP2_INDEX, &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX]);
2208 if (r) {
2209 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
2210 }
2211
2212 return 0;
2213 }
2214
2215 bool si_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
2216 {
2217 u32 srbm_status;
2218 u32 grbm_status, grbm_status2;
2219 u32 grbm_status_se0, grbm_status_se1;
2220
2221 srbm_status = RREG32(SRBM_STATUS);
2222 grbm_status = RREG32(GRBM_STATUS);
2223 grbm_status2 = RREG32(GRBM_STATUS2);
2224 grbm_status_se0 = RREG32(GRBM_STATUS_SE0);
2225 grbm_status_se1 = RREG32(GRBM_STATUS_SE1);
2226 if (!(grbm_status & GUI_ACTIVE)) {
2227 radeon_ring_lockup_update(ring);
2228 return false;
2229 }
2230 /* force CP activities */
2231 radeon_ring_force_activity(rdev, ring);
2232 return radeon_ring_test_lockup(rdev, ring);
2233 }
2234
2235 static int si_gpu_soft_reset(struct radeon_device *rdev)
2236 {
2237 struct evergreen_mc_save save;
2238 u32 grbm_reset = 0;
2239
2240 if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))
2241 return 0;
2242
2243 dev_info(rdev->dev, "GPU softreset \n");
2244 dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n",
2245 RREG32(GRBM_STATUS));
2246 dev_info(rdev->dev, " GRBM_STATUS2=0x%08X\n",
2247 RREG32(GRBM_STATUS2));
2248 dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n",
2249 RREG32(GRBM_STATUS_SE0));
2250 dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n",
2251 RREG32(GRBM_STATUS_SE1));
2252 dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n",
2253 RREG32(SRBM_STATUS));
2254 evergreen_mc_stop(rdev, &save);
2255 if (radeon_mc_wait_for_idle(rdev)) {
2256 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
2257 }
2258 /* Disable CP parsing/prefetching */
2259 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT);
2260
2261 /* reset all the gfx blocks */
2262 grbm_reset = (SOFT_RESET_CP |
2263 SOFT_RESET_CB |
2264 SOFT_RESET_DB |
2265 SOFT_RESET_GDS |
2266 SOFT_RESET_PA |
2267 SOFT_RESET_SC |
2268 SOFT_RESET_SPI |
2269 SOFT_RESET_SX |
2270 SOFT_RESET_TC |
2271 SOFT_RESET_TA |
2272 SOFT_RESET_VGT |
2273 SOFT_RESET_IA);
2274
2275 dev_info(rdev->dev, " GRBM_SOFT_RESET=0x%08X\n", grbm_reset);
2276 WREG32(GRBM_SOFT_RESET, grbm_reset);
2277 (void)RREG32(GRBM_SOFT_RESET);
2278 udelay(50);
2279 WREG32(GRBM_SOFT_RESET, 0);
2280 (void)RREG32(GRBM_SOFT_RESET);
2281 /* Wait a little for things to settle down */
2282 udelay(50);
2283 dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n",
2284 RREG32(GRBM_STATUS));
2285 dev_info(rdev->dev, " GRBM_STATUS2=0x%08X\n",
2286 RREG32(GRBM_STATUS2));
2287 dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n",
2288 RREG32(GRBM_STATUS_SE0));
2289 dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n",
2290 RREG32(GRBM_STATUS_SE1));
2291 dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n",
2292 RREG32(SRBM_STATUS));
2293 evergreen_mc_resume(rdev, &save);
2294 return 0;
2295 }
2296
2297 int si_asic_reset(struct radeon_device *rdev)
2298 {
2299 return si_gpu_soft_reset(rdev);
2300 }
2301
2302 /* MC */
2303 static void si_mc_program(struct radeon_device *rdev)
2304 {
2305 struct evergreen_mc_save save;
2306 u32 tmp;
2307 int i, j;
2308
2309 /* Initialize HDP */
2310 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
2311 WREG32((0x2c14 + j), 0x00000000);
2312 WREG32((0x2c18 + j), 0x00000000);
2313 WREG32((0x2c1c + j), 0x00000000);
2314 WREG32((0x2c20 + j), 0x00000000);
2315 WREG32((0x2c24 + j), 0x00000000);
2316 }
2317 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
2318
2319 evergreen_mc_stop(rdev, &save);
2320 if (radeon_mc_wait_for_idle(rdev)) {
2321 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
2322 }
2323 /* Lockout access through VGA aperture*/
2324 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
2325 /* Update configuration */
2326 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
2327 rdev->mc.vram_start >> 12);
2328 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
2329 rdev->mc.vram_end >> 12);
2330 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
2331 rdev->vram_scratch.gpu_addr >> 12);
2332 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
2333 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
2334 WREG32(MC_VM_FB_LOCATION, tmp);
2335 /* XXX double check these! */
2336 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
2337 WREG32(HDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
2338 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
2339 WREG32(MC_VM_AGP_BASE, 0);
2340 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
2341 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
2342 if (radeon_mc_wait_for_idle(rdev)) {
2343 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
2344 }
2345 evergreen_mc_resume(rdev, &save);
2346 /* we need to own VRAM, so turn off the VGA renderer here
2347 * to stop it overwriting our objects */
2348 rv515_vga_render_disable(rdev);
2349 }
2350
2351 /* SI MC address space is 40 bits */
2352 static void si_vram_location(struct radeon_device *rdev,
2353 struct radeon_mc *mc, u64 base)
2354 {
2355 mc->vram_start = base;
2356 if (mc->mc_vram_size > (0xFFFFFFFFFFULL - base + 1)) {
2357 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
2358 mc->real_vram_size = mc->aper_size;
2359 mc->mc_vram_size = mc->aper_size;
2360 }
2361 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
2362 dev_info(rdev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",
2363 mc->mc_vram_size >> 20, mc->vram_start,
2364 mc->vram_end, mc->real_vram_size >> 20);
2365 }
2366
2367 static void si_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
2368 {
2369 u64 size_af, size_bf;
2370
2371 size_af = ((0xFFFFFFFFFFULL - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align;
2372 size_bf = mc->vram_start & ~mc->gtt_base_align;
2373 if (size_bf > size_af) {
2374 if (mc->gtt_size > size_bf) {
2375 dev_warn(rdev->dev, "limiting GTT\n");
2376 mc->gtt_size = size_bf;
2377 }
2378 mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - mc->gtt_size;
2379 } else {
2380 if (mc->gtt_size > size_af) {
2381 dev_warn(rdev->dev, "limiting GTT\n");
2382 mc->gtt_size = size_af;
2383 }
2384 mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align;
2385 }
2386 mc->gtt_end = mc->gtt_start + mc->gtt_size - 1;
2387 dev_info(rdev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n",
2388 mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end);
2389 }
2390
2391 static void si_vram_gtt_location(struct radeon_device *rdev,
2392 struct radeon_mc *mc)
2393 {
2394 if (mc->mc_vram_size > 0xFFC0000000ULL) {
2395 /* leave room for at least 1024M GTT */
2396 dev_warn(rdev->dev, "limiting VRAM\n");
2397 mc->real_vram_size = 0xFFC0000000ULL;
2398 mc->mc_vram_size = 0xFFC0000000ULL;
2399 }
2400 si_vram_location(rdev, &rdev->mc, 0);
2401 rdev->mc.gtt_base_align = 0;
2402 si_gtt_location(rdev, mc);
2403 }
2404
2405 static int si_mc_init(struct radeon_device *rdev)
2406 {
2407 u32 tmp;
2408 int chansize, numchan;
2409
2410 /* Get VRAM informations */
2411 rdev->mc.vram_is_ddr = true;
2412 tmp = RREG32(MC_ARB_RAMCFG);
2413 if (tmp & CHANSIZE_OVERRIDE) {
2414 chansize = 16;
2415 } else if (tmp & CHANSIZE_MASK) {
2416 chansize = 64;
2417 } else {
2418 chansize = 32;
2419 }
2420 tmp = RREG32(MC_SHARED_CHMAP);
2421 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
2422 case 0:
2423 default:
2424 numchan = 1;
2425 break;
2426 case 1:
2427 numchan = 2;
2428 break;
2429 case 2:
2430 numchan = 4;
2431 break;
2432 case 3:
2433 numchan = 8;
2434 break;
2435 case 4:
2436 numchan = 3;
2437 break;
2438 case 5:
2439 numchan = 6;
2440 break;
2441 case 6:
2442 numchan = 10;
2443 break;
2444 case 7:
2445 numchan = 12;
2446 break;
2447 case 8:
2448 numchan = 16;
2449 break;
2450 }
2451 rdev->mc.vram_width = numchan * chansize;
2452 /* Could aper size report 0 ? */
2453 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
2454 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
2455 /* size in MB on si */
2456 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
2457 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
2458 rdev->mc.visible_vram_size = rdev->mc.aper_size;
2459 si_vram_gtt_location(rdev, &rdev->mc);
2460 radeon_update_bandwidth_info(rdev);
2461
2462 return 0;
2463 }
2464
2465 /*
2466 * GART
2467 */
2468 void si_pcie_gart_tlb_flush(struct radeon_device *rdev)
2469 {
2470 /* flush hdp cache */
2471 WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
2472
2473 /* bits 0-15 are the VM contexts0-15 */
2474 WREG32(VM_INVALIDATE_REQUEST, 1);
2475 }
2476
2477 int si_pcie_gart_enable(struct radeon_device *rdev)
2478 {
2479 int r, i;
2480
2481 if (rdev->gart.robj == NULL) {
2482 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
2483 return -EINVAL;
2484 }
2485 r = radeon_gart_table_vram_pin(rdev);
2486 if (r)
2487 return r;
2488 radeon_gart_restore(rdev);
2489 /* Setup TLB control */
2490 WREG32(MC_VM_MX_L1_TLB_CNTL,
2491 (0xA << 7) |
2492 ENABLE_L1_TLB |
2493 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
2494 ENABLE_ADVANCED_DRIVER_MODEL |
2495 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU);
2496 /* Setup L2 cache */
2497 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE |
2498 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
2499 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE |
2500 EFFECTIVE_L2_QUEUE_SIZE(7) |
2501 CONTEXT1_IDENTITY_ACCESS_MODE(1));
2502 WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE);
2503 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
2504 L2_CACHE_BIGK_FRAGMENT_SIZE(0));
2505 /* setup context0 */
2506 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
2507 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
2508 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
2509 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
2510 (u32)(rdev->dummy_page.addr >> 12));
2511 WREG32(VM_CONTEXT0_CNTL2, 0);
2512 WREG32(VM_CONTEXT0_CNTL, (ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
2513 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT));
2514
2515 WREG32(0x15D4, 0);
2516 WREG32(0x15D8, 0);
2517 WREG32(0x15DC, 0);
2518
2519 /* empty context1-15 */
2520 /* FIXME start with 1G, once using 2 level pt switch to full
2521 * vm size space
2522 */
2523 /* set vm size, must be a multiple of 4 */
2524 WREG32(VM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
2525 WREG32(VM_CONTEXT1_PAGE_TABLE_END_ADDR, (1 << 30) / RADEON_GPU_PAGE_SIZE);
2526 for (i = 1; i < 16; i++) {
2527 if (i < 8)
2528 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2),
2529 rdev->gart.table_addr >> 12);
2530 else
2531 WREG32(VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((i - 8) << 2),
2532 rdev->gart.table_addr >> 12);
2533 }
2534
2535 /* enable context1-15 */
2536 WREG32(VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
2537 (u32)(rdev->dummy_page.addr >> 12));
2538 WREG32(VM_CONTEXT1_CNTL2, 0);
2539 WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
2540 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
2541
2542 si_pcie_gart_tlb_flush(rdev);
2543 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
2544 (unsigned)(rdev->mc.gtt_size >> 20),
2545 (unsigned long long)rdev->gart.table_addr);
2546 rdev->gart.ready = true;
2547 return 0;
2548 }
2549
2550 void si_pcie_gart_disable(struct radeon_device *rdev)
2551 {
2552 /* Disable all tables */
2553 WREG32(VM_CONTEXT0_CNTL, 0);
2554 WREG32(VM_CONTEXT1_CNTL, 0);
2555 /* Setup TLB control */
2556 WREG32(MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE_NOT_IN_SYS |
2557 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU);
2558 /* Setup L2 cache */
2559 WREG32(VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
2560 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE |
2561 EFFECTIVE_L2_QUEUE_SIZE(7) |
2562 CONTEXT1_IDENTITY_ACCESS_MODE(1));
2563 WREG32(VM_L2_CNTL2, 0);
2564 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
2565 L2_CACHE_BIGK_FRAGMENT_SIZE(0));
2566 radeon_gart_table_vram_unpin(rdev);
2567 }
2568
2569 void si_pcie_gart_fini(struct radeon_device *rdev)
2570 {
2571 si_pcie_gart_disable(rdev);
2572 radeon_gart_table_vram_free(rdev);
2573 radeon_gart_fini(rdev);
2574 }
2575
2576 /* vm parser */
2577 static bool si_vm_reg_valid(u32 reg)
2578 {
2579 /* context regs are fine */
2580 if (reg >= 0x28000)
2581 return true;
2582
2583 /* check config regs */
2584 switch (reg) {
2585 case GRBM_GFX_INDEX:
2586 case VGT_VTX_VECT_EJECT_REG:
2587 case VGT_CACHE_INVALIDATION:
2588 case VGT_ESGS_RING_SIZE:
2589 case VGT_GSVS_RING_SIZE:
2590 case VGT_GS_VERTEX_REUSE:
2591 case VGT_PRIMITIVE_TYPE:
2592 case VGT_INDEX_TYPE:
2593 case VGT_NUM_INDICES:
2594 case VGT_NUM_INSTANCES:
2595 case VGT_TF_RING_SIZE:
2596 case VGT_HS_OFFCHIP_PARAM:
2597 case VGT_TF_MEMORY_BASE:
2598 case PA_CL_ENHANCE:
2599 case PA_SU_LINE_STIPPLE_VALUE:
2600 case PA_SC_LINE_STIPPLE_STATE:
2601 case PA_SC_ENHANCE:
2602 case SQC_CACHES:
2603 case SPI_STATIC_THREAD_MGMT_1:
2604 case SPI_STATIC_THREAD_MGMT_2:
2605 case SPI_STATIC_THREAD_MGMT_3:
2606 case SPI_PS_MAX_WAVE_ID:
2607 case SPI_CONFIG_CNTL:
2608 case SPI_CONFIG_CNTL_1:
2609 case TA_CNTL_AUX:
2610 return true;
2611 default:
2612 DRM_ERROR("Invalid register 0x%x in CS\n", reg);
2613 return false;
2614 }
2615 }
2616
2617 static int si_vm_packet3_ce_check(struct radeon_device *rdev,
2618 u32 *ib, struct radeon_cs_packet *pkt)
2619 {
2620 switch (pkt->opcode) {
2621 case PACKET3_NOP:
2622 case PACKET3_SET_BASE:
2623 case PACKET3_SET_CE_DE_COUNTERS:
2624 case PACKET3_LOAD_CONST_RAM:
2625 case PACKET3_WRITE_CONST_RAM:
2626 case PACKET3_WRITE_CONST_RAM_OFFSET:
2627 case PACKET3_DUMP_CONST_RAM:
2628 case PACKET3_INCREMENT_CE_COUNTER:
2629 case PACKET3_WAIT_ON_DE_COUNTER:
2630 case PACKET3_CE_WRITE:
2631 break;
2632 default:
2633 DRM_ERROR("Invalid CE packet3: 0x%x\n", pkt->opcode);
2634 return -EINVAL;
2635 }
2636 return 0;
2637 }
2638
2639 static int si_vm_packet3_gfx_check(struct radeon_device *rdev,
2640 u32 *ib, struct radeon_cs_packet *pkt)
2641 {
2642 u32 idx = pkt->idx + 1;
2643 u32 idx_value = ib[idx];
2644 u32 start_reg, end_reg, reg, i;
2645
2646 switch (pkt->opcode) {
2647 case PACKET3_NOP:
2648 case PACKET3_SET_BASE:
2649 case PACKET3_CLEAR_STATE:
2650 case PACKET3_INDEX_BUFFER_SIZE:
2651 case PACKET3_DISPATCH_DIRECT:
2652 case PACKET3_DISPATCH_INDIRECT:
2653 case PACKET3_ALLOC_GDS:
2654 case PACKET3_WRITE_GDS_RAM:
2655 case PACKET3_ATOMIC_GDS:
2656 case PACKET3_ATOMIC:
2657 case PACKET3_OCCLUSION_QUERY:
2658 case PACKET3_SET_PREDICATION:
2659 case PACKET3_COND_EXEC:
2660 case PACKET3_PRED_EXEC:
2661 case PACKET3_DRAW_INDIRECT:
2662 case PACKET3_DRAW_INDEX_INDIRECT:
2663 case PACKET3_INDEX_BASE:
2664 case PACKET3_DRAW_INDEX_2:
2665 case PACKET3_CONTEXT_CONTROL:
2666 case PACKET3_INDEX_TYPE:
2667 case PACKET3_DRAW_INDIRECT_MULTI:
2668 case PACKET3_DRAW_INDEX_AUTO:
2669 case PACKET3_DRAW_INDEX_IMMD:
2670 case PACKET3_NUM_INSTANCES:
2671 case PACKET3_DRAW_INDEX_MULTI_AUTO:
2672 case PACKET3_STRMOUT_BUFFER_UPDATE:
2673 case PACKET3_DRAW_INDEX_OFFSET_2:
2674 case PACKET3_DRAW_INDEX_MULTI_ELEMENT:
2675 case PACKET3_DRAW_INDEX_INDIRECT_MULTI:
2676 case PACKET3_MPEG_INDEX:
2677 case PACKET3_WAIT_REG_MEM:
2678 case PACKET3_MEM_WRITE:
2679 case PACKET3_PFP_SYNC_ME:
2680 case PACKET3_SURFACE_SYNC:
2681 case PACKET3_EVENT_WRITE:
2682 case PACKET3_EVENT_WRITE_EOP:
2683 case PACKET3_EVENT_WRITE_EOS:
2684 case PACKET3_SET_CONTEXT_REG:
2685 case PACKET3_SET_CONTEXT_REG_INDIRECT:
2686 case PACKET3_SET_SH_REG:
2687 case PACKET3_SET_SH_REG_OFFSET:
2688 case PACKET3_INCREMENT_DE_COUNTER:
2689 case PACKET3_WAIT_ON_CE_COUNTER:
2690 case PACKET3_WAIT_ON_AVAIL_BUFFER:
2691 case PACKET3_ME_WRITE:
2692 break;
2693 case PACKET3_COPY_DATA:
2694 if ((idx_value & 0xf00) == 0) {
2695 reg = ib[idx + 3] * 4;
2696 if (!si_vm_reg_valid(reg))
2697 return -EINVAL;
2698 }
2699 break;
2700 case PACKET3_WRITE_DATA:
2701 if ((idx_value & 0xf00) == 0) {
2702 start_reg = ib[idx + 1] * 4;
2703 if (idx_value & 0x10000) {
2704 if (!si_vm_reg_valid(start_reg))
2705 return -EINVAL;
2706 } else {
2707 for (i = 0; i < (pkt->count - 2); i++) {
2708 reg = start_reg + (4 * i);
2709 if (!si_vm_reg_valid(reg))
2710 return -EINVAL;
2711 }
2712 }
2713 }
2714 break;
2715 case PACKET3_COND_WRITE:
2716 if (idx_value & 0x100) {
2717 reg = ib[idx + 5] * 4;
2718 if (!si_vm_reg_valid(reg))
2719 return -EINVAL;
2720 }
2721 break;
2722 case PACKET3_COPY_DW:
2723 if (idx_value & 0x2) {
2724 reg = ib[idx + 3] * 4;
2725 if (!si_vm_reg_valid(reg))
2726 return -EINVAL;
2727 }
2728 break;
2729 case PACKET3_SET_CONFIG_REG:
2730 start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_START;
2731 end_reg = 4 * pkt->count + start_reg - 4;
2732 if ((start_reg < PACKET3_SET_CONFIG_REG_START) ||
2733 (start_reg >= PACKET3_SET_CONFIG_REG_END) ||
2734 (end_reg >= PACKET3_SET_CONFIG_REG_END)) {
2735 DRM_ERROR("bad PACKET3_SET_CONFIG_REG\n");
2736 return -EINVAL;
2737 }
2738 for (i = 0; i < pkt->count; i++) {
2739 reg = start_reg + (4 * i);
2740 if (!si_vm_reg_valid(reg))
2741 return -EINVAL;
2742 }
2743 break;
2744 default:
2745 DRM_ERROR("Invalid GFX packet3: 0x%x\n", pkt->opcode);
2746 return -EINVAL;
2747 }
2748 return 0;
2749 }
2750
2751 static int si_vm_packet3_compute_check(struct radeon_device *rdev,
2752 u32 *ib, struct radeon_cs_packet *pkt)
2753 {
2754 u32 idx = pkt->idx + 1;
2755 u32 idx_value = ib[idx];
2756 u32 start_reg, reg, i;
2757
2758 switch (pkt->opcode) {
2759 case PACKET3_NOP:
2760 case PACKET3_SET_BASE:
2761 case PACKET3_CLEAR_STATE:
2762 case PACKET3_DISPATCH_DIRECT:
2763 case PACKET3_DISPATCH_INDIRECT:
2764 case PACKET3_ALLOC_GDS:
2765 case PACKET3_WRITE_GDS_RAM:
2766 case PACKET3_ATOMIC_GDS:
2767 case PACKET3_ATOMIC:
2768 case PACKET3_OCCLUSION_QUERY:
2769 case PACKET3_SET_PREDICATION:
2770 case PACKET3_COND_EXEC:
2771 case PACKET3_PRED_EXEC:
2772 case PACKET3_CONTEXT_CONTROL:
2773 case PACKET3_STRMOUT_BUFFER_UPDATE:
2774 case PACKET3_WAIT_REG_MEM:
2775 case PACKET3_MEM_WRITE:
2776 case PACKET3_PFP_SYNC_ME:
2777 case PACKET3_SURFACE_SYNC:
2778 case PACKET3_EVENT_WRITE:
2779 case PACKET3_EVENT_WRITE_EOP:
2780 case PACKET3_EVENT_WRITE_EOS:
2781 case PACKET3_SET_CONTEXT_REG:
2782 case PACKET3_SET_CONTEXT_REG_INDIRECT:
2783 case PACKET3_SET_SH_REG:
2784 case PACKET3_SET_SH_REG_OFFSET:
2785 case PACKET3_INCREMENT_DE_COUNTER:
2786 case PACKET3_WAIT_ON_CE_COUNTER:
2787 case PACKET3_WAIT_ON_AVAIL_BUFFER:
2788 case PACKET3_ME_WRITE:
2789 break;
2790 case PACKET3_COPY_DATA:
2791 if ((idx_value & 0xf00) == 0) {
2792 reg = ib[idx + 3] * 4;
2793 if (!si_vm_reg_valid(reg))
2794 return -EINVAL;
2795 }
2796 break;
2797 case PACKET3_WRITE_DATA:
2798 if ((idx_value & 0xf00) == 0) {
2799 start_reg = ib[idx + 1] * 4;
2800 if (idx_value & 0x10000) {
2801 if (!si_vm_reg_valid(start_reg))
2802 return -EINVAL;
2803 } else {
2804 for (i = 0; i < (pkt->count - 2); i++) {
2805 reg = start_reg + (4 * i);
2806 if (!si_vm_reg_valid(reg))
2807 return -EINVAL;
2808 }
2809 }
2810 }
2811 break;
2812 case PACKET3_COND_WRITE:
2813 if (idx_value & 0x100) {
2814 reg = ib[idx + 5] * 4;
2815 if (!si_vm_reg_valid(reg))
2816 return -EINVAL;
2817 }
2818 break;
2819 case PACKET3_COPY_DW:
2820 if (idx_value & 0x2) {
2821 reg = ib[idx + 3] * 4;
2822 if (!si_vm_reg_valid(reg))
2823 return -EINVAL;
2824 }
2825 break;
2826 default:
2827 DRM_ERROR("Invalid Compute packet3: 0x%x\n", pkt->opcode);
2828 return -EINVAL;
2829 }
2830 return 0;
2831 }
2832
2833 int si_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib)
2834 {
2835 int ret = 0;
2836 u32 idx = 0;
2837 struct radeon_cs_packet pkt;
2838
2839 do {
2840 pkt.idx = idx;
2841 pkt.type = CP_PACKET_GET_TYPE(ib->ptr[idx]);
2842 pkt.count = CP_PACKET_GET_COUNT(ib->ptr[idx]);
2843 pkt.one_reg_wr = 0;
2844 switch (pkt.type) {
2845 case PACKET_TYPE0:
2846 dev_err(rdev->dev, "Packet0 not allowed!\n");
2847 ret = -EINVAL;
2848 break;
2849 case PACKET_TYPE2:
2850 idx += 1;
2851 break;
2852 case PACKET_TYPE3:
2853 pkt.opcode = CP_PACKET3_GET_OPCODE(ib->ptr[idx]);
2854 if (ib->is_const_ib)
2855 ret = si_vm_packet3_ce_check(rdev, ib->ptr, &pkt);
2856 else {
2857 switch (ib->fence->ring) {
2858 case RADEON_RING_TYPE_GFX_INDEX:
2859 ret = si_vm_packet3_gfx_check(rdev, ib->ptr, &pkt);
2860 break;
2861 case CAYMAN_RING_TYPE_CP1_INDEX:
2862 case CAYMAN_RING_TYPE_CP2_INDEX:
2863 ret = si_vm_packet3_compute_check(rdev, ib->ptr, &pkt);
2864 break;
2865 default:
2866 dev_err(rdev->dev, "Non-PM4 ring %d !\n", ib->fence->ring);
2867 ret = -EINVAL;
2868 break;
2869 }
2870 }
2871 idx += pkt.count + 2;
2872 break;
2873 default:
2874 dev_err(rdev->dev, "Unknown packet type %d !\n", pkt.type);
2875 ret = -EINVAL;
2876 break;
2877 }
2878 if (ret)
2879 break;
2880 } while (idx < ib->length_dw);
2881
2882 return ret;
2883 }
2884
2885 /*
2886 * vm
2887 */
2888 int si_vm_init(struct radeon_device *rdev)
2889 {
2890 /* number of VMs */
2891 rdev->vm_manager.nvm = 16;
2892 /* base offset of vram pages */
2893 rdev->vm_manager.vram_base_offset = 0;
2894
2895 return 0;
2896 }
2897
2898 void si_vm_fini(struct radeon_device *rdev)
2899 {
2900 }
2901
2902 int si_vm_bind(struct radeon_device *rdev, struct radeon_vm *vm, int id)
2903 {
2904 if (id < 8)
2905 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (id << 2), vm->pt_gpu_addr >> 12);
2906 else
2907 WREG32(VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((id - 8) << 2),
2908 vm->pt_gpu_addr >> 12);
2909 /* flush hdp cache */
2910 WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
2911 /* bits 0-15 are the VM contexts0-15 */
2912 WREG32(VM_INVALIDATE_REQUEST, 1 << id);
2913 return 0;
2914 }
2915
2916 void si_vm_unbind(struct radeon_device *rdev, struct radeon_vm *vm)
2917 {
2918 if (vm->id < 8)
2919 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm->id << 2), 0);
2920 else
2921 WREG32(VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((vm->id - 8) << 2), 0);
2922 /* flush hdp cache */
2923 WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
2924 /* bits 0-15 are the VM contexts0-15 */
2925 WREG32(VM_INVALIDATE_REQUEST, 1 << vm->id);
2926 }
2927
2928 void si_vm_tlb_flush(struct radeon_device *rdev, struct radeon_vm *vm)
2929 {
2930 if (vm->id == -1)
2931 return;
2932
2933 /* flush hdp cache */
2934 WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
2935 /* bits 0-15 are the VM contexts0-15 */
2936 WREG32(VM_INVALIDATE_REQUEST, 1 << vm->id);
2937 }
2938
2939 /*
2940 * RLC
2941 */
2942 void si_rlc_fini(struct radeon_device *rdev)
2943 {
2944 int r;
2945
2946 /* save restore block */
2947 if (rdev->rlc.save_restore_obj) {
2948 r = radeon_bo_reserve(rdev->rlc.save_restore_obj, false);
2949 if (unlikely(r != 0))
2950 dev_warn(rdev->dev, "(%d) reserve RLC sr bo failed\n", r);
2951 radeon_bo_unpin(rdev->rlc.save_restore_obj);
2952 radeon_bo_unreserve(rdev->rlc.save_restore_obj);
2953
2954 radeon_bo_unref(&rdev->rlc.save_restore_obj);
2955 rdev->rlc.save_restore_obj = NULL;
2956 }
2957
2958 /* clear state block */
2959 if (rdev->rlc.clear_state_obj) {
2960 r = radeon_bo_reserve(rdev->rlc.clear_state_obj, false);
2961 if (unlikely(r != 0))
2962 dev_warn(rdev->dev, "(%d) reserve RLC c bo failed\n", r);
2963 radeon_bo_unpin(rdev->rlc.clear_state_obj);
2964 radeon_bo_unreserve(rdev->rlc.clear_state_obj);
2965
2966 radeon_bo_unref(&rdev->rlc.clear_state_obj);
2967 rdev->rlc.clear_state_obj = NULL;
2968 }
2969 }
2970
2971 int si_rlc_init(struct radeon_device *rdev)
2972 {
2973 int r;
2974
2975 /* save restore block */
2976 if (rdev->rlc.save_restore_obj == NULL) {
2977 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, PAGE_SIZE, true,
2978 RADEON_GEM_DOMAIN_VRAM, &rdev->rlc.save_restore_obj);
2979 if (r) {
2980 dev_warn(rdev->dev, "(%d) create RLC sr bo failed\n", r);
2981 return r;
2982 }
2983 }
2984
2985 r = radeon_bo_reserve(rdev->rlc.save_restore_obj, false);
2986 if (unlikely(r != 0)) {
2987 si_rlc_fini(rdev);
2988 return r;
2989 }
2990 r = radeon_bo_pin(rdev->rlc.save_restore_obj, RADEON_GEM_DOMAIN_VRAM,
2991 &rdev->rlc.save_restore_gpu_addr);
2992 radeon_bo_unreserve(rdev->rlc.save_restore_obj);
2993 if (r) {
2994 dev_warn(rdev->dev, "(%d) pin RLC sr bo failed\n", r);
2995 si_rlc_fini(rdev);
2996 return r;
2997 }
2998
2999 /* clear state block */
3000 if (rdev->rlc.clear_state_obj == NULL) {
3001 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, PAGE_SIZE, true,
3002 RADEON_GEM_DOMAIN_VRAM, &rdev->rlc.clear_state_obj);
3003 if (r) {
3004 dev_warn(rdev->dev, "(%d) create RLC c bo failed\n", r);
3005 si_rlc_fini(rdev);
3006 return r;
3007 }
3008 }
3009 r = radeon_bo_reserve(rdev->rlc.clear_state_obj, false);
3010 if (unlikely(r != 0)) {
3011 si_rlc_fini(rdev);
3012 return r;
3013 }
3014 r = radeon_bo_pin(rdev->rlc.clear_state_obj, RADEON_GEM_DOMAIN_VRAM,
3015 &rdev->rlc.clear_state_gpu_addr);
3016 radeon_bo_unreserve(rdev->rlc.clear_state_obj);
3017 if (r) {
3018 dev_warn(rdev->dev, "(%d) pin RLC c bo failed\n", r);
3019 si_rlc_fini(rdev);
3020 return r;
3021 }
3022
3023 return 0;
3024 }
3025
3026 static void si_rlc_stop(struct radeon_device *rdev)
3027 {
3028 WREG32(RLC_CNTL, 0);
3029 }
3030
3031 static void si_rlc_start(struct radeon_device *rdev)
3032 {
3033 WREG32(RLC_CNTL, RLC_ENABLE);
3034 }
3035
3036 static int si_rlc_resume(struct radeon_device *rdev)
3037 {
3038 u32 i;
3039 const __be32 *fw_data;
3040
3041 if (!rdev->rlc_fw)
3042 return -EINVAL;
3043
3044 si_rlc_stop(rdev);
3045
3046 WREG32(RLC_RL_BASE, 0);
3047 WREG32(RLC_RL_SIZE, 0);
3048 WREG32(RLC_LB_CNTL, 0);
3049 WREG32(RLC_LB_CNTR_MAX, 0xffffffff);
3050 WREG32(RLC_LB_CNTR_INIT, 0);
3051
3052 WREG32(RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8);
3053 WREG32(RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8);
3054
3055 WREG32(RLC_MC_CNTL, 0);
3056 WREG32(RLC_UCODE_CNTL, 0);
3057
3058 fw_data = (const __be32 *)rdev->rlc_fw->data;
3059 for (i = 0; i < SI_RLC_UCODE_SIZE; i++) {
3060 WREG32(RLC_UCODE_ADDR, i);
3061 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
3062 }
3063 WREG32(RLC_UCODE_ADDR, 0);
3064
3065 si_rlc_start(rdev);
3066
3067 return 0;
3068 }
3069
3070 static void si_enable_interrupts(struct radeon_device *rdev)
3071 {
3072 u32 ih_cntl = RREG32(IH_CNTL);
3073 u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
3074
3075 ih_cntl |= ENABLE_INTR;
3076 ih_rb_cntl |= IH_RB_ENABLE;
3077 WREG32(IH_CNTL, ih_cntl);
3078 WREG32(IH_RB_CNTL, ih_rb_cntl);
3079 rdev->ih.enabled = true;
3080 }
3081
3082 static void si_disable_interrupts(struct radeon_device *rdev)
3083 {
3084 u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
3085 u32 ih_cntl = RREG32(IH_CNTL);
3086
3087 ih_rb_cntl &= ~IH_RB_ENABLE;
3088 ih_cntl &= ~ENABLE_INTR;
3089 WREG32(IH_RB_CNTL, ih_rb_cntl);
3090 WREG32(IH_CNTL, ih_cntl);
3091 /* set rptr, wptr to 0 */
3092 WREG32(IH_RB_RPTR, 0);
3093 WREG32(IH_RB_WPTR, 0);
3094 rdev->ih.enabled = false;
3095 rdev->ih.wptr = 0;
3096 rdev->ih.rptr = 0;
3097 }
3098
3099 static void si_disable_interrupt_state(struct radeon_device *rdev)
3100 {
3101 u32 tmp;
3102
3103 WREG32(CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
3104 WREG32(CP_INT_CNTL_RING1, 0);
3105 WREG32(CP_INT_CNTL_RING2, 0);
3106 WREG32(GRBM_INT_CNTL, 0);
3107 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
3108 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
3109 if (rdev->num_crtc >= 4) {
3110 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
3111 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
3112 }
3113 if (rdev->num_crtc >= 6) {
3114 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
3115 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
3116 }
3117
3118 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
3119 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
3120 if (rdev->num_crtc >= 4) {
3121 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
3122 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
3123 }
3124 if (rdev->num_crtc >= 6) {
3125 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
3126 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
3127 }
3128
3129 WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
3130
3131 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3132 WREG32(DC_HPD1_INT_CONTROL, tmp);
3133 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3134 WREG32(DC_HPD2_INT_CONTROL, tmp);
3135 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3136 WREG32(DC_HPD3_INT_CONTROL, tmp);
3137 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3138 WREG32(DC_HPD4_INT_CONTROL, tmp);
3139 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3140 WREG32(DC_HPD5_INT_CONTROL, tmp);
3141 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3142 WREG32(DC_HPD6_INT_CONTROL, tmp);
3143
3144 }
3145
3146 static int si_irq_init(struct radeon_device *rdev)
3147 {
3148 int ret = 0;
3149 int rb_bufsz;
3150 u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
3151
3152 /* allocate ring */
3153 ret = r600_ih_ring_alloc(rdev);
3154 if (ret)
3155 return ret;
3156
3157 /* disable irqs */
3158 si_disable_interrupts(rdev);
3159
3160 /* init rlc */
3161 ret = si_rlc_resume(rdev);
3162 if (ret) {
3163 r600_ih_ring_fini(rdev);
3164 return ret;
3165 }
3166
3167 /* setup interrupt control */
3168 /* set dummy read address to ring address */
3169 WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8);
3170 interrupt_cntl = RREG32(INTERRUPT_CNTL);
3171 /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi
3172 * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN
3173 */
3174 interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE;
3175 /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */
3176 interrupt_cntl &= ~IH_REQ_NONSNOOP_EN;
3177 WREG32(INTERRUPT_CNTL, interrupt_cntl);
3178
3179 WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8);
3180 rb_bufsz = drm_order(rdev->ih.ring_size / 4);
3181
3182 ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE |
3183 IH_WPTR_OVERFLOW_CLEAR |
3184 (rb_bufsz << 1));
3185
3186 if (rdev->wb.enabled)
3187 ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE;
3188
3189 /* set the writeback address whether it's enabled or not */
3190 WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC);
3191 WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF);
3192
3193 WREG32(IH_RB_CNTL, ih_rb_cntl);
3194
3195 /* set rptr, wptr to 0 */
3196 WREG32(IH_RB_RPTR, 0);
3197 WREG32(IH_RB_WPTR, 0);
3198
3199 /* Default settings for IH_CNTL (disabled at first) */
3200 ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10) | MC_VMID(0);
3201 /* RPTR_REARM only works if msi's are enabled */
3202 if (rdev->msi_enabled)
3203 ih_cntl |= RPTR_REARM;
3204 WREG32(IH_CNTL, ih_cntl);
3205
3206 /* force the active interrupt state to all disabled */
3207 si_disable_interrupt_state(rdev);
3208
3209 pci_set_master(rdev->pdev);
3210
3211 /* enable irqs */
3212 si_enable_interrupts(rdev);
3213
3214 return ret;
3215 }
3216
3217 int si_irq_set(struct radeon_device *rdev)
3218 {
3219 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
3220 u32 cp_int_cntl1 = 0, cp_int_cntl2 = 0;
3221 u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0;
3222 u32 hpd1, hpd2, hpd3, hpd4, hpd5, hpd6;
3223 u32 grbm_int_cntl = 0;
3224 u32 grph1 = 0, grph2 = 0, grph3 = 0, grph4 = 0, grph5 = 0, grph6 = 0;
3225
3226 if (!rdev->irq.installed) {
3227 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
3228 return -EINVAL;
3229 }
3230 /* don't enable anything if the ih is disabled */
3231 if (!rdev->ih.enabled) {
3232 si_disable_interrupts(rdev);
3233 /* force the active interrupt state to all disabled */
3234 si_disable_interrupt_state(rdev);
3235 return 0;
3236 }
3237
3238 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
3239 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
3240 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
3241 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
3242 hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
3243 hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
3244
3245 /* enable CP interrupts on all rings */
3246 if (rdev->irq.sw_int[RADEON_RING_TYPE_GFX_INDEX]) {
3247 DRM_DEBUG("si_irq_set: sw int gfx\n");
3248 cp_int_cntl |= TIME_STAMP_INT_ENABLE;
3249 }
3250 if (rdev->irq.sw_int[CAYMAN_RING_TYPE_CP1_INDEX]) {
3251 DRM_DEBUG("si_irq_set: sw int cp1\n");
3252 cp_int_cntl1 |= TIME_STAMP_INT_ENABLE;
3253 }
3254 if (rdev->irq.sw_int[CAYMAN_RING_TYPE_CP2_INDEX]) {
3255 DRM_DEBUG("si_irq_set: sw int cp2\n");
3256 cp_int_cntl2 |= TIME_STAMP_INT_ENABLE;
3257 }
3258 if (rdev->irq.crtc_vblank_int[0] ||
3259 rdev->irq.pflip[0]) {
3260 DRM_DEBUG("si_irq_set: vblank 0\n");
3261 crtc1 |= VBLANK_INT_MASK;
3262 }
3263 if (rdev->irq.crtc_vblank_int[1] ||
3264 rdev->irq.pflip[1]) {
3265 DRM_DEBUG("si_irq_set: vblank 1\n");
3266 crtc2 |= VBLANK_INT_MASK;
3267 }
3268 if (rdev->irq.crtc_vblank_int[2] ||
3269 rdev->irq.pflip[2]) {
3270 DRM_DEBUG("si_irq_set: vblank 2\n");
3271 crtc3 |= VBLANK_INT_MASK;
3272 }
3273 if (rdev->irq.crtc_vblank_int[3] ||
3274 rdev->irq.pflip[3]) {
3275 DRM_DEBUG("si_irq_set: vblank 3\n");
3276 crtc4 |= VBLANK_INT_MASK;
3277 }
3278 if (rdev->irq.crtc_vblank_int[4] ||
3279 rdev->irq.pflip[4]) {
3280 DRM_DEBUG("si_irq_set: vblank 4\n");
3281 crtc5 |= VBLANK_INT_MASK;
3282 }
3283 if (rdev->irq.crtc_vblank_int[5] ||
3284 rdev->irq.pflip[5]) {
3285 DRM_DEBUG("si_irq_set: vblank 5\n");
3286 crtc6 |= VBLANK_INT_MASK;
3287 }
3288 if (rdev->irq.hpd[0]) {
3289 DRM_DEBUG("si_irq_set: hpd 1\n");
3290 hpd1 |= DC_HPDx_INT_EN;
3291 }
3292 if (rdev->irq.hpd[1]) {
3293 DRM_DEBUG("si_irq_set: hpd 2\n");
3294 hpd2 |= DC_HPDx_INT_EN;
3295 }
3296 if (rdev->irq.hpd[2]) {
3297 DRM_DEBUG("si_irq_set: hpd 3\n");
3298 hpd3 |= DC_HPDx_INT_EN;
3299 }
3300 if (rdev->irq.hpd[3]) {
3301 DRM_DEBUG("si_irq_set: hpd 4\n");
3302 hpd4 |= DC_HPDx_INT_EN;
3303 }
3304 if (rdev->irq.hpd[4]) {
3305 DRM_DEBUG("si_irq_set: hpd 5\n");
3306 hpd5 |= DC_HPDx_INT_EN;
3307 }
3308 if (rdev->irq.hpd[5]) {
3309 DRM_DEBUG("si_irq_set: hpd 6\n");
3310 hpd6 |= DC_HPDx_INT_EN;
3311 }
3312 if (rdev->irq.gui_idle) {
3313 DRM_DEBUG("gui idle\n");
3314 grbm_int_cntl |= GUI_IDLE_INT_ENABLE;
3315 }
3316
3317 WREG32(CP_INT_CNTL_RING0, cp_int_cntl);
3318 WREG32(CP_INT_CNTL_RING1, cp_int_cntl1);
3319 WREG32(CP_INT_CNTL_RING2, cp_int_cntl2);
3320
3321 WREG32(GRBM_INT_CNTL, grbm_int_cntl);
3322
3323 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1);
3324 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2);
3325 if (rdev->num_crtc >= 4) {
3326 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3);
3327 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4);
3328 }
3329 if (rdev->num_crtc >= 6) {
3330 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5);
3331 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6);
3332 }
3333
3334 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, grph1);
3335 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, grph2);
3336 if (rdev->num_crtc >= 4) {
3337 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, grph3);
3338 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, grph4);
3339 }
3340 if (rdev->num_crtc >= 6) {
3341 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, grph5);
3342 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, grph6);
3343 }
3344
3345 WREG32(DC_HPD1_INT_CONTROL, hpd1);
3346 WREG32(DC_HPD2_INT_CONTROL, hpd2);
3347 WREG32(DC_HPD3_INT_CONTROL, hpd3);
3348 WREG32(DC_HPD4_INT_CONTROL, hpd4);
3349 WREG32(DC_HPD5_INT_CONTROL, hpd5);
3350 WREG32(DC_HPD6_INT_CONTROL, hpd6);
3351
3352 return 0;
3353 }
3354
3355 static inline void si_irq_ack(struct radeon_device *rdev)
3356 {
3357 u32 tmp;
3358
3359 rdev->irq.stat_regs.evergreen.disp_int = RREG32(DISP_INTERRUPT_STATUS);
3360 rdev->irq.stat_regs.evergreen.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
3361 rdev->irq.stat_regs.evergreen.disp_int_cont2 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE2);
3362 rdev->irq.stat_regs.evergreen.disp_int_cont3 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE3);
3363 rdev->irq.stat_regs.evergreen.disp_int_cont4 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE4);
3364 rdev->irq.stat_regs.evergreen.disp_int_cont5 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE5);
3365 rdev->irq.stat_regs.evergreen.d1grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET);
3366 rdev->irq.stat_regs.evergreen.d2grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET);
3367 if (rdev->num_crtc >= 4) {
3368 rdev->irq.stat_regs.evergreen.d3grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET);
3369 rdev->irq.stat_regs.evergreen.d4grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET);
3370 }
3371 if (rdev->num_crtc >= 6) {
3372 rdev->irq.stat_regs.evergreen.d5grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET);
3373 rdev->irq.stat_regs.evergreen.d6grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET);
3374 }
3375
3376 if (rdev->irq.stat_regs.evergreen.d1grph_int & GRPH_PFLIP_INT_OCCURRED)
3377 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
3378 if (rdev->irq.stat_regs.evergreen.d2grph_int & GRPH_PFLIP_INT_OCCURRED)
3379 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
3380 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT)
3381 WREG32(VBLANK_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VBLANK_ACK);
3382 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT)
3383 WREG32(VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VLINE_ACK);
3384 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT)
3385 WREG32(VBLANK_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VBLANK_ACK);
3386 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT)
3387 WREG32(VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VLINE_ACK);
3388
3389 if (rdev->num_crtc >= 4) {
3390 if (rdev->irq.stat_regs.evergreen.d3grph_int & GRPH_PFLIP_INT_OCCURRED)
3391 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
3392 if (rdev->irq.stat_regs.evergreen.d4grph_int & GRPH_PFLIP_INT_OCCURRED)
3393 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
3394 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT)
3395 WREG32(VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VBLANK_ACK);
3396 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT)
3397 WREG32(VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VLINE_ACK);
3398 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT)
3399 WREG32(VBLANK_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VBLANK_ACK);
3400 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT)
3401 WREG32(VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VLINE_ACK);
3402 }
3403
3404 if (rdev->num_crtc >= 6) {
3405 if (rdev->irq.stat_regs.evergreen.d5grph_int & GRPH_PFLIP_INT_OCCURRED)
3406 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
3407 if (rdev->irq.stat_regs.evergreen.d6grph_int & GRPH_PFLIP_INT_OCCURRED)
3408 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
3409 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT)
3410 WREG32(VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VBLANK_ACK);
3411 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT)
3412 WREG32(VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VLINE_ACK);
3413 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT)
3414 WREG32(VBLANK_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VBLANK_ACK);
3415 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT)
3416 WREG32(VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VLINE_ACK);
3417 }
3418
3419 if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) {
3420 tmp = RREG32(DC_HPD1_INT_CONTROL);
3421 tmp |= DC_HPDx_INT_ACK;
3422 WREG32(DC_HPD1_INT_CONTROL, tmp);
3423 }
3424 if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) {
3425 tmp = RREG32(DC_HPD2_INT_CONTROL);
3426 tmp |= DC_HPDx_INT_ACK;
3427 WREG32(DC_HPD2_INT_CONTROL, tmp);
3428 }
3429 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) {
3430 tmp = RREG32(DC_HPD3_INT_CONTROL);
3431 tmp |= DC_HPDx_INT_ACK;
3432 WREG32(DC_HPD3_INT_CONTROL, tmp);
3433 }
3434 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) {
3435 tmp = RREG32(DC_HPD4_INT_CONTROL);
3436 tmp |= DC_HPDx_INT_ACK;
3437 WREG32(DC_HPD4_INT_CONTROL, tmp);
3438 }
3439 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) {
3440 tmp = RREG32(DC_HPD5_INT_CONTROL);
3441 tmp |= DC_HPDx_INT_ACK;
3442 WREG32(DC_HPD5_INT_CONTROL, tmp);
3443 }
3444 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) {
3445 tmp = RREG32(DC_HPD5_INT_CONTROL);
3446 tmp |= DC_HPDx_INT_ACK;
3447 WREG32(DC_HPD6_INT_CONTROL, tmp);
3448 }
3449 }
3450
3451 static void si_irq_disable(struct radeon_device *rdev)
3452 {
3453 si_disable_interrupts(rdev);
3454 /* Wait and acknowledge irq */
3455 mdelay(1);
3456 si_irq_ack(rdev);
3457 si_disable_interrupt_state(rdev);
3458 }
3459
3460 static void si_irq_suspend(struct radeon_device *rdev)
3461 {
3462 si_irq_disable(rdev);
3463 si_rlc_stop(rdev);
3464 }
3465
3466 static void si_irq_fini(struct radeon_device *rdev)
3467 {
3468 si_irq_suspend(rdev);
3469 r600_ih_ring_fini(rdev);
3470 }
3471
3472 static inline u32 si_get_ih_wptr(struct radeon_device *rdev)
3473 {
3474 u32 wptr, tmp;
3475
3476 if (rdev->wb.enabled)
3477 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]);
3478 else
3479 wptr = RREG32(IH_RB_WPTR);
3480
3481 if (wptr & RB_OVERFLOW) {
3482 /* When a ring buffer overflow happen start parsing interrupt
3483 * from the last not overwritten vector (wptr + 16). Hopefully
3484 * this should allow us to catchup.
3485 */
3486 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
3487 wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
3488 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
3489 tmp = RREG32(IH_RB_CNTL);
3490 tmp |= IH_WPTR_OVERFLOW_CLEAR;
3491 WREG32(IH_RB_CNTL, tmp);
3492 }
3493 return (wptr & rdev->ih.ptr_mask);
3494 }
3495
3496 /* SI IV Ring
3497 * Each IV ring entry is 128 bits:
3498 * [7:0] - interrupt source id
3499 * [31:8] - reserved
3500 * [59:32] - interrupt source data
3501 * [63:60] - reserved
3502 * [71:64] - RINGID
3503 * [79:72] - VMID
3504 * [127:80] - reserved
3505 */
3506 int si_irq_process(struct radeon_device *rdev)
3507 {
3508 u32 wptr;
3509 u32 rptr;
3510 u32 src_id, src_data, ring_id;
3511 u32 ring_index;
3512 unsigned long flags;
3513 bool queue_hotplug = false;
3514
3515 if (!rdev->ih.enabled || rdev->shutdown)
3516 return IRQ_NONE;
3517
3518 wptr = si_get_ih_wptr(rdev);
3519 rptr = rdev->ih.rptr;
3520 DRM_DEBUG("si_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
3521
3522 spin_lock_irqsave(&rdev->ih.lock, flags);
3523 if (rptr == wptr) {
3524 spin_unlock_irqrestore(&rdev->ih.lock, flags);
3525 return IRQ_NONE;
3526 }
3527 restart_ih:
3528 /* Order reading of wptr vs. reading of IH ring data */
3529 rmb();
3530
3531 /* display interrupts */
3532 si_irq_ack(rdev);
3533
3534 rdev->ih.wptr = wptr;
3535 while (rptr != wptr) {
3536 /* wptr/rptr are in bytes! */
3537 ring_index = rptr / 4;
3538 src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff;
3539 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff;
3540 ring_id = le32_to_cpu(rdev->ih.ring[ring_index + 2]) & 0xff;
3541
3542 switch (src_id) {
3543 case 1: /* D1 vblank/vline */
3544 switch (src_data) {
3545 case 0: /* D1 vblank */
3546 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT) {
3547 if (rdev->irq.crtc_vblank_int[0]) {
3548 drm_handle_vblank(rdev->ddev, 0);
3549 rdev->pm.vblank_sync = true;
3550 wake_up(&rdev->irq.vblank_queue);
3551 }
3552 if (rdev->irq.pflip[0])
3553 radeon_crtc_handle_flip(rdev, 0);
3554 rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
3555 DRM_DEBUG("IH: D1 vblank\n");
3556 }
3557 break;
3558 case 1: /* D1 vline */
3559 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT) {
3560 rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VLINE_INTERRUPT;
3561 DRM_DEBUG("IH: D1 vline\n");
3562 }
3563 break;
3564 default:
3565 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3566 break;
3567 }
3568 break;
3569 case 2: /* D2 vblank/vline */
3570 switch (src_data) {
3571 case 0: /* D2 vblank */
3572 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT) {
3573 if (rdev->irq.crtc_vblank_int[1]) {
3574 drm_handle_vblank(rdev->ddev, 1);
3575 rdev->pm.vblank_sync = true;
3576 wake_up(&rdev->irq.vblank_queue);
3577 }
3578 if (rdev->irq.pflip[1])
3579 radeon_crtc_handle_flip(rdev, 1);
3580 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT;
3581 DRM_DEBUG("IH: D2 vblank\n");
3582 }
3583 break;
3584 case 1: /* D2 vline */
3585 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT) {
3586 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VLINE_INTERRUPT;
3587 DRM_DEBUG("IH: D2 vline\n");
3588 }
3589 break;
3590 default:
3591 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3592 break;
3593 }
3594 break;
3595 case 3: /* D3 vblank/vline */
3596 switch (src_data) {
3597 case 0: /* D3 vblank */
3598 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT) {
3599 if (rdev->irq.crtc_vblank_int[2]) {
3600 drm_handle_vblank(rdev->ddev, 2);
3601 rdev->pm.vblank_sync = true;
3602 wake_up(&rdev->irq.vblank_queue);
3603 }
3604 if (rdev->irq.pflip[2])
3605 radeon_crtc_handle_flip(rdev, 2);
3606 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VBLANK_INTERRUPT;
3607 DRM_DEBUG("IH: D3 vblank\n");
3608 }
3609 break;
3610 case 1: /* D3 vline */
3611 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT) {
3612 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VLINE_INTERRUPT;
3613 DRM_DEBUG("IH: D3 vline\n");
3614 }
3615 break;
3616 default:
3617 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3618 break;
3619 }
3620 break;
3621 case 4: /* D4 vblank/vline */
3622 switch (src_data) {
3623 case 0: /* D4 vblank */
3624 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT) {
3625 if (rdev->irq.crtc_vblank_int[3]) {
3626 drm_handle_vblank(rdev->ddev, 3);
3627 rdev->pm.vblank_sync = true;
3628 wake_up(&rdev->irq.vblank_queue);
3629 }
3630 if (rdev->irq.pflip[3])
3631 radeon_crtc_handle_flip(rdev, 3);
3632 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VBLANK_INTERRUPT;
3633 DRM_DEBUG("IH: D4 vblank\n");
3634 }
3635 break;
3636 case 1: /* D4 vline */
3637 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT) {
3638 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VLINE_INTERRUPT;
3639 DRM_DEBUG("IH: D4 vline\n");
3640 }
3641 break;
3642 default:
3643 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3644 break;
3645 }
3646 break;
3647 case 5: /* D5 vblank/vline */
3648 switch (src_data) {
3649 case 0: /* D5 vblank */
3650 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT) {
3651 if (rdev->irq.crtc_vblank_int[4]) {
3652 drm_handle_vblank(rdev->ddev, 4);
3653 rdev->pm.vblank_sync = true;
3654 wake_up(&rdev->irq.vblank_queue);
3655 }
3656 if (rdev->irq.pflip[4])
3657 radeon_crtc_handle_flip(rdev, 4);
3658 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VBLANK_INTERRUPT;
3659 DRM_DEBUG("IH: D5 vblank\n");
3660 }
3661 break;
3662 case 1: /* D5 vline */
3663 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT) {
3664 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VLINE_INTERRUPT;
3665 DRM_DEBUG("IH: D5 vline\n");
3666 }
3667 break;
3668 default:
3669 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3670 break;
3671 }
3672 break;
3673 case 6: /* D6 vblank/vline */
3674 switch (src_data) {
3675 case 0: /* D6 vblank */
3676 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT) {
3677 if (rdev->irq.crtc_vblank_int[5]) {
3678 drm_handle_vblank(rdev->ddev, 5);
3679 rdev->pm.vblank_sync = true;
3680 wake_up(&rdev->irq.vblank_queue);
3681 }
3682 if (rdev->irq.pflip[5])
3683 radeon_crtc_handle_flip(rdev, 5);
3684 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VBLANK_INTERRUPT;
3685 DRM_DEBUG("IH: D6 vblank\n");
3686 }
3687 break;
3688 case 1: /* D6 vline */
3689 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT) {
3690 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VLINE_INTERRUPT;
3691 DRM_DEBUG("IH: D6 vline\n");
3692 }
3693 break;
3694 default:
3695 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3696 break;
3697 }
3698 break;
3699 case 42: /* HPD hotplug */
3700 switch (src_data) {
3701 case 0:
3702 if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) {
3703 rdev->irq.stat_regs.evergreen.disp_int &= ~DC_HPD1_INTERRUPT;
3704 queue_hotplug = true;
3705 DRM_DEBUG("IH: HPD1\n");
3706 }
3707 break;
3708 case 1:
3709 if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) {
3710 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~DC_HPD2_INTERRUPT;
3711 queue_hotplug = true;
3712 DRM_DEBUG("IH: HPD2\n");
3713 }
3714 break;
3715 case 2:
3716 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) {
3717 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~DC_HPD3_INTERRUPT;
3718 queue_hotplug = true;
3719 DRM_DEBUG("IH: HPD3\n");
3720 }
3721 break;
3722 case 3:
3723 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) {
3724 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~DC_HPD4_INTERRUPT;
3725 queue_hotplug = true;
3726 DRM_DEBUG("IH: HPD4\n");
3727 }
3728 break;
3729 case 4:
3730 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) {
3731 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~DC_HPD5_INTERRUPT;
3732 queue_hotplug = true;
3733 DRM_DEBUG("IH: HPD5\n");
3734 }
3735 break;
3736 case 5:
3737 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) {
3738 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~DC_HPD6_INTERRUPT;
3739 queue_hotplug = true;
3740 DRM_DEBUG("IH: HPD6\n");
3741 }
3742 break;
3743 default:
3744 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3745 break;
3746 }
3747 break;
3748 case 176: /* RINGID0 CP_INT */
3749 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
3750 break;
3751 case 177: /* RINGID1 CP_INT */
3752 radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP1_INDEX);
3753 break;
3754 case 178: /* RINGID2 CP_INT */
3755 radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP2_INDEX);
3756 break;
3757 case 181: /* CP EOP event */
3758 DRM_DEBUG("IH: CP EOP\n");
3759 switch (ring_id) {
3760 case 0:
3761 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
3762 break;
3763 case 1:
3764 radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP1_INDEX);
3765 break;
3766 case 2:
3767 radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP2_INDEX);
3768 break;
3769 }
3770 break;
3771 case 233: /* GUI IDLE */
3772 DRM_DEBUG("IH: GUI idle\n");
3773 rdev->pm.gui_idle = true;
3774 wake_up(&rdev->irq.idle_queue);
3775 break;
3776 default:
3777 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3778 break;
3779 }
3780
3781 /* wptr/rptr are in bytes! */
3782 rptr += 16;
3783 rptr &= rdev->ih.ptr_mask;
3784 }
3785 /* make sure wptr hasn't changed while processing */
3786 wptr = si_get_ih_wptr(rdev);
3787 if (wptr != rdev->ih.wptr)
3788 goto restart_ih;
3789 if (queue_hotplug)
3790 schedule_work(&rdev->hotplug_work);
3791 rdev->ih.rptr = rptr;
3792 WREG32(IH_RB_RPTR, rdev->ih.rptr);
3793 spin_unlock_irqrestore(&rdev->ih.lock, flags);
3794 return IRQ_HANDLED;
3795 }
3796
3797 /*
3798 * startup/shutdown callbacks
3799 */
3800 static int si_startup(struct radeon_device *rdev)
3801 {
3802 struct radeon_ring *ring;
3803 int r;
3804
3805 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->ce_fw ||
3806 !rdev->rlc_fw || !rdev->mc_fw) {
3807 r = si_init_microcode(rdev);
3808 if (r) {
3809 DRM_ERROR("Failed to load firmware!\n");
3810 return r;
3811 }
3812 }
3813
3814 r = si_mc_load_microcode(rdev);
3815 if (r) {
3816 DRM_ERROR("Failed to load MC firmware!\n");
3817 return r;
3818 }
3819
3820 r = r600_vram_scratch_init(rdev);
3821 if (r)
3822 return r;
3823
3824 si_mc_program(rdev);
3825 r = si_pcie_gart_enable(rdev);
3826 if (r)
3827 return r;
3828 si_gpu_init(rdev);
3829
3830 #if 0
3831 r = evergreen_blit_init(rdev);
3832 if (r) {
3833 r600_blit_fini(rdev);
3834 rdev->asic->copy = NULL;
3835 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
3836 }
3837 #endif
3838 /* allocate rlc buffers */
3839 r = si_rlc_init(rdev);
3840 if (r) {
3841 DRM_ERROR("Failed to init rlc BOs!\n");
3842 return r;
3843 }
3844
3845 /* allocate wb buffer */
3846 r = radeon_wb_init(rdev);
3847 if (r)
3848 return r;
3849
3850 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
3851 if (r) {
3852 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
3853 return r;
3854 }
3855
3856 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP1_INDEX);
3857 if (r) {
3858 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
3859 return r;
3860 }
3861
3862 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP2_INDEX);
3863 if (r) {
3864 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
3865 return r;
3866 }
3867
3868 /* Enable IRQ */
3869 r = si_irq_init(rdev);
3870 if (r) {
3871 DRM_ERROR("radeon: IH init failed (%d).\n", r);
3872 radeon_irq_kms_fini(rdev);
3873 return r;
3874 }
3875 si_irq_set(rdev);
3876
3877 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3878 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
3879 CP_RB0_RPTR, CP_RB0_WPTR,
3880 0, 0xfffff, RADEON_CP_PACKET2);
3881 if (r)
3882 return r;
3883
3884 ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX];
3885 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP1_RPTR_OFFSET,
3886 CP_RB1_RPTR, CP_RB1_WPTR,
3887 0, 0xfffff, RADEON_CP_PACKET2);
3888 if (r)
3889 return r;
3890
3891 ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX];
3892 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP2_RPTR_OFFSET,
3893 CP_RB2_RPTR, CP_RB2_WPTR,
3894 0, 0xfffff, RADEON_CP_PACKET2);
3895 if (r)
3896 return r;
3897
3898 r = si_cp_load_microcode(rdev);
3899 if (r)
3900 return r;
3901 r = si_cp_resume(rdev);
3902 if (r)
3903 return r;
3904
3905 r = radeon_ib_pool_start(rdev);
3906 if (r)
3907 return r;
3908
3909 r = radeon_ib_test(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
3910 if (r) {
3911 DRM_ERROR("radeon: failed testing IB (%d) on CP ring 0\n", r);
3912 rdev->accel_working = false;
3913 return r;
3914 }
3915
3916 r = radeon_ib_test(rdev, CAYMAN_RING_TYPE_CP1_INDEX, &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX]);
3917 if (r) {
3918 DRM_ERROR("radeon: failed testing IB (%d) on CP ring 1\n", r);
3919 rdev->accel_working = false;
3920 return r;
3921 }
3922
3923 r = radeon_ib_test(rdev, CAYMAN_RING_TYPE_CP2_INDEX, &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX]);
3924 if (r) {
3925 DRM_ERROR("radeon: failed testing IB (%d) on CP ring 2\n", r);
3926 rdev->accel_working = false;
3927 return r;
3928 }
3929
3930 r = radeon_vm_manager_start(rdev);
3931 if (r)
3932 return r;
3933
3934 return 0;
3935 }
3936
3937 int si_resume(struct radeon_device *rdev)
3938 {
3939 int r;
3940
3941 /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
3942 * posting will perform necessary task to bring back GPU into good
3943 * shape.
3944 */
3945 /* post card */
3946 atom_asic_init(rdev->mode_info.atom_context);
3947
3948 rdev->accel_working = true;
3949 r = si_startup(rdev);
3950 if (r) {
3951 DRM_ERROR("si startup failed on resume\n");
3952 rdev->accel_working = false;
3953 return r;
3954 }
3955
3956 return r;
3957
3958 }
3959
3960 int si_suspend(struct radeon_device *rdev)
3961 {
3962 /* FIXME: we should wait for ring to be empty */
3963 radeon_ib_pool_suspend(rdev);
3964 radeon_vm_manager_suspend(rdev);
3965 #if 0
3966 r600_blit_suspend(rdev);
3967 #endif
3968 si_cp_enable(rdev, false);
3969 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
3970 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
3971 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
3972 si_irq_suspend(rdev);
3973 radeon_wb_disable(rdev);
3974 si_pcie_gart_disable(rdev);
3975 return 0;
3976 }
3977
3978 /* Plan is to move initialization in that function and use
3979 * helper function so that radeon_device_init pretty much
3980 * do nothing more than calling asic specific function. This
3981 * should also allow to remove a bunch of callback function
3982 * like vram_info.
3983 */
3984 int si_init(struct radeon_device *rdev)
3985 {
3986 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3987 int r;
3988
3989 /* This don't do much */
3990 r = radeon_gem_init(rdev);
3991 if (r)
3992 return r;
3993 /* Read BIOS */
3994 if (!radeon_get_bios(rdev)) {
3995 if (ASIC_IS_AVIVO(rdev))
3996 return -EINVAL;
3997 }
3998 /* Must be an ATOMBIOS */
3999 if (!rdev->is_atom_bios) {
4000 dev_err(rdev->dev, "Expecting atombios for cayman GPU\n");
4001 return -EINVAL;
4002 }
4003 r = radeon_atombios_init(rdev);
4004 if (r)
4005 return r;
4006
4007 /* Post card if necessary */
4008 if (!radeon_card_posted(rdev)) {
4009 if (!rdev->bios) {
4010 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
4011 return -EINVAL;
4012 }
4013 DRM_INFO("GPU not posted. posting now...\n");
4014 atom_asic_init(rdev->mode_info.atom_context);
4015 }
4016 /* Initialize scratch registers */
4017 si_scratch_init(rdev);
4018 /* Initialize surface registers */
4019 radeon_surface_init(rdev);
4020 /* Initialize clocks */
4021 radeon_get_clock_info(rdev->ddev);
4022
4023 /* Fence driver */
4024 r = radeon_fence_driver_init(rdev);
4025 if (r)
4026 return r;
4027
4028 /* initialize memory controller */
4029 r = si_mc_init(rdev);
4030 if (r)
4031 return r;
4032 /* Memory manager */
4033 r = radeon_bo_init(rdev);
4034 if (r)
4035 return r;
4036
4037 r = radeon_irq_kms_init(rdev);
4038 if (r)
4039 return r;
4040
4041 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
4042 ring->ring_obj = NULL;
4043 r600_ring_init(rdev, ring, 1024 * 1024);
4044
4045 ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX];
4046 ring->ring_obj = NULL;
4047 r600_ring_init(rdev, ring, 1024 * 1024);
4048
4049 ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX];
4050 ring->ring_obj = NULL;
4051 r600_ring_init(rdev, ring, 1024 * 1024);
4052
4053 rdev->ih.ring_obj = NULL;
4054 r600_ih_ring_init(rdev, 64 * 1024);
4055
4056 r = r600_pcie_gart_init(rdev);
4057 if (r)
4058 return r;
4059
4060 r = radeon_ib_pool_init(rdev);
4061 rdev->accel_working = true;
4062 if (r) {
4063 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
4064 rdev->accel_working = false;
4065 }
4066 r = radeon_vm_manager_init(rdev);
4067 if (r) {
4068 dev_err(rdev->dev, "vm manager initialization failed (%d).\n", r);
4069 }
4070
4071 r = si_startup(rdev);
4072 if (r) {
4073 dev_err(rdev->dev, "disabling GPU acceleration\n");
4074 si_cp_fini(rdev);
4075 si_irq_fini(rdev);
4076 si_rlc_fini(rdev);
4077 radeon_wb_fini(rdev);
4078 r100_ib_fini(rdev);
4079 radeon_vm_manager_fini(rdev);
4080 radeon_irq_kms_fini(rdev);
4081 si_pcie_gart_fini(rdev);
4082 rdev->accel_working = false;
4083 }
4084
4085 /* Don't start up if the MC ucode is missing.
4086 * The default clocks and voltages before the MC ucode
4087 * is loaded are not suffient for advanced operations.
4088 */
4089 if (!rdev->mc_fw) {
4090 DRM_ERROR("radeon: MC ucode required for NI+.\n");
4091 return -EINVAL;
4092 }
4093
4094 return 0;
4095 }
4096
4097 void si_fini(struct radeon_device *rdev)
4098 {
4099 #if 0
4100 r600_blit_fini(rdev);
4101 #endif
4102 si_cp_fini(rdev);
4103 si_irq_fini(rdev);
4104 si_rlc_fini(rdev);
4105 radeon_wb_fini(rdev);
4106 radeon_vm_manager_fini(rdev);
4107 r100_ib_fini(rdev);
4108 radeon_irq_kms_fini(rdev);
4109 si_pcie_gart_fini(rdev);
4110 r600_vram_scratch_fini(rdev);
4111 radeon_gem_fini(rdev);
4112 radeon_semaphore_driver_fini(rdev);
4113 radeon_fence_driver_fini(rdev);
4114 radeon_bo_fini(rdev);
4115 radeon_atombios_fini(rdev);
4116 kfree(rdev->bios);
4117 rdev->bios = NULL;
4118 }
4119
Linux kernel - Deliverables
This page took 0.127422 seconds and 5 git commands to generate.