2 * Copyright 2011 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 * Authors: Alex Deucher
24 #include <linux/firmware.h>
25 #include <linux/platform_device.h>
26 #include <linux/slab.h>
27 #include <linux/module.h>
30 #include "radeon_asic.h"
31 #include <drm/radeon_drm.h>
34 #include "si_blit_shaders.h"
36 #define SI_PFP_UCODE_SIZE 2144
37 #define SI_PM4_UCODE_SIZE 2144
38 #define SI_CE_UCODE_SIZE 2144
39 #define SI_RLC_UCODE_SIZE 2048
40 #define SI_MC_UCODE_SIZE 7769
42 MODULE_FIRMWARE("radeon/TAHITI_pfp.bin");
43 MODULE_FIRMWARE("radeon/TAHITI_me.bin");
44 MODULE_FIRMWARE("radeon/TAHITI_ce.bin");
45 MODULE_FIRMWARE("radeon/TAHITI_mc.bin");
46 MODULE_FIRMWARE("radeon/TAHITI_rlc.bin");
47 MODULE_FIRMWARE("radeon/PITCAIRN_pfp.bin");
48 MODULE_FIRMWARE("radeon/PITCAIRN_me.bin");
49 MODULE_FIRMWARE("radeon/PITCAIRN_ce.bin");
50 MODULE_FIRMWARE("radeon/PITCAIRN_mc.bin");
51 MODULE_FIRMWARE("radeon/PITCAIRN_rlc.bin");
52 MODULE_FIRMWARE("radeon/VERDE_pfp.bin");
53 MODULE_FIRMWARE("radeon/VERDE_me.bin");
54 MODULE_FIRMWARE("radeon/VERDE_ce.bin");
55 MODULE_FIRMWARE("radeon/VERDE_mc.bin");
56 MODULE_FIRMWARE("radeon/VERDE_rlc.bin");
58 extern int r600_ih_ring_alloc(struct radeon_device
*rdev
);
59 extern void r600_ih_ring_fini(struct radeon_device
*rdev
);
60 extern void evergreen_fix_pci_max_read_req_size(struct radeon_device
*rdev
);
61 extern void evergreen_mc_stop(struct radeon_device
*rdev
, struct evergreen_mc_save
*save
);
62 extern void evergreen_mc_resume(struct radeon_device
*rdev
, struct evergreen_mc_save
*save
);
63 extern u32
evergreen_get_number_of_dram_channels(struct radeon_device
*rdev
);
65 /* get temperature in millidegrees */
66 int si_get_temp(struct radeon_device
*rdev
)
71 temp
= (RREG32(CG_MULT_THERMAL_STATUS
) & CTF_TEMP_MASK
) >>
77 actual_temp
= temp
& 0x1ff;
79 actual_temp
= (actual_temp
* 1000);
84 #define TAHITI_IO_MC_REGS_SIZE 36
86 static const u32 tahiti_io_mc_regs
[TAHITI_IO_MC_REGS_SIZE
][2] = {
87 {0x0000006f, 0x03044000},
88 {0x00000070, 0x0480c018},
89 {0x00000071, 0x00000040},
90 {0x00000072, 0x01000000},
91 {0x00000074, 0x000000ff},
92 {0x00000075, 0x00143400},
93 {0x00000076, 0x08ec0800},
94 {0x00000077, 0x040000cc},
95 {0x00000079, 0x00000000},
96 {0x0000007a, 0x21000409},
97 {0x0000007c, 0x00000000},
98 {0x0000007d, 0xe8000000},
99 {0x0000007e, 0x044408a8},
100 {0x0000007f, 0x00000003},
101 {0x00000080, 0x00000000},
102 {0x00000081, 0x01000000},
103 {0x00000082, 0x02000000},
104 {0x00000083, 0x00000000},
105 {0x00000084, 0xe3f3e4f4},
106 {0x00000085, 0x00052024},
107 {0x00000087, 0x00000000},
108 {0x00000088, 0x66036603},
109 {0x00000089, 0x01000000},
110 {0x0000008b, 0x1c0a0000},
111 {0x0000008c, 0xff010000},
112 {0x0000008e, 0xffffefff},
113 {0x0000008f, 0xfff3efff},
114 {0x00000090, 0xfff3efbf},
115 {0x00000094, 0x00101101},
116 {0x00000095, 0x00000fff},
117 {0x00000096, 0x00116fff},
118 {0x00000097, 0x60010000},
119 {0x00000098, 0x10010000},
120 {0x00000099, 0x00006000},
121 {0x0000009a, 0x00001000},
122 {0x0000009f, 0x00a77400}
125 static const u32 pitcairn_io_mc_regs
[TAHITI_IO_MC_REGS_SIZE
][2] = {
126 {0x0000006f, 0x03044000},
127 {0x00000070, 0x0480c018},
128 {0x00000071, 0x00000040},
129 {0x00000072, 0x01000000},
130 {0x00000074, 0x000000ff},
131 {0x00000075, 0x00143400},
132 {0x00000076, 0x08ec0800},
133 {0x00000077, 0x040000cc},
134 {0x00000079, 0x00000000},
135 {0x0000007a, 0x21000409},
136 {0x0000007c, 0x00000000},
137 {0x0000007d, 0xe8000000},
138 {0x0000007e, 0x044408a8},
139 {0x0000007f, 0x00000003},
140 {0x00000080, 0x00000000},
141 {0x00000081, 0x01000000},
142 {0x00000082, 0x02000000},
143 {0x00000083, 0x00000000},
144 {0x00000084, 0xe3f3e4f4},
145 {0x00000085, 0x00052024},
146 {0x00000087, 0x00000000},
147 {0x00000088, 0x66036603},
148 {0x00000089, 0x01000000},
149 {0x0000008b, 0x1c0a0000},
150 {0x0000008c, 0xff010000},
151 {0x0000008e, 0xffffefff},
152 {0x0000008f, 0xfff3efff},
153 {0x00000090, 0xfff3efbf},
154 {0x00000094, 0x00101101},
155 {0x00000095, 0x00000fff},
156 {0x00000096, 0x00116fff},
157 {0x00000097, 0x60010000},
158 {0x00000098, 0x10010000},
159 {0x00000099, 0x00006000},
160 {0x0000009a, 0x00001000},
161 {0x0000009f, 0x00a47400}
164 static const u32 verde_io_mc_regs
[TAHITI_IO_MC_REGS_SIZE
][2] = {
165 {0x0000006f, 0x03044000},
166 {0x00000070, 0x0480c018},
167 {0x00000071, 0x00000040},
168 {0x00000072, 0x01000000},
169 {0x00000074, 0x000000ff},
170 {0x00000075, 0x00143400},
171 {0x00000076, 0x08ec0800},
172 {0x00000077, 0x040000cc},
173 {0x00000079, 0x00000000},
174 {0x0000007a, 0x21000409},
175 {0x0000007c, 0x00000000},
176 {0x0000007d, 0xe8000000},
177 {0x0000007e, 0x044408a8},
178 {0x0000007f, 0x00000003},
179 {0x00000080, 0x00000000},
180 {0x00000081, 0x01000000},
181 {0x00000082, 0x02000000},
182 {0x00000083, 0x00000000},
183 {0x00000084, 0xe3f3e4f4},
184 {0x00000085, 0x00052024},
185 {0x00000087, 0x00000000},
186 {0x00000088, 0x66036603},
187 {0x00000089, 0x01000000},
188 {0x0000008b, 0x1c0a0000},
189 {0x0000008c, 0xff010000},
190 {0x0000008e, 0xffffefff},
191 {0x0000008f, 0xfff3efff},
192 {0x00000090, 0xfff3efbf},
193 {0x00000094, 0x00101101},
194 {0x00000095, 0x00000fff},
195 {0x00000096, 0x00116fff},
196 {0x00000097, 0x60010000},
197 {0x00000098, 0x10010000},
198 {0x00000099, 0x00006000},
199 {0x0000009a, 0x00001000},
200 {0x0000009f, 0x00a37400}
204 static int si_mc_load_microcode(struct radeon_device
*rdev
)
206 const __be32
*fw_data
;
207 u32 running
, blackout
= 0;
209 int i
, ucode_size
, regs_size
;
214 switch (rdev
->family
) {
216 io_mc_regs
= (u32
*)&tahiti_io_mc_regs
;
217 ucode_size
= SI_MC_UCODE_SIZE
;
218 regs_size
= TAHITI_IO_MC_REGS_SIZE
;
221 io_mc_regs
= (u32
*)&pitcairn_io_mc_regs
;
222 ucode_size
= SI_MC_UCODE_SIZE
;
223 regs_size
= TAHITI_IO_MC_REGS_SIZE
;
227 io_mc_regs
= (u32
*)&verde_io_mc_regs
;
228 ucode_size
= SI_MC_UCODE_SIZE
;
229 regs_size
= TAHITI_IO_MC_REGS_SIZE
;
233 running
= RREG32(MC_SEQ_SUP_CNTL
) & RUN_MASK
;
237 blackout
= RREG32(MC_SHARED_BLACKOUT_CNTL
);
238 WREG32(MC_SHARED_BLACKOUT_CNTL
, blackout
| 1);
241 /* reset the engine and set to writable */
242 WREG32(MC_SEQ_SUP_CNTL
, 0x00000008);
243 WREG32(MC_SEQ_SUP_CNTL
, 0x00000010);
245 /* load mc io regs */
246 for (i
= 0; i
< regs_size
; i
++) {
247 WREG32(MC_SEQ_IO_DEBUG_INDEX
, io_mc_regs
[(i
<< 1)]);
248 WREG32(MC_SEQ_IO_DEBUG_DATA
, io_mc_regs
[(i
<< 1) + 1]);
250 /* load the MC ucode */
251 fw_data
= (const __be32
*)rdev
->mc_fw
->data
;
252 for (i
= 0; i
< ucode_size
; i
++)
253 WREG32(MC_SEQ_SUP_PGM
, be32_to_cpup(fw_data
++));
255 /* put the engine back into the active state */
256 WREG32(MC_SEQ_SUP_CNTL
, 0x00000008);
257 WREG32(MC_SEQ_SUP_CNTL
, 0x00000004);
258 WREG32(MC_SEQ_SUP_CNTL
, 0x00000001);
260 /* wait for training to complete */
261 for (i
= 0; i
< rdev
->usec_timeout
; i
++) {
262 if (RREG32(MC_SEQ_TRAIN_WAKEUP_CNTL
) & TRAIN_DONE_D0
)
266 for (i
= 0; i
< rdev
->usec_timeout
; i
++) {
267 if (RREG32(MC_SEQ_TRAIN_WAKEUP_CNTL
) & TRAIN_DONE_D1
)
273 WREG32(MC_SHARED_BLACKOUT_CNTL
, blackout
);
279 static int si_init_microcode(struct radeon_device
*rdev
)
281 struct platform_device
*pdev
;
282 const char *chip_name
;
283 const char *rlc_chip_name
;
284 size_t pfp_req_size
, me_req_size
, ce_req_size
, rlc_req_size
, mc_req_size
;
290 pdev
= platform_device_register_simple("radeon_cp", 0, NULL
, 0);
293 printk(KERN_ERR
"radeon_cp: Failed to register firmware\n");
297 switch (rdev
->family
) {
299 chip_name
= "TAHITI";
300 rlc_chip_name
= "TAHITI";
301 pfp_req_size
= SI_PFP_UCODE_SIZE
* 4;
302 me_req_size
= SI_PM4_UCODE_SIZE
* 4;
303 ce_req_size
= SI_CE_UCODE_SIZE
* 4;
304 rlc_req_size
= SI_RLC_UCODE_SIZE
* 4;
305 mc_req_size
= SI_MC_UCODE_SIZE
* 4;
308 chip_name
= "PITCAIRN";
309 rlc_chip_name
= "PITCAIRN";
310 pfp_req_size
= SI_PFP_UCODE_SIZE
* 4;
311 me_req_size
= SI_PM4_UCODE_SIZE
* 4;
312 ce_req_size
= SI_CE_UCODE_SIZE
* 4;
313 rlc_req_size
= SI_RLC_UCODE_SIZE
* 4;
314 mc_req_size
= SI_MC_UCODE_SIZE
* 4;
318 rlc_chip_name
= "VERDE";
319 pfp_req_size
= SI_PFP_UCODE_SIZE
* 4;
320 me_req_size
= SI_PM4_UCODE_SIZE
* 4;
321 ce_req_size
= SI_CE_UCODE_SIZE
* 4;
322 rlc_req_size
= SI_RLC_UCODE_SIZE
* 4;
323 mc_req_size
= SI_MC_UCODE_SIZE
* 4;
328 DRM_INFO("Loading %s Microcode\n", chip_name
);
330 snprintf(fw_name
, sizeof(fw_name
), "radeon/%s_pfp.bin", chip_name
);
331 err
= request_firmware(&rdev
->pfp_fw
, fw_name
, &pdev
->dev
);
334 if (rdev
->pfp_fw
->size
!= pfp_req_size
) {
336 "si_cp: Bogus length %zu in firmware \"%s\"\n",
337 rdev
->pfp_fw
->size
, fw_name
);
342 snprintf(fw_name
, sizeof(fw_name
), "radeon/%s_me.bin", chip_name
);
343 err
= request_firmware(&rdev
->me_fw
, fw_name
, &pdev
->dev
);
346 if (rdev
->me_fw
->size
!= me_req_size
) {
348 "si_cp: Bogus length %zu in firmware \"%s\"\n",
349 rdev
->me_fw
->size
, fw_name
);
353 snprintf(fw_name
, sizeof(fw_name
), "radeon/%s_ce.bin", chip_name
);
354 err
= request_firmware(&rdev
->ce_fw
, fw_name
, &pdev
->dev
);
357 if (rdev
->ce_fw
->size
!= ce_req_size
) {
359 "si_cp: Bogus length %zu in firmware \"%s\"\n",
360 rdev
->ce_fw
->size
, fw_name
);
364 snprintf(fw_name
, sizeof(fw_name
), "radeon/%s_rlc.bin", rlc_chip_name
);
365 err
= request_firmware(&rdev
->rlc_fw
, fw_name
, &pdev
->dev
);
368 if (rdev
->rlc_fw
->size
!= rlc_req_size
) {
370 "si_rlc: Bogus length %zu in firmware \"%s\"\n",
371 rdev
->rlc_fw
->size
, fw_name
);
375 snprintf(fw_name
, sizeof(fw_name
), "radeon/%s_mc.bin", chip_name
);
376 err
= request_firmware(&rdev
->mc_fw
, fw_name
, &pdev
->dev
);
379 if (rdev
->mc_fw
->size
!= mc_req_size
) {
381 "si_mc: Bogus length %zu in firmware \"%s\"\n",
382 rdev
->mc_fw
->size
, fw_name
);
387 platform_device_unregister(pdev
);
392 "si_cp: Failed to load firmware \"%s\"\n",
394 release_firmware(rdev
->pfp_fw
);
396 release_firmware(rdev
->me_fw
);
398 release_firmware(rdev
->ce_fw
);
400 release_firmware(rdev
->rlc_fw
);
402 release_firmware(rdev
->mc_fw
);
408 /* watermark setup */
409 static u32
dce6_line_buffer_adjust(struct radeon_device
*rdev
,
410 struct radeon_crtc
*radeon_crtc
,
411 struct drm_display_mode
*mode
,
412 struct drm_display_mode
*other_mode
)
417 * There are 3 line buffers, each one shared by 2 display controllers.
418 * DC_LB_MEMORY_SPLIT controls how that line buffer is shared between
419 * the display controllers. The paritioning is done via one of four
420 * preset allocations specified in bits 21:20:
422 * 2 - whole lb, other crtc must be disabled
424 /* this can get tricky if we have two large displays on a paired group
425 * of crtcs. Ideally for multiple large displays we'd assign them to
426 * non-linked crtcs for maximum line buffer allocation.
428 if (radeon_crtc
->base
.enabled
&& mode
) {
436 WREG32(DC_LB_MEMORY_SPLIT
+ radeon_crtc
->crtc_offset
,
437 DC_LB_MEMORY_CONFIG(tmp
));
439 if (radeon_crtc
->base
.enabled
&& mode
) {
449 /* controller not enabled, so no lb used */
453 static u32
si_get_number_of_dram_channels(struct radeon_device
*rdev
)
455 u32 tmp
= RREG32(MC_SHARED_CHMAP
);
457 switch ((tmp
& NOOFCHAN_MASK
) >> NOOFCHAN_SHIFT
) {
480 struct dce6_wm_params
{
481 u32 dram_channels
; /* number of dram channels */
482 u32 yclk
; /* bandwidth per dram data pin in kHz */
483 u32 sclk
; /* engine clock in kHz */
484 u32 disp_clk
; /* display clock in kHz */
485 u32 src_width
; /* viewport width */
486 u32 active_time
; /* active display time in ns */
487 u32 blank_time
; /* blank time in ns */
488 bool interlaced
; /* mode is interlaced */
489 fixed20_12 vsc
; /* vertical scale ratio */
490 u32 num_heads
; /* number of active crtcs */
491 u32 bytes_per_pixel
; /* bytes per pixel display + overlay */
492 u32 lb_size
; /* line buffer allocated to pipe */
493 u32 vtaps
; /* vertical scaler taps */
496 static u32
dce6_dram_bandwidth(struct dce6_wm_params
*wm
)
498 /* Calculate raw DRAM Bandwidth */
499 fixed20_12 dram_efficiency
; /* 0.7 */
500 fixed20_12 yclk
, dram_channels
, bandwidth
;
503 a
.full
= dfixed_const(1000);
504 yclk
.full
= dfixed_const(wm
->yclk
);
505 yclk
.full
= dfixed_div(yclk
, a
);
506 dram_channels
.full
= dfixed_const(wm
->dram_channels
* 4);
507 a
.full
= dfixed_const(10);
508 dram_efficiency
.full
= dfixed_const(7);
509 dram_efficiency
.full
= dfixed_div(dram_efficiency
, a
);
510 bandwidth
.full
= dfixed_mul(dram_channels
, yclk
);
511 bandwidth
.full
= dfixed_mul(bandwidth
, dram_efficiency
);
513 return dfixed_trunc(bandwidth
);
516 static u32
dce6_dram_bandwidth_for_display(struct dce6_wm_params
*wm
)
518 /* Calculate DRAM Bandwidth and the part allocated to display. */
519 fixed20_12 disp_dram_allocation
; /* 0.3 to 0.7 */
520 fixed20_12 yclk
, dram_channels
, bandwidth
;
523 a
.full
= dfixed_const(1000);
524 yclk
.full
= dfixed_const(wm
->yclk
);
525 yclk
.full
= dfixed_div(yclk
, a
);
526 dram_channels
.full
= dfixed_const(wm
->dram_channels
* 4);
527 a
.full
= dfixed_const(10);
528 disp_dram_allocation
.full
= dfixed_const(3); /* XXX worse case value 0.3 */
529 disp_dram_allocation
.full
= dfixed_div(disp_dram_allocation
, a
);
530 bandwidth
.full
= dfixed_mul(dram_channels
, yclk
);
531 bandwidth
.full
= dfixed_mul(bandwidth
, disp_dram_allocation
);
533 return dfixed_trunc(bandwidth
);
536 static u32
dce6_data_return_bandwidth(struct dce6_wm_params
*wm
)
538 /* Calculate the display Data return Bandwidth */
539 fixed20_12 return_efficiency
; /* 0.8 */
540 fixed20_12 sclk
, bandwidth
;
543 a
.full
= dfixed_const(1000);
544 sclk
.full
= dfixed_const(wm
->sclk
);
545 sclk
.full
= dfixed_div(sclk
, a
);
546 a
.full
= dfixed_const(10);
547 return_efficiency
.full
= dfixed_const(8);
548 return_efficiency
.full
= dfixed_div(return_efficiency
, a
);
549 a
.full
= dfixed_const(32);
550 bandwidth
.full
= dfixed_mul(a
, sclk
);
551 bandwidth
.full
= dfixed_mul(bandwidth
, return_efficiency
);
553 return dfixed_trunc(bandwidth
);
556 static u32
dce6_get_dmif_bytes_per_request(struct dce6_wm_params
*wm
)
561 static u32
dce6_dmif_request_bandwidth(struct dce6_wm_params
*wm
)
563 /* Calculate the DMIF Request Bandwidth */
564 fixed20_12 disp_clk_request_efficiency
; /* 0.8 */
565 fixed20_12 disp_clk
, sclk
, bandwidth
;
566 fixed20_12 a
, b1
, b2
;
569 a
.full
= dfixed_const(1000);
570 disp_clk
.full
= dfixed_const(wm
->disp_clk
);
571 disp_clk
.full
= dfixed_div(disp_clk
, a
);
572 a
.full
= dfixed_const(dce6_get_dmif_bytes_per_request(wm
) / 2);
573 b1
.full
= dfixed_mul(a
, disp_clk
);
575 a
.full
= dfixed_const(1000);
576 sclk
.full
= dfixed_const(wm
->sclk
);
577 sclk
.full
= dfixed_div(sclk
, a
);
578 a
.full
= dfixed_const(dce6_get_dmif_bytes_per_request(wm
));
579 b2
.full
= dfixed_mul(a
, sclk
);
581 a
.full
= dfixed_const(10);
582 disp_clk_request_efficiency
.full
= dfixed_const(8);
583 disp_clk_request_efficiency
.full
= dfixed_div(disp_clk_request_efficiency
, a
);
585 min_bandwidth
= min(dfixed_trunc(b1
), dfixed_trunc(b2
));
587 a
.full
= dfixed_const(min_bandwidth
);
588 bandwidth
.full
= dfixed_mul(a
, disp_clk_request_efficiency
);
590 return dfixed_trunc(bandwidth
);
593 static u32
dce6_available_bandwidth(struct dce6_wm_params
*wm
)
595 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
596 u32 dram_bandwidth
= dce6_dram_bandwidth(wm
);
597 u32 data_return_bandwidth
= dce6_data_return_bandwidth(wm
);
598 u32 dmif_req_bandwidth
= dce6_dmif_request_bandwidth(wm
);
600 return min(dram_bandwidth
, min(data_return_bandwidth
, dmif_req_bandwidth
));
603 static u32
dce6_average_bandwidth(struct dce6_wm_params
*wm
)
605 /* Calculate the display mode Average Bandwidth
606 * DisplayMode should contain the source and destination dimensions,
610 fixed20_12 line_time
;
611 fixed20_12 src_width
;
612 fixed20_12 bandwidth
;
615 a
.full
= dfixed_const(1000);
616 line_time
.full
= dfixed_const(wm
->active_time
+ wm
->blank_time
);
617 line_time
.full
= dfixed_div(line_time
, a
);
618 bpp
.full
= dfixed_const(wm
->bytes_per_pixel
);
619 src_width
.full
= dfixed_const(wm
->src_width
);
620 bandwidth
.full
= dfixed_mul(src_width
, bpp
);
621 bandwidth
.full
= dfixed_mul(bandwidth
, wm
->vsc
);
622 bandwidth
.full
= dfixed_div(bandwidth
, line_time
);
624 return dfixed_trunc(bandwidth
);
627 static u32
dce6_latency_watermark(struct dce6_wm_params
*wm
)
629 /* First calcualte the latency in ns */
630 u32 mc_latency
= 2000; /* 2000 ns. */
631 u32 available_bandwidth
= dce6_available_bandwidth(wm
);
632 u32 worst_chunk_return_time
= (512 * 8 * 1000) / available_bandwidth
;
633 u32 cursor_line_pair_return_time
= (128 * 4 * 1000) / available_bandwidth
;
634 u32 dc_latency
= 40000000 / wm
->disp_clk
; /* dc pipe latency */
635 u32 other_heads_data_return_time
= ((wm
->num_heads
+ 1) * worst_chunk_return_time
) +
636 (wm
->num_heads
* cursor_line_pair_return_time
);
637 u32 latency
= mc_latency
+ other_heads_data_return_time
+ dc_latency
;
638 u32 max_src_lines_per_dst_line
, lb_fill_bw
, line_fill_time
;
639 u32 tmp
, dmif_size
= 12288;
642 if (wm
->num_heads
== 0)
645 a
.full
= dfixed_const(2);
646 b
.full
= dfixed_const(1);
647 if ((wm
->vsc
.full
> a
.full
) ||
648 ((wm
->vsc
.full
> b
.full
) && (wm
->vtaps
>= 3)) ||
650 ((wm
->vsc
.full
>= a
.full
) && wm
->interlaced
))
651 max_src_lines_per_dst_line
= 4;
653 max_src_lines_per_dst_line
= 2;
655 a
.full
= dfixed_const(available_bandwidth
);
656 b
.full
= dfixed_const(wm
->num_heads
);
657 a
.full
= dfixed_div(a
, b
);
659 b
.full
= dfixed_const(mc_latency
+ 512);
660 c
.full
= dfixed_const(wm
->disp_clk
);
661 b
.full
= dfixed_div(b
, c
);
663 c
.full
= dfixed_const(dmif_size
);
664 b
.full
= dfixed_div(c
, b
);
666 tmp
= min(dfixed_trunc(a
), dfixed_trunc(b
));
668 b
.full
= dfixed_const(1000);
669 c
.full
= dfixed_const(wm
->disp_clk
);
670 b
.full
= dfixed_div(c
, b
);
671 c
.full
= dfixed_const(wm
->bytes_per_pixel
);
672 b
.full
= dfixed_mul(b
, c
);
674 lb_fill_bw
= min(tmp
, dfixed_trunc(b
));
676 a
.full
= dfixed_const(max_src_lines_per_dst_line
* wm
->src_width
* wm
->bytes_per_pixel
);
677 b
.full
= dfixed_const(1000);
678 c
.full
= dfixed_const(lb_fill_bw
);
679 b
.full
= dfixed_div(c
, b
);
680 a
.full
= dfixed_div(a
, b
);
681 line_fill_time
= dfixed_trunc(a
);
683 if (line_fill_time
< wm
->active_time
)
686 return latency
+ (line_fill_time
- wm
->active_time
);
690 static bool dce6_average_bandwidth_vs_dram_bandwidth_for_display(struct dce6_wm_params
*wm
)
692 if (dce6_average_bandwidth(wm
) <=
693 (dce6_dram_bandwidth_for_display(wm
) / wm
->num_heads
))
699 static bool dce6_average_bandwidth_vs_available_bandwidth(struct dce6_wm_params
*wm
)
701 if (dce6_average_bandwidth(wm
) <=
702 (dce6_available_bandwidth(wm
) / wm
->num_heads
))
708 static bool dce6_check_latency_hiding(struct dce6_wm_params
*wm
)
710 u32 lb_partitions
= wm
->lb_size
/ wm
->src_width
;
711 u32 line_time
= wm
->active_time
+ wm
->blank_time
;
712 u32 latency_tolerant_lines
;
716 a
.full
= dfixed_const(1);
717 if (wm
->vsc
.full
> a
.full
)
718 latency_tolerant_lines
= 1;
720 if (lb_partitions
<= (wm
->vtaps
+ 1))
721 latency_tolerant_lines
= 1;
723 latency_tolerant_lines
= 2;
726 latency_hiding
= (latency_tolerant_lines
* line_time
+ wm
->blank_time
);
728 if (dce6_latency_watermark(wm
) <= latency_hiding
)
734 static void dce6_program_watermarks(struct radeon_device
*rdev
,
735 struct radeon_crtc
*radeon_crtc
,
736 u32 lb_size
, u32 num_heads
)
738 struct drm_display_mode
*mode
= &radeon_crtc
->base
.mode
;
739 struct dce6_wm_params wm
;
742 u32 latency_watermark_a
= 0, latency_watermark_b
= 0;
743 u32 priority_a_mark
= 0, priority_b_mark
= 0;
744 u32 priority_a_cnt
= PRIORITY_OFF
;
745 u32 priority_b_cnt
= PRIORITY_OFF
;
746 u32 tmp
, arb_control3
;
749 if (radeon_crtc
->base
.enabled
&& num_heads
&& mode
) {
750 pixel_period
= 1000000 / (u32
)mode
->clock
;
751 line_time
= min((u32
)mode
->crtc_htotal
* pixel_period
, (u32
)65535);
755 wm
.yclk
= rdev
->pm
.current_mclk
* 10;
756 wm
.sclk
= rdev
->pm
.current_sclk
* 10;
757 wm
.disp_clk
= mode
->clock
;
758 wm
.src_width
= mode
->crtc_hdisplay
;
759 wm
.active_time
= mode
->crtc_hdisplay
* pixel_period
;
760 wm
.blank_time
= line_time
- wm
.active_time
;
761 wm
.interlaced
= false;
762 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
763 wm
.interlaced
= true;
764 wm
.vsc
= radeon_crtc
->vsc
;
766 if (radeon_crtc
->rmx_type
!= RMX_OFF
)
768 wm
.bytes_per_pixel
= 4; /* XXX: get this from fb config */
769 wm
.lb_size
= lb_size
;
770 if (rdev
->family
== CHIP_ARUBA
)
771 wm
.dram_channels
= evergreen_get_number_of_dram_channels(rdev
);
773 wm
.dram_channels
= si_get_number_of_dram_channels(rdev
);
774 wm
.num_heads
= num_heads
;
776 /* set for high clocks */
777 latency_watermark_a
= min(dce6_latency_watermark(&wm
), (u32
)65535);
778 /* set for low clocks */
779 /* wm.yclk = low clk; wm.sclk = low clk */
780 latency_watermark_b
= min(dce6_latency_watermark(&wm
), (u32
)65535);
782 /* possibly force display priority to high */
783 /* should really do this at mode validation time... */
784 if (!dce6_average_bandwidth_vs_dram_bandwidth_for_display(&wm
) ||
785 !dce6_average_bandwidth_vs_available_bandwidth(&wm
) ||
786 !dce6_check_latency_hiding(&wm
) ||
787 (rdev
->disp_priority
== 2)) {
788 DRM_DEBUG_KMS("force priority to high\n");
789 priority_a_cnt
|= PRIORITY_ALWAYS_ON
;
790 priority_b_cnt
|= PRIORITY_ALWAYS_ON
;
793 a
.full
= dfixed_const(1000);
794 b
.full
= dfixed_const(mode
->clock
);
795 b
.full
= dfixed_div(b
, a
);
796 c
.full
= dfixed_const(latency_watermark_a
);
797 c
.full
= dfixed_mul(c
, b
);
798 c
.full
= dfixed_mul(c
, radeon_crtc
->hsc
);
799 c
.full
= dfixed_div(c
, a
);
800 a
.full
= dfixed_const(16);
801 c
.full
= dfixed_div(c
, a
);
802 priority_a_mark
= dfixed_trunc(c
);
803 priority_a_cnt
|= priority_a_mark
& PRIORITY_MARK_MASK
;
805 a
.full
= dfixed_const(1000);
806 b
.full
= dfixed_const(mode
->clock
);
807 b
.full
= dfixed_div(b
, a
);
808 c
.full
= dfixed_const(latency_watermark_b
);
809 c
.full
= dfixed_mul(c
, b
);
810 c
.full
= dfixed_mul(c
, radeon_crtc
->hsc
);
811 c
.full
= dfixed_div(c
, a
);
812 a
.full
= dfixed_const(16);
813 c
.full
= dfixed_div(c
, a
);
814 priority_b_mark
= dfixed_trunc(c
);
815 priority_b_cnt
|= priority_b_mark
& PRIORITY_MARK_MASK
;
819 arb_control3
= RREG32(DPG_PIPE_ARBITRATION_CONTROL3
+ radeon_crtc
->crtc_offset
);
821 tmp
&= ~LATENCY_WATERMARK_MASK(3);
822 tmp
|= LATENCY_WATERMARK_MASK(1);
823 WREG32(DPG_PIPE_ARBITRATION_CONTROL3
+ radeon_crtc
->crtc_offset
, tmp
);
824 WREG32(DPG_PIPE_LATENCY_CONTROL
+ radeon_crtc
->crtc_offset
,
825 (LATENCY_LOW_WATERMARK(latency_watermark_a
) |
826 LATENCY_HIGH_WATERMARK(line_time
)));
828 tmp
= RREG32(DPG_PIPE_ARBITRATION_CONTROL3
+ radeon_crtc
->crtc_offset
);
829 tmp
&= ~LATENCY_WATERMARK_MASK(3);
830 tmp
|= LATENCY_WATERMARK_MASK(2);
831 WREG32(DPG_PIPE_ARBITRATION_CONTROL3
+ radeon_crtc
->crtc_offset
, tmp
);
832 WREG32(DPG_PIPE_LATENCY_CONTROL
+ radeon_crtc
->crtc_offset
,
833 (LATENCY_LOW_WATERMARK(latency_watermark_b
) |
834 LATENCY_HIGH_WATERMARK(line_time
)));
835 /* restore original selection */
836 WREG32(DPG_PIPE_ARBITRATION_CONTROL3
+ radeon_crtc
->crtc_offset
, arb_control3
);
838 /* write the priority marks */
839 WREG32(PRIORITY_A_CNT
+ radeon_crtc
->crtc_offset
, priority_a_cnt
);
840 WREG32(PRIORITY_B_CNT
+ radeon_crtc
->crtc_offset
, priority_b_cnt
);
844 void dce6_bandwidth_update(struct radeon_device
*rdev
)
846 struct drm_display_mode
*mode0
= NULL
;
847 struct drm_display_mode
*mode1
= NULL
;
848 u32 num_heads
= 0, lb_size
;
851 radeon_update_display_priority(rdev
);
853 for (i
= 0; i
< rdev
->num_crtc
; i
++) {
854 if (rdev
->mode_info
.crtcs
[i
]->base
.enabled
)
857 for (i
= 0; i
< rdev
->num_crtc
; i
+= 2) {
858 mode0
= &rdev
->mode_info
.crtcs
[i
]->base
.mode
;
859 mode1
= &rdev
->mode_info
.crtcs
[i
+1]->base
.mode
;
860 lb_size
= dce6_line_buffer_adjust(rdev
, rdev
->mode_info
.crtcs
[i
], mode0
, mode1
);
861 dce6_program_watermarks(rdev
, rdev
->mode_info
.crtcs
[i
], lb_size
, num_heads
);
862 lb_size
= dce6_line_buffer_adjust(rdev
, rdev
->mode_info
.crtcs
[i
+1], mode1
, mode0
);
863 dce6_program_watermarks(rdev
, rdev
->mode_info
.crtcs
[i
+1], lb_size
, num_heads
);
870 static void si_tiling_mode_table_init(struct radeon_device
*rdev
)
872 const u32 num_tile_mode_states
= 32;
873 u32 reg_offset
, gb_tile_moden
, split_equal_to_row_size
;
875 switch (rdev
->config
.si
.mem_row_size_in_kb
) {
877 split_equal_to_row_size
= ADDR_SURF_TILE_SPLIT_1KB
;
881 split_equal_to_row_size
= ADDR_SURF_TILE_SPLIT_2KB
;
884 split_equal_to_row_size
= ADDR_SURF_TILE_SPLIT_4KB
;
888 if ((rdev
->family
== CHIP_TAHITI
) ||
889 (rdev
->family
== CHIP_PITCAIRN
)) {
890 for (reg_offset
= 0; reg_offset
< num_tile_mode_states
; reg_offset
++) {
891 switch (reg_offset
) {
892 case 0: /* non-AA compressed depth or any compressed stencil */
893 gb_tile_moden
= (ARRAY_MODE(ARRAY_2D_TILED_THIN1
) |
894 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING
) |
895 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16
) |
896 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B
) |
897 NUM_BANKS(ADDR_SURF_16_BANK
) |
898 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1
) |
899 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4
) |
900 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2
));
902 case 1: /* 2xAA/4xAA compressed depth only */
903 gb_tile_moden
= (ARRAY_MODE(ARRAY_2D_TILED_THIN1
) |
904 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING
) |
905 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16
) |
906 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B
) |
907 NUM_BANKS(ADDR_SURF_16_BANK
) |
908 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1
) |
909 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4
) |
910 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2
));
912 case 2: /* 8xAA compressed depth only */
913 gb_tile_moden
= (ARRAY_MODE(ARRAY_2D_TILED_THIN1
) |
914 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING
) |
915 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16
) |
916 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B
) |
917 NUM_BANKS(ADDR_SURF_16_BANK
) |
918 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1
) |
919 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4
) |
920 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2
));
922 case 3: /* 2xAA/4xAA compressed depth with stencil (for depth buffer) */
923 gb_tile_moden
= (ARRAY_MODE(ARRAY_2D_TILED_THIN1
) |
924 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING
) |
925 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16
) |
926 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B
) |
927 NUM_BANKS(ADDR_SURF_16_BANK
) |
928 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1
) |
929 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4
) |
930 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2
));
932 case 4: /* Maps w/ a dimension less than the 2D macro-tile dimensions (for mipmapped depth textures) */
933 gb_tile_moden
= (ARRAY_MODE(ARRAY_1D_TILED_THIN1
) |
934 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING
) |
935 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16
) |
936 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B
) |
937 NUM_BANKS(ADDR_SURF_16_BANK
) |
938 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1
) |
939 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2
) |
940 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2
));
942 case 5: /* Uncompressed 16bpp depth - and stencil buffer allocated with it */
943 gb_tile_moden
= (ARRAY_MODE(ARRAY_2D_TILED_THIN1
) |
944 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING
) |
945 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16
) |
946 TILE_SPLIT(split_equal_to_row_size
) |
947 NUM_BANKS(ADDR_SURF_16_BANK
) |
948 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1
) |
949 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2
) |
950 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2
));
952 case 6: /* Uncompressed 32bpp depth - and stencil buffer allocated with it */
953 gb_tile_moden
= (ARRAY_MODE(ARRAY_2D_TILED_THIN1
) |
954 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING
) |
955 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16
) |
956 TILE_SPLIT(split_equal_to_row_size
) |
957 NUM_BANKS(ADDR_SURF_16_BANK
) |
958 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1
) |
959 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1
) |
960 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1
));
962 case 7: /* Uncompressed 8bpp stencil without depth (drivers typically do not use) */
963 gb_tile_moden
= (ARRAY_MODE(ARRAY_2D_TILED_THIN1
) |
964 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING
) |
965 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16
) |
966 TILE_SPLIT(split_equal_to_row_size
) |
967 NUM_BANKS(ADDR_SURF_16_BANK
) |
968 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1
) |
969 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4
) |
970 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2
));
972 case 8: /* 1D and 1D Array Surfaces */
973 gb_tile_moden
= (ARRAY_MODE(ARRAY_LINEAR_ALIGNED
) |
974 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING
) |
975 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16
) |
976 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B
) |
977 NUM_BANKS(ADDR_SURF_16_BANK
) |
978 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1
) |
979 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2
) |
980 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2
));
982 case 9: /* Displayable maps. */
983 gb_tile_moden
= (ARRAY_MODE(ARRAY_1D_TILED_THIN1
) |
984 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING
) |
985 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16
) |
986 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B
) |
987 NUM_BANKS(ADDR_SURF_16_BANK
) |
988 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1
) |
989 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2
) |
990 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2
));
992 case 10: /* Display 8bpp. */
993 gb_tile_moden
= (ARRAY_MODE(ARRAY_2D_TILED_THIN1
) |
994 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING
) |
995 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16
) |
996 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B
) |
997 NUM_BANKS(ADDR_SURF_16_BANK
) |
998 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1
) |
999 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4
) |
1000 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2
));
1002 case 11: /* Display 16bpp. */
1003 gb_tile_moden
= (ARRAY_MODE(ARRAY_2D_TILED_THIN1
) |
1004 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING
) |
1005 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16
) |
1006 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B
) |
1007 NUM_BANKS(ADDR_SURF_16_BANK
) |
1008 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1
) |
1009 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2
) |
1010 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2
));
1012 case 12: /* Display 32bpp. */
1013 gb_tile_moden
= (ARRAY_MODE(ARRAY_2D_TILED_THIN1
) |
1014 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING
) |
1015 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16
) |
1016 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B
) |
1017 NUM_BANKS(ADDR_SURF_16_BANK
) |
1018 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1
) |
1019 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1
) |
1020 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1
));
1022 case 13: /* Thin. */
1023 gb_tile_moden
= (ARRAY_MODE(ARRAY_1D_TILED_THIN1
) |
1024 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING
) |
1025 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16
) |
1026 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B
) |
1027 NUM_BANKS(ADDR_SURF_16_BANK
) |
1028 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1
) |
1029 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2
) |
1030 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2
));
1032 case 14: /* Thin 8 bpp. */
1033 gb_tile_moden
= (ARRAY_MODE(ARRAY_2D_TILED_THIN1
) |
1034 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING
) |
1035 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16
) |
1036 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B
) |
1037 NUM_BANKS(ADDR_SURF_16_BANK
) |
1038 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1
) |
1039 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4
) |
1040 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1
));
1042 case 15: /* Thin 16 bpp. */
1043 gb_tile_moden
= (ARRAY_MODE(ARRAY_2D_TILED_THIN1
) |
1044 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING
) |
1045 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16
) |
1046 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B
) |
1047 NUM_BANKS(ADDR_SURF_16_BANK
) |
1048 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1
) |
1049 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2
) |
1050 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1
));
1052 case 16: /* Thin 32 bpp. */
1053 gb_tile_moden
= (ARRAY_MODE(ARRAY_2D_TILED_THIN1
) |
1054 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING
) |
1055 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16
) |
1056 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B
) |
1057 NUM_BANKS(ADDR_SURF_16_BANK
) |
1058 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1
) |
1059 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1
) |
1060 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1
));
1062 case 17: /* Thin 64 bpp. */
1063 gb_tile_moden
= (ARRAY_MODE(ARRAY_2D_TILED_THIN1
) |
1064 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING
) |
1065 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16
) |
1066 TILE_SPLIT(split_equal_to_row_size
) |
1067 NUM_BANKS(ADDR_SURF_16_BANK
) |
1068 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1
) |
1069 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1
) |
1070 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1
));
1072 case 21: /* 8 bpp PRT. */
1073 gb_tile_moden
= (ARRAY_MODE(ARRAY_2D_TILED_THIN1
) |
1074 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING
) |
1075 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16
) |
1076 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B
) |
1077 NUM_BANKS(ADDR_SURF_16_BANK
) |
1078 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2
) |
1079 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4
) |
1080 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2
));
1082 case 22: /* 16 bpp PRT */
1083 gb_tile_moden
= (ARRAY_MODE(ARRAY_2D_TILED_THIN1
) |
1084 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING
) |
1085 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16
) |
1086 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B
) |
1087 NUM_BANKS(ADDR_SURF_16_BANK
) |
1088 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1
) |
1089 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4
) |
1090 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4
));
1092 case 23: /* 32 bpp PRT */
1093 gb_tile_moden
= (ARRAY_MODE(ARRAY_2D_TILED_THIN1
) |
1094 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING
) |
1095 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16
) |
1096 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B
) |
1097 NUM_BANKS(ADDR_SURF_16_BANK
) |
1098 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1
) |
1099 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2
) |
1100 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2
));
1102 case 24: /* 64 bpp PRT */
1103 gb_tile_moden
= (ARRAY_MODE(ARRAY_2D_TILED_THIN1
) |
1104 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING
) |
1105 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16
) |
1106 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B
) |
1107 NUM_BANKS(ADDR_SURF_16_BANK
) |
1108 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1
) |
1109 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1
) |
1110 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2
));
1112 case 25: /* 128 bpp PRT */
1113 gb_tile_moden
= (ARRAY_MODE(ARRAY_2D_TILED_THIN1
) |
1114 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING
) |
1115 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16
) |
1116 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB
) |
1117 NUM_BANKS(ADDR_SURF_8_BANK
) |
1118 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1
) |
1119 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1
) |
1120 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1
));
1126 WREG32(GB_TILE_MODE0
+ (reg_offset
* 4), gb_tile_moden
);
1128 } else if (rdev
->family
== CHIP_VERDE
) {
1129 for (reg_offset
= 0; reg_offset
< num_tile_mode_states
; reg_offset
++) {
1130 switch (reg_offset
) {
1131 case 0: /* non-AA compressed depth or any compressed stencil */
1132 gb_tile_moden
= (ARRAY_MODE(ARRAY_2D_TILED_THIN1
) |
1133 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING
) |
1134 PIPE_CONFIG(ADDR_SURF_P4_8x16
) |
1135 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B
) |
1136 NUM_BANKS(ADDR_SURF_16_BANK
) |
1137 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1
) |
1138 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4
) |
1139 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4
));
1141 case 1: /* 2xAA/4xAA compressed depth only */
1142 gb_tile_moden
= (ARRAY_MODE(ARRAY_2D_TILED_THIN1
) |
1143 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING
) |
1144 PIPE_CONFIG(ADDR_SURF_P4_8x16
) |
1145 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B
) |
1146 NUM_BANKS(ADDR_SURF_16_BANK
) |
1147 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1
) |
1148 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4
) |
1149 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4
));
1151 case 2: /* 8xAA compressed depth only */
1152 gb_tile_moden
= (ARRAY_MODE(ARRAY_2D_TILED_THIN1
) |
1153 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING
) |
1154 PIPE_CONFIG(ADDR_SURF_P4_8x16
) |
1155 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B
) |
1156 NUM_BANKS(ADDR_SURF_16_BANK
) |
1157 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1
) |
1158 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4
) |
1159 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4
));
1161 case 3: /* 2xAA/4xAA compressed depth with stencil (for depth buffer) */
1162 gb_tile_moden
= (ARRAY_MODE(ARRAY_2D_TILED_THIN1
) |
1163 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING
) |
1164 PIPE_CONFIG(ADDR_SURF_P4_8x16
) |
1165 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B
) |
1166 NUM_BANKS(ADDR_SURF_16_BANK
) |
1167 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1
) |
1168 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4
) |
1169 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4
));
1171 case 4: /* Maps w/ a dimension less than the 2D macro-tile dimensions (for mipmapped depth textures) */
1172 gb_tile_moden
= (ARRAY_MODE(ARRAY_1D_TILED_THIN1
) |
1173 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING
) |
1174 PIPE_CONFIG(ADDR_SURF_P4_8x16
) |
1175 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B
) |
1176 NUM_BANKS(ADDR_SURF_16_BANK
) |
1177 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1
) |
1178 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2
) |
1179 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2
));
1181 case 5: /* Uncompressed 16bpp depth - and stencil buffer allocated with it */
1182 gb_tile_moden
= (ARRAY_MODE(ARRAY_2D_TILED_THIN1
) |
1183 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING
) |
1184 PIPE_CONFIG(ADDR_SURF_P4_8x16
) |
1185 TILE_SPLIT(split_equal_to_row_size
) |
1186 NUM_BANKS(ADDR_SURF_16_BANK
) |
1187 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1
) |
1188 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2
) |
1189 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2
));
1191 case 6: /* Uncompressed 32bpp depth - and stencil buffer allocated with it */
1192 gb_tile_moden
= (ARRAY_MODE(ARRAY_2D_TILED_THIN1
) |
1193 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING
) |
1194 PIPE_CONFIG(ADDR_SURF_P4_8x16
) |
1195 TILE_SPLIT(split_equal_to_row_size
) |
1196 NUM_BANKS(ADDR_SURF_16_BANK
) |
1197 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1
) |
1198 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1
) |
1199 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2
));
1201 case 7: /* Uncompressed 8bpp stencil without depth (drivers typically do not use) */
1202 gb_tile_moden
= (ARRAY_MODE(ARRAY_2D_TILED_THIN1
) |
1203 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING
) |
1204 PIPE_CONFIG(ADDR_SURF_P4_8x16
) |
1205 TILE_SPLIT(split_equal_to_row_size
) |
1206 NUM_BANKS(ADDR_SURF_16_BANK
) |
1207 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1
) |
1208 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4
) |
1209 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4
));
1211 case 8: /* 1D and 1D Array Surfaces */
1212 gb_tile_moden
= (ARRAY_MODE(ARRAY_LINEAR_ALIGNED
) |
1213 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING
) |
1214 PIPE_CONFIG(ADDR_SURF_P4_8x16
) |
1215 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B
) |
1216 NUM_BANKS(ADDR_SURF_16_BANK
) |
1217 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1
) |
1218 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2
) |
1219 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2
));
1221 case 9: /* Displayable maps. */
1222 gb_tile_moden
= (ARRAY_MODE(ARRAY_1D_TILED_THIN1
) |
1223 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING
) |
1224 PIPE_CONFIG(ADDR_SURF_P4_8x16
) |
1225 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B
) |
1226 NUM_BANKS(ADDR_SURF_16_BANK
) |
1227 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1
) |
1228 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2
) |
1229 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2
));
1231 case 10: /* Display 8bpp. */
1232 gb_tile_moden
= (ARRAY_MODE(ARRAY_2D_TILED_THIN1
) |
1233 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING
) |
1234 PIPE_CONFIG(ADDR_SURF_P4_8x16
) |
1235 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B
) |
1236 NUM_BANKS(ADDR_SURF_16_BANK
) |
1237 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1
) |
1238 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4
) |
1239 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4
));
1241 case 11: /* Display 16bpp. */
1242 gb_tile_moden
= (ARRAY_MODE(ARRAY_2D_TILED_THIN1
) |
1243 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING
) |
1244 PIPE_CONFIG(ADDR_SURF_P4_8x16
) |
1245 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B
) |
1246 NUM_BANKS(ADDR_SURF_16_BANK
) |
1247 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1
) |
1248 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2
) |
1249 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2
));
1251 case 12: /* Display 32bpp. */
1252 gb_tile_moden
= (ARRAY_MODE(ARRAY_2D_TILED_THIN1
) |
1253 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING
) |
1254 PIPE_CONFIG(ADDR_SURF_P4_8x16
) |
1255 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B
) |
1256 NUM_BANKS(ADDR_SURF_16_BANK
) |
1257 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1
) |
1258 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1
) |
1259 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2
));
1261 case 13: /* Thin. */
1262 gb_tile_moden
= (ARRAY_MODE(ARRAY_1D_TILED_THIN1
) |
1263 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING
) |
1264 PIPE_CONFIG(ADDR_SURF_P4_8x16
) |
1265 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B
) |
1266 NUM_BANKS(ADDR_SURF_16_BANK
) |
1267 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1
) |
1268 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2
) |
1269 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2
));
1271 case 14: /* Thin 8 bpp. */
1272 gb_tile_moden
= (ARRAY_MODE(ARRAY_2D_TILED_THIN1
) |
1273 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING
) |
1274 PIPE_CONFIG(ADDR_SURF_P4_8x16
) |
1275 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B
) |
1276 NUM_BANKS(ADDR_SURF_16_BANK
) |
1277 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1
) |
1278 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4
) |
1279 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2
));
1281 case 15: /* Thin 16 bpp. */
1282 gb_tile_moden
= (ARRAY_MODE(ARRAY_2D_TILED_THIN1
) |
1283 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING
) |
1284 PIPE_CONFIG(ADDR_SURF_P4_8x16
) |
1285 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B
) |
1286 NUM_BANKS(ADDR_SURF_16_BANK
) |
1287 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1
) |
1288 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2
) |
1289 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2
));
1291 case 16: /* Thin 32 bpp. */
1292 gb_tile_moden
= (ARRAY_MODE(ARRAY_2D_TILED_THIN1
) |
1293 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING
) |
1294 PIPE_CONFIG(ADDR_SURF_P4_8x16
) |
1295 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B
) |
1296 NUM_BANKS(ADDR_SURF_16_BANK
) |
1297 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1
) |
1298 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1
) |
1299 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2
));
1301 case 17: /* Thin 64 bpp. */
1302 gb_tile_moden
= (ARRAY_MODE(ARRAY_2D_TILED_THIN1
) |
1303 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING
) |
1304 PIPE_CONFIG(ADDR_SURF_P4_8x16
) |
1305 TILE_SPLIT(split_equal_to_row_size
) |
1306 NUM_BANKS(ADDR_SURF_16_BANK
) |
1307 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1
) |
1308 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1
) |
1309 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2
));
1311 case 21: /* 8 bpp PRT. */
1312 gb_tile_moden
= (ARRAY_MODE(ARRAY_2D_TILED_THIN1
) |
1313 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING
) |
1314 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16
) |
1315 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B
) |
1316 NUM_BANKS(ADDR_SURF_16_BANK
) |
1317 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2
) |
1318 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4
) |
1319 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2
));
1321 case 22: /* 16 bpp PRT */
1322 gb_tile_moden
= (ARRAY_MODE(ARRAY_2D_TILED_THIN1
) |
1323 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING
) |
1324 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16
) |
1325 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B
) |
1326 NUM_BANKS(ADDR_SURF_16_BANK
) |
1327 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1
) |
1328 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4
) |
1329 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4
));
1331 case 23: /* 32 bpp PRT */
1332 gb_tile_moden
= (ARRAY_MODE(ARRAY_2D_TILED_THIN1
) |
1333 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING
) |
1334 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16
) |
1335 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B
) |
1336 NUM_BANKS(ADDR_SURF_16_BANK
) |
1337 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1
) |
1338 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2
) |
1339 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2
));
1341 case 24: /* 64 bpp PRT */
1342 gb_tile_moden
= (ARRAY_MODE(ARRAY_2D_TILED_THIN1
) |
1343 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING
) |
1344 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16
) |
1345 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B
) |
1346 NUM_BANKS(ADDR_SURF_16_BANK
) |
1347 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1
) |
1348 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1
) |
1349 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2
));
1351 case 25: /* 128 bpp PRT */
1352 gb_tile_moden
= (ARRAY_MODE(ARRAY_2D_TILED_THIN1
) |
1353 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING
) |
1354 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16
) |
1355 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB
) |
1356 NUM_BANKS(ADDR_SURF_8_BANK
) |
1357 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1
) |
1358 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1
) |
1359 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1
));
1365 WREG32(GB_TILE_MODE0
+ (reg_offset
* 4), gb_tile_moden
);
1368 DRM_ERROR("unknown asic: 0x%x\n", rdev
->family
);
1371 static void si_select_se_sh(struct radeon_device
*rdev
,
1372 u32 se_num
, u32 sh_num
)
1374 u32 data
= INSTANCE_BROADCAST_WRITES
;
1376 if ((se_num
== 0xffffffff) && (sh_num
== 0xffffffff))
1377 data
= SH_BROADCAST_WRITES
| SE_BROADCAST_WRITES
;
1378 else if (se_num
== 0xffffffff)
1379 data
|= SE_BROADCAST_WRITES
| SH_INDEX(sh_num
);
1380 else if (sh_num
== 0xffffffff)
1381 data
|= SH_BROADCAST_WRITES
| SE_INDEX(se_num
);
1383 data
|= SH_INDEX(sh_num
) | SE_INDEX(se_num
);
1384 WREG32(GRBM_GFX_INDEX
, data
);
1387 static u32
si_create_bitmask(u32 bit_width
)
1391 for (i
= 0; i
< bit_width
; i
++) {
1398 static u32
si_get_cu_enabled(struct radeon_device
*rdev
, u32 cu_per_sh
)
1402 data
= RREG32(CC_GC_SHADER_ARRAY_CONFIG
);
1404 data
&= INACTIVE_CUS_MASK
;
1407 data
|= RREG32(GC_USER_SHADER_ARRAY_CONFIG
);
1409 data
>>= INACTIVE_CUS_SHIFT
;
1411 mask
= si_create_bitmask(cu_per_sh
);
1413 return ~data
& mask
;
1416 static void si_setup_spi(struct radeon_device
*rdev
,
1417 u32 se_num
, u32 sh_per_se
,
1421 u32 data
, mask
, active_cu
;
1423 for (i
= 0; i
< se_num
; i
++) {
1424 for (j
= 0; j
< sh_per_se
; j
++) {
1425 si_select_se_sh(rdev
, i
, j
);
1426 data
= RREG32(SPI_STATIC_THREAD_MGMT_3
);
1427 active_cu
= si_get_cu_enabled(rdev
, cu_per_sh
);
1430 for (k
= 0; k
< 16; k
++) {
1432 if (active_cu
& mask
) {
1434 WREG32(SPI_STATIC_THREAD_MGMT_3
, data
);
1440 si_select_se_sh(rdev
, 0xffffffff, 0xffffffff);
1443 static u32
si_get_rb_disabled(struct radeon_device
*rdev
,
1444 u32 max_rb_num
, u32 se_num
,
1449 data
= RREG32(CC_RB_BACKEND_DISABLE
);
1451 data
&= BACKEND_DISABLE_MASK
;
1454 data
|= RREG32(GC_USER_RB_BACKEND_DISABLE
);
1456 data
>>= BACKEND_DISABLE_SHIFT
;
1458 mask
= si_create_bitmask(max_rb_num
/ se_num
/ sh_per_se
);
1463 static void si_setup_rb(struct radeon_device
*rdev
,
1464 u32 se_num
, u32 sh_per_se
,
1469 u32 disabled_rbs
= 0;
1470 u32 enabled_rbs
= 0;
1472 for (i
= 0; i
< se_num
; i
++) {
1473 for (j
= 0; j
< sh_per_se
; j
++) {
1474 si_select_se_sh(rdev
, i
, j
);
1475 data
= si_get_rb_disabled(rdev
, max_rb_num
, se_num
, sh_per_se
);
1476 disabled_rbs
|= data
<< ((i
* sh_per_se
+ j
) * TAHITI_RB_BITMAP_WIDTH_PER_SH
);
1479 si_select_se_sh(rdev
, 0xffffffff, 0xffffffff);
1482 for (i
= 0; i
< max_rb_num
; i
++) {
1483 if (!(disabled_rbs
& mask
))
1484 enabled_rbs
|= mask
;
1488 for (i
= 0; i
< se_num
; i
++) {
1489 si_select_se_sh(rdev
, i
, 0xffffffff);
1491 for (j
= 0; j
< sh_per_se
; j
++) {
1492 switch (enabled_rbs
& 3) {
1494 data
|= (RASTER_CONFIG_RB_MAP_0
<< (i
* sh_per_se
+ j
) * 2);
1497 data
|= (RASTER_CONFIG_RB_MAP_3
<< (i
* sh_per_se
+ j
) * 2);
1501 data
|= (RASTER_CONFIG_RB_MAP_2
<< (i
* sh_per_se
+ j
) * 2);
1506 WREG32(PA_SC_RASTER_CONFIG
, data
);
1508 si_select_se_sh(rdev
, 0xffffffff, 0xffffffff);
1511 static void si_gpu_init(struct radeon_device
*rdev
)
1513 u32 gb_addr_config
= 0;
1514 u32 mc_shared_chmap
, mc_arb_ramcfg
;
1516 u32 hdp_host_path_cntl
;
1520 switch (rdev
->family
) {
1522 rdev
->config
.si
.max_shader_engines
= 2;
1523 rdev
->config
.si
.max_tile_pipes
= 12;
1524 rdev
->config
.si
.max_cu_per_sh
= 8;
1525 rdev
->config
.si
.max_sh_per_se
= 2;
1526 rdev
->config
.si
.max_backends_per_se
= 4;
1527 rdev
->config
.si
.max_texture_channel_caches
= 12;
1528 rdev
->config
.si
.max_gprs
= 256;
1529 rdev
->config
.si
.max_gs_threads
= 32;
1530 rdev
->config
.si
.max_hw_contexts
= 8;
1532 rdev
->config
.si
.sc_prim_fifo_size_frontend
= 0x20;
1533 rdev
->config
.si
.sc_prim_fifo_size_backend
= 0x100;
1534 rdev
->config
.si
.sc_hiz_tile_fifo_size
= 0x30;
1535 rdev
->config
.si
.sc_earlyz_tile_fifo_size
= 0x130;
1536 gb_addr_config
= TAHITI_GB_ADDR_CONFIG_GOLDEN
;
1539 rdev
->config
.si
.max_shader_engines
= 2;
1540 rdev
->config
.si
.max_tile_pipes
= 8;
1541 rdev
->config
.si
.max_cu_per_sh
= 5;
1542 rdev
->config
.si
.max_sh_per_se
= 2;
1543 rdev
->config
.si
.max_backends_per_se
= 4;
1544 rdev
->config
.si
.max_texture_channel_caches
= 8;
1545 rdev
->config
.si
.max_gprs
= 256;
1546 rdev
->config
.si
.max_gs_threads
= 32;
1547 rdev
->config
.si
.max_hw_contexts
= 8;
1549 rdev
->config
.si
.sc_prim_fifo_size_frontend
= 0x20;
1550 rdev
->config
.si
.sc_prim_fifo_size_backend
= 0x100;
1551 rdev
->config
.si
.sc_hiz_tile_fifo_size
= 0x30;
1552 rdev
->config
.si
.sc_earlyz_tile_fifo_size
= 0x130;
1553 gb_addr_config
= TAHITI_GB_ADDR_CONFIG_GOLDEN
;
1557 rdev
->config
.si
.max_shader_engines
= 1;
1558 rdev
->config
.si
.max_tile_pipes
= 4;
1559 rdev
->config
.si
.max_cu_per_sh
= 2;
1560 rdev
->config
.si
.max_sh_per_se
= 2;
1561 rdev
->config
.si
.max_backends_per_se
= 4;
1562 rdev
->config
.si
.max_texture_channel_caches
= 4;
1563 rdev
->config
.si
.max_gprs
= 256;
1564 rdev
->config
.si
.max_gs_threads
= 32;
1565 rdev
->config
.si
.max_hw_contexts
= 8;
1567 rdev
->config
.si
.sc_prim_fifo_size_frontend
= 0x20;
1568 rdev
->config
.si
.sc_prim_fifo_size_backend
= 0x40;
1569 rdev
->config
.si
.sc_hiz_tile_fifo_size
= 0x30;
1570 rdev
->config
.si
.sc_earlyz_tile_fifo_size
= 0x130;
1571 gb_addr_config
= VERDE_GB_ADDR_CONFIG_GOLDEN
;
1575 /* Initialize HDP */
1576 for (i
= 0, j
= 0; i
< 32; i
++, j
+= 0x18) {
1577 WREG32((0x2c14 + j
), 0x00000000);
1578 WREG32((0x2c18 + j
), 0x00000000);
1579 WREG32((0x2c1c + j
), 0x00000000);
1580 WREG32((0x2c20 + j
), 0x00000000);
1581 WREG32((0x2c24 + j
), 0x00000000);
1584 WREG32(GRBM_CNTL
, GRBM_READ_TIMEOUT(0xff));
1586 evergreen_fix_pci_max_read_req_size(rdev
);
1588 WREG32(BIF_FB_EN
, FB_READ_EN
| FB_WRITE_EN
);
1590 mc_shared_chmap
= RREG32(MC_SHARED_CHMAP
);
1591 mc_arb_ramcfg
= RREG32(MC_ARB_RAMCFG
);
1593 rdev
->config
.si
.num_tile_pipes
= rdev
->config
.si
.max_tile_pipes
;
1594 rdev
->config
.si
.mem_max_burst_length_bytes
= 256;
1595 tmp
= (mc_arb_ramcfg
& NOOFCOLS_MASK
) >> NOOFCOLS_SHIFT
;
1596 rdev
->config
.si
.mem_row_size_in_kb
= (4 * (1 << (8 + tmp
))) / 1024;
1597 if (rdev
->config
.si
.mem_row_size_in_kb
> 4)
1598 rdev
->config
.si
.mem_row_size_in_kb
= 4;
1599 /* XXX use MC settings? */
1600 rdev
->config
.si
.shader_engine_tile_size
= 32;
1601 rdev
->config
.si
.num_gpus
= 1;
1602 rdev
->config
.si
.multi_gpu_tile_size
= 64;
1604 /* fix up row size */
1605 gb_addr_config
&= ~ROW_SIZE_MASK
;
1606 switch (rdev
->config
.si
.mem_row_size_in_kb
) {
1609 gb_addr_config
|= ROW_SIZE(0);
1612 gb_addr_config
|= ROW_SIZE(1);
1615 gb_addr_config
|= ROW_SIZE(2);
1619 /* setup tiling info dword. gb_addr_config is not adequate since it does
1620 * not have bank info, so create a custom tiling dword.
1621 * bits 3:0 num_pipes
1622 * bits 7:4 num_banks
1623 * bits 11:8 group_size
1624 * bits 15:12 row_size
1626 rdev
->config
.si
.tile_config
= 0;
1627 switch (rdev
->config
.si
.num_tile_pipes
) {
1629 rdev
->config
.si
.tile_config
|= (0 << 0);
1632 rdev
->config
.si
.tile_config
|= (1 << 0);
1635 rdev
->config
.si
.tile_config
|= (2 << 0);
1639 /* XXX what about 12? */
1640 rdev
->config
.si
.tile_config
|= (3 << 0);
1643 switch ((mc_arb_ramcfg
& NOOFBANK_MASK
) >> NOOFBANK_SHIFT
) {
1644 case 0: /* four banks */
1645 rdev
->config
.si
.tile_config
|= 0 << 4;
1647 case 1: /* eight banks */
1648 rdev
->config
.si
.tile_config
|= 1 << 4;
1650 case 2: /* sixteen banks */
1652 rdev
->config
.si
.tile_config
|= 2 << 4;
1655 rdev
->config
.si
.tile_config
|=
1656 ((gb_addr_config
& PIPE_INTERLEAVE_SIZE_MASK
) >> PIPE_INTERLEAVE_SIZE_SHIFT
) << 8;
1657 rdev
->config
.si
.tile_config
|=
1658 ((gb_addr_config
& ROW_SIZE_MASK
) >> ROW_SIZE_SHIFT
) << 12;
1660 WREG32(GB_ADDR_CONFIG
, gb_addr_config
);
1661 WREG32(DMIF_ADDR_CONFIG
, gb_addr_config
);
1662 WREG32(HDP_ADDR_CONFIG
, gb_addr_config
);
1663 WREG32(DMA_TILING_CONFIG
+ DMA0_REGISTER_OFFSET
, gb_addr_config
);
1664 WREG32(DMA_TILING_CONFIG
+ DMA1_REGISTER_OFFSET
, gb_addr_config
);
1666 si_tiling_mode_table_init(rdev
);
1668 si_setup_rb(rdev
, rdev
->config
.si
.max_shader_engines
,
1669 rdev
->config
.si
.max_sh_per_se
,
1670 rdev
->config
.si
.max_backends_per_se
);
1672 si_setup_spi(rdev
, rdev
->config
.si
.max_shader_engines
,
1673 rdev
->config
.si
.max_sh_per_se
,
1674 rdev
->config
.si
.max_cu_per_sh
);
1677 /* set HW defaults for 3D engine */
1678 WREG32(CP_QUEUE_THRESHOLDS
, (ROQ_IB1_START(0x16) |
1679 ROQ_IB2_START(0x2b)));
1680 WREG32(CP_MEQ_THRESHOLDS
, MEQ1_START(0x30) | MEQ2_START(0x60));
1682 sx_debug_1
= RREG32(SX_DEBUG_1
);
1683 WREG32(SX_DEBUG_1
, sx_debug_1
);
1685 WREG32(SPI_CONFIG_CNTL_1
, VTX_DONE_DELAY(4));
1687 WREG32(PA_SC_FIFO_SIZE
, (SC_FRONTEND_PRIM_FIFO_SIZE(rdev
->config
.si
.sc_prim_fifo_size_frontend
) |
1688 SC_BACKEND_PRIM_FIFO_SIZE(rdev
->config
.si
.sc_prim_fifo_size_backend
) |
1689 SC_HIZ_TILE_FIFO_SIZE(rdev
->config
.si
.sc_hiz_tile_fifo_size
) |
1690 SC_EARLYZ_TILE_FIFO_SIZE(rdev
->config
.si
.sc_earlyz_tile_fifo_size
)));
1692 WREG32(VGT_NUM_INSTANCES
, 1);
1694 WREG32(CP_PERFMON_CNTL
, 0);
1696 WREG32(SQ_CONFIG
, 0);
1698 WREG32(PA_SC_FORCE_EOV_MAX_CNTS
, (FORCE_EOV_MAX_CLK_CNT(4095) |
1699 FORCE_EOV_MAX_REZ_CNT(255)));
1701 WREG32(VGT_CACHE_INVALIDATION
, CACHE_INVALIDATION(VC_AND_TC
) |
1702 AUTO_INVLD_EN(ES_AND_GS_AUTO
));
1704 WREG32(VGT_GS_VERTEX_REUSE
, 16);
1705 WREG32(PA_SC_LINE_STIPPLE_STATE
, 0);
1707 WREG32(CB_PERFCOUNTER0_SELECT0
, 0);
1708 WREG32(CB_PERFCOUNTER0_SELECT1
, 0);
1709 WREG32(CB_PERFCOUNTER1_SELECT0
, 0);
1710 WREG32(CB_PERFCOUNTER1_SELECT1
, 0);
1711 WREG32(CB_PERFCOUNTER2_SELECT0
, 0);
1712 WREG32(CB_PERFCOUNTER2_SELECT1
, 0);
1713 WREG32(CB_PERFCOUNTER3_SELECT0
, 0);
1714 WREG32(CB_PERFCOUNTER3_SELECT1
, 0);
1716 tmp
= RREG32(HDP_MISC_CNTL
);
1717 tmp
|= HDP_FLUSH_INVALIDATE_CACHE
;
1718 WREG32(HDP_MISC_CNTL
, tmp
);
1720 hdp_host_path_cntl
= RREG32(HDP_HOST_PATH_CNTL
);
1721 WREG32(HDP_HOST_PATH_CNTL
, hdp_host_path_cntl
);
1723 WREG32(PA_CL_ENHANCE
, CLIP_VTX_REORDER_ENA
| NUM_CLIP_SEQ(3));
1729 * GPU scratch registers helpers function.
1731 static void si_scratch_init(struct radeon_device
*rdev
)
1735 rdev
->scratch
.num_reg
= 7;
1736 rdev
->scratch
.reg_base
= SCRATCH_REG0
;
1737 for (i
= 0; i
< rdev
->scratch
.num_reg
; i
++) {
1738 rdev
->scratch
.free
[i
] = true;
1739 rdev
->scratch
.reg
[i
] = rdev
->scratch
.reg_base
+ (i
* 4);
1743 void si_fence_ring_emit(struct radeon_device
*rdev
,
1744 struct radeon_fence
*fence
)
1746 struct radeon_ring
*ring
= &rdev
->ring
[fence
->ring
];
1747 u64 addr
= rdev
->fence_drv
[fence
->ring
].gpu_addr
;
1749 /* flush read cache over gart */
1750 radeon_ring_write(ring
, PACKET3(PACKET3_SET_CONFIG_REG
, 1));
1751 radeon_ring_write(ring
, (CP_COHER_CNTL2
- PACKET3_SET_CONFIG_REG_START
) >> 2);
1752 radeon_ring_write(ring
, 0);
1753 radeon_ring_write(ring
, PACKET3(PACKET3_SURFACE_SYNC
, 3));
1754 radeon_ring_write(ring
, PACKET3_TCL1_ACTION_ENA
|
1755 PACKET3_TC_ACTION_ENA
|
1756 PACKET3_SH_KCACHE_ACTION_ENA
|
1757 PACKET3_SH_ICACHE_ACTION_ENA
);
1758 radeon_ring_write(ring
, 0xFFFFFFFF);
1759 radeon_ring_write(ring
, 0);
1760 radeon_ring_write(ring
, 10); /* poll interval */
1761 /* EVENT_WRITE_EOP - flush caches, send int */
1762 radeon_ring_write(ring
, PACKET3(PACKET3_EVENT_WRITE_EOP
, 4));
1763 radeon_ring_write(ring
, EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT
) | EVENT_INDEX(5));
1764 radeon_ring_write(ring
, addr
& 0xffffffff);
1765 radeon_ring_write(ring
, (upper_32_bits(addr
) & 0xff) | DATA_SEL(1) | INT_SEL(2));
1766 radeon_ring_write(ring
, fence
->seq
);
1767 radeon_ring_write(ring
, 0);
1773 void si_ring_ib_execute(struct radeon_device
*rdev
, struct radeon_ib
*ib
)
1775 struct radeon_ring
*ring
= &rdev
->ring
[ib
->ring
];
1778 if (ib
->is_const_ib
) {
1779 /* set switch buffer packet before const IB */
1780 radeon_ring_write(ring
, PACKET3(PACKET3_SWITCH_BUFFER
, 0));
1781 radeon_ring_write(ring
, 0);
1783 header
= PACKET3(PACKET3_INDIRECT_BUFFER_CONST
, 2);
1786 if (ring
->rptr_save_reg
) {
1787 next_rptr
= ring
->wptr
+ 3 + 4 + 8;
1788 radeon_ring_write(ring
, PACKET3(PACKET3_SET_CONFIG_REG
, 1));
1789 radeon_ring_write(ring
, ((ring
->rptr_save_reg
-
1790 PACKET3_SET_CONFIG_REG_START
) >> 2));
1791 radeon_ring_write(ring
, next_rptr
);
1792 } else if (rdev
->wb
.enabled
) {
1793 next_rptr
= ring
->wptr
+ 5 + 4 + 8;
1794 radeon_ring_write(ring
, PACKET3(PACKET3_WRITE_DATA
, 3));
1795 radeon_ring_write(ring
, (1 << 8));
1796 radeon_ring_write(ring
, ring
->next_rptr_gpu_addr
& 0xfffffffc);
1797 radeon_ring_write(ring
, upper_32_bits(ring
->next_rptr_gpu_addr
) & 0xffffffff);
1798 radeon_ring_write(ring
, next_rptr
);
1801 header
= PACKET3(PACKET3_INDIRECT_BUFFER
, 2);
1804 radeon_ring_write(ring
, header
);
1805 radeon_ring_write(ring
,
1809 (ib
->gpu_addr
& 0xFFFFFFFC));
1810 radeon_ring_write(ring
, upper_32_bits(ib
->gpu_addr
) & 0xFFFF);
1811 radeon_ring_write(ring
, ib
->length_dw
|
1812 (ib
->vm
? (ib
->vm
->id
<< 24) : 0));
1814 if (!ib
->is_const_ib
) {
1815 /* flush read cache over gart for this vmid */
1816 radeon_ring_write(ring
, PACKET3(PACKET3_SET_CONFIG_REG
, 1));
1817 radeon_ring_write(ring
, (CP_COHER_CNTL2
- PACKET3_SET_CONFIG_REG_START
) >> 2);
1818 radeon_ring_write(ring
, ib
->vm
? ib
->vm
->id
: 0);
1819 radeon_ring_write(ring
, PACKET3(PACKET3_SURFACE_SYNC
, 3));
1820 radeon_ring_write(ring
, PACKET3_TCL1_ACTION_ENA
|
1821 PACKET3_TC_ACTION_ENA
|
1822 PACKET3_SH_KCACHE_ACTION_ENA
|
1823 PACKET3_SH_ICACHE_ACTION_ENA
);
1824 radeon_ring_write(ring
, 0xFFFFFFFF);
1825 radeon_ring_write(ring
, 0);
1826 radeon_ring_write(ring
, 10); /* poll interval */
1833 static void si_cp_enable(struct radeon_device
*rdev
, bool enable
)
1836 WREG32(CP_ME_CNTL
, 0);
1838 radeon_ttm_set_active_vram_size(rdev
, rdev
->mc
.visible_vram_size
);
1839 WREG32(CP_ME_CNTL
, (CP_ME_HALT
| CP_PFP_HALT
| CP_CE_HALT
));
1840 WREG32(SCRATCH_UMSK
, 0);
1841 rdev
->ring
[RADEON_RING_TYPE_GFX_INDEX
].ready
= false;
1842 rdev
->ring
[CAYMAN_RING_TYPE_CP1_INDEX
].ready
= false;
1843 rdev
->ring
[CAYMAN_RING_TYPE_CP2_INDEX
].ready
= false;
1848 static int si_cp_load_microcode(struct radeon_device
*rdev
)
1850 const __be32
*fw_data
;
1853 if (!rdev
->me_fw
|| !rdev
->pfp_fw
)
1856 si_cp_enable(rdev
, false);
1859 fw_data
= (const __be32
*)rdev
->pfp_fw
->data
;
1860 WREG32(CP_PFP_UCODE_ADDR
, 0);
1861 for (i
= 0; i
< SI_PFP_UCODE_SIZE
; i
++)
1862 WREG32(CP_PFP_UCODE_DATA
, be32_to_cpup(fw_data
++));
1863 WREG32(CP_PFP_UCODE_ADDR
, 0);
1866 fw_data
= (const __be32
*)rdev
->ce_fw
->data
;
1867 WREG32(CP_CE_UCODE_ADDR
, 0);
1868 for (i
= 0; i
< SI_CE_UCODE_SIZE
; i
++)
1869 WREG32(CP_CE_UCODE_DATA
, be32_to_cpup(fw_data
++));
1870 WREG32(CP_CE_UCODE_ADDR
, 0);
1873 fw_data
= (const __be32
*)rdev
->me_fw
->data
;
1874 WREG32(CP_ME_RAM_WADDR
, 0);
1875 for (i
= 0; i
< SI_PM4_UCODE_SIZE
; i
++)
1876 WREG32(CP_ME_RAM_DATA
, be32_to_cpup(fw_data
++));
1877 WREG32(CP_ME_RAM_WADDR
, 0);
1879 WREG32(CP_PFP_UCODE_ADDR
, 0);
1880 WREG32(CP_CE_UCODE_ADDR
, 0);
1881 WREG32(CP_ME_RAM_WADDR
, 0);
1882 WREG32(CP_ME_RAM_RADDR
, 0);
1886 static int si_cp_start(struct radeon_device
*rdev
)
1888 struct radeon_ring
*ring
= &rdev
->ring
[RADEON_RING_TYPE_GFX_INDEX
];
1891 r
= radeon_ring_lock(rdev
, ring
, 7 + 4);
1893 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r
);
1897 radeon_ring_write(ring
, PACKET3(PACKET3_ME_INITIALIZE
, 5));
1898 radeon_ring_write(ring
, 0x1);
1899 radeon_ring_write(ring
, 0x0);
1900 radeon_ring_write(ring
, rdev
->config
.si
.max_hw_contexts
- 1);
1901 radeon_ring_write(ring
, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
1902 radeon_ring_write(ring
, 0);
1903 radeon_ring_write(ring
, 0);
1905 /* init the CE partitions */
1906 radeon_ring_write(ring
, PACKET3(PACKET3_SET_BASE
, 2));
1907 radeon_ring_write(ring
, PACKET3_BASE_INDEX(CE_PARTITION_BASE
));
1908 radeon_ring_write(ring
, 0xc000);
1909 radeon_ring_write(ring
, 0xe000);
1910 radeon_ring_unlock_commit(rdev
, ring
);
1912 si_cp_enable(rdev
, true);
1914 r
= radeon_ring_lock(rdev
, ring
, si_default_size
+ 10);
1916 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r
);
1920 /* setup clear context state */
1921 radeon_ring_write(ring
, PACKET3(PACKET3_PREAMBLE_CNTL
, 0));
1922 radeon_ring_write(ring
, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE
);
1924 for (i
= 0; i
< si_default_size
; i
++)
1925 radeon_ring_write(ring
, si_default_state
[i
]);
1927 radeon_ring_write(ring
, PACKET3(PACKET3_PREAMBLE_CNTL
, 0));
1928 radeon_ring_write(ring
, PACKET3_PREAMBLE_END_CLEAR_STATE
);
1930 /* set clear context state */
1931 radeon_ring_write(ring
, PACKET3(PACKET3_CLEAR_STATE
, 0));
1932 radeon_ring_write(ring
, 0);
1934 radeon_ring_write(ring
, PACKET3(PACKET3_SET_CONTEXT_REG
, 2));
1935 radeon_ring_write(ring
, 0x00000316);
1936 radeon_ring_write(ring
, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
1937 radeon_ring_write(ring
, 0x00000010); /* VGT_OUT_DEALLOC_CNTL */
1939 radeon_ring_unlock_commit(rdev
, ring
);
1941 for (i
= RADEON_RING_TYPE_GFX_INDEX
; i
<= CAYMAN_RING_TYPE_CP2_INDEX
; ++i
) {
1942 ring
= &rdev
->ring
[i
];
1943 r
= radeon_ring_lock(rdev
, ring
, 2);
1945 /* clear the compute context state */
1946 radeon_ring_write(ring
, PACKET3_COMPUTE(PACKET3_CLEAR_STATE
, 0));
1947 radeon_ring_write(ring
, 0);
1949 radeon_ring_unlock_commit(rdev
, ring
);
1955 static void si_cp_fini(struct radeon_device
*rdev
)
1957 struct radeon_ring
*ring
;
1958 si_cp_enable(rdev
, false);
1960 ring
= &rdev
->ring
[RADEON_RING_TYPE_GFX_INDEX
];
1961 radeon_ring_fini(rdev
, ring
);
1962 radeon_scratch_free(rdev
, ring
->rptr_save_reg
);
1964 ring
= &rdev
->ring
[CAYMAN_RING_TYPE_CP1_INDEX
];
1965 radeon_ring_fini(rdev
, ring
);
1966 radeon_scratch_free(rdev
, ring
->rptr_save_reg
);
1968 ring
= &rdev
->ring
[CAYMAN_RING_TYPE_CP2_INDEX
];
1969 radeon_ring_fini(rdev
, ring
);
1970 radeon_scratch_free(rdev
, ring
->rptr_save_reg
);
1973 static int si_cp_resume(struct radeon_device
*rdev
)
1975 struct radeon_ring
*ring
;
1980 /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */
1981 WREG32(GRBM_SOFT_RESET
, (SOFT_RESET_CP
|
1986 RREG32(GRBM_SOFT_RESET
);
1988 WREG32(GRBM_SOFT_RESET
, 0);
1989 RREG32(GRBM_SOFT_RESET
);
1991 WREG32(CP_SEM_WAIT_TIMER
, 0x0);
1992 WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL
, 0x0);
1994 /* Set the write pointer delay */
1995 WREG32(CP_RB_WPTR_DELAY
, 0);
1997 WREG32(CP_DEBUG
, 0);
1998 WREG32(SCRATCH_ADDR
, ((rdev
->wb
.gpu_addr
+ RADEON_WB_SCRATCH_OFFSET
) >> 8) & 0xFFFFFFFF);
2000 /* ring 0 - compute and gfx */
2001 /* Set ring buffer size */
2002 ring
= &rdev
->ring
[RADEON_RING_TYPE_GFX_INDEX
];
2003 rb_bufsz
= drm_order(ring
->ring_size
/ 8);
2004 tmp
= (drm_order(RADEON_GPU_PAGE_SIZE
/8) << 8) | rb_bufsz
;
2006 tmp
|= BUF_SWAP_32BIT
;
2008 WREG32(CP_RB0_CNTL
, tmp
);
2010 /* Initialize the ring buffer's read and write pointers */
2011 WREG32(CP_RB0_CNTL
, tmp
| RB_RPTR_WR_ENA
);
2013 WREG32(CP_RB0_WPTR
, ring
->wptr
);
2015 /* set the wb address wether it's enabled or not */
2016 WREG32(CP_RB0_RPTR_ADDR
, (rdev
->wb
.gpu_addr
+ RADEON_WB_CP_RPTR_OFFSET
) & 0xFFFFFFFC);
2017 WREG32(CP_RB0_RPTR_ADDR_HI
, upper_32_bits(rdev
->wb
.gpu_addr
+ RADEON_WB_CP_RPTR_OFFSET
) & 0xFF);
2019 if (rdev
->wb
.enabled
)
2020 WREG32(SCRATCH_UMSK
, 0xff);
2022 tmp
|= RB_NO_UPDATE
;
2023 WREG32(SCRATCH_UMSK
, 0);
2027 WREG32(CP_RB0_CNTL
, tmp
);
2029 WREG32(CP_RB0_BASE
, ring
->gpu_addr
>> 8);
2031 ring
->rptr
= RREG32(CP_RB0_RPTR
);
2033 /* ring1 - compute only */
2034 /* Set ring buffer size */
2035 ring
= &rdev
->ring
[CAYMAN_RING_TYPE_CP1_INDEX
];
2036 rb_bufsz
= drm_order(ring
->ring_size
/ 8);
2037 tmp
= (drm_order(RADEON_GPU_PAGE_SIZE
/8) << 8) | rb_bufsz
;
2039 tmp
|= BUF_SWAP_32BIT
;
2041 WREG32(CP_RB1_CNTL
, tmp
);
2043 /* Initialize the ring buffer's read and write pointers */
2044 WREG32(CP_RB1_CNTL
, tmp
| RB_RPTR_WR_ENA
);
2046 WREG32(CP_RB1_WPTR
, ring
->wptr
);
2048 /* set the wb address wether it's enabled or not */
2049 WREG32(CP_RB1_RPTR_ADDR
, (rdev
->wb
.gpu_addr
+ RADEON_WB_CP1_RPTR_OFFSET
) & 0xFFFFFFFC);
2050 WREG32(CP_RB1_RPTR_ADDR_HI
, upper_32_bits(rdev
->wb
.gpu_addr
+ RADEON_WB_CP1_RPTR_OFFSET
) & 0xFF);
2053 WREG32(CP_RB1_CNTL
, tmp
);
2055 WREG32(CP_RB1_BASE
, ring
->gpu_addr
>> 8);
2057 ring
->rptr
= RREG32(CP_RB1_RPTR
);
2059 /* ring2 - compute only */
2060 /* Set ring buffer size */
2061 ring
= &rdev
->ring
[CAYMAN_RING_TYPE_CP2_INDEX
];
2062 rb_bufsz
= drm_order(ring
->ring_size
/ 8);
2063 tmp
= (drm_order(RADEON_GPU_PAGE_SIZE
/8) << 8) | rb_bufsz
;
2065 tmp
|= BUF_SWAP_32BIT
;
2067 WREG32(CP_RB2_CNTL
, tmp
);
2069 /* Initialize the ring buffer's read and write pointers */
2070 WREG32(CP_RB2_CNTL
, tmp
| RB_RPTR_WR_ENA
);
2072 WREG32(CP_RB2_WPTR
, ring
->wptr
);
2074 /* set the wb address wether it's enabled or not */
2075 WREG32(CP_RB2_RPTR_ADDR
, (rdev
->wb
.gpu_addr
+ RADEON_WB_CP2_RPTR_OFFSET
) & 0xFFFFFFFC);
2076 WREG32(CP_RB2_RPTR_ADDR_HI
, upper_32_bits(rdev
->wb
.gpu_addr
+ RADEON_WB_CP2_RPTR_OFFSET
) & 0xFF);
2079 WREG32(CP_RB2_CNTL
, tmp
);
2081 WREG32(CP_RB2_BASE
, ring
->gpu_addr
>> 8);
2083 ring
->rptr
= RREG32(CP_RB2_RPTR
);
2085 /* start the rings */
2087 rdev
->ring
[RADEON_RING_TYPE_GFX_INDEX
].ready
= true;
2088 rdev
->ring
[CAYMAN_RING_TYPE_CP1_INDEX
].ready
= true;
2089 rdev
->ring
[CAYMAN_RING_TYPE_CP2_INDEX
].ready
= true;
2090 r
= radeon_ring_test(rdev
, RADEON_RING_TYPE_GFX_INDEX
, &rdev
->ring
[RADEON_RING_TYPE_GFX_INDEX
]);
2092 rdev
->ring
[RADEON_RING_TYPE_GFX_INDEX
].ready
= false;
2093 rdev
->ring
[CAYMAN_RING_TYPE_CP1_INDEX
].ready
= false;
2094 rdev
->ring
[CAYMAN_RING_TYPE_CP2_INDEX
].ready
= false;
2097 r
= radeon_ring_test(rdev
, CAYMAN_RING_TYPE_CP1_INDEX
, &rdev
->ring
[CAYMAN_RING_TYPE_CP1_INDEX
]);
2099 rdev
->ring
[CAYMAN_RING_TYPE_CP1_INDEX
].ready
= false;
2101 r
= radeon_ring_test(rdev
, CAYMAN_RING_TYPE_CP2_INDEX
, &rdev
->ring
[CAYMAN_RING_TYPE_CP2_INDEX
]);
2103 rdev
->ring
[CAYMAN_RING_TYPE_CP2_INDEX
].ready
= false;
2109 bool si_gpu_is_lockup(struct radeon_device
*rdev
, struct radeon_ring
*ring
)
2112 u32 grbm_status
, grbm_status2
;
2113 u32 grbm_status_se0
, grbm_status_se1
;
2115 srbm_status
= RREG32(SRBM_STATUS
);
2116 grbm_status
= RREG32(GRBM_STATUS
);
2117 grbm_status2
= RREG32(GRBM_STATUS2
);
2118 grbm_status_se0
= RREG32(GRBM_STATUS_SE0
);
2119 grbm_status_se1
= RREG32(GRBM_STATUS_SE1
);
2120 if (!(grbm_status
& GUI_ACTIVE
)) {
2121 radeon_ring_lockup_update(ring
);
2124 /* force CP activities */
2125 radeon_ring_force_activity(rdev
, ring
);
2126 return radeon_ring_test_lockup(rdev
, ring
);
2129 static int si_gpu_soft_reset(struct radeon_device
*rdev
)
2131 struct evergreen_mc_save save
;
2134 if (!(RREG32(GRBM_STATUS
) & GUI_ACTIVE
))
2137 dev_info(rdev
->dev
, "GPU softreset \n");
2138 dev_info(rdev
->dev
, " GRBM_STATUS=0x%08X\n",
2139 RREG32(GRBM_STATUS
));
2140 dev_info(rdev
->dev
, " GRBM_STATUS2=0x%08X\n",
2141 RREG32(GRBM_STATUS2
));
2142 dev_info(rdev
->dev
, " GRBM_STATUS_SE0=0x%08X\n",
2143 RREG32(GRBM_STATUS_SE0
));
2144 dev_info(rdev
->dev
, " GRBM_STATUS_SE1=0x%08X\n",
2145 RREG32(GRBM_STATUS_SE1
));
2146 dev_info(rdev
->dev
, " SRBM_STATUS=0x%08X\n",
2147 RREG32(SRBM_STATUS
));
2148 evergreen_mc_stop(rdev
, &save
);
2149 if (radeon_mc_wait_for_idle(rdev
)) {
2150 dev_warn(rdev
->dev
, "Wait for MC idle timedout !\n");
2152 /* Disable CP parsing/prefetching */
2153 WREG32(CP_ME_CNTL
, CP_ME_HALT
| CP_PFP_HALT
| CP_CE_HALT
);
2155 /* reset all the gfx blocks */
2156 grbm_reset
= (SOFT_RESET_CP
|
2170 dev_info(rdev
->dev
, " GRBM_SOFT_RESET=0x%08X\n", grbm_reset
);
2171 WREG32(GRBM_SOFT_RESET
, grbm_reset
);
2172 (void)RREG32(GRBM_SOFT_RESET
);
2174 WREG32(GRBM_SOFT_RESET
, 0);
2175 (void)RREG32(GRBM_SOFT_RESET
);
2176 /* Wait a little for things to settle down */
2178 dev_info(rdev
->dev
, " GRBM_STATUS=0x%08X\n",
2179 RREG32(GRBM_STATUS
));
2180 dev_info(rdev
->dev
, " GRBM_STATUS2=0x%08X\n",
2181 RREG32(GRBM_STATUS2
));
2182 dev_info(rdev
->dev
, " GRBM_STATUS_SE0=0x%08X\n",
2183 RREG32(GRBM_STATUS_SE0
));
2184 dev_info(rdev
->dev
, " GRBM_STATUS_SE1=0x%08X\n",
2185 RREG32(GRBM_STATUS_SE1
));
2186 dev_info(rdev
->dev
, " SRBM_STATUS=0x%08X\n",
2187 RREG32(SRBM_STATUS
));
2188 evergreen_mc_resume(rdev
, &save
);
2192 int si_asic_reset(struct radeon_device
*rdev
)
2194 return si_gpu_soft_reset(rdev
);
2198 static void si_mc_program(struct radeon_device
*rdev
)
2200 struct evergreen_mc_save save
;
2204 /* Initialize HDP */
2205 for (i
= 0, j
= 0; i
< 32; i
++, j
+= 0x18) {
2206 WREG32((0x2c14 + j
), 0x00000000);
2207 WREG32((0x2c18 + j
), 0x00000000);
2208 WREG32((0x2c1c + j
), 0x00000000);
2209 WREG32((0x2c20 + j
), 0x00000000);
2210 WREG32((0x2c24 + j
), 0x00000000);
2212 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL
, 0);
2214 evergreen_mc_stop(rdev
, &save
);
2215 if (radeon_mc_wait_for_idle(rdev
)) {
2216 dev_warn(rdev
->dev
, "Wait for MC idle timedout !\n");
2218 /* Lockout access through VGA aperture*/
2219 WREG32(VGA_HDP_CONTROL
, VGA_MEMORY_DISABLE
);
2220 /* Update configuration */
2221 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR
,
2222 rdev
->mc
.vram_start
>> 12);
2223 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR
,
2224 rdev
->mc
.vram_end
>> 12);
2225 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR
,
2226 rdev
->vram_scratch
.gpu_addr
>> 12);
2227 tmp
= ((rdev
->mc
.vram_end
>> 24) & 0xFFFF) << 16;
2228 tmp
|= ((rdev
->mc
.vram_start
>> 24) & 0xFFFF);
2229 WREG32(MC_VM_FB_LOCATION
, tmp
);
2230 /* XXX double check these! */
2231 WREG32(HDP_NONSURFACE_BASE
, (rdev
->mc
.vram_start
>> 8));
2232 WREG32(HDP_NONSURFACE_INFO
, (2 << 7) | (1 << 30));
2233 WREG32(HDP_NONSURFACE_SIZE
, 0x3FFFFFFF);
2234 WREG32(MC_VM_AGP_BASE
, 0);
2235 WREG32(MC_VM_AGP_TOP
, 0x0FFFFFFF);
2236 WREG32(MC_VM_AGP_BOT
, 0x0FFFFFFF);
2237 if (radeon_mc_wait_for_idle(rdev
)) {
2238 dev_warn(rdev
->dev
, "Wait for MC idle timedout !\n");
2240 evergreen_mc_resume(rdev
, &save
);
2241 /* we need to own VRAM, so turn off the VGA renderer here
2242 * to stop it overwriting our objects */
2243 rv515_vga_render_disable(rdev
);
2246 /* SI MC address space is 40 bits */
2247 static void si_vram_location(struct radeon_device
*rdev
,
2248 struct radeon_mc
*mc
, u64 base
)
2250 mc
->vram_start
= base
;
2251 if (mc
->mc_vram_size
> (0xFFFFFFFFFFULL
- base
+ 1)) {
2252 dev_warn(rdev
->dev
, "limiting VRAM to PCI aperture size\n");
2253 mc
->real_vram_size
= mc
->aper_size
;
2254 mc
->mc_vram_size
= mc
->aper_size
;
2256 mc
->vram_end
= mc
->vram_start
+ mc
->mc_vram_size
- 1;
2257 dev_info(rdev
->dev
, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",
2258 mc
->mc_vram_size
>> 20, mc
->vram_start
,
2259 mc
->vram_end
, mc
->real_vram_size
>> 20);
2262 static void si_gtt_location(struct radeon_device
*rdev
, struct radeon_mc
*mc
)
2264 u64 size_af
, size_bf
;
2266 size_af
= ((0xFFFFFFFFFFULL
- mc
->vram_end
) + mc
->gtt_base_align
) & ~mc
->gtt_base_align
;
2267 size_bf
= mc
->vram_start
& ~mc
->gtt_base_align
;
2268 if (size_bf
> size_af
) {
2269 if (mc
->gtt_size
> size_bf
) {
2270 dev_warn(rdev
->dev
, "limiting GTT\n");
2271 mc
->gtt_size
= size_bf
;
2273 mc
->gtt_start
= (mc
->vram_start
& ~mc
->gtt_base_align
) - mc
->gtt_size
;
2275 if (mc
->gtt_size
> size_af
) {
2276 dev_warn(rdev
->dev
, "limiting GTT\n");
2277 mc
->gtt_size
= size_af
;
2279 mc
->gtt_start
= (mc
->vram_end
+ 1 + mc
->gtt_base_align
) & ~mc
->gtt_base_align
;
2281 mc
->gtt_end
= mc
->gtt_start
+ mc
->gtt_size
- 1;
2282 dev_info(rdev
->dev
, "GTT: %lluM 0x%016llX - 0x%016llX\n",
2283 mc
->gtt_size
>> 20, mc
->gtt_start
, mc
->gtt_end
);
2286 static void si_vram_gtt_location(struct radeon_device
*rdev
,
2287 struct radeon_mc
*mc
)
2289 if (mc
->mc_vram_size
> 0xFFC0000000ULL
) {
2290 /* leave room for at least 1024M GTT */
2291 dev_warn(rdev
->dev
, "limiting VRAM\n");
2292 mc
->real_vram_size
= 0xFFC0000000ULL
;
2293 mc
->mc_vram_size
= 0xFFC0000000ULL
;
2295 si_vram_location(rdev
, &rdev
->mc
, 0);
2296 rdev
->mc
.gtt_base_align
= 0;
2297 si_gtt_location(rdev
, mc
);
2300 static int si_mc_init(struct radeon_device
*rdev
)
2303 int chansize
, numchan
;
2305 /* Get VRAM informations */
2306 rdev
->mc
.vram_is_ddr
= true;
2307 tmp
= RREG32(MC_ARB_RAMCFG
);
2308 if (tmp
& CHANSIZE_OVERRIDE
) {
2310 } else if (tmp
& CHANSIZE_MASK
) {
2315 tmp
= RREG32(MC_SHARED_CHMAP
);
2316 switch ((tmp
& NOOFCHAN_MASK
) >> NOOFCHAN_SHIFT
) {
2346 rdev
->mc
.vram_width
= numchan
* chansize
;
2347 /* Could aper size report 0 ? */
2348 rdev
->mc
.aper_base
= pci_resource_start(rdev
->pdev
, 0);
2349 rdev
->mc
.aper_size
= pci_resource_len(rdev
->pdev
, 0);
2350 /* size in MB on si */
2351 rdev
->mc
.mc_vram_size
= RREG32(CONFIG_MEMSIZE
) * 1024 * 1024;
2352 rdev
->mc
.real_vram_size
= RREG32(CONFIG_MEMSIZE
) * 1024 * 1024;
2353 rdev
->mc
.visible_vram_size
= rdev
->mc
.aper_size
;
2354 si_vram_gtt_location(rdev
, &rdev
->mc
);
2355 radeon_update_bandwidth_info(rdev
);
2363 void si_pcie_gart_tlb_flush(struct radeon_device
*rdev
)
2365 /* flush hdp cache */
2366 WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL
, 0x1);
2368 /* bits 0-15 are the VM contexts0-15 */
2369 WREG32(VM_INVALIDATE_REQUEST
, 1);
2372 static int si_pcie_gart_enable(struct radeon_device
*rdev
)
2376 if (rdev
->gart
.robj
== NULL
) {
2377 dev_err(rdev
->dev
, "No VRAM object for PCIE GART.\n");
2380 r
= radeon_gart_table_vram_pin(rdev
);
2383 radeon_gart_restore(rdev
);
2384 /* Setup TLB control */
2385 WREG32(MC_VM_MX_L1_TLB_CNTL
,
2388 SYSTEM_ACCESS_MODE_NOT_IN_SYS
|
2389 ENABLE_ADVANCED_DRIVER_MODEL
|
2390 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU
);
2391 /* Setup L2 cache */
2392 WREG32(VM_L2_CNTL
, ENABLE_L2_CACHE
|
2393 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE
|
2394 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE
|
2395 EFFECTIVE_L2_QUEUE_SIZE(7) |
2396 CONTEXT1_IDENTITY_ACCESS_MODE(1));
2397 WREG32(VM_L2_CNTL2
, INVALIDATE_ALL_L1_TLBS
| INVALIDATE_L2_CACHE
);
2398 WREG32(VM_L2_CNTL3
, L2_CACHE_BIGK_ASSOCIATIVITY
|
2399 L2_CACHE_BIGK_FRAGMENT_SIZE(0));
2400 /* setup context0 */
2401 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR
, rdev
->mc
.gtt_start
>> 12);
2402 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR
, rdev
->mc
.gtt_end
>> 12);
2403 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR
, rdev
->gart
.table_addr
>> 12);
2404 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR
,
2405 (u32
)(rdev
->dummy_page
.addr
>> 12));
2406 WREG32(VM_CONTEXT0_CNTL2
, 0);
2407 WREG32(VM_CONTEXT0_CNTL
, (ENABLE_CONTEXT
| PAGE_TABLE_DEPTH(0) |
2408 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT
));
2414 /* empty context1-15 */
2415 /* set vm size, must be a multiple of 4 */
2416 WREG32(VM_CONTEXT1_PAGE_TABLE_START_ADDR
, 0);
2417 WREG32(VM_CONTEXT1_PAGE_TABLE_END_ADDR
, rdev
->vm_manager
.max_pfn
);
2418 /* Assign the pt base to something valid for now; the pts used for
2419 * the VMs are determined by the application and setup and assigned
2420 * on the fly in the vm part of radeon_gart.c
2422 for (i
= 1; i
< 16; i
++) {
2424 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR
+ (i
<< 2),
2425 rdev
->gart
.table_addr
>> 12);
2427 WREG32(VM_CONTEXT8_PAGE_TABLE_BASE_ADDR
+ ((i
- 8) << 2),
2428 rdev
->gart
.table_addr
>> 12);
2431 /* enable context1-15 */
2432 WREG32(VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR
,
2433 (u32
)(rdev
->dummy_page
.addr
>> 12));
2434 WREG32(VM_CONTEXT1_CNTL2
, 4);
2435 WREG32(VM_CONTEXT1_CNTL
, ENABLE_CONTEXT
| PAGE_TABLE_DEPTH(1) |
2436 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT
|
2437 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT
|
2438 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT
|
2439 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT
|
2440 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT
|
2441 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT
|
2442 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT
|
2443 VALID_PROTECTION_FAULT_ENABLE_DEFAULT
|
2444 READ_PROTECTION_FAULT_ENABLE_INTERRUPT
|
2445 READ_PROTECTION_FAULT_ENABLE_DEFAULT
|
2446 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT
|
2447 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT
);
2449 si_pcie_gart_tlb_flush(rdev
);
2450 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
2451 (unsigned)(rdev
->mc
.gtt_size
>> 20),
2452 (unsigned long long)rdev
->gart
.table_addr
);
2453 rdev
->gart
.ready
= true;
2457 static void si_pcie_gart_disable(struct radeon_device
*rdev
)
2459 /* Disable all tables */
2460 WREG32(VM_CONTEXT0_CNTL
, 0);
2461 WREG32(VM_CONTEXT1_CNTL
, 0);
2462 /* Setup TLB control */
2463 WREG32(MC_VM_MX_L1_TLB_CNTL
, SYSTEM_ACCESS_MODE_NOT_IN_SYS
|
2464 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU
);
2465 /* Setup L2 cache */
2466 WREG32(VM_L2_CNTL
, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE
|
2467 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE
|
2468 EFFECTIVE_L2_QUEUE_SIZE(7) |
2469 CONTEXT1_IDENTITY_ACCESS_MODE(1));
2470 WREG32(VM_L2_CNTL2
, 0);
2471 WREG32(VM_L2_CNTL3
, L2_CACHE_BIGK_ASSOCIATIVITY
|
2472 L2_CACHE_BIGK_FRAGMENT_SIZE(0));
2473 radeon_gart_table_vram_unpin(rdev
);
2476 static void si_pcie_gart_fini(struct radeon_device
*rdev
)
2478 si_pcie_gart_disable(rdev
);
2479 radeon_gart_table_vram_free(rdev
);
2480 radeon_gart_fini(rdev
);
2484 static bool si_vm_reg_valid(u32 reg
)
2486 /* context regs are fine */
2490 /* check config regs */
2492 case GRBM_GFX_INDEX
:
2493 case CP_STRMOUT_CNTL
:
2494 case VGT_VTX_VECT_EJECT_REG
:
2495 case VGT_CACHE_INVALIDATION
:
2496 case VGT_ESGS_RING_SIZE
:
2497 case VGT_GSVS_RING_SIZE
:
2498 case VGT_GS_VERTEX_REUSE
:
2499 case VGT_PRIMITIVE_TYPE
:
2500 case VGT_INDEX_TYPE
:
2501 case VGT_NUM_INDICES
:
2502 case VGT_NUM_INSTANCES
:
2503 case VGT_TF_RING_SIZE
:
2504 case VGT_HS_OFFCHIP_PARAM
:
2505 case VGT_TF_MEMORY_BASE
:
2507 case PA_SU_LINE_STIPPLE_VALUE
:
2508 case PA_SC_LINE_STIPPLE_STATE
:
2511 case SPI_STATIC_THREAD_MGMT_1
:
2512 case SPI_STATIC_THREAD_MGMT_2
:
2513 case SPI_STATIC_THREAD_MGMT_3
:
2514 case SPI_PS_MAX_WAVE_ID
:
2515 case SPI_CONFIG_CNTL
:
2516 case SPI_CONFIG_CNTL_1
:
2520 DRM_ERROR("Invalid register 0x%x in CS\n", reg
);
2525 static int si_vm_packet3_ce_check(struct radeon_device
*rdev
,
2526 u32
*ib
, struct radeon_cs_packet
*pkt
)
2528 switch (pkt
->opcode
) {
2530 case PACKET3_SET_BASE
:
2531 case PACKET3_SET_CE_DE_COUNTERS
:
2532 case PACKET3_LOAD_CONST_RAM
:
2533 case PACKET3_WRITE_CONST_RAM
:
2534 case PACKET3_WRITE_CONST_RAM_OFFSET
:
2535 case PACKET3_DUMP_CONST_RAM
:
2536 case PACKET3_INCREMENT_CE_COUNTER
:
2537 case PACKET3_WAIT_ON_DE_COUNTER
:
2538 case PACKET3_CE_WRITE
:
2541 DRM_ERROR("Invalid CE packet3: 0x%x\n", pkt
->opcode
);
2547 static int si_vm_packet3_gfx_check(struct radeon_device
*rdev
,
2548 u32
*ib
, struct radeon_cs_packet
*pkt
)
2550 u32 idx
= pkt
->idx
+ 1;
2551 u32 idx_value
= ib
[idx
];
2552 u32 start_reg
, end_reg
, reg
, i
;
2555 switch (pkt
->opcode
) {
2557 case PACKET3_SET_BASE
:
2558 case PACKET3_CLEAR_STATE
:
2559 case PACKET3_INDEX_BUFFER_SIZE
:
2560 case PACKET3_DISPATCH_DIRECT
:
2561 case PACKET3_DISPATCH_INDIRECT
:
2562 case PACKET3_ALLOC_GDS
:
2563 case PACKET3_WRITE_GDS_RAM
:
2564 case PACKET3_ATOMIC_GDS
:
2565 case PACKET3_ATOMIC
:
2566 case PACKET3_OCCLUSION_QUERY
:
2567 case PACKET3_SET_PREDICATION
:
2568 case PACKET3_COND_EXEC
:
2569 case PACKET3_PRED_EXEC
:
2570 case PACKET3_DRAW_INDIRECT
:
2571 case PACKET3_DRAW_INDEX_INDIRECT
:
2572 case PACKET3_INDEX_BASE
:
2573 case PACKET3_DRAW_INDEX_2
:
2574 case PACKET3_CONTEXT_CONTROL
:
2575 case PACKET3_INDEX_TYPE
:
2576 case PACKET3_DRAW_INDIRECT_MULTI
:
2577 case PACKET3_DRAW_INDEX_AUTO
:
2578 case PACKET3_DRAW_INDEX_IMMD
:
2579 case PACKET3_NUM_INSTANCES
:
2580 case PACKET3_DRAW_INDEX_MULTI_AUTO
:
2581 case PACKET3_STRMOUT_BUFFER_UPDATE
:
2582 case PACKET3_DRAW_INDEX_OFFSET_2
:
2583 case PACKET3_DRAW_INDEX_MULTI_ELEMENT
:
2584 case PACKET3_DRAW_INDEX_INDIRECT_MULTI
:
2585 case PACKET3_MPEG_INDEX
:
2586 case PACKET3_WAIT_REG_MEM
:
2587 case PACKET3_MEM_WRITE
:
2588 case PACKET3_PFP_SYNC_ME
:
2589 case PACKET3_SURFACE_SYNC
:
2590 case PACKET3_EVENT_WRITE
:
2591 case PACKET3_EVENT_WRITE_EOP
:
2592 case PACKET3_EVENT_WRITE_EOS
:
2593 case PACKET3_SET_CONTEXT_REG
:
2594 case PACKET3_SET_CONTEXT_REG_INDIRECT
:
2595 case PACKET3_SET_SH_REG
:
2596 case PACKET3_SET_SH_REG_OFFSET
:
2597 case PACKET3_INCREMENT_DE_COUNTER
:
2598 case PACKET3_WAIT_ON_CE_COUNTER
:
2599 case PACKET3_WAIT_ON_AVAIL_BUFFER
:
2600 case PACKET3_ME_WRITE
:
2602 case PACKET3_COPY_DATA
:
2603 if ((idx_value
& 0xf00) == 0) {
2604 reg
= ib
[idx
+ 3] * 4;
2605 if (!si_vm_reg_valid(reg
))
2609 case PACKET3_WRITE_DATA
:
2610 if ((idx_value
& 0xf00) == 0) {
2611 start_reg
= ib
[idx
+ 1] * 4;
2612 if (idx_value
& 0x10000) {
2613 if (!si_vm_reg_valid(start_reg
))
2616 for (i
= 0; i
< (pkt
->count
- 2); i
++) {
2617 reg
= start_reg
+ (4 * i
);
2618 if (!si_vm_reg_valid(reg
))
2624 case PACKET3_COND_WRITE
:
2625 if (idx_value
& 0x100) {
2626 reg
= ib
[idx
+ 5] * 4;
2627 if (!si_vm_reg_valid(reg
))
2631 case PACKET3_COPY_DW
:
2632 if (idx_value
& 0x2) {
2633 reg
= ib
[idx
+ 3] * 4;
2634 if (!si_vm_reg_valid(reg
))
2638 case PACKET3_SET_CONFIG_REG
:
2639 start_reg
= (idx_value
<< 2) + PACKET3_SET_CONFIG_REG_START
;
2640 end_reg
= 4 * pkt
->count
+ start_reg
- 4;
2641 if ((start_reg
< PACKET3_SET_CONFIG_REG_START
) ||
2642 (start_reg
>= PACKET3_SET_CONFIG_REG_END
) ||
2643 (end_reg
>= PACKET3_SET_CONFIG_REG_END
)) {
2644 DRM_ERROR("bad PACKET3_SET_CONFIG_REG\n");
2647 for (i
= 0; i
< pkt
->count
; i
++) {
2648 reg
= start_reg
+ (4 * i
);
2649 if (!si_vm_reg_valid(reg
))
2653 case PACKET3_CP_DMA
:
2654 command
= ib
[idx
+ 4];
2656 if (command
& PACKET3_CP_DMA_CMD_SAS
) {
2657 /* src address space is register */
2658 if (((info
& 0x60000000) >> 29) == 0) {
2659 start_reg
= idx_value
<< 2;
2660 if (command
& PACKET3_CP_DMA_CMD_SAIC
) {
2662 if (!si_vm_reg_valid(reg
)) {
2663 DRM_ERROR("CP DMA Bad SRC register\n");
2667 for (i
= 0; i
< (command
& 0x1fffff); i
++) {
2668 reg
= start_reg
+ (4 * i
);
2669 if (!si_vm_reg_valid(reg
)) {
2670 DRM_ERROR("CP DMA Bad SRC register\n");
2677 if (command
& PACKET3_CP_DMA_CMD_DAS
) {
2678 /* dst address space is register */
2679 if (((info
& 0x00300000) >> 20) == 0) {
2680 start_reg
= ib
[idx
+ 2];
2681 if (command
& PACKET3_CP_DMA_CMD_DAIC
) {
2683 if (!si_vm_reg_valid(reg
)) {
2684 DRM_ERROR("CP DMA Bad DST register\n");
2688 for (i
= 0; i
< (command
& 0x1fffff); i
++) {
2689 reg
= start_reg
+ (4 * i
);
2690 if (!si_vm_reg_valid(reg
)) {
2691 DRM_ERROR("CP DMA Bad DST register\n");
2700 DRM_ERROR("Invalid GFX packet3: 0x%x\n", pkt
->opcode
);
2706 static int si_vm_packet3_compute_check(struct radeon_device
*rdev
,
2707 u32
*ib
, struct radeon_cs_packet
*pkt
)
2709 u32 idx
= pkt
->idx
+ 1;
2710 u32 idx_value
= ib
[idx
];
2711 u32 start_reg
, reg
, i
;
2713 switch (pkt
->opcode
) {
2715 case PACKET3_SET_BASE
:
2716 case PACKET3_CLEAR_STATE
:
2717 case PACKET3_DISPATCH_DIRECT
:
2718 case PACKET3_DISPATCH_INDIRECT
:
2719 case PACKET3_ALLOC_GDS
:
2720 case PACKET3_WRITE_GDS_RAM
:
2721 case PACKET3_ATOMIC_GDS
:
2722 case PACKET3_ATOMIC
:
2723 case PACKET3_OCCLUSION_QUERY
:
2724 case PACKET3_SET_PREDICATION
:
2725 case PACKET3_COND_EXEC
:
2726 case PACKET3_PRED_EXEC
:
2727 case PACKET3_CONTEXT_CONTROL
:
2728 case PACKET3_STRMOUT_BUFFER_UPDATE
:
2729 case PACKET3_WAIT_REG_MEM
:
2730 case PACKET3_MEM_WRITE
:
2731 case PACKET3_PFP_SYNC_ME
:
2732 case PACKET3_SURFACE_SYNC
:
2733 case PACKET3_EVENT_WRITE
:
2734 case PACKET3_EVENT_WRITE_EOP
:
2735 case PACKET3_EVENT_WRITE_EOS
:
2736 case PACKET3_SET_CONTEXT_REG
:
2737 case PACKET3_SET_CONTEXT_REG_INDIRECT
:
2738 case PACKET3_SET_SH_REG
:
2739 case PACKET3_SET_SH_REG_OFFSET
:
2740 case PACKET3_INCREMENT_DE_COUNTER
:
2741 case PACKET3_WAIT_ON_CE_COUNTER
:
2742 case PACKET3_WAIT_ON_AVAIL_BUFFER
:
2743 case PACKET3_ME_WRITE
:
2745 case PACKET3_COPY_DATA
:
2746 if ((idx_value
& 0xf00) == 0) {
2747 reg
= ib
[idx
+ 3] * 4;
2748 if (!si_vm_reg_valid(reg
))
2752 case PACKET3_WRITE_DATA
:
2753 if ((idx_value
& 0xf00) == 0) {
2754 start_reg
= ib
[idx
+ 1] * 4;
2755 if (idx_value
& 0x10000) {
2756 if (!si_vm_reg_valid(start_reg
))
2759 for (i
= 0; i
< (pkt
->count
- 2); i
++) {
2760 reg
= start_reg
+ (4 * i
);
2761 if (!si_vm_reg_valid(reg
))
2767 case PACKET3_COND_WRITE
:
2768 if (idx_value
& 0x100) {
2769 reg
= ib
[idx
+ 5] * 4;
2770 if (!si_vm_reg_valid(reg
))
2774 case PACKET3_COPY_DW
:
2775 if (idx_value
& 0x2) {
2776 reg
= ib
[idx
+ 3] * 4;
2777 if (!si_vm_reg_valid(reg
))
2782 DRM_ERROR("Invalid Compute packet3: 0x%x\n", pkt
->opcode
);
2788 int si_ib_parse(struct radeon_device
*rdev
, struct radeon_ib
*ib
)
2792 struct radeon_cs_packet pkt
;
2796 pkt
.type
= CP_PACKET_GET_TYPE(ib
->ptr
[idx
]);
2797 pkt
.count
= CP_PACKET_GET_COUNT(ib
->ptr
[idx
]);
2801 dev_err(rdev
->dev
, "Packet0 not allowed!\n");
2808 pkt
.opcode
= CP_PACKET3_GET_OPCODE(ib
->ptr
[idx
]);
2809 if (ib
->is_const_ib
)
2810 ret
= si_vm_packet3_ce_check(rdev
, ib
->ptr
, &pkt
);
2813 case RADEON_RING_TYPE_GFX_INDEX
:
2814 ret
= si_vm_packet3_gfx_check(rdev
, ib
->ptr
, &pkt
);
2816 case CAYMAN_RING_TYPE_CP1_INDEX
:
2817 case CAYMAN_RING_TYPE_CP2_INDEX
:
2818 ret
= si_vm_packet3_compute_check(rdev
, ib
->ptr
, &pkt
);
2821 dev_err(rdev
->dev
, "Non-PM4 ring %d !\n", ib
->ring
);
2826 idx
+= pkt
.count
+ 2;
2829 dev_err(rdev
->dev
, "Unknown packet type %d !\n", pkt
.type
);
2835 } while (idx
< ib
->length_dw
);
2843 int si_vm_init(struct radeon_device
*rdev
)
2846 rdev
->vm_manager
.nvm
= 16;
2847 /* base offset of vram pages */
2848 rdev
->vm_manager
.vram_base_offset
= 0;
2853 void si_vm_fini(struct radeon_device
*rdev
)
2858 * si_vm_set_page - update the page tables using the CP
2860 * @rdev: radeon_device pointer
2861 * @pe: addr of the page entry
2862 * @addr: dst addr to write into pe
2863 * @count: number of page entries to update
2864 * @incr: increase next addr by incr bytes
2865 * @flags: access flags
2867 * Update the page tables using the CP (cayman-si).
2869 void si_vm_set_page(struct radeon_device
*rdev
, uint64_t pe
,
2870 uint64_t addr
, unsigned count
,
2871 uint32_t incr
, uint32_t flags
)
2873 struct radeon_ring
*ring
= &rdev
->ring
[rdev
->asic
->vm
.pt_ring_index
];
2874 uint32_t r600_flags
= cayman_vm_page_flags(rdev
, flags
);
2878 if (rdev
->asic
->vm
.pt_ring_index
== RADEON_RING_TYPE_GFX_INDEX
) {
2880 ndw
= 2 + count
* 2;
2884 radeon_ring_write(ring
, PACKET3(PACKET3_WRITE_DATA
, ndw
));
2885 radeon_ring_write(ring
, (WRITE_DATA_ENGINE_SEL(0) |
2886 WRITE_DATA_DST_SEL(1)));
2887 radeon_ring_write(ring
, pe
);
2888 radeon_ring_write(ring
, upper_32_bits(pe
));
2889 for (; ndw
> 2; ndw
-= 2, --count
, pe
+= 8) {
2890 if (flags
& RADEON_VM_PAGE_SYSTEM
) {
2891 value
= radeon_vm_map_gart(rdev
, addr
);
2892 value
&= 0xFFFFFFFFFFFFF000ULL
;
2893 } else if (flags
& RADEON_VM_PAGE_VALID
) {
2899 value
|= r600_flags
;
2900 radeon_ring_write(ring
, value
);
2901 radeon_ring_write(ring
, upper_32_bits(value
));
2906 if (flags
& RADEON_VM_PAGE_SYSTEM
) {
2912 /* for non-physically contiguous pages (system) */
2913 radeon_ring_write(ring
, DMA_PACKET(DMA_PACKET_WRITE
, 0, 0, 0, ndw
));
2914 radeon_ring_write(ring
, pe
);
2915 radeon_ring_write(ring
, upper_32_bits(pe
) & 0xff);
2916 for (; ndw
> 0; ndw
-= 2, --count
, pe
+= 8) {
2917 if (flags
& RADEON_VM_PAGE_SYSTEM
) {
2918 value
= radeon_vm_map_gart(rdev
, addr
);
2919 value
&= 0xFFFFFFFFFFFFF000ULL
;
2920 } else if (flags
& RADEON_VM_PAGE_VALID
) {
2926 value
|= r600_flags
;
2927 radeon_ring_write(ring
, value
);
2928 radeon_ring_write(ring
, upper_32_bits(value
));
2937 if (flags
& RADEON_VM_PAGE_VALID
)
2941 /* for physically contiguous pages (vram) */
2942 radeon_ring_write(ring
, DMA_PTE_PDE_PACKET(ndw
));
2943 radeon_ring_write(ring
, pe
); /* dst addr */
2944 radeon_ring_write(ring
, upper_32_bits(pe
) & 0xff);
2945 radeon_ring_write(ring
, r600_flags
); /* mask */
2946 radeon_ring_write(ring
, 0);
2947 radeon_ring_write(ring
, value
); /* value */
2948 radeon_ring_write(ring
, upper_32_bits(value
));
2949 radeon_ring_write(ring
, incr
); /* increment size */
2950 radeon_ring_write(ring
, 0);
2952 addr
+= (ndw
/ 2) * incr
;
2959 void si_vm_flush(struct radeon_device
*rdev
, int ridx
, struct radeon_vm
*vm
)
2961 struct radeon_ring
*ring
= &rdev
->ring
[ridx
];
2966 /* write new base address */
2967 radeon_ring_write(ring
, PACKET3(PACKET3_WRITE_DATA
, 3));
2968 radeon_ring_write(ring
, (WRITE_DATA_ENGINE_SEL(0) |
2969 WRITE_DATA_DST_SEL(0)));
2972 radeon_ring_write(ring
,
2973 (VM_CONTEXT0_PAGE_TABLE_BASE_ADDR
+ (vm
->id
<< 2)) >> 2);
2975 radeon_ring_write(ring
,
2976 (VM_CONTEXT8_PAGE_TABLE_BASE_ADDR
+ ((vm
->id
- 8) << 2)) >> 2);
2978 radeon_ring_write(ring
, 0);
2979 radeon_ring_write(ring
, vm
->pd_gpu_addr
>> 12);
2981 /* flush hdp cache */
2982 radeon_ring_write(ring
, PACKET3(PACKET3_WRITE_DATA
, 3));
2983 radeon_ring_write(ring
, (WRITE_DATA_ENGINE_SEL(0) |
2984 WRITE_DATA_DST_SEL(0)));
2985 radeon_ring_write(ring
, HDP_MEM_COHERENCY_FLUSH_CNTL
>> 2);
2986 radeon_ring_write(ring
, 0);
2987 radeon_ring_write(ring
, 0x1);
2989 /* bits 0-15 are the VM contexts0-15 */
2990 radeon_ring_write(ring
, PACKET3(PACKET3_WRITE_DATA
, 3));
2991 radeon_ring_write(ring
, (WRITE_DATA_ENGINE_SEL(0) |
2992 WRITE_DATA_DST_SEL(0)));
2993 radeon_ring_write(ring
, VM_INVALIDATE_REQUEST
>> 2);
2994 radeon_ring_write(ring
, 0);
2995 radeon_ring_write(ring
, 1 << vm
->id
);
2997 /* sync PFP to ME, otherwise we might get invalid PFP reads */
2998 radeon_ring_write(ring
, PACKET3(PACKET3_PFP_SYNC_ME
, 0));
2999 radeon_ring_write(ring
, 0x0);
3002 void si_dma_vm_flush(struct radeon_device
*rdev
, int ridx
, struct radeon_vm
*vm
)
3004 struct radeon_ring
*ring
= &rdev
->ring
[ridx
];
3009 radeon_ring_write(ring
, DMA_PACKET(DMA_PACKET_SRBM_WRITE
, 0, 0, 0, 0));
3011 radeon_ring_write(ring
, (0xf << 16) | ((VM_CONTEXT0_PAGE_TABLE_BASE_ADDR
+ (vm
->id
<< 2)) >> 2));
3013 radeon_ring_write(ring
, (0xf << 16) | ((VM_CONTEXT8_PAGE_TABLE_BASE_ADDR
+ ((vm
->id
- 8) << 2)) >> 2));
3015 radeon_ring_write(ring
, vm
->pd_gpu_addr
>> 12);
3017 /* flush hdp cache */
3018 radeon_ring_write(ring
, DMA_PACKET(DMA_PACKET_SRBM_WRITE
, 0, 0, 0, 0));
3019 radeon_ring_write(ring
, (0xf << 16) | (HDP_MEM_COHERENCY_FLUSH_CNTL
>> 2));
3020 radeon_ring_write(ring
, 1);
3022 /* bits 0-7 are the VM contexts0-7 */
3023 radeon_ring_write(ring
, DMA_PACKET(DMA_PACKET_SRBM_WRITE
, 0, 0, 0, 0));
3024 radeon_ring_write(ring
, (0xf << 16) | (VM_INVALIDATE_REQUEST
>> 2));
3025 radeon_ring_write(ring
, 1 << vm
->id
);
3031 void si_rlc_fini(struct radeon_device
*rdev
)
3035 /* save restore block */
3036 if (rdev
->rlc
.save_restore_obj
) {
3037 r
= radeon_bo_reserve(rdev
->rlc
.save_restore_obj
, false);
3038 if (unlikely(r
!= 0))
3039 dev_warn(rdev
->dev
, "(%d) reserve RLC sr bo failed\n", r
);
3040 radeon_bo_unpin(rdev
->rlc
.save_restore_obj
);
3041 radeon_bo_unreserve(rdev
->rlc
.save_restore_obj
);
3043 radeon_bo_unref(&rdev
->rlc
.save_restore_obj
);
3044 rdev
->rlc
.save_restore_obj
= NULL
;
3047 /* clear state block */
3048 if (rdev
->rlc
.clear_state_obj
) {
3049 r
= radeon_bo_reserve(rdev
->rlc
.clear_state_obj
, false);
3050 if (unlikely(r
!= 0))
3051 dev_warn(rdev
->dev
, "(%d) reserve RLC c bo failed\n", r
);
3052 radeon_bo_unpin(rdev
->rlc
.clear_state_obj
);
3053 radeon_bo_unreserve(rdev
->rlc
.clear_state_obj
);
3055 radeon_bo_unref(&rdev
->rlc
.clear_state_obj
);
3056 rdev
->rlc
.clear_state_obj
= NULL
;
3060 int si_rlc_init(struct radeon_device
*rdev
)
3064 /* save restore block */
3065 if (rdev
->rlc
.save_restore_obj
== NULL
) {
3066 r
= radeon_bo_create(rdev
, RADEON_GPU_PAGE_SIZE
, PAGE_SIZE
, true,
3067 RADEON_GEM_DOMAIN_VRAM
, NULL
,
3068 &rdev
->rlc
.save_restore_obj
);
3070 dev_warn(rdev
->dev
, "(%d) create RLC sr bo failed\n", r
);
3075 r
= radeon_bo_reserve(rdev
->rlc
.save_restore_obj
, false);
3076 if (unlikely(r
!= 0)) {
3080 r
= radeon_bo_pin(rdev
->rlc
.save_restore_obj
, RADEON_GEM_DOMAIN_VRAM
,
3081 &rdev
->rlc
.save_restore_gpu_addr
);
3082 radeon_bo_unreserve(rdev
->rlc
.save_restore_obj
);
3084 dev_warn(rdev
->dev
, "(%d) pin RLC sr bo failed\n", r
);
3089 /* clear state block */
3090 if (rdev
->rlc
.clear_state_obj
== NULL
) {
3091 r
= radeon_bo_create(rdev
, RADEON_GPU_PAGE_SIZE
, PAGE_SIZE
, true,
3092 RADEON_GEM_DOMAIN_VRAM
, NULL
,
3093 &rdev
->rlc
.clear_state_obj
);
3095 dev_warn(rdev
->dev
, "(%d) create RLC c bo failed\n", r
);
3100 r
= radeon_bo_reserve(rdev
->rlc
.clear_state_obj
, false);
3101 if (unlikely(r
!= 0)) {
3105 r
= radeon_bo_pin(rdev
->rlc
.clear_state_obj
, RADEON_GEM_DOMAIN_VRAM
,
3106 &rdev
->rlc
.clear_state_gpu_addr
);
3107 radeon_bo_unreserve(rdev
->rlc
.clear_state_obj
);
3109 dev_warn(rdev
->dev
, "(%d) pin RLC c bo failed\n", r
);
3117 static void si_rlc_stop(struct radeon_device
*rdev
)
3119 WREG32(RLC_CNTL
, 0);
3122 static void si_rlc_start(struct radeon_device
*rdev
)
3124 WREG32(RLC_CNTL
, RLC_ENABLE
);
3127 static int si_rlc_resume(struct radeon_device
*rdev
)
3130 const __be32
*fw_data
;
3137 WREG32(RLC_RL_BASE
, 0);
3138 WREG32(RLC_RL_SIZE
, 0);
3139 WREG32(RLC_LB_CNTL
, 0);
3140 WREG32(RLC_LB_CNTR_MAX
, 0xffffffff);
3141 WREG32(RLC_LB_CNTR_INIT
, 0);
3143 WREG32(RLC_SAVE_AND_RESTORE_BASE
, rdev
->rlc
.save_restore_gpu_addr
>> 8);
3144 WREG32(RLC_CLEAR_STATE_RESTORE_BASE
, rdev
->rlc
.clear_state_gpu_addr
>> 8);
3146 WREG32(RLC_MC_CNTL
, 0);
3147 WREG32(RLC_UCODE_CNTL
, 0);
3149 fw_data
= (const __be32
*)rdev
->rlc_fw
->data
;
3150 for (i
= 0; i
< SI_RLC_UCODE_SIZE
; i
++) {
3151 WREG32(RLC_UCODE_ADDR
, i
);
3152 WREG32(RLC_UCODE_DATA
, be32_to_cpup(fw_data
++));
3154 WREG32(RLC_UCODE_ADDR
, 0);
3161 static void si_enable_interrupts(struct radeon_device
*rdev
)
3163 u32 ih_cntl
= RREG32(IH_CNTL
);
3164 u32 ih_rb_cntl
= RREG32(IH_RB_CNTL
);
3166 ih_cntl
|= ENABLE_INTR
;
3167 ih_rb_cntl
|= IH_RB_ENABLE
;
3168 WREG32(IH_CNTL
, ih_cntl
);
3169 WREG32(IH_RB_CNTL
, ih_rb_cntl
);
3170 rdev
->ih
.enabled
= true;
3173 static void si_disable_interrupts(struct radeon_device
*rdev
)
3175 u32 ih_rb_cntl
= RREG32(IH_RB_CNTL
);
3176 u32 ih_cntl
= RREG32(IH_CNTL
);
3178 ih_rb_cntl
&= ~IH_RB_ENABLE
;
3179 ih_cntl
&= ~ENABLE_INTR
;
3180 WREG32(IH_RB_CNTL
, ih_rb_cntl
);
3181 WREG32(IH_CNTL
, ih_cntl
);
3182 /* set rptr, wptr to 0 */
3183 WREG32(IH_RB_RPTR
, 0);
3184 WREG32(IH_RB_WPTR
, 0);
3185 rdev
->ih
.enabled
= false;
3189 static void si_disable_interrupt_state(struct radeon_device
*rdev
)
3193 WREG32(CP_INT_CNTL_RING0
, CNTX_BUSY_INT_ENABLE
| CNTX_EMPTY_INT_ENABLE
);
3194 WREG32(CP_INT_CNTL_RING1
, 0);
3195 WREG32(CP_INT_CNTL_RING2
, 0);
3196 tmp
= RREG32(DMA_CNTL
+ DMA0_REGISTER_OFFSET
) & ~TRAP_ENABLE
;
3197 WREG32(DMA_CNTL
+ DMA0_REGISTER_OFFSET
, tmp
);
3198 tmp
= RREG32(DMA_CNTL
+ DMA1_REGISTER_OFFSET
) & ~TRAP_ENABLE
;
3199 WREG32(DMA_CNTL
+ DMA1_REGISTER_OFFSET
, tmp
);
3200 WREG32(GRBM_INT_CNTL
, 0);
3201 WREG32(INT_MASK
+ EVERGREEN_CRTC0_REGISTER_OFFSET
, 0);
3202 WREG32(INT_MASK
+ EVERGREEN_CRTC1_REGISTER_OFFSET
, 0);
3203 if (rdev
->num_crtc
>= 4) {
3204 WREG32(INT_MASK
+ EVERGREEN_CRTC2_REGISTER_OFFSET
, 0);
3205 WREG32(INT_MASK
+ EVERGREEN_CRTC3_REGISTER_OFFSET
, 0);
3207 if (rdev
->num_crtc
>= 6) {
3208 WREG32(INT_MASK
+ EVERGREEN_CRTC4_REGISTER_OFFSET
, 0);
3209 WREG32(INT_MASK
+ EVERGREEN_CRTC5_REGISTER_OFFSET
, 0);
3212 WREG32(GRPH_INT_CONTROL
+ EVERGREEN_CRTC0_REGISTER_OFFSET
, 0);
3213 WREG32(GRPH_INT_CONTROL
+ EVERGREEN_CRTC1_REGISTER_OFFSET
, 0);
3214 if (rdev
->num_crtc
>= 4) {
3215 WREG32(GRPH_INT_CONTROL
+ EVERGREEN_CRTC2_REGISTER_OFFSET
, 0);
3216 WREG32(GRPH_INT_CONTROL
+ EVERGREEN_CRTC3_REGISTER_OFFSET
, 0);
3218 if (rdev
->num_crtc
>= 6) {
3219 WREG32(GRPH_INT_CONTROL
+ EVERGREEN_CRTC4_REGISTER_OFFSET
, 0);
3220 WREG32(GRPH_INT_CONTROL
+ EVERGREEN_CRTC5_REGISTER_OFFSET
, 0);
3223 WREG32(DACA_AUTODETECT_INT_CONTROL
, 0);
3225 tmp
= RREG32(DC_HPD1_INT_CONTROL
) & DC_HPDx_INT_POLARITY
;
3226 WREG32(DC_HPD1_INT_CONTROL
, tmp
);
3227 tmp
= RREG32(DC_HPD2_INT_CONTROL
) & DC_HPDx_INT_POLARITY
;
3228 WREG32(DC_HPD2_INT_CONTROL
, tmp
);
3229 tmp
= RREG32(DC_HPD3_INT_CONTROL
) & DC_HPDx_INT_POLARITY
;
3230 WREG32(DC_HPD3_INT_CONTROL
, tmp
);
3231 tmp
= RREG32(DC_HPD4_INT_CONTROL
) & DC_HPDx_INT_POLARITY
;
3232 WREG32(DC_HPD4_INT_CONTROL
, tmp
);
3233 tmp
= RREG32(DC_HPD5_INT_CONTROL
) & DC_HPDx_INT_POLARITY
;
3234 WREG32(DC_HPD5_INT_CONTROL
, tmp
);
3235 tmp
= RREG32(DC_HPD6_INT_CONTROL
) & DC_HPDx_INT_POLARITY
;
3236 WREG32(DC_HPD6_INT_CONTROL
, tmp
);
3240 static int si_irq_init(struct radeon_device
*rdev
)
3244 u32 interrupt_cntl
, ih_cntl
, ih_rb_cntl
;
3247 ret
= r600_ih_ring_alloc(rdev
);
3252 si_disable_interrupts(rdev
);
3255 ret
= si_rlc_resume(rdev
);
3257 r600_ih_ring_fini(rdev
);
3261 /* setup interrupt control */
3262 /* set dummy read address to ring address */
3263 WREG32(INTERRUPT_CNTL2
, rdev
->ih
.gpu_addr
>> 8);
3264 interrupt_cntl
= RREG32(INTERRUPT_CNTL
);
3265 /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi
3266 * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN
3268 interrupt_cntl
&= ~IH_DUMMY_RD_OVERRIDE
;
3269 /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */
3270 interrupt_cntl
&= ~IH_REQ_NONSNOOP_EN
;
3271 WREG32(INTERRUPT_CNTL
, interrupt_cntl
);
3273 WREG32(IH_RB_BASE
, rdev
->ih
.gpu_addr
>> 8);
3274 rb_bufsz
= drm_order(rdev
->ih
.ring_size
/ 4);
3276 ih_rb_cntl
= (IH_WPTR_OVERFLOW_ENABLE
|
3277 IH_WPTR_OVERFLOW_CLEAR
|
3280 if (rdev
->wb
.enabled
)
3281 ih_rb_cntl
|= IH_WPTR_WRITEBACK_ENABLE
;
3283 /* set the writeback address whether it's enabled or not */
3284 WREG32(IH_RB_WPTR_ADDR_LO
, (rdev
->wb
.gpu_addr
+ R600_WB_IH_WPTR_OFFSET
) & 0xFFFFFFFC);
3285 WREG32(IH_RB_WPTR_ADDR_HI
, upper_32_bits(rdev
->wb
.gpu_addr
+ R600_WB_IH_WPTR_OFFSET
) & 0xFF);
3287 WREG32(IH_RB_CNTL
, ih_rb_cntl
);
3289 /* set rptr, wptr to 0 */
3290 WREG32(IH_RB_RPTR
, 0);
3291 WREG32(IH_RB_WPTR
, 0);
3293 /* Default settings for IH_CNTL (disabled at first) */
3294 ih_cntl
= MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10) | MC_VMID(0);
3295 /* RPTR_REARM only works if msi's are enabled */
3296 if (rdev
->msi_enabled
)
3297 ih_cntl
|= RPTR_REARM
;
3298 WREG32(IH_CNTL
, ih_cntl
);
3300 /* force the active interrupt state to all disabled */
3301 si_disable_interrupt_state(rdev
);
3303 pci_set_master(rdev
->pdev
);
3306 si_enable_interrupts(rdev
);
3311 int si_irq_set(struct radeon_device
*rdev
)
3313 u32 cp_int_cntl
= CNTX_BUSY_INT_ENABLE
| CNTX_EMPTY_INT_ENABLE
;
3314 u32 cp_int_cntl1
= 0, cp_int_cntl2
= 0;
3315 u32 crtc1
= 0, crtc2
= 0, crtc3
= 0, crtc4
= 0, crtc5
= 0, crtc6
= 0;
3316 u32 hpd1
, hpd2
, hpd3
, hpd4
, hpd5
, hpd6
;
3317 u32 grbm_int_cntl
= 0;
3318 u32 grph1
= 0, grph2
= 0, grph3
= 0, grph4
= 0, grph5
= 0, grph6
= 0;
3319 u32 dma_cntl
, dma_cntl1
;
3321 if (!rdev
->irq
.installed
) {
3322 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
3325 /* don't enable anything if the ih is disabled */
3326 if (!rdev
->ih
.enabled
) {
3327 si_disable_interrupts(rdev
);
3328 /* force the active interrupt state to all disabled */
3329 si_disable_interrupt_state(rdev
);
3333 hpd1
= RREG32(DC_HPD1_INT_CONTROL
) & ~DC_HPDx_INT_EN
;
3334 hpd2
= RREG32(DC_HPD2_INT_CONTROL
) & ~DC_HPDx_INT_EN
;
3335 hpd3
= RREG32(DC_HPD3_INT_CONTROL
) & ~DC_HPDx_INT_EN
;
3336 hpd4
= RREG32(DC_HPD4_INT_CONTROL
) & ~DC_HPDx_INT_EN
;
3337 hpd5
= RREG32(DC_HPD5_INT_CONTROL
) & ~DC_HPDx_INT_EN
;
3338 hpd6
= RREG32(DC_HPD6_INT_CONTROL
) & ~DC_HPDx_INT_EN
;
3340 dma_cntl
= RREG32(DMA_CNTL
+ DMA0_REGISTER_OFFSET
) & ~TRAP_ENABLE
;
3341 dma_cntl1
= RREG32(DMA_CNTL
+ DMA1_REGISTER_OFFSET
) & ~TRAP_ENABLE
;
3343 /* enable CP interrupts on all rings */
3344 if (atomic_read(&rdev
->irq
.ring_int
[RADEON_RING_TYPE_GFX_INDEX
])) {
3345 DRM_DEBUG("si_irq_set: sw int gfx\n");
3346 cp_int_cntl
|= TIME_STAMP_INT_ENABLE
;
3348 if (atomic_read(&rdev
->irq
.ring_int
[CAYMAN_RING_TYPE_CP1_INDEX
])) {
3349 DRM_DEBUG("si_irq_set: sw int cp1\n");
3350 cp_int_cntl1
|= TIME_STAMP_INT_ENABLE
;
3352 if (atomic_read(&rdev
->irq
.ring_int
[CAYMAN_RING_TYPE_CP2_INDEX
])) {
3353 DRM_DEBUG("si_irq_set: sw int cp2\n");
3354 cp_int_cntl2
|= TIME_STAMP_INT_ENABLE
;
3356 if (atomic_read(&rdev
->irq
.ring_int
[R600_RING_TYPE_DMA_INDEX
])) {
3357 DRM_DEBUG("si_irq_set: sw int dma\n");
3358 dma_cntl
|= TRAP_ENABLE
;
3361 if (atomic_read(&rdev
->irq
.ring_int
[CAYMAN_RING_TYPE_DMA1_INDEX
])) {
3362 DRM_DEBUG("si_irq_set: sw int dma1\n");
3363 dma_cntl1
|= TRAP_ENABLE
;
3365 if (rdev
->irq
.crtc_vblank_int
[0] ||
3366 atomic_read(&rdev
->irq
.pflip
[0])) {
3367 DRM_DEBUG("si_irq_set: vblank 0\n");
3368 crtc1
|= VBLANK_INT_MASK
;
3370 if (rdev
->irq
.crtc_vblank_int
[1] ||
3371 atomic_read(&rdev
->irq
.pflip
[1])) {
3372 DRM_DEBUG("si_irq_set: vblank 1\n");
3373 crtc2
|= VBLANK_INT_MASK
;
3375 if (rdev
->irq
.crtc_vblank_int
[2] ||
3376 atomic_read(&rdev
->irq
.pflip
[2])) {
3377 DRM_DEBUG("si_irq_set: vblank 2\n");
3378 crtc3
|= VBLANK_INT_MASK
;
3380 if (rdev
->irq
.crtc_vblank_int
[3] ||
3381 atomic_read(&rdev
->irq
.pflip
[3])) {
3382 DRM_DEBUG("si_irq_set: vblank 3\n");
3383 crtc4
|= VBLANK_INT_MASK
;
3385 if (rdev
->irq
.crtc_vblank_int
[4] ||
3386 atomic_read(&rdev
->irq
.pflip
[4])) {
3387 DRM_DEBUG("si_irq_set: vblank 4\n");
3388 crtc5
|= VBLANK_INT_MASK
;
3390 if (rdev
->irq
.crtc_vblank_int
[5] ||
3391 atomic_read(&rdev
->irq
.pflip
[5])) {
3392 DRM_DEBUG("si_irq_set: vblank 5\n");
3393 crtc6
|= VBLANK_INT_MASK
;
3395 if (rdev
->irq
.hpd
[0]) {
3396 DRM_DEBUG("si_irq_set: hpd 1\n");
3397 hpd1
|= DC_HPDx_INT_EN
;
3399 if (rdev
->irq
.hpd
[1]) {
3400 DRM_DEBUG("si_irq_set: hpd 2\n");
3401 hpd2
|= DC_HPDx_INT_EN
;
3403 if (rdev
->irq
.hpd
[2]) {
3404 DRM_DEBUG("si_irq_set: hpd 3\n");
3405 hpd3
|= DC_HPDx_INT_EN
;
3407 if (rdev
->irq
.hpd
[3]) {
3408 DRM_DEBUG("si_irq_set: hpd 4\n");
3409 hpd4
|= DC_HPDx_INT_EN
;
3411 if (rdev
->irq
.hpd
[4]) {
3412 DRM_DEBUG("si_irq_set: hpd 5\n");
3413 hpd5
|= DC_HPDx_INT_EN
;
3415 if (rdev
->irq
.hpd
[5]) {
3416 DRM_DEBUG("si_irq_set: hpd 6\n");
3417 hpd6
|= DC_HPDx_INT_EN
;
3420 WREG32(CP_INT_CNTL_RING0
, cp_int_cntl
);
3421 WREG32(CP_INT_CNTL_RING1
, cp_int_cntl1
);
3422 WREG32(CP_INT_CNTL_RING2
, cp_int_cntl2
);
3424 WREG32(DMA_CNTL
+ DMA0_REGISTER_OFFSET
, dma_cntl
);
3425 WREG32(DMA_CNTL
+ DMA1_REGISTER_OFFSET
, dma_cntl1
);
3427 WREG32(GRBM_INT_CNTL
, grbm_int_cntl
);
3429 WREG32(INT_MASK
+ EVERGREEN_CRTC0_REGISTER_OFFSET
, crtc1
);
3430 WREG32(INT_MASK
+ EVERGREEN_CRTC1_REGISTER_OFFSET
, crtc2
);
3431 if (rdev
->num_crtc
>= 4) {
3432 WREG32(INT_MASK
+ EVERGREEN_CRTC2_REGISTER_OFFSET
, crtc3
);
3433 WREG32(INT_MASK
+ EVERGREEN_CRTC3_REGISTER_OFFSET
, crtc4
);
3435 if (rdev
->num_crtc
>= 6) {
3436 WREG32(INT_MASK
+ EVERGREEN_CRTC4_REGISTER_OFFSET
, crtc5
);
3437 WREG32(INT_MASK
+ EVERGREEN_CRTC5_REGISTER_OFFSET
, crtc6
);
3440 WREG32(GRPH_INT_CONTROL
+ EVERGREEN_CRTC0_REGISTER_OFFSET
, grph1
);
3441 WREG32(GRPH_INT_CONTROL
+ EVERGREEN_CRTC1_REGISTER_OFFSET
, grph2
);
3442 if (rdev
->num_crtc
>= 4) {
3443 WREG32(GRPH_INT_CONTROL
+ EVERGREEN_CRTC2_REGISTER_OFFSET
, grph3
);
3444 WREG32(GRPH_INT_CONTROL
+ EVERGREEN_CRTC3_REGISTER_OFFSET
, grph4
);
3446 if (rdev
->num_crtc
>= 6) {
3447 WREG32(GRPH_INT_CONTROL
+ EVERGREEN_CRTC4_REGISTER_OFFSET
, grph5
);
3448 WREG32(GRPH_INT_CONTROL
+ EVERGREEN_CRTC5_REGISTER_OFFSET
, grph6
);
3451 WREG32(DC_HPD1_INT_CONTROL
, hpd1
);
3452 WREG32(DC_HPD2_INT_CONTROL
, hpd2
);
3453 WREG32(DC_HPD3_INT_CONTROL
, hpd3
);
3454 WREG32(DC_HPD4_INT_CONTROL
, hpd4
);
3455 WREG32(DC_HPD5_INT_CONTROL
, hpd5
);
3456 WREG32(DC_HPD6_INT_CONTROL
, hpd6
);
3461 static inline void si_irq_ack(struct radeon_device
*rdev
)
3465 rdev
->irq
.stat_regs
.evergreen
.disp_int
= RREG32(DISP_INTERRUPT_STATUS
);
3466 rdev
->irq
.stat_regs
.evergreen
.disp_int_cont
= RREG32(DISP_INTERRUPT_STATUS_CONTINUE
);
3467 rdev
->irq
.stat_regs
.evergreen
.disp_int_cont2
= RREG32(DISP_INTERRUPT_STATUS_CONTINUE2
);
3468 rdev
->irq
.stat_regs
.evergreen
.disp_int_cont3
= RREG32(DISP_INTERRUPT_STATUS_CONTINUE3
);
3469 rdev
->irq
.stat_regs
.evergreen
.disp_int_cont4
= RREG32(DISP_INTERRUPT_STATUS_CONTINUE4
);
3470 rdev
->irq
.stat_regs
.evergreen
.disp_int_cont5
= RREG32(DISP_INTERRUPT_STATUS_CONTINUE5
);
3471 rdev
->irq
.stat_regs
.evergreen
.d1grph_int
= RREG32(GRPH_INT_STATUS
+ EVERGREEN_CRTC0_REGISTER_OFFSET
);
3472 rdev
->irq
.stat_regs
.evergreen
.d2grph_int
= RREG32(GRPH_INT_STATUS
+ EVERGREEN_CRTC1_REGISTER_OFFSET
);
3473 if (rdev
->num_crtc
>= 4) {
3474 rdev
->irq
.stat_regs
.evergreen
.d3grph_int
= RREG32(GRPH_INT_STATUS
+ EVERGREEN_CRTC2_REGISTER_OFFSET
);
3475 rdev
->irq
.stat_regs
.evergreen
.d4grph_int
= RREG32(GRPH_INT_STATUS
+ EVERGREEN_CRTC3_REGISTER_OFFSET
);
3477 if (rdev
->num_crtc
>= 6) {
3478 rdev
->irq
.stat_regs
.evergreen
.d5grph_int
= RREG32(GRPH_INT_STATUS
+ EVERGREEN_CRTC4_REGISTER_OFFSET
);
3479 rdev
->irq
.stat_regs
.evergreen
.d6grph_int
= RREG32(GRPH_INT_STATUS
+ EVERGREEN_CRTC5_REGISTER_OFFSET
);
3482 if (rdev
->irq
.stat_regs
.evergreen
.d1grph_int
& GRPH_PFLIP_INT_OCCURRED
)
3483 WREG32(GRPH_INT_STATUS
+ EVERGREEN_CRTC0_REGISTER_OFFSET
, GRPH_PFLIP_INT_CLEAR
);
3484 if (rdev
->irq
.stat_regs
.evergreen
.d2grph_int
& GRPH_PFLIP_INT_OCCURRED
)
3485 WREG32(GRPH_INT_STATUS
+ EVERGREEN_CRTC1_REGISTER_OFFSET
, GRPH_PFLIP_INT_CLEAR
);
3486 if (rdev
->irq
.stat_regs
.evergreen
.disp_int
& LB_D1_VBLANK_INTERRUPT
)
3487 WREG32(VBLANK_STATUS
+ EVERGREEN_CRTC0_REGISTER_OFFSET
, VBLANK_ACK
);
3488 if (rdev
->irq
.stat_regs
.evergreen
.disp_int
& LB_D1_VLINE_INTERRUPT
)
3489 WREG32(VLINE_STATUS
+ EVERGREEN_CRTC0_REGISTER_OFFSET
, VLINE_ACK
);
3490 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont
& LB_D2_VBLANK_INTERRUPT
)
3491 WREG32(VBLANK_STATUS
+ EVERGREEN_CRTC1_REGISTER_OFFSET
, VBLANK_ACK
);
3492 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont
& LB_D2_VLINE_INTERRUPT
)
3493 WREG32(VLINE_STATUS
+ EVERGREEN_CRTC1_REGISTER_OFFSET
, VLINE_ACK
);
3495 if (rdev
->num_crtc
>= 4) {
3496 if (rdev
->irq
.stat_regs
.evergreen
.d3grph_int
& GRPH_PFLIP_INT_OCCURRED
)
3497 WREG32(GRPH_INT_STATUS
+ EVERGREEN_CRTC2_REGISTER_OFFSET
, GRPH_PFLIP_INT_CLEAR
);
3498 if (rdev
->irq
.stat_regs
.evergreen
.d4grph_int
& GRPH_PFLIP_INT_OCCURRED
)
3499 WREG32(GRPH_INT_STATUS
+ EVERGREEN_CRTC3_REGISTER_OFFSET
, GRPH_PFLIP_INT_CLEAR
);
3500 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont2
& LB_D3_VBLANK_INTERRUPT
)
3501 WREG32(VBLANK_STATUS
+ EVERGREEN_CRTC2_REGISTER_OFFSET
, VBLANK_ACK
);
3502 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont2
& LB_D3_VLINE_INTERRUPT
)
3503 WREG32(VLINE_STATUS
+ EVERGREEN_CRTC2_REGISTER_OFFSET
, VLINE_ACK
);
3504 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont3
& LB_D4_VBLANK_INTERRUPT
)
3505 WREG32(VBLANK_STATUS
+ EVERGREEN_CRTC3_REGISTER_OFFSET
, VBLANK_ACK
);
3506 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont3
& LB_D4_VLINE_INTERRUPT
)
3507 WREG32(VLINE_STATUS
+ EVERGREEN_CRTC3_REGISTER_OFFSET
, VLINE_ACK
);
3510 if (rdev
->num_crtc
>= 6) {
3511 if (rdev
->irq
.stat_regs
.evergreen
.d5grph_int
& GRPH_PFLIP_INT_OCCURRED
)
3512 WREG32(GRPH_INT_STATUS
+ EVERGREEN_CRTC4_REGISTER_OFFSET
, GRPH_PFLIP_INT_CLEAR
);
3513 if (rdev
->irq
.stat_regs
.evergreen
.d6grph_int
& GRPH_PFLIP_INT_OCCURRED
)
3514 WREG32(GRPH_INT_STATUS
+ EVERGREEN_CRTC5_REGISTER_OFFSET
, GRPH_PFLIP_INT_CLEAR
);
3515 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont4
& LB_D5_VBLANK_INTERRUPT
)
3516 WREG32(VBLANK_STATUS
+ EVERGREEN_CRTC4_REGISTER_OFFSET
, VBLANK_ACK
);
3517 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont4
& LB_D5_VLINE_INTERRUPT
)
3518 WREG32(VLINE_STATUS
+ EVERGREEN_CRTC4_REGISTER_OFFSET
, VLINE_ACK
);
3519 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont5
& LB_D6_VBLANK_INTERRUPT
)
3520 WREG32(VBLANK_STATUS
+ EVERGREEN_CRTC5_REGISTER_OFFSET
, VBLANK_ACK
);
3521 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont5
& LB_D6_VLINE_INTERRUPT
)
3522 WREG32(VLINE_STATUS
+ EVERGREEN_CRTC5_REGISTER_OFFSET
, VLINE_ACK
);
3525 if (rdev
->irq
.stat_regs
.evergreen
.disp_int
& DC_HPD1_INTERRUPT
) {
3526 tmp
= RREG32(DC_HPD1_INT_CONTROL
);
3527 tmp
|= DC_HPDx_INT_ACK
;
3528 WREG32(DC_HPD1_INT_CONTROL
, tmp
);
3530 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont
& DC_HPD2_INTERRUPT
) {
3531 tmp
= RREG32(DC_HPD2_INT_CONTROL
);
3532 tmp
|= DC_HPDx_INT_ACK
;
3533 WREG32(DC_HPD2_INT_CONTROL
, tmp
);
3535 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont2
& DC_HPD3_INTERRUPT
) {
3536 tmp
= RREG32(DC_HPD3_INT_CONTROL
);
3537 tmp
|= DC_HPDx_INT_ACK
;
3538 WREG32(DC_HPD3_INT_CONTROL
, tmp
);
3540 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont3
& DC_HPD4_INTERRUPT
) {
3541 tmp
= RREG32(DC_HPD4_INT_CONTROL
);
3542 tmp
|= DC_HPDx_INT_ACK
;
3543 WREG32(DC_HPD4_INT_CONTROL
, tmp
);
3545 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont4
& DC_HPD5_INTERRUPT
) {
3546 tmp
= RREG32(DC_HPD5_INT_CONTROL
);
3547 tmp
|= DC_HPDx_INT_ACK
;
3548 WREG32(DC_HPD5_INT_CONTROL
, tmp
);
3550 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont5
& DC_HPD6_INTERRUPT
) {
3551 tmp
= RREG32(DC_HPD5_INT_CONTROL
);
3552 tmp
|= DC_HPDx_INT_ACK
;
3553 WREG32(DC_HPD6_INT_CONTROL
, tmp
);
3557 static void si_irq_disable(struct radeon_device
*rdev
)
3559 si_disable_interrupts(rdev
);
3560 /* Wait and acknowledge irq */
3563 si_disable_interrupt_state(rdev
);
3566 static void si_irq_suspend(struct radeon_device
*rdev
)
3568 si_irq_disable(rdev
);
3572 static void si_irq_fini(struct radeon_device
*rdev
)
3574 si_irq_suspend(rdev
);
3575 r600_ih_ring_fini(rdev
);
3578 static inline u32
si_get_ih_wptr(struct radeon_device
*rdev
)
3582 if (rdev
->wb
.enabled
)
3583 wptr
= le32_to_cpu(rdev
->wb
.wb
[R600_WB_IH_WPTR_OFFSET
/4]);
3585 wptr
= RREG32(IH_RB_WPTR
);
3587 if (wptr
& RB_OVERFLOW
) {
3588 /* When a ring buffer overflow happen start parsing interrupt
3589 * from the last not overwritten vector (wptr + 16). Hopefully
3590 * this should allow us to catchup.
3592 dev_warn(rdev
->dev
, "IH ring buffer overflow (0x%08X, %d, %d)\n",
3593 wptr
, rdev
->ih
.rptr
, (wptr
+ 16) + rdev
->ih
.ptr_mask
);
3594 rdev
->ih
.rptr
= (wptr
+ 16) & rdev
->ih
.ptr_mask
;
3595 tmp
= RREG32(IH_RB_CNTL
);
3596 tmp
|= IH_WPTR_OVERFLOW_CLEAR
;
3597 WREG32(IH_RB_CNTL
, tmp
);
3599 return (wptr
& rdev
->ih
.ptr_mask
);
3603 * Each IV ring entry is 128 bits:
3604 * [7:0] - interrupt source id
3606 * [59:32] - interrupt source data
3607 * [63:60] - reserved
3610 * [127:80] - reserved
3612 int si_irq_process(struct radeon_device
*rdev
)
3616 u32 src_id
, src_data
, ring_id
;
3618 bool queue_hotplug
= false;
3620 if (!rdev
->ih
.enabled
|| rdev
->shutdown
)
3623 wptr
= si_get_ih_wptr(rdev
);
3626 /* is somebody else already processing irqs? */
3627 if (atomic_xchg(&rdev
->ih
.lock
, 1))
3630 rptr
= rdev
->ih
.rptr
;
3631 DRM_DEBUG("si_irq_process start: rptr %d, wptr %d\n", rptr
, wptr
);
3633 /* Order reading of wptr vs. reading of IH ring data */
3636 /* display interrupts */
3639 while (rptr
!= wptr
) {
3640 /* wptr/rptr are in bytes! */
3641 ring_index
= rptr
/ 4;
3642 src_id
= le32_to_cpu(rdev
->ih
.ring
[ring_index
]) & 0xff;
3643 src_data
= le32_to_cpu(rdev
->ih
.ring
[ring_index
+ 1]) & 0xfffffff;
3644 ring_id
= le32_to_cpu(rdev
->ih
.ring
[ring_index
+ 2]) & 0xff;
3647 case 1: /* D1 vblank/vline */
3649 case 0: /* D1 vblank */
3650 if (rdev
->irq
.stat_regs
.evergreen
.disp_int
& LB_D1_VBLANK_INTERRUPT
) {
3651 if (rdev
->irq
.crtc_vblank_int
[0]) {
3652 drm_handle_vblank(rdev
->ddev
, 0);
3653 rdev
->pm
.vblank_sync
= true;
3654 wake_up(&rdev
->irq
.vblank_queue
);
3656 if (atomic_read(&rdev
->irq
.pflip
[0]))
3657 radeon_crtc_handle_flip(rdev
, 0);
3658 rdev
->irq
.stat_regs
.evergreen
.disp_int
&= ~LB_D1_VBLANK_INTERRUPT
;
3659 DRM_DEBUG("IH: D1 vblank\n");
3662 case 1: /* D1 vline */
3663 if (rdev
->irq
.stat_regs
.evergreen
.disp_int
& LB_D1_VLINE_INTERRUPT
) {
3664 rdev
->irq
.stat_regs
.evergreen
.disp_int
&= ~LB_D1_VLINE_INTERRUPT
;
3665 DRM_DEBUG("IH: D1 vline\n");
3669 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id
, src_data
);
3673 case 2: /* D2 vblank/vline */
3675 case 0: /* D2 vblank */
3676 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont
& LB_D2_VBLANK_INTERRUPT
) {
3677 if (rdev
->irq
.crtc_vblank_int
[1]) {
3678 drm_handle_vblank(rdev
->ddev
, 1);
3679 rdev
->pm
.vblank_sync
= true;
3680 wake_up(&rdev
->irq
.vblank_queue
);
3682 if (atomic_read(&rdev
->irq
.pflip
[1]))
3683 radeon_crtc_handle_flip(rdev
, 1);
3684 rdev
->irq
.stat_regs
.evergreen
.disp_int_cont
&= ~LB_D2_VBLANK_INTERRUPT
;
3685 DRM_DEBUG("IH: D2 vblank\n");
3688 case 1: /* D2 vline */
3689 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont
& LB_D2_VLINE_INTERRUPT
) {
3690 rdev
->irq
.stat_regs
.evergreen
.disp_int_cont
&= ~LB_D2_VLINE_INTERRUPT
;
3691 DRM_DEBUG("IH: D2 vline\n");
3695 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id
, src_data
);
3699 case 3: /* D3 vblank/vline */
3701 case 0: /* D3 vblank */
3702 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont2
& LB_D3_VBLANK_INTERRUPT
) {
3703 if (rdev
->irq
.crtc_vblank_int
[2]) {
3704 drm_handle_vblank(rdev
->ddev
, 2);
3705 rdev
->pm
.vblank_sync
= true;
3706 wake_up(&rdev
->irq
.vblank_queue
);
3708 if (atomic_read(&rdev
->irq
.pflip
[2]))
3709 radeon_crtc_handle_flip(rdev
, 2);
3710 rdev
->irq
.stat_regs
.evergreen
.disp_int_cont2
&= ~LB_D3_VBLANK_INTERRUPT
;
3711 DRM_DEBUG("IH: D3 vblank\n");
3714 case 1: /* D3 vline */
3715 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont2
& LB_D3_VLINE_INTERRUPT
) {
3716 rdev
->irq
.stat_regs
.evergreen
.disp_int_cont2
&= ~LB_D3_VLINE_INTERRUPT
;
3717 DRM_DEBUG("IH: D3 vline\n");
3721 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id
, src_data
);
3725 case 4: /* D4 vblank/vline */
3727 case 0: /* D4 vblank */
3728 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont3
& LB_D4_VBLANK_INTERRUPT
) {
3729 if (rdev
->irq
.crtc_vblank_int
[3]) {
3730 drm_handle_vblank(rdev
->ddev
, 3);
3731 rdev
->pm
.vblank_sync
= true;
3732 wake_up(&rdev
->irq
.vblank_queue
);
3734 if (atomic_read(&rdev
->irq
.pflip
[3]))
3735 radeon_crtc_handle_flip(rdev
, 3);
3736 rdev
->irq
.stat_regs
.evergreen
.disp_int_cont3
&= ~LB_D4_VBLANK_INTERRUPT
;
3737 DRM_DEBUG("IH: D4 vblank\n");
3740 case 1: /* D4 vline */
3741 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont3
& LB_D4_VLINE_INTERRUPT
) {
3742 rdev
->irq
.stat_regs
.evergreen
.disp_int_cont3
&= ~LB_D4_VLINE_INTERRUPT
;
3743 DRM_DEBUG("IH: D4 vline\n");
3747 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id
, src_data
);
3751 case 5: /* D5 vblank/vline */
3753 case 0: /* D5 vblank */
3754 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont4
& LB_D5_VBLANK_INTERRUPT
) {
3755 if (rdev
->irq
.crtc_vblank_int
[4]) {
3756 drm_handle_vblank(rdev
->ddev
, 4);
3757 rdev
->pm
.vblank_sync
= true;
3758 wake_up(&rdev
->irq
.vblank_queue
);
3760 if (atomic_read(&rdev
->irq
.pflip
[4]))
3761 radeon_crtc_handle_flip(rdev
, 4);
3762 rdev
->irq
.stat_regs
.evergreen
.disp_int_cont4
&= ~LB_D5_VBLANK_INTERRUPT
;
3763 DRM_DEBUG("IH: D5 vblank\n");
3766 case 1: /* D5 vline */
3767 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont4
& LB_D5_VLINE_INTERRUPT
) {
3768 rdev
->irq
.stat_regs
.evergreen
.disp_int_cont4
&= ~LB_D5_VLINE_INTERRUPT
;
3769 DRM_DEBUG("IH: D5 vline\n");
3773 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id
, src_data
);
3777 case 6: /* D6 vblank/vline */
3779 case 0: /* D6 vblank */
3780 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont5
& LB_D6_VBLANK_INTERRUPT
) {
3781 if (rdev
->irq
.crtc_vblank_int
[5]) {
3782 drm_handle_vblank(rdev
->ddev
, 5);
3783 rdev
->pm
.vblank_sync
= true;
3784 wake_up(&rdev
->irq
.vblank_queue
);
3786 if (atomic_read(&rdev
->irq
.pflip
[5]))
3787 radeon_crtc_handle_flip(rdev
, 5);
3788 rdev
->irq
.stat_regs
.evergreen
.disp_int_cont5
&= ~LB_D6_VBLANK_INTERRUPT
;
3789 DRM_DEBUG("IH: D6 vblank\n");
3792 case 1: /* D6 vline */
3793 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont5
& LB_D6_VLINE_INTERRUPT
) {
3794 rdev
->irq
.stat_regs
.evergreen
.disp_int_cont5
&= ~LB_D6_VLINE_INTERRUPT
;
3795 DRM_DEBUG("IH: D6 vline\n");
3799 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id
, src_data
);
3803 case 42: /* HPD hotplug */
3806 if (rdev
->irq
.stat_regs
.evergreen
.disp_int
& DC_HPD1_INTERRUPT
) {
3807 rdev
->irq
.stat_regs
.evergreen
.disp_int
&= ~DC_HPD1_INTERRUPT
;
3808 queue_hotplug
= true;
3809 DRM_DEBUG("IH: HPD1\n");
3813 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont
& DC_HPD2_INTERRUPT
) {
3814 rdev
->irq
.stat_regs
.evergreen
.disp_int_cont
&= ~DC_HPD2_INTERRUPT
;
3815 queue_hotplug
= true;
3816 DRM_DEBUG("IH: HPD2\n");
3820 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont2
& DC_HPD3_INTERRUPT
) {
3821 rdev
->irq
.stat_regs
.evergreen
.disp_int_cont2
&= ~DC_HPD3_INTERRUPT
;
3822 queue_hotplug
= true;
3823 DRM_DEBUG("IH: HPD3\n");
3827 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont3
& DC_HPD4_INTERRUPT
) {
3828 rdev
->irq
.stat_regs
.evergreen
.disp_int_cont3
&= ~DC_HPD4_INTERRUPT
;
3829 queue_hotplug
= true;
3830 DRM_DEBUG("IH: HPD4\n");
3834 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont4
& DC_HPD5_INTERRUPT
) {
3835 rdev
->irq
.stat_regs
.evergreen
.disp_int_cont4
&= ~DC_HPD5_INTERRUPT
;
3836 queue_hotplug
= true;
3837 DRM_DEBUG("IH: HPD5\n");
3841 if (rdev
->irq
.stat_regs
.evergreen
.disp_int_cont5
& DC_HPD6_INTERRUPT
) {
3842 rdev
->irq
.stat_regs
.evergreen
.disp_int_cont5
&= ~DC_HPD6_INTERRUPT
;
3843 queue_hotplug
= true;
3844 DRM_DEBUG("IH: HPD6\n");
3848 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id
, src_data
);
3854 dev_err(rdev
->dev
, "GPU fault detected: %d 0x%08x\n", src_id
, src_data
);
3855 dev_err(rdev
->dev
, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
3856 RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR
));
3857 dev_err(rdev
->dev
, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
3858 RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS
));
3859 /* reset addr and status */
3860 WREG32_P(VM_CONTEXT1_CNTL2
, 1, ~1);
3862 case 176: /* RINGID0 CP_INT */
3863 radeon_fence_process(rdev
, RADEON_RING_TYPE_GFX_INDEX
);
3865 case 177: /* RINGID1 CP_INT */
3866 radeon_fence_process(rdev
, CAYMAN_RING_TYPE_CP1_INDEX
);
3868 case 178: /* RINGID2 CP_INT */
3869 radeon_fence_process(rdev
, CAYMAN_RING_TYPE_CP2_INDEX
);
3871 case 181: /* CP EOP event */
3872 DRM_DEBUG("IH: CP EOP\n");
3875 radeon_fence_process(rdev
, RADEON_RING_TYPE_GFX_INDEX
);
3878 radeon_fence_process(rdev
, CAYMAN_RING_TYPE_CP1_INDEX
);
3881 radeon_fence_process(rdev
, CAYMAN_RING_TYPE_CP2_INDEX
);
3885 case 224: /* DMA trap event */
3886 DRM_DEBUG("IH: DMA trap\n");
3887 radeon_fence_process(rdev
, R600_RING_TYPE_DMA_INDEX
);
3889 case 233: /* GUI IDLE */
3890 DRM_DEBUG("IH: GUI idle\n");
3892 case 244: /* DMA trap event */
3893 DRM_DEBUG("IH: DMA1 trap\n");
3894 radeon_fence_process(rdev
, CAYMAN_RING_TYPE_DMA1_INDEX
);
3897 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id
, src_data
);
3901 /* wptr/rptr are in bytes! */
3903 rptr
&= rdev
->ih
.ptr_mask
;
3906 schedule_work(&rdev
->hotplug_work
);
3907 rdev
->ih
.rptr
= rptr
;
3908 WREG32(IH_RB_RPTR
, rdev
->ih
.rptr
);
3909 atomic_set(&rdev
->ih
.lock
, 0);
3911 /* make sure wptr hasn't changed while processing */
3912 wptr
= si_get_ih_wptr(rdev
);
3920 * si_copy_dma - copy pages using the DMA engine
3922 * @rdev: radeon_device pointer
3923 * @src_offset: src GPU address
3924 * @dst_offset: dst GPU address
3925 * @num_gpu_pages: number of GPU pages to xfer
3926 * @fence: radeon fence object
3928 * Copy GPU paging using the DMA engine (SI).
3929 * Used by the radeon ttm implementation to move pages if
3930 * registered as the asic copy callback.
3932 int si_copy_dma(struct radeon_device
*rdev
,
3933 uint64_t src_offset
, uint64_t dst_offset
,
3934 unsigned num_gpu_pages
,
3935 struct radeon_fence
**fence
)
3937 struct radeon_semaphore
*sem
= NULL
;
3938 int ring_index
= rdev
->asic
->copy
.dma_ring_index
;
3939 struct radeon_ring
*ring
= &rdev
->ring
[ring_index
];
3940 u32 size_in_bytes
, cur_size_in_bytes
;
3944 r
= radeon_semaphore_create(rdev
, &sem
);
3946 DRM_ERROR("radeon: moving bo (%d).\n", r
);
3950 size_in_bytes
= (num_gpu_pages
<< RADEON_GPU_PAGE_SHIFT
);
3951 num_loops
= DIV_ROUND_UP(size_in_bytes
, 0xfffff);
3952 r
= radeon_ring_lock(rdev
, ring
, num_loops
* 5 + 11);
3954 DRM_ERROR("radeon: moving bo (%d).\n", r
);
3955 radeon_semaphore_free(rdev
, &sem
, NULL
);
3959 if (radeon_fence_need_sync(*fence
, ring
->idx
)) {
3960 radeon_semaphore_sync_rings(rdev
, sem
, (*fence
)->ring
,
3962 radeon_fence_note_sync(*fence
, ring
->idx
);
3964 radeon_semaphore_free(rdev
, &sem
, NULL
);
3967 for (i
= 0; i
< num_loops
; i
++) {
3968 cur_size_in_bytes
= size_in_bytes
;
3969 if (cur_size_in_bytes
> 0xFFFFF)
3970 cur_size_in_bytes
= 0xFFFFF;
3971 size_in_bytes
-= cur_size_in_bytes
;
3972 radeon_ring_write(ring
, DMA_PACKET(DMA_PACKET_COPY
, 1, 0, 0, cur_size_in_bytes
));
3973 radeon_ring_write(ring
, dst_offset
& 0xffffffff);
3974 radeon_ring_write(ring
, src_offset
& 0xffffffff);
3975 radeon_ring_write(ring
, upper_32_bits(dst_offset
) & 0xff);
3976 radeon_ring_write(ring
, upper_32_bits(src_offset
) & 0xff);
3977 src_offset
+= cur_size_in_bytes
;
3978 dst_offset
+= cur_size_in_bytes
;
3981 r
= radeon_fence_emit(rdev
, fence
, ring
->idx
);
3983 radeon_ring_unlock_undo(rdev
, ring
);
3987 radeon_ring_unlock_commit(rdev
, ring
);
3988 radeon_semaphore_free(rdev
, &sem
, *fence
);
3994 * startup/shutdown callbacks
3996 static int si_startup(struct radeon_device
*rdev
)
3998 struct radeon_ring
*ring
;
4001 if (!rdev
->me_fw
|| !rdev
->pfp_fw
|| !rdev
->ce_fw
||
4002 !rdev
->rlc_fw
|| !rdev
->mc_fw
) {
4003 r
= si_init_microcode(rdev
);
4005 DRM_ERROR("Failed to load firmware!\n");
4010 r
= si_mc_load_microcode(rdev
);
4012 DRM_ERROR("Failed to load MC firmware!\n");
4016 r
= r600_vram_scratch_init(rdev
);
4020 si_mc_program(rdev
);
4021 r
= si_pcie_gart_enable(rdev
);
4027 r
= evergreen_blit_init(rdev
);
4029 r600_blit_fini(rdev
);
4030 rdev
->asic
->copy
= NULL
;
4031 dev_warn(rdev
->dev
, "failed blitter (%d) falling back to memcpy\n", r
);
4034 /* allocate rlc buffers */
4035 r
= si_rlc_init(rdev
);
4037 DRM_ERROR("Failed to init rlc BOs!\n");
4041 /* allocate wb buffer */
4042 r
= radeon_wb_init(rdev
);
4046 r
= radeon_fence_driver_start_ring(rdev
, RADEON_RING_TYPE_GFX_INDEX
);
4048 dev_err(rdev
->dev
, "failed initializing CP fences (%d).\n", r
);
4052 r
= radeon_fence_driver_start_ring(rdev
, CAYMAN_RING_TYPE_CP1_INDEX
);
4054 dev_err(rdev
->dev
, "failed initializing CP fences (%d).\n", r
);
4058 r
= radeon_fence_driver_start_ring(rdev
, CAYMAN_RING_TYPE_CP2_INDEX
);
4060 dev_err(rdev
->dev
, "failed initializing CP fences (%d).\n", r
);
4064 r
= radeon_fence_driver_start_ring(rdev
, R600_RING_TYPE_DMA_INDEX
);
4066 dev_err(rdev
->dev
, "failed initializing DMA fences (%d).\n", r
);
4070 r
= radeon_fence_driver_start_ring(rdev
, CAYMAN_RING_TYPE_DMA1_INDEX
);
4072 dev_err(rdev
->dev
, "failed initializing DMA fences (%d).\n", r
);
4077 r
= si_irq_init(rdev
);
4079 DRM_ERROR("radeon: IH init failed (%d).\n", r
);
4080 radeon_irq_kms_fini(rdev
);
4085 ring
= &rdev
->ring
[RADEON_RING_TYPE_GFX_INDEX
];
4086 r
= radeon_ring_init(rdev
, ring
, ring
->ring_size
, RADEON_WB_CP_RPTR_OFFSET
,
4087 CP_RB0_RPTR
, CP_RB0_WPTR
,
4088 0, 0xfffff, RADEON_CP_PACKET2
);
4092 ring
= &rdev
->ring
[CAYMAN_RING_TYPE_CP1_INDEX
];
4093 r
= radeon_ring_init(rdev
, ring
, ring
->ring_size
, RADEON_WB_CP1_RPTR_OFFSET
,
4094 CP_RB1_RPTR
, CP_RB1_WPTR
,
4095 0, 0xfffff, RADEON_CP_PACKET2
);
4099 ring
= &rdev
->ring
[CAYMAN_RING_TYPE_CP2_INDEX
];
4100 r
= radeon_ring_init(rdev
, ring
, ring
->ring_size
, RADEON_WB_CP2_RPTR_OFFSET
,
4101 CP_RB2_RPTR
, CP_RB2_WPTR
,
4102 0, 0xfffff, RADEON_CP_PACKET2
);
4106 ring
= &rdev
->ring
[R600_RING_TYPE_DMA_INDEX
];
4107 r
= radeon_ring_init(rdev
, ring
, ring
->ring_size
, R600_WB_DMA_RPTR_OFFSET
,
4108 DMA_RB_RPTR
+ DMA0_REGISTER_OFFSET
,
4109 DMA_RB_WPTR
+ DMA0_REGISTER_OFFSET
,
4110 2, 0x3fffc, DMA_PACKET(DMA_PACKET_NOP
, 0, 0, 0, 0));
4114 ring
= &rdev
->ring
[CAYMAN_RING_TYPE_DMA1_INDEX
];
4115 r
= radeon_ring_init(rdev
, ring
, ring
->ring_size
, CAYMAN_WB_DMA1_RPTR_OFFSET
,
4116 DMA_RB_RPTR
+ DMA1_REGISTER_OFFSET
,
4117 DMA_RB_WPTR
+ DMA1_REGISTER_OFFSET
,
4118 2, 0x3fffc, DMA_PACKET(DMA_PACKET_NOP
, 0, 0, 0, 0));
4122 r
= si_cp_load_microcode(rdev
);
4125 r
= si_cp_resume(rdev
);
4129 r
= cayman_dma_resume(rdev
);
4133 r
= radeon_ib_pool_init(rdev
);
4135 dev_err(rdev
->dev
, "IB initialization failed (%d).\n", r
);
4139 r
= radeon_vm_manager_init(rdev
);
4141 dev_err(rdev
->dev
, "vm manager initialization failed (%d).\n", r
);
4148 int si_resume(struct radeon_device
*rdev
)
4152 /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
4153 * posting will perform necessary task to bring back GPU into good
4157 atom_asic_init(rdev
->mode_info
.atom_context
);
4159 rdev
->accel_working
= true;
4160 r
= si_startup(rdev
);
4162 DRM_ERROR("si startup failed on resume\n");
4163 rdev
->accel_working
= false;
4171 int si_suspend(struct radeon_device
*rdev
)
4173 si_cp_enable(rdev
, false);
4174 cayman_dma_stop(rdev
);
4175 si_irq_suspend(rdev
);
4176 radeon_wb_disable(rdev
);
4177 si_pcie_gart_disable(rdev
);
4181 /* Plan is to move initialization in that function and use
4182 * helper function so that radeon_device_init pretty much
4183 * do nothing more than calling asic specific function. This
4184 * should also allow to remove a bunch of callback function
4187 int si_init(struct radeon_device
*rdev
)
4189 struct radeon_ring
*ring
= &rdev
->ring
[RADEON_RING_TYPE_GFX_INDEX
];
4193 if (!radeon_get_bios(rdev
)) {
4194 if (ASIC_IS_AVIVO(rdev
))
4197 /* Must be an ATOMBIOS */
4198 if (!rdev
->is_atom_bios
) {
4199 dev_err(rdev
->dev
, "Expecting atombios for cayman GPU\n");
4202 r
= radeon_atombios_init(rdev
);
4206 /* Post card if necessary */
4207 if (!radeon_card_posted(rdev
)) {
4209 dev_err(rdev
->dev
, "Card not posted and no BIOS - ignoring\n");
4212 DRM_INFO("GPU not posted. posting now...\n");
4213 atom_asic_init(rdev
->mode_info
.atom_context
);
4215 /* Initialize scratch registers */
4216 si_scratch_init(rdev
);
4217 /* Initialize surface registers */
4218 radeon_surface_init(rdev
);
4219 /* Initialize clocks */
4220 radeon_get_clock_info(rdev
->ddev
);
4223 r
= radeon_fence_driver_init(rdev
);
4227 /* initialize memory controller */
4228 r
= si_mc_init(rdev
);
4231 /* Memory manager */
4232 r
= radeon_bo_init(rdev
);
4236 r
= radeon_irq_kms_init(rdev
);
4240 ring
= &rdev
->ring
[RADEON_RING_TYPE_GFX_INDEX
];
4241 ring
->ring_obj
= NULL
;
4242 r600_ring_init(rdev
, ring
, 1024 * 1024);
4244 ring
= &rdev
->ring
[CAYMAN_RING_TYPE_CP1_INDEX
];
4245 ring
->ring_obj
= NULL
;
4246 r600_ring_init(rdev
, ring
, 1024 * 1024);
4248 ring
= &rdev
->ring
[CAYMAN_RING_TYPE_CP2_INDEX
];
4249 ring
->ring_obj
= NULL
;
4250 r600_ring_init(rdev
, ring
, 1024 * 1024);
4252 ring
= &rdev
->ring
[R600_RING_TYPE_DMA_INDEX
];
4253 ring
->ring_obj
= NULL
;
4254 r600_ring_init(rdev
, ring
, 64 * 1024);
4256 ring
= &rdev
->ring
[CAYMAN_RING_TYPE_DMA1_INDEX
];
4257 ring
->ring_obj
= NULL
;
4258 r600_ring_init(rdev
, ring
, 64 * 1024);
4260 rdev
->ih
.ring_obj
= NULL
;
4261 r600_ih_ring_init(rdev
, 64 * 1024);
4263 r
= r600_pcie_gart_init(rdev
);
4267 rdev
->accel_working
= true;
4268 r
= si_startup(rdev
);
4270 dev_err(rdev
->dev
, "disabling GPU acceleration\n");
4272 cayman_dma_fini(rdev
);
4275 radeon_wb_fini(rdev
);
4276 radeon_ib_pool_fini(rdev
);
4277 radeon_vm_manager_fini(rdev
);
4278 radeon_irq_kms_fini(rdev
);
4279 si_pcie_gart_fini(rdev
);
4280 rdev
->accel_working
= false;
4283 /* Don't start up if the MC ucode is missing.
4284 * The default clocks and voltages before the MC ucode
4285 * is loaded are not suffient for advanced operations.
4288 DRM_ERROR("radeon: MC ucode required for NI+.\n");
4295 void si_fini(struct radeon_device
*rdev
)
4298 r600_blit_fini(rdev
);
4301 cayman_dma_fini(rdev
);
4304 radeon_wb_fini(rdev
);
4305 radeon_vm_manager_fini(rdev
);
4306 radeon_ib_pool_fini(rdev
);
4307 radeon_irq_kms_fini(rdev
);
4308 si_pcie_gart_fini(rdev
);
4309 r600_vram_scratch_fini(rdev
);
4310 radeon_gem_fini(rdev
);
4311 radeon_fence_driver_fini(rdev
);
4312 radeon_bo_fini(rdev
);
4313 radeon_atombios_fini(rdev
);
4319 * si_get_gpu_clock - return GPU clock counter snapshot
4321 * @rdev: radeon_device pointer
4323 * Fetches a GPU clock counter snapshot (SI).
4324 * Returns the 64 bit clock counter snapshot.
4326 uint64_t si_get_gpu_clock(struct radeon_device
*rdev
)
4330 mutex_lock(&rdev
->gpu_clock_mutex
);
4331 WREG32(RLC_CAPTURE_GPU_CLOCK_COUNT
, 1);
4332 clock
= (uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_LSB
) |
4333 ((uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_MSB
) << 32ULL);
4334 mutex_unlock(&rdev
->gpu_clock_mutex
);