2 * Copyright 2013 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 * Authors: Alex Deucher
26 #include "radeon_asic.h"
29 u32
si_gpu_check_soft_reset(struct radeon_device
*rdev
);
32 * si_dma_is_lockup - Check if the DMA engine is locked up
34 * @rdev: radeon_device pointer
35 * @ring: radeon_ring structure holding ring information
37 * Check if the async DMA engine is locked up.
38 * Returns true if the engine appears to be locked up, false if not.
40 bool si_dma_is_lockup(struct radeon_device
*rdev
, struct radeon_ring
*ring
)
42 u32 reset_mask
= si_gpu_check_soft_reset(rdev
);
45 if (ring
->idx
== R600_RING_TYPE_DMA_INDEX
)
46 mask
= RADEON_RESET_DMA
;
48 mask
= RADEON_RESET_DMA1
;
50 if (!(reset_mask
& mask
)) {
51 radeon_ring_lockup_update(ring
);
54 /* force ring activities */
55 radeon_ring_force_activity(rdev
, ring
);
56 return radeon_ring_test_lockup(rdev
, ring
);
60 * si_dma_vm_set_page - update the page tables using the DMA
62 * @rdev: radeon_device pointer
63 * @ib: indirect buffer to fill with commands
64 * @pe: addr of the page entry
65 * @addr: dst addr to write into pe
66 * @count: number of page entries to update
67 * @incr: increase next addr by incr bytes
68 * @flags: access flags
70 * Update the page tables using the DMA (SI).
72 void si_dma_vm_set_page(struct radeon_device
*rdev
,
75 uint64_t addr
, unsigned count
,
76 uint32_t incr
, uint32_t flags
)
78 uint32_t r600_flags
= cayman_vm_page_flags(rdev
, flags
);
82 if (flags
& RADEON_VM_PAGE_SYSTEM
) {
88 /* for non-physically contiguous pages (system) */
89 ib
->ptr
[ib
->length_dw
++] = DMA_PACKET(DMA_PACKET_WRITE
, 0, 0, 0, ndw
);
90 ib
->ptr
[ib
->length_dw
++] = pe
;
91 ib
->ptr
[ib
->length_dw
++] = upper_32_bits(pe
) & 0xff;
92 for (; ndw
> 0; ndw
-= 2, --count
, pe
+= 8) {
93 if (flags
& RADEON_VM_PAGE_SYSTEM
) {
94 value
= radeon_vm_map_gart(rdev
, addr
);
95 value
&= 0xFFFFFFFFFFFFF000ULL
;
96 } else if (flags
& RADEON_VM_PAGE_VALID
) {
103 ib
->ptr
[ib
->length_dw
++] = value
;
104 ib
->ptr
[ib
->length_dw
++] = upper_32_bits(value
);
113 if (flags
& RADEON_VM_PAGE_VALID
)
117 /* for physically contiguous pages (vram) */
118 ib
->ptr
[ib
->length_dw
++] = DMA_PTE_PDE_PACKET(ndw
);
119 ib
->ptr
[ib
->length_dw
++] = pe
; /* dst addr */
120 ib
->ptr
[ib
->length_dw
++] = upper_32_bits(pe
) & 0xff;
121 ib
->ptr
[ib
->length_dw
++] = r600_flags
; /* mask */
122 ib
->ptr
[ib
->length_dw
++] = 0;
123 ib
->ptr
[ib
->length_dw
++] = value
; /* value */
124 ib
->ptr
[ib
->length_dw
++] = upper_32_bits(value
);
125 ib
->ptr
[ib
->length_dw
++] = incr
; /* increment size */
126 ib
->ptr
[ib
->length_dw
++] = 0;
128 addr
+= (ndw
/ 2) * incr
;
132 while (ib
->length_dw
& 0x7)
133 ib
->ptr
[ib
->length_dw
++] = DMA_PACKET(DMA_PACKET_NOP
, 0, 0, 0, 0);
136 void si_dma_vm_flush(struct radeon_device
*rdev
, int ridx
, struct radeon_vm
*vm
)
138 struct radeon_ring
*ring
= &rdev
->ring
[ridx
];
143 radeon_ring_write(ring
, DMA_PACKET(DMA_PACKET_SRBM_WRITE
, 0, 0, 0, 0));
145 radeon_ring_write(ring
, (0xf << 16) | ((VM_CONTEXT0_PAGE_TABLE_BASE_ADDR
+ (vm
->id
<< 2)) >> 2));
147 radeon_ring_write(ring
, (0xf << 16) | ((VM_CONTEXT8_PAGE_TABLE_BASE_ADDR
+ ((vm
->id
- 8) << 2)) >> 2));
149 radeon_ring_write(ring
, vm
->pd_gpu_addr
>> 12);
151 /* flush hdp cache */
152 radeon_ring_write(ring
, DMA_PACKET(DMA_PACKET_SRBM_WRITE
, 0, 0, 0, 0));
153 radeon_ring_write(ring
, (0xf << 16) | (HDP_MEM_COHERENCY_FLUSH_CNTL
>> 2));
154 radeon_ring_write(ring
, 1);
156 /* bits 0-7 are the VM contexts0-7 */
157 radeon_ring_write(ring
, DMA_PACKET(DMA_PACKET_SRBM_WRITE
, 0, 0, 0, 0));
158 radeon_ring_write(ring
, (0xf << 16) | (VM_INVALIDATE_REQUEST
>> 2));
159 radeon_ring_write(ring
, 1 << vm
->id
);
163 * si_copy_dma - copy pages using the DMA engine
165 * @rdev: radeon_device pointer
166 * @src_offset: src GPU address
167 * @dst_offset: dst GPU address
168 * @num_gpu_pages: number of GPU pages to xfer
169 * @fence: radeon fence object
171 * Copy GPU paging using the DMA engine (SI).
172 * Used by the radeon ttm implementation to move pages if
173 * registered as the asic copy callback.
175 int si_copy_dma(struct radeon_device
*rdev
,
176 uint64_t src_offset
, uint64_t dst_offset
,
177 unsigned num_gpu_pages
,
178 struct radeon_fence
**fence
)
180 struct radeon_semaphore
*sem
= NULL
;
181 int ring_index
= rdev
->asic
->copy
.dma_ring_index
;
182 struct radeon_ring
*ring
= &rdev
->ring
[ring_index
];
183 u32 size_in_bytes
, cur_size_in_bytes
;
187 r
= radeon_semaphore_create(rdev
, &sem
);
189 DRM_ERROR("radeon: moving bo (%d).\n", r
);
193 size_in_bytes
= (num_gpu_pages
<< RADEON_GPU_PAGE_SHIFT
);
194 num_loops
= DIV_ROUND_UP(size_in_bytes
, 0xfffff);
195 r
= radeon_ring_lock(rdev
, ring
, num_loops
* 5 + 11);
197 DRM_ERROR("radeon: moving bo (%d).\n", r
);
198 radeon_semaphore_free(rdev
, &sem
, NULL
);
202 if (radeon_fence_need_sync(*fence
, ring
->idx
)) {
203 radeon_semaphore_sync_rings(rdev
, sem
, (*fence
)->ring
,
205 radeon_fence_note_sync(*fence
, ring
->idx
);
207 radeon_semaphore_free(rdev
, &sem
, NULL
);
210 for (i
= 0; i
< num_loops
; i
++) {
211 cur_size_in_bytes
= size_in_bytes
;
212 if (cur_size_in_bytes
> 0xFFFFF)
213 cur_size_in_bytes
= 0xFFFFF;
214 size_in_bytes
-= cur_size_in_bytes
;
215 radeon_ring_write(ring
, DMA_PACKET(DMA_PACKET_COPY
, 1, 0, 0, cur_size_in_bytes
));
216 radeon_ring_write(ring
, dst_offset
& 0xffffffff);
217 radeon_ring_write(ring
, src_offset
& 0xffffffff);
218 radeon_ring_write(ring
, upper_32_bits(dst_offset
) & 0xff);
219 radeon_ring_write(ring
, upper_32_bits(src_offset
) & 0xff);
220 src_offset
+= cur_size_in_bytes
;
221 dst_offset
+= cur_size_in_bytes
;
224 r
= radeon_fence_emit(rdev
, fence
, ring
->idx
);
226 radeon_ring_unlock_undo(rdev
, ring
);
230 radeon_ring_unlock_commit(rdev
, ring
);
231 radeon_semaphore_free(rdev
, &sem
, *fence
);