2 * Copyright 2013 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 #include "radeon_asic.h"
31 #include <linux/math64.h>
32 #include <linux/seq_file.h>
34 #define MC_CG_ARB_FREQ_F0 0x0a
35 #define MC_CG_ARB_FREQ_F1 0x0b
36 #define MC_CG_ARB_FREQ_F2 0x0c
37 #define MC_CG_ARB_FREQ_F3 0x0d
39 #define SMC_RAM_END 0x20000
41 #define SCLK_MIN_DEEPSLEEP_FREQ 1350
43 static const struct si_cac_config_reg cac_weights_tahiti
[] =
45 { 0x0, 0x0000ffff, 0, 0xc, SISLANDS_CACCONFIG_CGIND
},
46 { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
47 { 0x1, 0x0000ffff, 0, 0x101, SISLANDS_CACCONFIG_CGIND
},
48 { 0x1, 0xffff0000, 16, 0xc, SISLANDS_CACCONFIG_CGIND
},
49 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
50 { 0x3, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
51 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
52 { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
53 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
54 { 0x5, 0x0000ffff, 0, 0x8fc, SISLANDS_CACCONFIG_CGIND
},
55 { 0x5, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
56 { 0x6, 0x0000ffff, 0, 0x95, SISLANDS_CACCONFIG_CGIND
},
57 { 0x6, 0xffff0000, 16, 0x34e, SISLANDS_CACCONFIG_CGIND
},
58 { 0x18f, 0x0000ffff, 0, 0x1a1, SISLANDS_CACCONFIG_CGIND
},
59 { 0x7, 0x0000ffff, 0, 0xda, SISLANDS_CACCONFIG_CGIND
},
60 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
61 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
62 { 0x8, 0xffff0000, 16, 0x46, SISLANDS_CACCONFIG_CGIND
},
63 { 0x9, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
64 { 0xa, 0x0000ffff, 0, 0x208, SISLANDS_CACCONFIG_CGIND
},
65 { 0xb, 0x0000ffff, 0, 0xe7, SISLANDS_CACCONFIG_CGIND
},
66 { 0xb, 0xffff0000, 16, 0x948, SISLANDS_CACCONFIG_CGIND
},
67 { 0xc, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
68 { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
69 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
70 { 0xe, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
71 { 0xf, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
72 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
73 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
74 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
75 { 0x11, 0x0000ffff, 0, 0x167, SISLANDS_CACCONFIG_CGIND
},
76 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
77 { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
78 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
79 { 0x13, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND
},
80 { 0x14, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
81 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
82 { 0x15, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND
},
83 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
84 { 0x16, 0x0000ffff, 0, 0x31, SISLANDS_CACCONFIG_CGIND
},
85 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
86 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
87 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
88 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
89 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
90 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
91 { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
92 { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
93 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
94 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
95 { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
96 { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
97 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
98 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
99 { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
100 { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
101 { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
102 { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
103 { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
104 { 0x6d, 0x0000ffff, 0, 0x18e, SISLANDS_CACCONFIG_CGIND
},
108 static const struct si_cac_config_reg lcac_tahiti
[] =
110 { 0x143, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND
},
111 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
112 { 0x146, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND
},
113 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
114 { 0x149, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND
},
115 { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
116 { 0x14c, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND
},
117 { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
118 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND
},
119 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
120 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND
},
121 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
122 { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND
},
123 { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
124 { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND
},
125 { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
126 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND
},
127 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
128 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND
},
129 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
130 { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND
},
131 { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
132 { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND
},
133 { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
134 { 0x8c, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND
},
135 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
136 { 0x8f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND
},
137 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
138 { 0x92, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND
},
139 { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
140 { 0x95, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND
},
141 { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
142 { 0x14f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND
},
143 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
144 { 0x152, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND
},
145 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
146 { 0x155, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND
},
147 { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
148 { 0x158, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND
},
149 { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
150 { 0x110, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND
},
151 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
152 { 0x113, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND
},
153 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
154 { 0x116, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND
},
155 { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
156 { 0x119, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND
},
157 { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
158 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND
},
159 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
160 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND
},
161 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
162 { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND
},
163 { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
164 { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND
},
165 { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
166 { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND
},
167 { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
168 { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND
},
169 { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
170 { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND
},
171 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
172 { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND
},
173 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
174 { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND
},
175 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
176 { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND
},
177 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
178 { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND
},
179 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
180 { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND
},
181 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
182 { 0x16d, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND
},
183 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
184 { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND
},
185 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
186 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND
},
187 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
188 { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND
},
189 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
190 { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND
},
191 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
192 { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND
},
193 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
194 { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND
},
195 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
200 static const struct si_cac_config_reg cac_override_tahiti
[] =
205 static const struct si_powertune_data powertune_data_tahiti
=
236 static const struct si_dte_data dte_data_tahiti
=
238 { 1159409, 0, 0, 0, 0 },
247 { 27, 31, 35, 39, 43, 47, 54, 61, 67, 74, 81, 88, 95, 0, 0, 0 },
248 { 240888759, 221057860, 235370597, 162287531, 158510299, 131423027, 116673180, 103067515, 87941937, 76209048, 68209175, 64090048, 58301890, 0, 0, 0 },
249 { 12024, 11189, 11451, 8411, 7939, 6666, 5681, 4905, 4241, 3720, 3354, 3122, 2890, 0, 0, 0 },
254 static const struct si_dte_data dte_data_tahiti_le
=
256 { 0x1E8480, 0x7A1200, 0x2160EC0, 0x3938700, 0 },
257 { 0x7D, 0x7D, 0x4E4, 0xB00, 0 },
265 { 0x78, 0x7C, 0x82, 0x88, 0x8E, 0x94, 0x9A, 0xA0, 0xA6, 0xAC, 0xB0, 0xB4, 0xB8, 0xBC, 0xC0, 0xC4 },
266 { 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700 },
267 { 0x2AF8, 0x2AF8, 0x29BB, 0x27F9, 0x2637, 0x2475, 0x22B3, 0x20F1, 0x1F2F, 0x1D6D, 0x1734, 0x1414, 0x10F4, 0xDD4, 0xAB4, 0x794 },
272 static const struct si_dte_data dte_data_tahiti_pro
=
274 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
275 { 0x0, 0x0, 0x0, 0x0, 0x0 },
283 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
284 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
285 { 0x7D0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
290 static const struct si_dte_data dte_data_new_zealand
=
292 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0 },
293 { 0x29B, 0x3E9, 0x537, 0x7D2, 0 },
301 { 0x82, 0xA0, 0xB4, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE },
302 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
303 { 0xDAC, 0x1388, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685 },
308 static const struct si_dte_data dte_data_aruba_pro
=
310 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
311 { 0x0, 0x0, 0x0, 0x0, 0x0 },
319 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
320 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
321 { 0x1000, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
326 static const struct si_dte_data dte_data_malta
=
328 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
329 { 0x0, 0x0, 0x0, 0x0, 0x0 },
337 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
338 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
339 { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
344 struct si_cac_config_reg cac_weights_pitcairn
[] =
346 { 0x0, 0x0000ffff, 0, 0x8a, SISLANDS_CACCONFIG_CGIND
},
347 { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
348 { 0x1, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
349 { 0x1, 0xffff0000, 16, 0x24d, SISLANDS_CACCONFIG_CGIND
},
350 { 0x2, 0x0000ffff, 0, 0x19, SISLANDS_CACCONFIG_CGIND
},
351 { 0x3, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND
},
352 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
353 { 0x4, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND
},
354 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
355 { 0x5, 0x0000ffff, 0, 0xc11, SISLANDS_CACCONFIG_CGIND
},
356 { 0x5, 0xffff0000, 16, 0x7f3, SISLANDS_CACCONFIG_CGIND
},
357 { 0x6, 0x0000ffff, 0, 0x403, SISLANDS_CACCONFIG_CGIND
},
358 { 0x6, 0xffff0000, 16, 0x367, SISLANDS_CACCONFIG_CGIND
},
359 { 0x18f, 0x0000ffff, 0, 0x4c9, SISLANDS_CACCONFIG_CGIND
},
360 { 0x7, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
361 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
362 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
363 { 0x8, 0xffff0000, 16, 0x45d, SISLANDS_CACCONFIG_CGIND
},
364 { 0x9, 0x0000ffff, 0, 0x36d, SISLANDS_CACCONFIG_CGIND
},
365 { 0xa, 0x0000ffff, 0, 0x534, SISLANDS_CACCONFIG_CGIND
},
366 { 0xb, 0x0000ffff, 0, 0x5da, SISLANDS_CACCONFIG_CGIND
},
367 { 0xb, 0xffff0000, 16, 0x880, SISLANDS_CACCONFIG_CGIND
},
368 { 0xc, 0x0000ffff, 0, 0x201, SISLANDS_CACCONFIG_CGIND
},
369 { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
370 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
371 { 0xe, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND
},
372 { 0xf, 0x0000ffff, 0, 0x1f, SISLANDS_CACCONFIG_CGIND
},
373 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
374 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
375 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
376 { 0x11, 0x0000ffff, 0, 0x5de, SISLANDS_CACCONFIG_CGIND
},
377 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
378 { 0x12, 0x0000ffff, 0, 0x7b, SISLANDS_CACCONFIG_CGIND
},
379 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
380 { 0x13, 0xffff0000, 16, 0x13, SISLANDS_CACCONFIG_CGIND
},
381 { 0x14, 0x0000ffff, 0, 0xf9, SISLANDS_CACCONFIG_CGIND
},
382 { 0x15, 0x0000ffff, 0, 0x66, SISLANDS_CACCONFIG_CGIND
},
383 { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
384 { 0x4e, 0x0000ffff, 0, 0x13, SISLANDS_CACCONFIG_CGIND
},
385 { 0x16, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
386 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
387 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
388 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
389 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
390 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
391 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
392 { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
393 { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
394 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
395 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
396 { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
397 { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
398 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
399 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
400 { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
401 { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
402 { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
403 { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
404 { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
405 { 0x6d, 0x0000ffff, 0, 0x186, SISLANDS_CACCONFIG_CGIND
},
409 static const struct si_cac_config_reg lcac_pitcairn
[] =
411 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND
},
412 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
413 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND
},
414 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
415 { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND
},
416 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
417 { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND
},
418 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
419 { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND
},
420 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
421 { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND
},
422 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
423 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND
},
424 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
425 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND
},
426 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
427 { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND
},
428 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
429 { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND
},
430 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
431 { 0x8f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND
},
432 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
433 { 0x146, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND
},
434 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
435 { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND
},
436 { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
437 { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND
},
438 { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
439 { 0x116, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND
},
440 { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
441 { 0x155, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND
},
442 { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
443 { 0x92, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND
},
444 { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
445 { 0x149, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND
},
446 { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
447 { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND
},
448 { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
449 { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND
},
450 { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
451 { 0x119, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND
},
452 { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
453 { 0x158, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND
},
454 { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
455 { 0x95, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND
},
456 { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
457 { 0x14c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND
},
458 { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
459 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND
},
460 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
461 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND
},
462 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
463 { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND
},
464 { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
465 { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND
},
466 { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
467 { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND
},
468 { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
469 { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND
},
470 { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
471 { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND
},
472 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
473 { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND
},
474 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
475 { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND
},
476 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
477 { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND
},
478 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
479 { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND
},
480 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
481 { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND
},
482 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
483 { 0x16d, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND
},
484 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
485 { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND
},
486 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
487 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND
},
488 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
489 { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND
},
490 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
491 { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND
},
492 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
493 { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND
},
494 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
495 { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND
},
496 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
500 static const struct si_cac_config_reg cac_override_pitcairn
[] =
505 static const struct si_powertune_data powertune_data_pitcairn
=
536 static const struct si_dte_data dte_data_pitcairn
=
547 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
548 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
549 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
554 static const struct si_dte_data dte_data_curacao_xt
=
556 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
557 { 0x0, 0x0, 0x0, 0x0, 0x0 },
565 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
566 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
567 { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
572 static const struct si_dte_data dte_data_curacao_pro
=
574 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
575 { 0x0, 0x0, 0x0, 0x0, 0x0 },
583 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
584 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
585 { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
590 static const struct si_dte_data dte_data_neptune_xt
=
592 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
593 { 0x0, 0x0, 0x0, 0x0, 0x0 },
601 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
602 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
603 { 0x3A2F, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
608 static const struct si_cac_config_reg cac_weights_chelsea_pro
[] =
610 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND
},
611 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND
},
612 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND
},
613 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND
},
614 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
615 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND
},
616 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND
},
617 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND
},
618 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND
},
619 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND
},
620 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND
},
621 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND
},
622 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND
},
623 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND
},
624 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND
},
625 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND
},
626 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND
},
627 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND
},
628 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND
},
629 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND
},
630 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND
},
631 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND
},
632 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND
},
633 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND
},
634 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND
},
635 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND
},
636 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND
},
637 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
638 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
639 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND
},
640 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND
},
641 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND
},
642 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND
},
643 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND
},
644 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND
},
645 { 0x14, 0x0000ffff, 0, 0x2BD, SISLANDS_CACCONFIG_CGIND
},
646 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
647 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND
},
648 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
649 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND
},
650 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND
},
651 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
652 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
653 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
654 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
655 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
656 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND
},
657 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND
},
658 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND
},
659 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND
},
660 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND
},
661 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND
},
662 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND
},
663 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND
},
664 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND
},
665 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND
},
666 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND
},
667 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND
},
668 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND
},
669 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND
},
673 static const struct si_cac_config_reg cac_weights_chelsea_xt
[] =
675 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND
},
676 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND
},
677 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND
},
678 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND
},
679 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
680 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND
},
681 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND
},
682 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND
},
683 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND
},
684 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND
},
685 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND
},
686 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND
},
687 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND
},
688 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND
},
689 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND
},
690 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND
},
691 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND
},
692 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND
},
693 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND
},
694 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND
},
695 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND
},
696 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND
},
697 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND
},
698 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND
},
699 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND
},
700 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND
},
701 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND
},
702 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
703 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
704 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND
},
705 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND
},
706 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND
},
707 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND
},
708 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND
},
709 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND
},
710 { 0x14, 0x0000ffff, 0, 0x30A, SISLANDS_CACCONFIG_CGIND
},
711 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
712 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND
},
713 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
714 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND
},
715 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND
},
716 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
717 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
718 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
719 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
720 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
721 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND
},
722 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND
},
723 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND
},
724 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND
},
725 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND
},
726 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND
},
727 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND
},
728 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND
},
729 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND
},
730 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND
},
731 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND
},
732 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND
},
733 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND
},
734 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND
},
738 static const struct si_cac_config_reg cac_weights_heathrow
[] =
740 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND
},
741 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND
},
742 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND
},
743 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND
},
744 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
745 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND
},
746 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND
},
747 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND
},
748 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND
},
749 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND
},
750 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND
},
751 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND
},
752 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND
},
753 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND
},
754 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND
},
755 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND
},
756 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND
},
757 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND
},
758 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND
},
759 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND
},
760 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND
},
761 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND
},
762 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND
},
763 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND
},
764 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND
},
765 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND
},
766 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND
},
767 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
768 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
769 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND
},
770 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND
},
771 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND
},
772 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND
},
773 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND
},
774 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND
},
775 { 0x14, 0x0000ffff, 0, 0x362, SISLANDS_CACCONFIG_CGIND
},
776 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
777 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND
},
778 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
779 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND
},
780 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND
},
781 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
782 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
783 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
784 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
785 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
786 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND
},
787 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND
},
788 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND
},
789 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND
},
790 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND
},
791 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND
},
792 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND
},
793 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND
},
794 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND
},
795 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND
},
796 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND
},
797 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND
},
798 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND
},
799 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND
},
803 static const struct si_cac_config_reg cac_weights_cape_verde_pro
[] =
805 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND
},
806 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND
},
807 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND
},
808 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND
},
809 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
810 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND
},
811 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND
},
812 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND
},
813 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND
},
814 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND
},
815 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND
},
816 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND
},
817 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND
},
818 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND
},
819 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND
},
820 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND
},
821 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND
},
822 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND
},
823 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND
},
824 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND
},
825 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND
},
826 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND
},
827 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND
},
828 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND
},
829 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND
},
830 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND
},
831 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND
},
832 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
833 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
834 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND
},
835 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND
},
836 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND
},
837 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND
},
838 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND
},
839 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND
},
840 { 0x14, 0x0000ffff, 0, 0x315, SISLANDS_CACCONFIG_CGIND
},
841 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
842 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND
},
843 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
844 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND
},
845 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND
},
846 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
847 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
848 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
849 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
850 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
851 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND
},
852 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND
},
853 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND
},
854 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND
},
855 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND
},
856 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND
},
857 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND
},
858 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND
},
859 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND
},
860 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND
},
861 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND
},
862 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND
},
863 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND
},
864 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND
},
868 static const struct si_cac_config_reg cac_weights_cape_verde
[] =
870 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND
},
871 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND
},
872 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND
},
873 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND
},
874 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
875 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND
},
876 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND
},
877 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND
},
878 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND
},
879 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND
},
880 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND
},
881 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND
},
882 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND
},
883 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND
},
884 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND
},
885 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND
},
886 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND
},
887 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND
},
888 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND
},
889 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND
},
890 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND
},
891 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND
},
892 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND
},
893 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND
},
894 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND
},
895 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND
},
896 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND
},
897 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
898 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
899 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND
},
900 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND
},
901 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND
},
902 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND
},
903 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND
},
904 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND
},
905 { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND
},
906 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
907 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND
},
908 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
909 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND
},
910 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND
},
911 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
912 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
913 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
914 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
915 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
916 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND
},
917 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND
},
918 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND
},
919 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND
},
920 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND
},
921 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND
},
922 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND
},
923 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND
},
924 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND
},
925 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND
},
926 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND
},
927 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND
},
928 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND
},
929 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND
},
933 static const struct si_cac_config_reg lcac_cape_verde
[] =
935 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND
},
936 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
937 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND
},
938 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
939 { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND
},
940 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
941 { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND
},
942 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
943 { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND
},
944 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
945 { 0x143, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND
},
946 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
947 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND
},
948 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
949 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND
},
950 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
951 { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND
},
952 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
953 { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND
},
954 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
955 { 0x8f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND
},
956 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
957 { 0x146, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND
},
958 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
959 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND
},
960 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
961 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND
},
962 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
963 { 0x164, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND
},
964 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
965 { 0x167, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND
},
966 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
967 { 0x16a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND
},
968 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
969 { 0x15e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND
},
970 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
971 { 0x161, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND
},
972 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
973 { 0x15b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND
},
974 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
975 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND
},
976 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
977 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND
},
978 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
979 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND
},
980 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
981 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND
},
982 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
983 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND
},
984 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
985 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND
},
986 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
987 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND
},
988 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
992 static const struct si_cac_config_reg cac_override_cape_verde
[] =
997 static const struct si_powertune_data powertune_data_cape_verde
=
999 ((1 << 16) | 0x6993),
1028 static const struct si_dte_data dte_data_cape_verde
=
1039 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1040 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1041 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1046 static const struct si_dte_data dte_data_venus_xtx
=
1048 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1049 { 0x71C, 0xAAB, 0xE39, 0x11C7, 0x0 },
1057 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1058 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1059 { 0xD6D8, 0x88B8, 0x1555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1064 static const struct si_dte_data dte_data_venus_xt
=
1066 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1067 { 0xBDA, 0x11C7, 0x17B4, 0x1DA1, 0x0 },
1075 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1076 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1077 { 0xAFC8, 0x88B8, 0x238E, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1082 static const struct si_dte_data dte_data_venus_pro
=
1084 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1085 { 0x11C7, 0x1AAB, 0x238E, 0x2C72, 0x0 },
1093 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1094 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1095 { 0x88B8, 0x88B8, 0x3555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1100 struct si_cac_config_reg cac_weights_oland
[] =
1102 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND
},
1103 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND
},
1104 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND
},
1105 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND
},
1106 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
1107 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND
},
1108 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND
},
1109 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND
},
1110 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND
},
1111 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND
},
1112 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND
},
1113 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND
},
1114 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND
},
1115 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND
},
1116 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND
},
1117 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND
},
1118 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND
},
1119 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND
},
1120 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND
},
1121 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND
},
1122 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND
},
1123 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND
},
1124 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND
},
1125 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND
},
1126 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND
},
1127 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND
},
1128 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND
},
1129 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
1130 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
1131 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND
},
1132 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND
},
1133 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND
},
1134 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND
},
1135 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND
},
1136 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND
},
1137 { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND
},
1138 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
1139 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND
},
1140 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
1141 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND
},
1142 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND
},
1143 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
1144 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
1145 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
1146 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
1147 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
1148 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND
},
1149 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND
},
1150 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND
},
1151 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND
},
1152 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND
},
1153 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND
},
1154 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND
},
1155 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND
},
1156 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND
},
1157 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND
},
1158 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND
},
1159 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND
},
1160 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND
},
1161 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND
},
1165 static const struct si_cac_config_reg cac_weights_mars_pro
[] =
1167 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND
},
1168 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND
},
1169 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND
},
1170 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND
},
1171 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
1172 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND
},
1173 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND
},
1174 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND
},
1175 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND
},
1176 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND
},
1177 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND
},
1178 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND
},
1179 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND
},
1180 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND
},
1181 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND
},
1182 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND
},
1183 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND
},
1184 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND
},
1185 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND
},
1186 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND
},
1187 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND
},
1188 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND
},
1189 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND
},
1190 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND
},
1191 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND
},
1192 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND
},
1193 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND
},
1194 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND
},
1195 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
1196 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND
},
1197 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND
},
1198 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND
},
1199 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND
},
1200 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND
},
1201 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND
},
1202 { 0x14, 0x0000ffff, 0, 0x2, SISLANDS_CACCONFIG_CGIND
},
1203 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
1204 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND
},
1205 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
1206 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND
},
1207 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND
},
1208 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
1209 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
1210 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
1211 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
1212 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
1213 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND
},
1214 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND
},
1215 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
1216 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
1217 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND
},
1218 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND
},
1219 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
1220 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
1221 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND
},
1222 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND
},
1223 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND
},
1224 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND
},
1225 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND
},
1226 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND
},
1230 static const struct si_cac_config_reg cac_weights_mars_xt
[] =
1232 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND
},
1233 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND
},
1234 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND
},
1235 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND
},
1236 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
1237 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND
},
1238 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND
},
1239 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND
},
1240 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND
},
1241 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND
},
1242 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND
},
1243 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND
},
1244 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND
},
1245 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND
},
1246 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND
},
1247 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND
},
1248 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND
},
1249 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND
},
1250 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND
},
1251 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND
},
1252 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND
},
1253 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND
},
1254 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND
},
1255 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND
},
1256 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND
},
1257 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND
},
1258 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND
},
1259 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND
},
1260 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
1261 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND
},
1262 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND
},
1263 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND
},
1264 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND
},
1265 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND
},
1266 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND
},
1267 { 0x14, 0x0000ffff, 0, 0x60, SISLANDS_CACCONFIG_CGIND
},
1268 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
1269 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND
},
1270 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
1271 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND
},
1272 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND
},
1273 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
1274 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
1275 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
1276 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
1277 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
1278 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND
},
1279 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND
},
1280 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
1281 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
1282 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND
},
1283 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND
},
1284 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
1285 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
1286 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND
},
1287 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND
},
1288 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND
},
1289 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND
},
1290 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND
},
1291 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND
},
1295 static const struct si_cac_config_reg cac_weights_oland_pro
[] =
1297 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND
},
1298 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND
},
1299 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND
},
1300 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND
},
1301 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
1302 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND
},
1303 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND
},
1304 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND
},
1305 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND
},
1306 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND
},
1307 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND
},
1308 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND
},
1309 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND
},
1310 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND
},
1311 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND
},
1312 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND
},
1313 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND
},
1314 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND
},
1315 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND
},
1316 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND
},
1317 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND
},
1318 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND
},
1319 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND
},
1320 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND
},
1321 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND
},
1322 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND
},
1323 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND
},
1324 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND
},
1325 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
1326 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND
},
1327 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND
},
1328 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND
},
1329 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND
},
1330 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND
},
1331 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND
},
1332 { 0x14, 0x0000ffff, 0, 0x90, SISLANDS_CACCONFIG_CGIND
},
1333 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
1334 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND
},
1335 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
1336 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND
},
1337 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND
},
1338 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
1339 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
1340 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
1341 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
1342 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
1343 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND
},
1344 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND
},
1345 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
1346 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
1347 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND
},
1348 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND
},
1349 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
1350 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
1351 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND
},
1352 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND
},
1353 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND
},
1354 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND
},
1355 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND
},
1356 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND
},
1360 static const struct si_cac_config_reg cac_weights_oland_xt
[] =
1362 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND
},
1363 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND
},
1364 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND
},
1365 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND
},
1366 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
1367 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND
},
1368 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND
},
1369 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND
},
1370 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND
},
1371 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND
},
1372 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND
},
1373 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND
},
1374 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND
},
1375 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND
},
1376 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND
},
1377 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND
},
1378 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND
},
1379 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND
},
1380 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND
},
1381 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND
},
1382 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND
},
1383 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND
},
1384 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND
},
1385 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND
},
1386 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND
},
1387 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND
},
1388 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND
},
1389 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND
},
1390 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
1391 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND
},
1392 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND
},
1393 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND
},
1394 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND
},
1395 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND
},
1396 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND
},
1397 { 0x14, 0x0000ffff, 0, 0x120, SISLANDS_CACCONFIG_CGIND
},
1398 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
1399 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND
},
1400 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
1401 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND
},
1402 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND
},
1403 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
1404 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
1405 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
1406 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
1407 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
1408 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND
},
1409 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND
},
1410 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
1411 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
1412 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND
},
1413 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND
},
1414 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
1415 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
1416 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND
},
1417 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND
},
1418 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND
},
1419 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND
},
1420 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND
},
1421 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND
},
1425 static const struct si_cac_config_reg lcac_oland
[] =
1427 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND
},
1428 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
1429 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND
},
1430 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
1431 { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND
},
1432 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
1433 { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND
},
1434 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
1435 { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND
},
1436 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
1437 { 0x143, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND
},
1438 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
1439 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND
},
1440 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
1441 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND
},
1442 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
1443 { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND
},
1444 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
1445 { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND
},
1446 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
1447 { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND
},
1448 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
1449 { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND
},
1450 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
1451 { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND
},
1452 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
1453 { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND
},
1454 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
1455 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND
},
1456 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
1457 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND
},
1458 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
1459 { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND
},
1460 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
1461 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND
},
1462 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
1463 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND
},
1464 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
1465 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND
},
1466 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
1467 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND
},
1468 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
1472 static const struct si_cac_config_reg lcac_mars_pro
[] =
1474 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND
},
1475 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
1476 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND
},
1477 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
1478 { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND
},
1479 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
1480 { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND
},
1481 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
1482 { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND
},
1483 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
1484 { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND
},
1485 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
1486 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND
},
1487 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
1488 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND
},
1489 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
1490 { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND
},
1491 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
1492 { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND
},
1493 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
1494 { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND
},
1495 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
1496 { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND
},
1497 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
1498 { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND
},
1499 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
1500 { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND
},
1501 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
1502 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND
},
1503 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
1504 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND
},
1505 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
1506 { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND
},
1507 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
1508 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND
},
1509 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
1510 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND
},
1511 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
1512 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND
},
1513 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
1514 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND
},
1515 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND
},
1519 static const struct si_cac_config_reg cac_override_oland
[] =
1524 static const struct si_powertune_data powertune_data_oland
=
1526 ((1 << 16) | 0x6993),
1555 static const struct si_powertune_data powertune_data_mars_pro
=
1557 ((1 << 16) | 0x6993),
1586 static const struct si_dte_data dte_data_oland
=
1597 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1598 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1599 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1604 static const struct si_dte_data dte_data_mars_pro
=
1606 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1607 { 0x0, 0x0, 0x0, 0x0, 0x0 },
1615 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
1616 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
1617 { 0xF627, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1622 static const struct si_dte_data dte_data_sun_xt
=
1624 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1625 { 0x0, 0x0, 0x0, 0x0, 0x0 },
1633 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
1634 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
1635 { 0xD555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1641 static const struct si_cac_config_reg cac_weights_hainan
[] =
1643 { 0x0, 0x0000ffff, 0, 0x2d9, SISLANDS_CACCONFIG_CGIND
},
1644 { 0x0, 0xffff0000, 16, 0x22b, SISLANDS_CACCONFIG_CGIND
},
1645 { 0x1, 0x0000ffff, 0, 0x21c, SISLANDS_CACCONFIG_CGIND
},
1646 { 0x1, 0xffff0000, 16, 0x1dc, SISLANDS_CACCONFIG_CGIND
},
1647 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
1648 { 0x3, 0x0000ffff, 0, 0x24e, SISLANDS_CACCONFIG_CGIND
},
1649 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
1650 { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
1651 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
1652 { 0x5, 0x0000ffff, 0, 0x35e, SISLANDS_CACCONFIG_CGIND
},
1653 { 0x5, 0xffff0000, 16, 0x1143, SISLANDS_CACCONFIG_CGIND
},
1654 { 0x6, 0x0000ffff, 0, 0xe17, SISLANDS_CACCONFIG_CGIND
},
1655 { 0x6, 0xffff0000, 16, 0x441, SISLANDS_CACCONFIG_CGIND
},
1656 { 0x18f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
1657 { 0x7, 0x0000ffff, 0, 0x28b, SISLANDS_CACCONFIG_CGIND
},
1658 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
1659 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
1660 { 0x8, 0xffff0000, 16, 0xabe, SISLANDS_CACCONFIG_CGIND
},
1661 { 0x9, 0x0000ffff, 0, 0xf11, SISLANDS_CACCONFIG_CGIND
},
1662 { 0xa, 0x0000ffff, 0, 0x907, SISLANDS_CACCONFIG_CGIND
},
1663 { 0xb, 0x0000ffff, 0, 0xb45, SISLANDS_CACCONFIG_CGIND
},
1664 { 0xb, 0xffff0000, 16, 0xd1e, SISLANDS_CACCONFIG_CGIND
},
1665 { 0xc, 0x0000ffff, 0, 0xa2c, SISLANDS_CACCONFIG_CGIND
},
1666 { 0xd, 0x0000ffff, 0, 0x62, SISLANDS_CACCONFIG_CGIND
},
1667 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
1668 { 0xe, 0x0000ffff, 0, 0x1f3, SISLANDS_CACCONFIG_CGIND
},
1669 { 0xf, 0x0000ffff, 0, 0x42, SISLANDS_CACCONFIG_CGIND
},
1670 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
1671 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
1672 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
1673 { 0x11, 0x0000ffff, 0, 0x709, SISLANDS_CACCONFIG_CGIND
},
1674 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
1675 { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
1676 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
1677 { 0x13, 0xffff0000, 16, 0x3a, SISLANDS_CACCONFIG_CGIND
},
1678 { 0x14, 0x0000ffff, 0, 0x357, SISLANDS_CACCONFIG_CGIND
},
1679 { 0x15, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND
},
1680 { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
1681 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
1682 { 0x16, 0x0000ffff, 0, 0x314, SISLANDS_CACCONFIG_CGIND
},
1683 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
1684 { 0x17, 0x0000ffff, 0, 0x6d, SISLANDS_CACCONFIG_CGIND
},
1685 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
1686 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
1687 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND
},
1688 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND
},
1689 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND
},
1690 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND
},
1691 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND
},
1692 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND
},
1693 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND
},
1694 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND
},
1695 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND
},
1696 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND
},
1697 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND
},
1698 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND
},
1699 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND
},
1700 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND
},
1701 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND
},
1702 { 0x6d, 0x0000ffff, 0, 0x1b9, SISLANDS_CACCONFIG_CGIND
},
1706 static const struct si_powertune_data powertune_data_hainan
=
1708 ((1 << 16) | 0x6993),
1737 struct rv7xx_power_info
*rv770_get_pi(struct radeon_device
*rdev
);
1738 struct evergreen_power_info
*evergreen_get_pi(struct radeon_device
*rdev
);
1739 struct ni_power_info
*ni_get_pi(struct radeon_device
*rdev
);
1740 struct ni_ps
*ni_get_ps(struct radeon_ps
*rps
);
1742 extern int si_mc_load_microcode(struct radeon_device
*rdev
);
1744 static int si_populate_voltage_value(struct radeon_device
*rdev
,
1745 const struct atom_voltage_table
*table
,
1746 u16 value
, SISLANDS_SMC_VOLTAGE_VALUE
*voltage
);
1747 static int si_get_std_voltage_value(struct radeon_device
*rdev
,
1748 SISLANDS_SMC_VOLTAGE_VALUE
*voltage
,
1750 static int si_write_smc_soft_register(struct radeon_device
*rdev
,
1751 u16 reg_offset
, u32 value
);
1752 static int si_convert_power_level_to_smc(struct radeon_device
*rdev
,
1753 struct rv7xx_pl
*pl
,
1754 SISLANDS_SMC_HW_PERFORMANCE_LEVEL
*level
);
1755 static int si_calculate_sclk_params(struct radeon_device
*rdev
,
1757 SISLANDS_SMC_SCLK_VALUE
*sclk
);
1759 static void si_thermal_start_smc_fan_control(struct radeon_device
*rdev
);
1760 static void si_fan_ctrl_set_default_mode(struct radeon_device
*rdev
);
1762 static struct si_power_info
*si_get_pi(struct radeon_device
*rdev
)
1764 struct si_power_info
*pi
= rdev
->pm
.dpm
.priv
;
1769 static void si_calculate_leakage_for_v_and_t_formula(const struct ni_leakage_coeffients
*coeff
,
1770 u16 v
, s32 t
, u32 ileakage
, u32
*leakage
)
1772 s64 kt
, kv
, leakage_w
, i_leakage
, vddc
;
1773 s64 temperature
, t_slope
, t_intercept
, av
, bv
, t_ref
;
1776 i_leakage
= div64_s64(drm_int2fixp(ileakage
), 100);
1777 vddc
= div64_s64(drm_int2fixp(v
), 1000);
1778 temperature
= div64_s64(drm_int2fixp(t
), 1000);
1780 t_slope
= div64_s64(drm_int2fixp(coeff
->t_slope
), 100000000);
1781 t_intercept
= div64_s64(drm_int2fixp(coeff
->t_intercept
), 100000000);
1782 av
= div64_s64(drm_int2fixp(coeff
->av
), 100000000);
1783 bv
= div64_s64(drm_int2fixp(coeff
->bv
), 100000000);
1784 t_ref
= drm_int2fixp(coeff
->t_ref
);
1786 tmp
= drm_fixp_mul(t_slope
, vddc
) + t_intercept
;
1787 kt
= drm_fixp_exp(drm_fixp_mul(tmp
, temperature
));
1788 kt
= drm_fixp_div(kt
, drm_fixp_exp(drm_fixp_mul(tmp
, t_ref
)));
1789 kv
= drm_fixp_mul(av
, drm_fixp_exp(drm_fixp_mul(bv
, vddc
)));
1791 leakage_w
= drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage
, kt
), kv
), vddc
);
1793 *leakage
= drm_fixp2int(leakage_w
* 1000);
1796 static void si_calculate_leakage_for_v_and_t(struct radeon_device
*rdev
,
1797 const struct ni_leakage_coeffients
*coeff
,
1803 si_calculate_leakage_for_v_and_t_formula(coeff
, v
, t
, i_leakage
, leakage
);
1806 static void si_calculate_leakage_for_v_formula(const struct ni_leakage_coeffients
*coeff
,
1807 const u32 fixed_kt
, u16 v
,
1808 u32 ileakage
, u32
*leakage
)
1810 s64 kt
, kv
, leakage_w
, i_leakage
, vddc
;
1812 i_leakage
= div64_s64(drm_int2fixp(ileakage
), 100);
1813 vddc
= div64_s64(drm_int2fixp(v
), 1000);
1815 kt
= div64_s64(drm_int2fixp(fixed_kt
), 100000000);
1816 kv
= drm_fixp_mul(div64_s64(drm_int2fixp(coeff
->av
), 100000000),
1817 drm_fixp_exp(drm_fixp_mul(div64_s64(drm_int2fixp(coeff
->bv
), 100000000), vddc
)));
1819 leakage_w
= drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage
, kt
), kv
), vddc
);
1821 *leakage
= drm_fixp2int(leakage_w
* 1000);
1824 static void si_calculate_leakage_for_v(struct radeon_device
*rdev
,
1825 const struct ni_leakage_coeffients
*coeff
,
1831 si_calculate_leakage_for_v_formula(coeff
, fixed_kt
, v
, i_leakage
, leakage
);
1835 static void si_update_dte_from_pl2(struct radeon_device
*rdev
,
1836 struct si_dte_data
*dte_data
)
1838 u32 p_limit1
= rdev
->pm
.dpm
.tdp_limit
;
1839 u32 p_limit2
= rdev
->pm
.dpm
.near_tdp_limit
;
1840 u32 k
= dte_data
->k
;
1841 u32 t_max
= dte_data
->max_t
;
1842 u32 t_split
[5] = { 10, 15, 20, 25, 30 };
1843 u32 t_0
= dte_data
->t0
;
1846 if (p_limit2
!= 0 && p_limit2
<= p_limit1
) {
1847 dte_data
->tdep_count
= 3;
1849 for (i
= 0; i
< k
; i
++) {
1851 (t_split
[i
] * (t_max
- t_0
/(u32
)1000) * (1 << 14)) /
1852 (p_limit2
* (u32
)100);
1855 dte_data
->tdep_r
[1] = dte_data
->r
[4] * 2;
1857 for (i
= 2; i
< SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE
; i
++) {
1858 dte_data
->tdep_r
[i
] = dte_data
->r
[4];
1861 DRM_ERROR("Invalid PL2! DTE will not be updated.\n");
1865 static void si_initialize_powertune_defaults(struct radeon_device
*rdev
)
1867 struct ni_power_info
*ni_pi
= ni_get_pi(rdev
);
1868 struct si_power_info
*si_pi
= si_get_pi(rdev
);
1869 bool update_dte_from_pl2
= false;
1871 if (rdev
->family
== CHIP_TAHITI
) {
1872 si_pi
->cac_weights
= cac_weights_tahiti
;
1873 si_pi
->lcac_config
= lcac_tahiti
;
1874 si_pi
->cac_override
= cac_override_tahiti
;
1875 si_pi
->powertune_data
= &powertune_data_tahiti
;
1876 si_pi
->dte_data
= dte_data_tahiti
;
1878 switch (rdev
->pdev
->device
) {
1880 si_pi
->dte_data
.enable_dte_by_default
= true;
1883 si_pi
->dte_data
= dte_data_new_zealand
;
1889 si_pi
->dte_data
= dte_data_aruba_pro
;
1890 update_dte_from_pl2
= true;
1893 si_pi
->dte_data
= dte_data_malta
;
1894 update_dte_from_pl2
= true;
1897 si_pi
->dte_data
= dte_data_tahiti_pro
;
1898 update_dte_from_pl2
= true;
1901 if (si_pi
->dte_data
.enable_dte_by_default
== true)
1902 DRM_ERROR("DTE is not enabled!\n");
1905 } else if (rdev
->family
== CHIP_PITCAIRN
) {
1906 switch (rdev
->pdev
->device
) {
1909 si_pi
->cac_weights
= cac_weights_pitcairn
;
1910 si_pi
->lcac_config
= lcac_pitcairn
;
1911 si_pi
->cac_override
= cac_override_pitcairn
;
1912 si_pi
->powertune_data
= &powertune_data_pitcairn
;
1913 si_pi
->dte_data
= dte_data_curacao_xt
;
1914 update_dte_from_pl2
= true;
1918 si_pi
->cac_weights
= cac_weights_pitcairn
;
1919 si_pi
->lcac_config
= lcac_pitcairn
;
1920 si_pi
->cac_override
= cac_override_pitcairn
;
1921 si_pi
->powertune_data
= &powertune_data_pitcairn
;
1922 si_pi
->dte_data
= dte_data_curacao_pro
;
1923 update_dte_from_pl2
= true;
1927 si_pi
->cac_weights
= cac_weights_pitcairn
;
1928 si_pi
->lcac_config
= lcac_pitcairn
;
1929 si_pi
->cac_override
= cac_override_pitcairn
;
1930 si_pi
->powertune_data
= &powertune_data_pitcairn
;
1931 si_pi
->dte_data
= dte_data_neptune_xt
;
1932 update_dte_from_pl2
= true;
1935 si_pi
->cac_weights
= cac_weights_pitcairn
;
1936 si_pi
->lcac_config
= lcac_pitcairn
;
1937 si_pi
->cac_override
= cac_override_pitcairn
;
1938 si_pi
->powertune_data
= &powertune_data_pitcairn
;
1939 si_pi
->dte_data
= dte_data_pitcairn
;
1942 } else if (rdev
->family
== CHIP_VERDE
) {
1943 si_pi
->lcac_config
= lcac_cape_verde
;
1944 si_pi
->cac_override
= cac_override_cape_verde
;
1945 si_pi
->powertune_data
= &powertune_data_cape_verde
;
1947 switch (rdev
->pdev
->device
) {
1952 si_pi
->cac_weights
= cac_weights_cape_verde_pro
;
1953 si_pi
->dte_data
= dte_data_cape_verde
;
1956 si_pi
->cac_weights
= cac_weights_cape_verde_pro
;
1957 si_pi
->dte_data
= dte_data_sun_xt
;
1961 si_pi
->cac_weights
= cac_weights_heathrow
;
1962 si_pi
->dte_data
= dte_data_cape_verde
;
1966 si_pi
->cac_weights
= cac_weights_chelsea_xt
;
1967 si_pi
->dte_data
= dte_data_cape_verde
;
1970 si_pi
->cac_weights
= cac_weights_chelsea_pro
;
1971 si_pi
->dte_data
= dte_data_cape_verde
;
1974 si_pi
->cac_weights
= cac_weights_heathrow
;
1975 si_pi
->dte_data
= dte_data_venus_xtx
;
1978 si_pi
->cac_weights
= cac_weights_heathrow
;
1979 si_pi
->dte_data
= dte_data_venus_xt
;
1985 si_pi
->cac_weights
= cac_weights_chelsea_pro
;
1986 si_pi
->dte_data
= dte_data_venus_pro
;
1989 si_pi
->cac_weights
= cac_weights_cape_verde
;
1990 si_pi
->dte_data
= dte_data_cape_verde
;
1993 } else if (rdev
->family
== CHIP_OLAND
) {
1994 switch (rdev
->pdev
->device
) {
1999 si_pi
->cac_weights
= cac_weights_mars_pro
;
2000 si_pi
->lcac_config
= lcac_mars_pro
;
2001 si_pi
->cac_override
= cac_override_oland
;
2002 si_pi
->powertune_data
= &powertune_data_mars_pro
;
2003 si_pi
->dte_data
= dte_data_mars_pro
;
2004 update_dte_from_pl2
= true;
2010 si_pi
->cac_weights
= cac_weights_mars_xt
;
2011 si_pi
->lcac_config
= lcac_mars_pro
;
2012 si_pi
->cac_override
= cac_override_oland
;
2013 si_pi
->powertune_data
= &powertune_data_mars_pro
;
2014 si_pi
->dte_data
= dte_data_mars_pro
;
2015 update_dte_from_pl2
= true;
2020 si_pi
->cac_weights
= cac_weights_oland_pro
;
2021 si_pi
->lcac_config
= lcac_mars_pro
;
2022 si_pi
->cac_override
= cac_override_oland
;
2023 si_pi
->powertune_data
= &powertune_data_mars_pro
;
2024 si_pi
->dte_data
= dte_data_mars_pro
;
2025 update_dte_from_pl2
= true;
2028 si_pi
->cac_weights
= cac_weights_oland_xt
;
2029 si_pi
->lcac_config
= lcac_mars_pro
;
2030 si_pi
->cac_override
= cac_override_oland
;
2031 si_pi
->powertune_data
= &powertune_data_mars_pro
;
2032 si_pi
->dte_data
= dte_data_mars_pro
;
2033 update_dte_from_pl2
= true;
2036 si_pi
->cac_weights
= cac_weights_oland
;
2037 si_pi
->lcac_config
= lcac_oland
;
2038 si_pi
->cac_override
= cac_override_oland
;
2039 si_pi
->powertune_data
= &powertune_data_oland
;
2040 si_pi
->dte_data
= dte_data_oland
;
2043 } else if (rdev
->family
== CHIP_HAINAN
) {
2044 si_pi
->cac_weights
= cac_weights_hainan
;
2045 si_pi
->lcac_config
= lcac_oland
;
2046 si_pi
->cac_override
= cac_override_oland
;
2047 si_pi
->powertune_data
= &powertune_data_hainan
;
2048 si_pi
->dte_data
= dte_data_sun_xt
;
2049 update_dte_from_pl2
= true;
2051 DRM_ERROR("Unknown SI asic revision, failed to initialize PowerTune!\n");
2055 ni_pi
->enable_power_containment
= false;
2056 ni_pi
->enable_cac
= false;
2057 ni_pi
->enable_sq_ramping
= false;
2058 si_pi
->enable_dte
= false;
2060 if (si_pi
->powertune_data
->enable_powertune_by_default
) {
2061 ni_pi
->enable_power_containment
= true;
2062 ni_pi
->enable_cac
= true;
2063 if (si_pi
->dte_data
.enable_dte_by_default
) {
2064 si_pi
->enable_dte
= true;
2065 if (update_dte_from_pl2
)
2066 si_update_dte_from_pl2(rdev
, &si_pi
->dte_data
);
2069 ni_pi
->enable_sq_ramping
= true;
2072 ni_pi
->driver_calculate_cac_leakage
= true;
2073 ni_pi
->cac_configuration_required
= true;
2075 if (ni_pi
->cac_configuration_required
) {
2076 ni_pi
->support_cac_long_term_average
= true;
2077 si_pi
->dyn_powertune_data
.l2_lta_window_size
=
2078 si_pi
->powertune_data
->l2_lta_window_size_default
;
2079 si_pi
->dyn_powertune_data
.lts_truncate
=
2080 si_pi
->powertune_data
->lts_truncate_default
;
2082 ni_pi
->support_cac_long_term_average
= false;
2083 si_pi
->dyn_powertune_data
.l2_lta_window_size
= 0;
2084 si_pi
->dyn_powertune_data
.lts_truncate
= 0;
2087 si_pi
->dyn_powertune_data
.disable_uvd_powertune
= false;
2090 static u32
si_get_smc_power_scaling_factor(struct radeon_device
*rdev
)
2095 static u32
si_calculate_cac_wintime(struct radeon_device
*rdev
)
2100 u32 cac_window_size
;
2102 xclk
= radeon_get_xclk(rdev
);
2107 cac_window
= RREG32(CG_CAC_CTRL
) & CAC_WINDOW_MASK
;
2108 cac_window_size
= ((cac_window
& 0xFFFF0000) >> 16) * (cac_window
& 0x0000FFFF);
2110 wintime
= (cac_window_size
* 100) / xclk
;
2115 static u32
si_scale_power_for_smc(u32 power_in_watts
, u32 scaling_factor
)
2117 return power_in_watts
;
2120 static int si_calculate_adjusted_tdp_limits(struct radeon_device
*rdev
,
2121 bool adjust_polarity
,
2124 u32
*near_tdp_limit
)
2126 u32 adjustment_delta
, max_tdp_limit
;
2128 if (tdp_adjustment
> (u32
)rdev
->pm
.dpm
.tdp_od_limit
)
2131 max_tdp_limit
= ((100 + 100) * rdev
->pm
.dpm
.tdp_limit
) / 100;
2133 if (adjust_polarity
) {
2134 *tdp_limit
= ((100 + tdp_adjustment
) * rdev
->pm
.dpm
.tdp_limit
) / 100;
2135 *near_tdp_limit
= rdev
->pm
.dpm
.near_tdp_limit_adjusted
+ (*tdp_limit
- rdev
->pm
.dpm
.tdp_limit
);
2137 *tdp_limit
= ((100 - tdp_adjustment
) * rdev
->pm
.dpm
.tdp_limit
) / 100;
2138 adjustment_delta
= rdev
->pm
.dpm
.tdp_limit
- *tdp_limit
;
2139 if (adjustment_delta
< rdev
->pm
.dpm
.near_tdp_limit_adjusted
)
2140 *near_tdp_limit
= rdev
->pm
.dpm
.near_tdp_limit_adjusted
- adjustment_delta
;
2142 *near_tdp_limit
= 0;
2145 if ((*tdp_limit
<= 0) || (*tdp_limit
> max_tdp_limit
))
2147 if ((*near_tdp_limit
<= 0) || (*near_tdp_limit
> *tdp_limit
))
2153 static int si_populate_smc_tdp_limits(struct radeon_device
*rdev
,
2154 struct radeon_ps
*radeon_state
)
2156 struct ni_power_info
*ni_pi
= ni_get_pi(rdev
);
2157 struct si_power_info
*si_pi
= si_get_pi(rdev
);
2159 if (ni_pi
->enable_power_containment
) {
2160 SISLANDS_SMC_STATETABLE
*smc_table
= &si_pi
->smc_statetable
;
2161 PP_SIslands_PAPMParameters
*papm_parm
;
2162 struct radeon_ppm_table
*ppm
= rdev
->pm
.dpm
.dyn_state
.ppm_table
;
2163 u32 scaling_factor
= si_get_smc_power_scaling_factor(rdev
);
2168 if (scaling_factor
== 0)
2171 memset(smc_table
, 0, sizeof(SISLANDS_SMC_STATETABLE
));
2173 ret
= si_calculate_adjusted_tdp_limits(rdev
,
2175 rdev
->pm
.dpm
.tdp_adjustment
,
2181 smc_table
->dpm2Params
.TDPLimit
=
2182 cpu_to_be32(si_scale_power_for_smc(tdp_limit
, scaling_factor
) * 1000);
2183 smc_table
->dpm2Params
.NearTDPLimit
=
2184 cpu_to_be32(si_scale_power_for_smc(near_tdp_limit
, scaling_factor
) * 1000);
2185 smc_table
->dpm2Params
.SafePowerLimit
=
2186 cpu_to_be32(si_scale_power_for_smc((near_tdp_limit
* SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT
) / 100, scaling_factor
) * 1000);
2188 ret
= si_copy_bytes_to_smc(rdev
,
2189 (si_pi
->state_table_start
+ offsetof(SISLANDS_SMC_STATETABLE
, dpm2Params
) +
2190 offsetof(PP_SIslands_DPM2Parameters
, TDPLimit
)),
2191 (u8
*)(&(smc_table
->dpm2Params
.TDPLimit
)),
2197 if (si_pi
->enable_ppm
) {
2198 papm_parm
= &si_pi
->papm_parm
;
2199 memset(papm_parm
, 0, sizeof(PP_SIslands_PAPMParameters
));
2200 papm_parm
->NearTDPLimitTherm
= cpu_to_be32(ppm
->dgpu_tdp
);
2201 papm_parm
->dGPU_T_Limit
= cpu_to_be32(ppm
->tj_max
);
2202 papm_parm
->dGPU_T_Warning
= cpu_to_be32(95);
2203 papm_parm
->dGPU_T_Hysteresis
= cpu_to_be32(5);
2204 papm_parm
->PlatformPowerLimit
= 0xffffffff;
2205 papm_parm
->NearTDPLimitPAPM
= 0xffffffff;
2207 ret
= si_copy_bytes_to_smc(rdev
, si_pi
->papm_cfg_table_start
,
2209 sizeof(PP_SIslands_PAPMParameters
),
2218 static int si_populate_smc_tdp_limits_2(struct radeon_device
*rdev
,
2219 struct radeon_ps
*radeon_state
)
2221 struct ni_power_info
*ni_pi
= ni_get_pi(rdev
);
2222 struct si_power_info
*si_pi
= si_get_pi(rdev
);
2224 if (ni_pi
->enable_power_containment
) {
2225 SISLANDS_SMC_STATETABLE
*smc_table
= &si_pi
->smc_statetable
;
2226 u32 scaling_factor
= si_get_smc_power_scaling_factor(rdev
);
2229 memset(smc_table
, 0, sizeof(SISLANDS_SMC_STATETABLE
));
2231 smc_table
->dpm2Params
.NearTDPLimit
=
2232 cpu_to_be32(si_scale_power_for_smc(rdev
->pm
.dpm
.near_tdp_limit_adjusted
, scaling_factor
) * 1000);
2233 smc_table
->dpm2Params
.SafePowerLimit
=
2234 cpu_to_be32(si_scale_power_for_smc((rdev
->pm
.dpm
.near_tdp_limit_adjusted
* SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT
) / 100, scaling_factor
) * 1000);
2236 ret
= si_copy_bytes_to_smc(rdev
,
2237 (si_pi
->state_table_start
+
2238 offsetof(SISLANDS_SMC_STATETABLE
, dpm2Params
) +
2239 offsetof(PP_SIslands_DPM2Parameters
, NearTDPLimit
)),
2240 (u8
*)(&(smc_table
->dpm2Params
.NearTDPLimit
)),
2250 static u16
si_calculate_power_efficiency_ratio(struct radeon_device
*rdev
,
2251 const u16 prev_std_vddc
,
2252 const u16 curr_std_vddc
)
2254 u64 margin
= (u64
)SISLANDS_DPM2_PWREFFICIENCYRATIO_MARGIN
;
2255 u64 prev_vddc
= (u64
)prev_std_vddc
;
2256 u64 curr_vddc
= (u64
)curr_std_vddc
;
2257 u64 pwr_efficiency_ratio
, n
, d
;
2259 if ((prev_vddc
== 0) || (curr_vddc
== 0))
2262 n
= div64_u64((u64
)1024 * curr_vddc
* curr_vddc
* ((u64
)1000 + margin
), (u64
)1000);
2263 d
= prev_vddc
* prev_vddc
;
2264 pwr_efficiency_ratio
= div64_u64(n
, d
);
2266 if (pwr_efficiency_ratio
> (u64
)0xFFFF)
2269 return (u16
)pwr_efficiency_ratio
;
2272 static bool si_should_disable_uvd_powertune(struct radeon_device
*rdev
,
2273 struct radeon_ps
*radeon_state
)
2275 struct si_power_info
*si_pi
= si_get_pi(rdev
);
2277 if (si_pi
->dyn_powertune_data
.disable_uvd_powertune
&&
2278 radeon_state
->vclk
&& radeon_state
->dclk
)
2284 static int si_populate_power_containment_values(struct radeon_device
*rdev
,
2285 struct radeon_ps
*radeon_state
,
2286 SISLANDS_SMC_SWSTATE
*smc_state
)
2288 struct evergreen_power_info
*eg_pi
= evergreen_get_pi(rdev
);
2289 struct ni_power_info
*ni_pi
= ni_get_pi(rdev
);
2290 struct ni_ps
*state
= ni_get_ps(radeon_state
);
2291 SISLANDS_SMC_VOLTAGE_VALUE vddc
;
2298 u16 pwr_efficiency_ratio
;
2300 bool disable_uvd_power_tune
;
2303 if (ni_pi
->enable_power_containment
== false)
2306 if (state
->performance_level_count
== 0)
2309 if (smc_state
->levelCount
!= state
->performance_level_count
)
2312 disable_uvd_power_tune
= si_should_disable_uvd_powertune(rdev
, radeon_state
);
2314 smc_state
->levels
[0].dpm2
.MaxPS
= 0;
2315 smc_state
->levels
[0].dpm2
.NearTDPDec
= 0;
2316 smc_state
->levels
[0].dpm2
.AboveSafeInc
= 0;
2317 smc_state
->levels
[0].dpm2
.BelowSafeInc
= 0;
2318 smc_state
->levels
[0].dpm2
.PwrEfficiencyRatio
= 0;
2320 for (i
= 1; i
< state
->performance_level_count
; i
++) {
2321 prev_sclk
= state
->performance_levels
[i
-1].sclk
;
2322 max_sclk
= state
->performance_levels
[i
].sclk
;
2324 max_ps_percent
= SISLANDS_DPM2_MAXPS_PERCENT_M
;
2326 max_ps_percent
= SISLANDS_DPM2_MAXPS_PERCENT_H
;
2328 if (prev_sclk
> max_sclk
)
2331 if ((max_ps_percent
== 0) ||
2332 (prev_sclk
== max_sclk
) ||
2333 disable_uvd_power_tune
) {
2334 min_sclk
= max_sclk
;
2335 } else if (i
== 1) {
2336 min_sclk
= prev_sclk
;
2338 min_sclk
= (prev_sclk
* (u32
)max_ps_percent
) / 100;
2341 if (min_sclk
< state
->performance_levels
[0].sclk
)
2342 min_sclk
= state
->performance_levels
[0].sclk
;
2347 ret
= si_populate_voltage_value(rdev
, &eg_pi
->vddc_voltage_table
,
2348 state
->performance_levels
[i
-1].vddc
, &vddc
);
2352 ret
= si_get_std_voltage_value(rdev
, &vddc
, &prev_std_vddc
);
2356 ret
= si_populate_voltage_value(rdev
, &eg_pi
->vddc_voltage_table
,
2357 state
->performance_levels
[i
].vddc
, &vddc
);
2361 ret
= si_get_std_voltage_value(rdev
, &vddc
, &curr_std_vddc
);
2365 pwr_efficiency_ratio
= si_calculate_power_efficiency_ratio(rdev
,
2366 prev_std_vddc
, curr_std_vddc
);
2368 smc_state
->levels
[i
].dpm2
.MaxPS
= (u8
)((SISLANDS_DPM2_MAX_PULSE_SKIP
* (max_sclk
- min_sclk
)) / max_sclk
);
2369 smc_state
->levels
[i
].dpm2
.NearTDPDec
= SISLANDS_DPM2_NEAR_TDP_DEC
;
2370 smc_state
->levels
[i
].dpm2
.AboveSafeInc
= SISLANDS_DPM2_ABOVE_SAFE_INC
;
2371 smc_state
->levels
[i
].dpm2
.BelowSafeInc
= SISLANDS_DPM2_BELOW_SAFE_INC
;
2372 smc_state
->levels
[i
].dpm2
.PwrEfficiencyRatio
= cpu_to_be16(pwr_efficiency_ratio
);
2378 static int si_populate_sq_ramping_values(struct radeon_device
*rdev
,
2379 struct radeon_ps
*radeon_state
,
2380 SISLANDS_SMC_SWSTATE
*smc_state
)
2382 struct ni_power_info
*ni_pi
= ni_get_pi(rdev
);
2383 struct ni_ps
*state
= ni_get_ps(radeon_state
);
2384 u32 sq_power_throttle
, sq_power_throttle2
;
2385 bool enable_sq_ramping
= ni_pi
->enable_sq_ramping
;
2388 if (state
->performance_level_count
== 0)
2391 if (smc_state
->levelCount
!= state
->performance_level_count
)
2394 if (rdev
->pm
.dpm
.sq_ramping_threshold
== 0)
2397 if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER
> (MAX_POWER_MASK
>> MAX_POWER_SHIFT
))
2398 enable_sq_ramping
= false;
2400 if (SISLANDS_DPM2_SQ_RAMP_MIN_POWER
> (MIN_POWER_MASK
>> MIN_POWER_SHIFT
))
2401 enable_sq_ramping
= false;
2403 if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA
> (MAX_POWER_DELTA_MASK
>> MAX_POWER_DELTA_SHIFT
))
2404 enable_sq_ramping
= false;
2406 if (SISLANDS_DPM2_SQ_RAMP_STI_SIZE
> (STI_SIZE_MASK
>> STI_SIZE_SHIFT
))
2407 enable_sq_ramping
= false;
2409 if (SISLANDS_DPM2_SQ_RAMP_LTI_RATIO
> (LTI_RATIO_MASK
>> LTI_RATIO_SHIFT
))
2410 enable_sq_ramping
= false;
2412 for (i
= 0; i
< state
->performance_level_count
; i
++) {
2413 sq_power_throttle
= 0;
2414 sq_power_throttle2
= 0;
2416 if ((state
->performance_levels
[i
].sclk
>= rdev
->pm
.dpm
.sq_ramping_threshold
) &&
2417 enable_sq_ramping
) {
2418 sq_power_throttle
|= MAX_POWER(SISLANDS_DPM2_SQ_RAMP_MAX_POWER
);
2419 sq_power_throttle
|= MIN_POWER(SISLANDS_DPM2_SQ_RAMP_MIN_POWER
);
2420 sq_power_throttle2
|= MAX_POWER_DELTA(SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA
);
2421 sq_power_throttle2
|= STI_SIZE(SISLANDS_DPM2_SQ_RAMP_STI_SIZE
);
2422 sq_power_throttle2
|= LTI_RATIO(SISLANDS_DPM2_SQ_RAMP_LTI_RATIO
);
2424 sq_power_throttle
|= MAX_POWER_MASK
| MIN_POWER_MASK
;
2425 sq_power_throttle2
|= MAX_POWER_DELTA_MASK
| STI_SIZE_MASK
| LTI_RATIO_MASK
;
2428 smc_state
->levels
[i
].SQPowerThrottle
= cpu_to_be32(sq_power_throttle
);
2429 smc_state
->levels
[i
].SQPowerThrottle_2
= cpu_to_be32(sq_power_throttle2
);
2435 static int si_enable_power_containment(struct radeon_device
*rdev
,
2436 struct radeon_ps
*radeon_new_state
,
2439 struct ni_power_info
*ni_pi
= ni_get_pi(rdev
);
2440 PPSMC_Result smc_result
;
2443 if (ni_pi
->enable_power_containment
) {
2445 if (!si_should_disable_uvd_powertune(rdev
, radeon_new_state
)) {
2446 smc_result
= si_send_msg_to_smc(rdev
, PPSMC_TDPClampingActive
);
2447 if (smc_result
!= PPSMC_Result_OK
) {
2449 ni_pi
->pc_enabled
= false;
2451 ni_pi
->pc_enabled
= true;
2455 smc_result
= si_send_msg_to_smc(rdev
, PPSMC_TDPClampingInactive
);
2456 if (smc_result
!= PPSMC_Result_OK
)
2458 ni_pi
->pc_enabled
= false;
2465 static int si_initialize_smc_dte_tables(struct radeon_device
*rdev
)
2467 struct si_power_info
*si_pi
= si_get_pi(rdev
);
2469 struct si_dte_data
*dte_data
= &si_pi
->dte_data
;
2470 Smc_SIslands_DTE_Configuration
*dte_tables
= NULL
;
2475 if (dte_data
== NULL
)
2476 si_pi
->enable_dte
= false;
2478 if (si_pi
->enable_dte
== false)
2481 if (dte_data
->k
<= 0)
2484 dte_tables
= kzalloc(sizeof(Smc_SIslands_DTE_Configuration
), GFP_KERNEL
);
2485 if (dte_tables
== NULL
) {
2486 si_pi
->enable_dte
= false;
2490 table_size
= dte_data
->k
;
2492 if (table_size
> SMC_SISLANDS_DTE_MAX_FILTER_STAGES
)
2493 table_size
= SMC_SISLANDS_DTE_MAX_FILTER_STAGES
;
2495 tdep_count
= dte_data
->tdep_count
;
2496 if (tdep_count
> SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE
)
2497 tdep_count
= SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE
;
2499 dte_tables
->K
= cpu_to_be32(table_size
);
2500 dte_tables
->T0
= cpu_to_be32(dte_data
->t0
);
2501 dte_tables
->MaxT
= cpu_to_be32(dte_data
->max_t
);
2502 dte_tables
->WindowSize
= dte_data
->window_size
;
2503 dte_tables
->temp_select
= dte_data
->temp_select
;
2504 dte_tables
->DTE_mode
= dte_data
->dte_mode
;
2505 dte_tables
->Tthreshold
= cpu_to_be32(dte_data
->t_threshold
);
2510 for (i
= 0; i
< table_size
; i
++) {
2511 dte_tables
->tau
[i
] = cpu_to_be32(dte_data
->tau
[i
]);
2512 dte_tables
->R
[i
] = cpu_to_be32(dte_data
->r
[i
]);
2515 dte_tables
->Tdep_count
= tdep_count
;
2517 for (i
= 0; i
< (u32
)tdep_count
; i
++) {
2518 dte_tables
->T_limits
[i
] = dte_data
->t_limits
[i
];
2519 dte_tables
->Tdep_tau
[i
] = cpu_to_be32(dte_data
->tdep_tau
[i
]);
2520 dte_tables
->Tdep_R
[i
] = cpu_to_be32(dte_data
->tdep_r
[i
]);
2523 ret
= si_copy_bytes_to_smc(rdev
, si_pi
->dte_table_start
, (u8
*)dte_tables
,
2524 sizeof(Smc_SIslands_DTE_Configuration
), si_pi
->sram_end
);
2530 static int si_get_cac_std_voltage_max_min(struct radeon_device
*rdev
,
2533 struct si_power_info
*si_pi
= si_get_pi(rdev
);
2534 struct radeon_cac_leakage_table
*table
=
2535 &rdev
->pm
.dpm
.dyn_state
.cac_leakage_table
;
2546 for (i
= 0; i
< table
->count
; i
++) {
2547 if (table
->entries
[i
].vddc
> *max
)
2548 *max
= table
->entries
[i
].vddc
;
2549 if (table
->entries
[i
].vddc
< *min
)
2550 *min
= table
->entries
[i
].vddc
;
2553 if (si_pi
->powertune_data
->lkge_lut_v0_percent
> 100)
2556 v0_loadline
= (*min
) * (100 - si_pi
->powertune_data
->lkge_lut_v0_percent
) / 100;
2558 if (v0_loadline
> 0xFFFFUL
)
2561 *min
= (u16
)v0_loadline
;
2563 if ((*min
> *max
) || (*max
== 0) || (*min
== 0))
2569 static u16
si_get_cac_std_voltage_step(u16 max
, u16 min
)
2571 return ((max
- min
) + (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES
- 1)) /
2572 SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES
;
2575 static int si_init_dte_leakage_table(struct radeon_device
*rdev
,
2576 PP_SIslands_CacConfig
*cac_tables
,
2577 u16 vddc_max
, u16 vddc_min
, u16 vddc_step
,
2580 struct si_power_info
*si_pi
= si_get_pi(rdev
);
2588 scaling_factor
= si_get_smc_power_scaling_factor(rdev
);
2590 for (i
= 0; i
< SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES
; i
++) {
2591 t
= (1000 * (i
* t_step
+ t0
));
2593 for (j
= 0; j
< SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES
; j
++) {
2594 voltage
= vddc_max
- (vddc_step
* j
);
2596 si_calculate_leakage_for_v_and_t(rdev
,
2597 &si_pi
->powertune_data
->leakage_coefficients
,
2600 si_pi
->dyn_powertune_data
.cac_leakage
,
2603 smc_leakage
= si_scale_power_for_smc(leakage
, scaling_factor
) / 4;
2605 if (smc_leakage
> 0xFFFF)
2606 smc_leakage
= 0xFFFF;
2608 cac_tables
->cac_lkge_lut
[i
][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES
-1-j
] =
2609 cpu_to_be16((u16
)smc_leakage
);
2615 static int si_init_simplified_leakage_table(struct radeon_device
*rdev
,
2616 PP_SIslands_CacConfig
*cac_tables
,
2617 u16 vddc_max
, u16 vddc_min
, u16 vddc_step
)
2619 struct si_power_info
*si_pi
= si_get_pi(rdev
);
2626 scaling_factor
= si_get_smc_power_scaling_factor(rdev
);
2628 for (j
= 0; j
< SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES
; j
++) {
2629 voltage
= vddc_max
- (vddc_step
* j
);
2631 si_calculate_leakage_for_v(rdev
,
2632 &si_pi
->powertune_data
->leakage_coefficients
,
2633 si_pi
->powertune_data
->fixed_kt
,
2635 si_pi
->dyn_powertune_data
.cac_leakage
,
2638 smc_leakage
= si_scale_power_for_smc(leakage
, scaling_factor
) / 4;
2640 if (smc_leakage
> 0xFFFF)
2641 smc_leakage
= 0xFFFF;
2643 for (i
= 0; i
< SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES
; i
++)
2644 cac_tables
->cac_lkge_lut
[i
][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES
-1-j
] =
2645 cpu_to_be16((u16
)smc_leakage
);
2650 static int si_initialize_smc_cac_tables(struct radeon_device
*rdev
)
2652 struct ni_power_info
*ni_pi
= ni_get_pi(rdev
);
2653 struct si_power_info
*si_pi
= si_get_pi(rdev
);
2654 PP_SIslands_CacConfig
*cac_tables
= NULL
;
2655 u16 vddc_max
, vddc_min
, vddc_step
;
2657 u32 load_line_slope
, reg
;
2659 u32 ticks_per_us
= radeon_get_xclk(rdev
) / 100;
2661 if (ni_pi
->enable_cac
== false)
2664 cac_tables
= kzalloc(sizeof(PP_SIslands_CacConfig
), GFP_KERNEL
);
2668 reg
= RREG32(CG_CAC_CTRL
) & ~CAC_WINDOW_MASK
;
2669 reg
|= CAC_WINDOW(si_pi
->powertune_data
->cac_window
);
2670 WREG32(CG_CAC_CTRL
, reg
);
2672 si_pi
->dyn_powertune_data
.cac_leakage
= rdev
->pm
.dpm
.cac_leakage
;
2673 si_pi
->dyn_powertune_data
.dc_pwr_value
=
2674 si_pi
->powertune_data
->dc_cac
[NISLANDS_DCCAC_LEVEL_0
];
2675 si_pi
->dyn_powertune_data
.wintime
= si_calculate_cac_wintime(rdev
);
2676 si_pi
->dyn_powertune_data
.shift_n
= si_pi
->powertune_data
->shift_n_default
;
2678 si_pi
->dyn_powertune_data
.leakage_minimum_temperature
= 80 * 1000;
2680 ret
= si_get_cac_std_voltage_max_min(rdev
, &vddc_max
, &vddc_min
);
2684 vddc_step
= si_get_cac_std_voltage_step(vddc_max
, vddc_min
);
2685 vddc_min
= vddc_max
- (vddc_step
* (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES
- 1));
2689 if (si_pi
->enable_dte
|| ni_pi
->driver_calculate_cac_leakage
)
2690 ret
= si_init_dte_leakage_table(rdev
, cac_tables
,
2691 vddc_max
, vddc_min
, vddc_step
,
2694 ret
= si_init_simplified_leakage_table(rdev
, cac_tables
,
2695 vddc_max
, vddc_min
, vddc_step
);
2699 load_line_slope
= ((u32
)rdev
->pm
.dpm
.load_line_slope
<< SMC_SISLANDS_SCALE_R
) / 100;
2701 cac_tables
->l2numWin_TDP
= cpu_to_be32(si_pi
->dyn_powertune_data
.l2_lta_window_size
);
2702 cac_tables
->lts_truncate_n
= si_pi
->dyn_powertune_data
.lts_truncate
;
2703 cac_tables
->SHIFT_N
= si_pi
->dyn_powertune_data
.shift_n
;
2704 cac_tables
->lkge_lut_V0
= cpu_to_be32((u32
)vddc_min
);
2705 cac_tables
->lkge_lut_Vstep
= cpu_to_be32((u32
)vddc_step
);
2706 cac_tables
->R_LL
= cpu_to_be32(load_line_slope
);
2707 cac_tables
->WinTime
= cpu_to_be32(si_pi
->dyn_powertune_data
.wintime
);
2708 cac_tables
->calculation_repeats
= cpu_to_be32(2);
2709 cac_tables
->dc_cac
= cpu_to_be32(0);
2710 cac_tables
->log2_PG_LKG_SCALE
= 12;
2711 cac_tables
->cac_temp
= si_pi
->powertune_data
->operating_temp
;
2712 cac_tables
->lkge_lut_T0
= cpu_to_be32((u32
)t0
);
2713 cac_tables
->lkge_lut_Tstep
= cpu_to_be32((u32
)t_step
);
2715 ret
= si_copy_bytes_to_smc(rdev
, si_pi
->cac_table_start
, (u8
*)cac_tables
,
2716 sizeof(PP_SIslands_CacConfig
), si_pi
->sram_end
);
2721 ret
= si_write_smc_soft_register(rdev
, SI_SMC_SOFT_REGISTER_ticks_per_us
, ticks_per_us
);
2725 ni_pi
->enable_cac
= false;
2726 ni_pi
->enable_power_containment
= false;
2734 static int si_program_cac_config_registers(struct radeon_device
*rdev
,
2735 const struct si_cac_config_reg
*cac_config_regs
)
2737 const struct si_cac_config_reg
*config_regs
= cac_config_regs
;
2738 u32 data
= 0, offset
;
2743 while (config_regs
->offset
!= 0xFFFFFFFF) {
2744 switch (config_regs
->type
) {
2745 case SISLANDS_CACCONFIG_CGIND
:
2746 offset
= SMC_CG_IND_START
+ config_regs
->offset
;
2747 if (offset
< SMC_CG_IND_END
)
2748 data
= RREG32_SMC(offset
);
2751 data
= RREG32(config_regs
->offset
<< 2);
2755 data
&= ~config_regs
->mask
;
2756 data
|= ((config_regs
->value
<< config_regs
->shift
) & config_regs
->mask
);
2758 switch (config_regs
->type
) {
2759 case SISLANDS_CACCONFIG_CGIND
:
2760 offset
= SMC_CG_IND_START
+ config_regs
->offset
;
2761 if (offset
< SMC_CG_IND_END
)
2762 WREG32_SMC(offset
, data
);
2765 WREG32(config_regs
->offset
<< 2, data
);
2773 static int si_initialize_hardware_cac_manager(struct radeon_device
*rdev
)
2775 struct ni_power_info
*ni_pi
= ni_get_pi(rdev
);
2776 struct si_power_info
*si_pi
= si_get_pi(rdev
);
2779 if ((ni_pi
->enable_cac
== false) ||
2780 (ni_pi
->cac_configuration_required
== false))
2783 ret
= si_program_cac_config_registers(rdev
, si_pi
->lcac_config
);
2786 ret
= si_program_cac_config_registers(rdev
, si_pi
->cac_override
);
2789 ret
= si_program_cac_config_registers(rdev
, si_pi
->cac_weights
);
2796 static int si_enable_smc_cac(struct radeon_device
*rdev
,
2797 struct radeon_ps
*radeon_new_state
,
2800 struct ni_power_info
*ni_pi
= ni_get_pi(rdev
);
2801 struct si_power_info
*si_pi
= si_get_pi(rdev
);
2802 PPSMC_Result smc_result
;
2805 if (ni_pi
->enable_cac
) {
2807 if (!si_should_disable_uvd_powertune(rdev
, radeon_new_state
)) {
2808 if (ni_pi
->support_cac_long_term_average
) {
2809 smc_result
= si_send_msg_to_smc(rdev
, PPSMC_CACLongTermAvgEnable
);
2810 if (smc_result
!= PPSMC_Result_OK
)
2811 ni_pi
->support_cac_long_term_average
= false;
2814 smc_result
= si_send_msg_to_smc(rdev
, PPSMC_MSG_EnableCac
);
2815 if (smc_result
!= PPSMC_Result_OK
) {
2817 ni_pi
->cac_enabled
= false;
2819 ni_pi
->cac_enabled
= true;
2822 if (si_pi
->enable_dte
) {
2823 smc_result
= si_send_msg_to_smc(rdev
, PPSMC_MSG_EnableDTE
);
2824 if (smc_result
!= PPSMC_Result_OK
)
2828 } else if (ni_pi
->cac_enabled
) {
2829 if (si_pi
->enable_dte
)
2830 smc_result
= si_send_msg_to_smc(rdev
, PPSMC_MSG_DisableDTE
);
2832 smc_result
= si_send_msg_to_smc(rdev
, PPSMC_MSG_DisableCac
);
2834 ni_pi
->cac_enabled
= false;
2836 if (ni_pi
->support_cac_long_term_average
)
2837 smc_result
= si_send_msg_to_smc(rdev
, PPSMC_CACLongTermAvgDisable
);
2843 static int si_init_smc_spll_table(struct radeon_device
*rdev
)
2845 struct ni_power_info
*ni_pi
= ni_get_pi(rdev
);
2846 struct si_power_info
*si_pi
= si_get_pi(rdev
);
2847 SMC_SISLANDS_SPLL_DIV_TABLE
*spll_table
;
2848 SISLANDS_SMC_SCLK_VALUE sclk_params
;
2856 if (si_pi
->spll_table_start
== 0)
2859 spll_table
= kzalloc(sizeof(SMC_SISLANDS_SPLL_DIV_TABLE
), GFP_KERNEL
);
2860 if (spll_table
== NULL
)
2863 for (i
= 0; i
< 256; i
++) {
2864 ret
= si_calculate_sclk_params(rdev
, sclk
, &sclk_params
);
2868 p_div
= (sclk_params
.vCG_SPLL_FUNC_CNTL
& SPLL_PDIV_A_MASK
) >> SPLL_PDIV_A_SHIFT
;
2869 fb_div
= (sclk_params
.vCG_SPLL_FUNC_CNTL_3
& SPLL_FB_DIV_MASK
) >> SPLL_FB_DIV_SHIFT
;
2870 clk_s
= (sclk_params
.vCG_SPLL_SPREAD_SPECTRUM
& CLK_S_MASK
) >> CLK_S_SHIFT
;
2871 clk_v
= (sclk_params
.vCG_SPLL_SPREAD_SPECTRUM_2
& CLK_V_MASK
) >> CLK_V_SHIFT
;
2873 fb_div
&= ~0x00001FFF;
2877 if (p_div
& ~(SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK
>> SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT
))
2879 if (fb_div
& ~(SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK
>> SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT
))
2881 if (clk_s
& ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK
>> SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT
))
2883 if (clk_v
& ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK
>> SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT
))
2889 tmp
= ((fb_div
<< SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT
) & SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK
) |
2890 ((p_div
<< SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT
) & SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK
);
2891 spll_table
->freq
[i
] = cpu_to_be32(tmp
);
2893 tmp
= ((clk_v
<< SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT
) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK
) |
2894 ((clk_s
<< SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT
) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK
);
2895 spll_table
->ss
[i
] = cpu_to_be32(tmp
);
2902 ret
= si_copy_bytes_to_smc(rdev
, si_pi
->spll_table_start
,
2903 (u8
*)spll_table
, sizeof(SMC_SISLANDS_SPLL_DIV_TABLE
),
2907 ni_pi
->enable_power_containment
= false;
2914 struct si_dpm_quirk
{
2923 /* cards with dpm stability problems */
2924 static struct si_dpm_quirk si_dpm_quirk_list
[] = {
2925 /* PITCAIRN - https://bugs.freedesktop.org/show_bug.cgi?id=76490 */
2926 { PCI_VENDOR_ID_ATI
, 0x6810, 0x1462, 0x3036, 0, 120000 },
2930 static void si_apply_state_adjust_rules(struct radeon_device
*rdev
,
2931 struct radeon_ps
*rps
)
2933 struct ni_ps
*ps
= ni_get_ps(rps
);
2934 struct radeon_clock_and_voltage_limits
*max_limits
;
2935 bool disable_mclk_switching
= false;
2936 bool disable_sclk_switching
= false;
2939 u32 max_sclk_vddc
, max_mclk_vddci
, max_mclk_vddc
;
2940 u32 max_sclk
= 0, max_mclk
= 0;
2942 struct si_dpm_quirk
*p
= si_dpm_quirk_list
;
2944 /* Apply dpm quirks */
2945 while (p
&& p
->chip_device
!= 0) {
2946 if (rdev
->pdev
->vendor
== p
->chip_vendor
&&
2947 rdev
->pdev
->device
== p
->chip_device
&&
2948 rdev
->pdev
->subsystem_vendor
== p
->subsys_vendor
&&
2949 rdev
->pdev
->subsystem_device
== p
->subsys_device
) {
2950 max_sclk
= p
->max_sclk
;
2951 max_mclk
= p
->max_mclk
;
2957 if ((rdev
->pm
.dpm
.new_active_crtc_count
> 1) ||
2958 ni_dpm_vblank_too_short(rdev
))
2959 disable_mclk_switching
= true;
2961 if (rps
->vclk
|| rps
->dclk
) {
2962 disable_mclk_switching
= true;
2963 disable_sclk_switching
= true;
2966 if (rdev
->pm
.dpm
.ac_power
)
2967 max_limits
= &rdev
->pm
.dpm
.dyn_state
.max_clock_voltage_on_ac
;
2969 max_limits
= &rdev
->pm
.dpm
.dyn_state
.max_clock_voltage_on_dc
;
2971 for (i
= ps
->performance_level_count
- 2; i
>= 0; i
--) {
2972 if (ps
->performance_levels
[i
].vddc
> ps
->performance_levels
[i
+1].vddc
)
2973 ps
->performance_levels
[i
].vddc
= ps
->performance_levels
[i
+1].vddc
;
2975 if (rdev
->pm
.dpm
.ac_power
== false) {
2976 for (i
= 0; i
< ps
->performance_level_count
; i
++) {
2977 if (ps
->performance_levels
[i
].mclk
> max_limits
->mclk
)
2978 ps
->performance_levels
[i
].mclk
= max_limits
->mclk
;
2979 if (ps
->performance_levels
[i
].sclk
> max_limits
->sclk
)
2980 ps
->performance_levels
[i
].sclk
= max_limits
->sclk
;
2981 if (ps
->performance_levels
[i
].vddc
> max_limits
->vddc
)
2982 ps
->performance_levels
[i
].vddc
= max_limits
->vddc
;
2983 if (ps
->performance_levels
[i
].vddci
> max_limits
->vddci
)
2984 ps
->performance_levels
[i
].vddci
= max_limits
->vddci
;
2988 /* limit clocks to max supported clocks based on voltage dependency tables */
2989 btc_get_max_clock_from_voltage_dependency_table(&rdev
->pm
.dpm
.dyn_state
.vddc_dependency_on_sclk
,
2991 btc_get_max_clock_from_voltage_dependency_table(&rdev
->pm
.dpm
.dyn_state
.vddci_dependency_on_mclk
,
2993 btc_get_max_clock_from_voltage_dependency_table(&rdev
->pm
.dpm
.dyn_state
.vddc_dependency_on_mclk
,
2996 for (i
= 0; i
< ps
->performance_level_count
; i
++) {
2997 if (max_sclk_vddc
) {
2998 if (ps
->performance_levels
[i
].sclk
> max_sclk_vddc
)
2999 ps
->performance_levels
[i
].sclk
= max_sclk_vddc
;
3001 if (max_mclk_vddci
) {
3002 if (ps
->performance_levels
[i
].mclk
> max_mclk_vddci
)
3003 ps
->performance_levels
[i
].mclk
= max_mclk_vddci
;
3005 if (max_mclk_vddc
) {
3006 if (ps
->performance_levels
[i
].mclk
> max_mclk_vddc
)
3007 ps
->performance_levels
[i
].mclk
= max_mclk_vddc
;
3010 if (ps
->performance_levels
[i
].mclk
> max_mclk
)
3011 ps
->performance_levels
[i
].mclk
= max_mclk
;
3014 if (ps
->performance_levels
[i
].sclk
> max_sclk
)
3015 ps
->performance_levels
[i
].sclk
= max_sclk
;
3019 /* XXX validate the min clocks required for display */
3021 if (disable_mclk_switching
) {
3022 mclk
= ps
->performance_levels
[ps
->performance_level_count
- 1].mclk
;
3023 vddci
= ps
->performance_levels
[ps
->performance_level_count
- 1].vddci
;
3025 mclk
= ps
->performance_levels
[0].mclk
;
3026 vddci
= ps
->performance_levels
[0].vddci
;
3029 if (disable_sclk_switching
) {
3030 sclk
= ps
->performance_levels
[ps
->performance_level_count
- 1].sclk
;
3031 vddc
= ps
->performance_levels
[ps
->performance_level_count
- 1].vddc
;
3033 sclk
= ps
->performance_levels
[0].sclk
;
3034 vddc
= ps
->performance_levels
[0].vddc
;
3037 /* adjusted low state */
3038 ps
->performance_levels
[0].sclk
= sclk
;
3039 ps
->performance_levels
[0].mclk
= mclk
;
3040 ps
->performance_levels
[0].vddc
= vddc
;
3041 ps
->performance_levels
[0].vddci
= vddci
;
3043 if (disable_sclk_switching
) {
3044 sclk
= ps
->performance_levels
[0].sclk
;
3045 for (i
= 1; i
< ps
->performance_level_count
; i
++) {
3046 if (sclk
< ps
->performance_levels
[i
].sclk
)
3047 sclk
= ps
->performance_levels
[i
].sclk
;
3049 for (i
= 0; i
< ps
->performance_level_count
; i
++) {
3050 ps
->performance_levels
[i
].sclk
= sclk
;
3051 ps
->performance_levels
[i
].vddc
= vddc
;
3054 for (i
= 1; i
< ps
->performance_level_count
; i
++) {
3055 if (ps
->performance_levels
[i
].sclk
< ps
->performance_levels
[i
- 1].sclk
)
3056 ps
->performance_levels
[i
].sclk
= ps
->performance_levels
[i
- 1].sclk
;
3057 if (ps
->performance_levels
[i
].vddc
< ps
->performance_levels
[i
- 1].vddc
)
3058 ps
->performance_levels
[i
].vddc
= ps
->performance_levels
[i
- 1].vddc
;
3062 if (disable_mclk_switching
) {
3063 mclk
= ps
->performance_levels
[0].mclk
;
3064 for (i
= 1; i
< ps
->performance_level_count
; i
++) {
3065 if (mclk
< ps
->performance_levels
[i
].mclk
)
3066 mclk
= ps
->performance_levels
[i
].mclk
;
3068 for (i
= 0; i
< ps
->performance_level_count
; i
++) {
3069 ps
->performance_levels
[i
].mclk
= mclk
;
3070 ps
->performance_levels
[i
].vddci
= vddci
;
3073 for (i
= 1; i
< ps
->performance_level_count
; i
++) {
3074 if (ps
->performance_levels
[i
].mclk
< ps
->performance_levels
[i
- 1].mclk
)
3075 ps
->performance_levels
[i
].mclk
= ps
->performance_levels
[i
- 1].mclk
;
3076 if (ps
->performance_levels
[i
].vddci
< ps
->performance_levels
[i
- 1].vddci
)
3077 ps
->performance_levels
[i
].vddci
= ps
->performance_levels
[i
- 1].vddci
;
3081 for (i
= 0; i
< ps
->performance_level_count
; i
++)
3082 btc_adjust_clock_combinations(rdev
, max_limits
,
3083 &ps
->performance_levels
[i
]);
3085 for (i
= 0; i
< ps
->performance_level_count
; i
++) {
3086 btc_apply_voltage_dependency_rules(&rdev
->pm
.dpm
.dyn_state
.vddc_dependency_on_sclk
,
3087 ps
->performance_levels
[i
].sclk
,
3088 max_limits
->vddc
, &ps
->performance_levels
[i
].vddc
);
3089 btc_apply_voltage_dependency_rules(&rdev
->pm
.dpm
.dyn_state
.vddci_dependency_on_mclk
,
3090 ps
->performance_levels
[i
].mclk
,
3091 max_limits
->vddci
, &ps
->performance_levels
[i
].vddci
);
3092 btc_apply_voltage_dependency_rules(&rdev
->pm
.dpm
.dyn_state
.vddc_dependency_on_mclk
,
3093 ps
->performance_levels
[i
].mclk
,
3094 max_limits
->vddc
, &ps
->performance_levels
[i
].vddc
);
3095 btc_apply_voltage_dependency_rules(&rdev
->pm
.dpm
.dyn_state
.vddc_dependency_on_dispclk
,
3096 rdev
->clock
.current_dispclk
,
3097 max_limits
->vddc
, &ps
->performance_levels
[i
].vddc
);
3100 for (i
= 0; i
< ps
->performance_level_count
; i
++) {
3101 btc_apply_voltage_delta_rules(rdev
,
3102 max_limits
->vddc
, max_limits
->vddci
,
3103 &ps
->performance_levels
[i
].vddc
,
3104 &ps
->performance_levels
[i
].vddci
);
3107 ps
->dc_compatible
= true;
3108 for (i
= 0; i
< ps
->performance_level_count
; i
++) {
3109 if (ps
->performance_levels
[i
].vddc
> rdev
->pm
.dpm
.dyn_state
.max_clock_voltage_on_dc
.vddc
)
3110 ps
->dc_compatible
= false;
3116 static int si_read_smc_soft_register(struct radeon_device
*rdev
,
3117 u16 reg_offset
, u32
*value
)
3119 struct si_power_info
*si_pi
= si_get_pi(rdev
);
3121 return si_read_smc_sram_dword(rdev
,
3122 si_pi
->soft_regs_start
+ reg_offset
, value
,
3127 static int si_write_smc_soft_register(struct radeon_device
*rdev
,
3128 u16 reg_offset
, u32 value
)
3130 struct si_power_info
*si_pi
= si_get_pi(rdev
);
3132 return si_write_smc_sram_dword(rdev
,
3133 si_pi
->soft_regs_start
+ reg_offset
,
3134 value
, si_pi
->sram_end
);
3137 static bool si_is_special_1gb_platform(struct radeon_device
*rdev
)
3140 u32 tmp
, width
, row
, column
, bank
, density
;
3141 bool is_memory_gddr5
, is_special
;
3143 tmp
= RREG32(MC_SEQ_MISC0
);
3144 is_memory_gddr5
= (MC_SEQ_MISC0_GDDR5_VALUE
== ((tmp
& MC_SEQ_MISC0_GDDR5_MASK
) >> MC_SEQ_MISC0_GDDR5_SHIFT
));
3145 is_special
= (MC_SEQ_MISC0_REV_ID_VALUE
== ((tmp
& MC_SEQ_MISC0_REV_ID_MASK
) >> MC_SEQ_MISC0_REV_ID_SHIFT
))
3146 & (MC_SEQ_MISC0_VEN_ID_VALUE
== ((tmp
& MC_SEQ_MISC0_VEN_ID_MASK
) >> MC_SEQ_MISC0_VEN_ID_SHIFT
));
3148 WREG32(MC_SEQ_IO_DEBUG_INDEX
, 0xb);
3149 width
= ((RREG32(MC_SEQ_IO_DEBUG_DATA
) >> 1) & 1) ? 16 : 32;
3151 tmp
= RREG32(MC_ARB_RAMCFG
);
3152 row
= ((tmp
& NOOFROWS_MASK
) >> NOOFROWS_SHIFT
) + 10;
3153 column
= ((tmp
& NOOFCOLS_MASK
) >> NOOFCOLS_SHIFT
) + 8;
3154 bank
= ((tmp
& NOOFBANK_MASK
) >> NOOFBANK_SHIFT
) + 2;
3156 density
= (1 << (row
+ column
- 20 + bank
)) * width
;
3158 if ((rdev
->pdev
->device
== 0x6819) &&
3159 is_memory_gddr5
&& is_special
&& (density
== 0x400))
3165 static void si_get_leakage_vddc(struct radeon_device
*rdev
)
3167 struct si_power_info
*si_pi
= si_get_pi(rdev
);
3168 u16 vddc
, count
= 0;
3171 for (i
= 0; i
< SISLANDS_MAX_LEAKAGE_COUNT
; i
++) {
3172 ret
= radeon_atom_get_leakage_vddc_based_on_leakage_idx(rdev
, &vddc
, SISLANDS_LEAKAGE_INDEX0
+ i
);
3174 if (!ret
&& (vddc
> 0) && (vddc
!= (SISLANDS_LEAKAGE_INDEX0
+ i
))) {
3175 si_pi
->leakage_voltage
.entries
[count
].voltage
= vddc
;
3176 si_pi
->leakage_voltage
.entries
[count
].leakage_index
=
3177 SISLANDS_LEAKAGE_INDEX0
+ i
;
3181 si_pi
->leakage_voltage
.count
= count
;
3184 static int si_get_leakage_voltage_from_leakage_index(struct radeon_device
*rdev
,
3185 u32 index
, u16
*leakage_voltage
)
3187 struct si_power_info
*si_pi
= si_get_pi(rdev
);
3190 if (leakage_voltage
== NULL
)
3193 if ((index
& 0xff00) != 0xff00)
3196 if ((index
& 0xff) > SISLANDS_MAX_LEAKAGE_COUNT
+ 1)
3199 if (index
< SISLANDS_LEAKAGE_INDEX0
)
3202 for (i
= 0; i
< si_pi
->leakage_voltage
.count
; i
++) {
3203 if (si_pi
->leakage_voltage
.entries
[i
].leakage_index
== index
) {
3204 *leakage_voltage
= si_pi
->leakage_voltage
.entries
[i
].voltage
;
3211 static void si_set_dpm_event_sources(struct radeon_device
*rdev
, u32 sources
)
3213 struct rv7xx_power_info
*pi
= rv770_get_pi(rdev
);
3214 bool want_thermal_protection
;
3215 enum radeon_dpm_event_src dpm_event_src
;
3220 want_thermal_protection
= false;
3222 case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL
):
3223 want_thermal_protection
= true;
3224 dpm_event_src
= RADEON_DPM_EVENT_SRC_DIGITAL
;
3226 case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL
):
3227 want_thermal_protection
= true;
3228 dpm_event_src
= RADEON_DPM_EVENT_SRC_EXTERNAL
;
3230 case ((1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL
) |
3231 (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL
)):
3232 want_thermal_protection
= true;
3233 dpm_event_src
= RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL
;
3237 if (want_thermal_protection
) {
3238 WREG32_P(CG_THERMAL_CTRL
, DPM_EVENT_SRC(dpm_event_src
), ~DPM_EVENT_SRC_MASK
);
3239 if (pi
->thermal_protection
)
3240 WREG32_P(GENERAL_PWRMGT
, 0, ~THERMAL_PROTECTION_DIS
);
3242 WREG32_P(GENERAL_PWRMGT
, THERMAL_PROTECTION_DIS
, ~THERMAL_PROTECTION_DIS
);
3246 static void si_enable_auto_throttle_source(struct radeon_device
*rdev
,
3247 enum radeon_dpm_auto_throttle_src source
,
3250 struct rv7xx_power_info
*pi
= rv770_get_pi(rdev
);
3253 if (!(pi
->active_auto_throttle_sources
& (1 << source
))) {
3254 pi
->active_auto_throttle_sources
|= 1 << source
;
3255 si_set_dpm_event_sources(rdev
, pi
->active_auto_throttle_sources
);
3258 if (pi
->active_auto_throttle_sources
& (1 << source
)) {
3259 pi
->active_auto_throttle_sources
&= ~(1 << source
);
3260 si_set_dpm_event_sources(rdev
, pi
->active_auto_throttle_sources
);
3265 static void si_start_dpm(struct radeon_device
*rdev
)
3267 WREG32_P(GENERAL_PWRMGT
, GLOBAL_PWRMGT_EN
, ~GLOBAL_PWRMGT_EN
);
3270 static void si_stop_dpm(struct radeon_device
*rdev
)
3272 WREG32_P(GENERAL_PWRMGT
, 0, ~GLOBAL_PWRMGT_EN
);
3275 static void si_enable_sclk_control(struct radeon_device
*rdev
, bool enable
)
3278 WREG32_P(SCLK_PWRMGT_CNTL
, 0, ~SCLK_PWRMGT_OFF
);
3280 WREG32_P(SCLK_PWRMGT_CNTL
, SCLK_PWRMGT_OFF
, ~SCLK_PWRMGT_OFF
);
3285 static int si_notify_hardware_of_thermal_state(struct radeon_device
*rdev
,
3290 if (thermal_level
== 0) {
3291 ret
= si_send_msg_to_smc(rdev
, PPSMC_MSG_EnableThermalInterrupt
);
3292 if (ret
== PPSMC_Result_OK
)
3300 static void si_notify_hardware_vpu_recovery_event(struct radeon_device
*rdev
)
3302 si_write_smc_soft_register(rdev
, SI_SMC_SOFT_REGISTER_tdr_is_about_to_happen
, true);
3307 static int si_notify_hw_of_powersource(struct radeon_device
*rdev
, bool ac_power
)
3310 return (si_send_msg_to_smc(rdev
, PPSMC_MSG_RunningOnAC
) == PPSMC_Result_OK
) ?
3317 static PPSMC_Result
si_send_msg_to_smc_with_parameter(struct radeon_device
*rdev
,
3318 PPSMC_Msg msg
, u32 parameter
)
3320 WREG32(SMC_SCRATCH0
, parameter
);
3321 return si_send_msg_to_smc(rdev
, msg
);
3324 static int si_restrict_performance_levels_before_switch(struct radeon_device
*rdev
)
3326 if (si_send_msg_to_smc(rdev
, PPSMC_MSG_NoForcedLevel
) != PPSMC_Result_OK
)
3329 return (si_send_msg_to_smc_with_parameter(rdev
, PPSMC_MSG_SetEnabledLevels
, 1) == PPSMC_Result_OK
) ?
3333 int si_dpm_force_performance_level(struct radeon_device
*rdev
,
3334 enum radeon_dpm_forced_level level
)
3336 struct radeon_ps
*rps
= rdev
->pm
.dpm
.current_ps
;
3337 struct ni_ps
*ps
= ni_get_ps(rps
);
3338 u32 levels
= ps
->performance_level_count
;
3340 if (level
== RADEON_DPM_FORCED_LEVEL_HIGH
) {
3341 if (si_send_msg_to_smc_with_parameter(rdev
, PPSMC_MSG_SetEnabledLevels
, levels
) != PPSMC_Result_OK
)
3344 if (si_send_msg_to_smc_with_parameter(rdev
, PPSMC_MSG_SetForcedLevels
, 1) != PPSMC_Result_OK
)
3346 } else if (level
== RADEON_DPM_FORCED_LEVEL_LOW
) {
3347 if (si_send_msg_to_smc_with_parameter(rdev
, PPSMC_MSG_SetForcedLevels
, 0) != PPSMC_Result_OK
)
3350 if (si_send_msg_to_smc_with_parameter(rdev
, PPSMC_MSG_SetEnabledLevels
, 1) != PPSMC_Result_OK
)
3352 } else if (level
== RADEON_DPM_FORCED_LEVEL_AUTO
) {
3353 if (si_send_msg_to_smc_with_parameter(rdev
, PPSMC_MSG_SetForcedLevels
, 0) != PPSMC_Result_OK
)
3356 if (si_send_msg_to_smc_with_parameter(rdev
, PPSMC_MSG_SetEnabledLevels
, levels
) != PPSMC_Result_OK
)
3360 rdev
->pm
.dpm
.forced_level
= level
;
3365 static int si_set_boot_state(struct radeon_device
*rdev
)
3367 return (si_send_msg_to_smc(rdev
, PPSMC_MSG_SwitchToInitialState
) == PPSMC_Result_OK
) ?
3371 static int si_set_sw_state(struct radeon_device
*rdev
)
3373 return (si_send_msg_to_smc(rdev
, PPSMC_MSG_SwitchToSwState
) == PPSMC_Result_OK
) ?
3377 static int si_halt_smc(struct radeon_device
*rdev
)
3379 if (si_send_msg_to_smc(rdev
, PPSMC_MSG_Halt
) != PPSMC_Result_OK
)
3382 return (si_wait_for_smc_inactive(rdev
) == PPSMC_Result_OK
) ?
3386 static int si_resume_smc(struct radeon_device
*rdev
)
3388 if (si_send_msg_to_smc(rdev
, PPSMC_FlushDataCache
) != PPSMC_Result_OK
)
3391 return (si_send_msg_to_smc(rdev
, PPSMC_MSG_Resume
) == PPSMC_Result_OK
) ?
3395 static void si_dpm_start_smc(struct radeon_device
*rdev
)
3397 si_program_jump_on_start(rdev
);
3399 si_start_smc_clock(rdev
);
3402 static void si_dpm_stop_smc(struct radeon_device
*rdev
)
3405 si_stop_smc_clock(rdev
);
3408 static int si_process_firmware_header(struct radeon_device
*rdev
)
3410 struct si_power_info
*si_pi
= si_get_pi(rdev
);
3414 ret
= si_read_smc_sram_dword(rdev
,
3415 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION
+
3416 SISLANDS_SMC_FIRMWARE_HEADER_stateTable
,
3417 &tmp
, si_pi
->sram_end
);
3421 si_pi
->state_table_start
= tmp
;
3423 ret
= si_read_smc_sram_dword(rdev
,
3424 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION
+
3425 SISLANDS_SMC_FIRMWARE_HEADER_softRegisters
,
3426 &tmp
, si_pi
->sram_end
);
3430 si_pi
->soft_regs_start
= tmp
;
3432 ret
= si_read_smc_sram_dword(rdev
,
3433 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION
+
3434 SISLANDS_SMC_FIRMWARE_HEADER_mcRegisterTable
,
3435 &tmp
, si_pi
->sram_end
);
3439 si_pi
->mc_reg_table_start
= tmp
;
3441 ret
= si_read_smc_sram_dword(rdev
,
3442 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION
+
3443 SISLANDS_SMC_FIRMWARE_HEADER_fanTable
,
3444 &tmp
, si_pi
->sram_end
);
3448 si_pi
->fan_table_start
= tmp
;
3450 ret
= si_read_smc_sram_dword(rdev
,
3451 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION
+
3452 SISLANDS_SMC_FIRMWARE_HEADER_mcArbDramAutoRefreshTable
,
3453 &tmp
, si_pi
->sram_end
);
3457 si_pi
->arb_table_start
= tmp
;
3459 ret
= si_read_smc_sram_dword(rdev
,
3460 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION
+
3461 SISLANDS_SMC_FIRMWARE_HEADER_CacConfigTable
,
3462 &tmp
, si_pi
->sram_end
);
3466 si_pi
->cac_table_start
= tmp
;
3468 ret
= si_read_smc_sram_dword(rdev
,
3469 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION
+
3470 SISLANDS_SMC_FIRMWARE_HEADER_DteConfiguration
,
3471 &tmp
, si_pi
->sram_end
);
3475 si_pi
->dte_table_start
= tmp
;
3477 ret
= si_read_smc_sram_dword(rdev
,
3478 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION
+
3479 SISLANDS_SMC_FIRMWARE_HEADER_spllTable
,
3480 &tmp
, si_pi
->sram_end
);
3484 si_pi
->spll_table_start
= tmp
;
3486 ret
= si_read_smc_sram_dword(rdev
,
3487 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION
+
3488 SISLANDS_SMC_FIRMWARE_HEADER_PAPMParameters
,
3489 &tmp
, si_pi
->sram_end
);
3493 si_pi
->papm_cfg_table_start
= tmp
;
3498 static void si_read_clock_registers(struct radeon_device
*rdev
)
3500 struct si_power_info
*si_pi
= si_get_pi(rdev
);
3502 si_pi
->clock_registers
.cg_spll_func_cntl
= RREG32(CG_SPLL_FUNC_CNTL
);
3503 si_pi
->clock_registers
.cg_spll_func_cntl_2
= RREG32(CG_SPLL_FUNC_CNTL_2
);
3504 si_pi
->clock_registers
.cg_spll_func_cntl_3
= RREG32(CG_SPLL_FUNC_CNTL_3
);
3505 si_pi
->clock_registers
.cg_spll_func_cntl_4
= RREG32(CG_SPLL_FUNC_CNTL_4
);
3506 si_pi
->clock_registers
.cg_spll_spread_spectrum
= RREG32(CG_SPLL_SPREAD_SPECTRUM
);
3507 si_pi
->clock_registers
.cg_spll_spread_spectrum_2
= RREG32(CG_SPLL_SPREAD_SPECTRUM_2
);
3508 si_pi
->clock_registers
.dll_cntl
= RREG32(DLL_CNTL
);
3509 si_pi
->clock_registers
.mclk_pwrmgt_cntl
= RREG32(MCLK_PWRMGT_CNTL
);
3510 si_pi
->clock_registers
.mpll_ad_func_cntl
= RREG32(MPLL_AD_FUNC_CNTL
);
3511 si_pi
->clock_registers
.mpll_dq_func_cntl
= RREG32(MPLL_DQ_FUNC_CNTL
);
3512 si_pi
->clock_registers
.mpll_func_cntl
= RREG32(MPLL_FUNC_CNTL
);
3513 si_pi
->clock_registers
.mpll_func_cntl_1
= RREG32(MPLL_FUNC_CNTL_1
);
3514 si_pi
->clock_registers
.mpll_func_cntl_2
= RREG32(MPLL_FUNC_CNTL_2
);
3515 si_pi
->clock_registers
.mpll_ss1
= RREG32(MPLL_SS1
);
3516 si_pi
->clock_registers
.mpll_ss2
= RREG32(MPLL_SS2
);
3519 static void si_enable_thermal_protection(struct radeon_device
*rdev
,
3523 WREG32_P(GENERAL_PWRMGT
, 0, ~THERMAL_PROTECTION_DIS
);
3525 WREG32_P(GENERAL_PWRMGT
, THERMAL_PROTECTION_DIS
, ~THERMAL_PROTECTION_DIS
);
3528 static void si_enable_acpi_power_management(struct radeon_device
*rdev
)
3530 WREG32_P(GENERAL_PWRMGT
, STATIC_PM_EN
, ~STATIC_PM_EN
);
3534 static int si_enter_ulp_state(struct radeon_device
*rdev
)
3536 WREG32(SMC_MESSAGE_0
, PPSMC_MSG_SwitchToMinimumPower
);
3543 static int si_exit_ulp_state(struct radeon_device
*rdev
)
3547 WREG32(SMC_MESSAGE_0
, PPSMC_MSG_ResumeFromMinimumPower
);
3551 for (i
= 0; i
< rdev
->usec_timeout
; i
++) {
3552 if (RREG32(SMC_RESP_0
) == 1)
3561 static int si_notify_smc_display_change(struct radeon_device
*rdev
,
3564 PPSMC_Msg msg
= has_display
?
3565 PPSMC_MSG_HasDisplay
: PPSMC_MSG_NoDisplay
;
3567 return (si_send_msg_to_smc(rdev
, msg
) == PPSMC_Result_OK
) ?
3571 static void si_program_response_times(struct radeon_device
*rdev
)
3573 u32 voltage_response_time
, backbias_response_time
, acpi_delay_time
, vbi_time_out
;
3574 u32 vddc_dly
, acpi_dly
, vbi_dly
;
3575 u32 reference_clock
;
3577 si_write_smc_soft_register(rdev
, SI_SMC_SOFT_REGISTER_mvdd_chg_time
, 1);
3579 voltage_response_time
= (u32
)rdev
->pm
.dpm
.voltage_response_time
;
3580 backbias_response_time
= (u32
)rdev
->pm
.dpm
.backbias_response_time
;
3582 if (voltage_response_time
== 0)
3583 voltage_response_time
= 1000;
3585 acpi_delay_time
= 15000;
3586 vbi_time_out
= 100000;
3588 reference_clock
= radeon_get_xclk(rdev
);
3590 vddc_dly
= (voltage_response_time
* reference_clock
) / 100;
3591 acpi_dly
= (acpi_delay_time
* reference_clock
) / 100;
3592 vbi_dly
= (vbi_time_out
* reference_clock
) / 100;
3594 si_write_smc_soft_register(rdev
, SI_SMC_SOFT_REGISTER_delay_vreg
, vddc_dly
);
3595 si_write_smc_soft_register(rdev
, SI_SMC_SOFT_REGISTER_delay_acpi
, acpi_dly
);
3596 si_write_smc_soft_register(rdev
, SI_SMC_SOFT_REGISTER_mclk_chg_timeout
, vbi_dly
);
3597 si_write_smc_soft_register(rdev
, SI_SMC_SOFT_REGISTER_mc_block_delay
, 0xAA);
3600 static void si_program_ds_registers(struct radeon_device
*rdev
)
3602 struct evergreen_power_info
*eg_pi
= evergreen_get_pi(rdev
);
3603 u32 tmp
= 1; /* XXX: 0x10 on tahiti A0 */
3605 if (eg_pi
->sclk_deep_sleep
) {
3606 WREG32_P(MISC_CLK_CNTL
, DEEP_SLEEP_CLK_SEL(tmp
), ~DEEP_SLEEP_CLK_SEL_MASK
);
3607 WREG32_P(CG_SPLL_AUTOSCALE_CNTL
, AUTOSCALE_ON_SS_CLEAR
,
3608 ~AUTOSCALE_ON_SS_CLEAR
);
3612 static void si_program_display_gap(struct radeon_device
*rdev
)
3617 tmp
= RREG32(CG_DISPLAY_GAP_CNTL
) & ~(DISP1_GAP_MASK
| DISP2_GAP_MASK
);
3618 if (rdev
->pm
.dpm
.new_active_crtc_count
> 0)
3619 tmp
|= DISP1_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM
);
3621 tmp
|= DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE
);
3623 if (rdev
->pm
.dpm
.new_active_crtc_count
> 1)
3624 tmp
|= DISP2_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM
);
3626 tmp
|= DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE
);
3628 WREG32(CG_DISPLAY_GAP_CNTL
, tmp
);
3630 tmp
= RREG32(DCCG_DISP_SLOW_SELECT_REG
);
3631 pipe
= (tmp
& DCCG_DISP1_SLOW_SELECT_MASK
) >> DCCG_DISP1_SLOW_SELECT_SHIFT
;
3633 if ((rdev
->pm
.dpm
.new_active_crtc_count
> 0) &&
3634 (!(rdev
->pm
.dpm
.new_active_crtcs
& (1 << pipe
)))) {
3635 /* find the first active crtc */
3636 for (i
= 0; i
< rdev
->num_crtc
; i
++) {
3637 if (rdev
->pm
.dpm
.new_active_crtcs
& (1 << i
))
3640 if (i
== rdev
->num_crtc
)
3645 tmp
&= ~DCCG_DISP1_SLOW_SELECT_MASK
;
3646 tmp
|= DCCG_DISP1_SLOW_SELECT(pipe
);
3647 WREG32(DCCG_DISP_SLOW_SELECT_REG
, tmp
);
3650 /* Setting this to false forces the performance state to low if the crtcs are disabled.
3651 * This can be a problem on PowerXpress systems or if you want to use the card
3652 * for offscreen rendering or compute if there are no crtcs enabled.
3654 si_notify_smc_display_change(rdev
, rdev
->pm
.dpm
.new_active_crtc_count
> 0);
3657 static void si_enable_spread_spectrum(struct radeon_device
*rdev
, bool enable
)
3659 struct rv7xx_power_info
*pi
= rv770_get_pi(rdev
);
3663 WREG32_P(GENERAL_PWRMGT
, DYN_SPREAD_SPECTRUM_EN
, ~DYN_SPREAD_SPECTRUM_EN
);
3665 WREG32_P(CG_SPLL_SPREAD_SPECTRUM
, 0, ~SSEN
);
3666 WREG32_P(GENERAL_PWRMGT
, 0, ~DYN_SPREAD_SPECTRUM_EN
);
3670 static void si_setup_bsp(struct radeon_device
*rdev
)
3672 struct rv7xx_power_info
*pi
= rv770_get_pi(rdev
);
3673 u32 xclk
= radeon_get_xclk(rdev
);
3675 r600_calculate_u_and_p(pi
->asi
,
3681 r600_calculate_u_and_p(pi
->pasi
,
3688 pi
->dsp
= BSP(pi
->bsp
) | BSU(pi
->bsu
);
3689 pi
->psp
= BSP(pi
->pbsp
) | BSU(pi
->pbsu
);
3691 WREG32(CG_BSP
, pi
->dsp
);
3694 static void si_program_git(struct radeon_device
*rdev
)
3696 WREG32_P(CG_GIT
, CG_GICST(R600_GICST_DFLT
), ~CG_GICST_MASK
);
3699 static void si_program_tp(struct radeon_device
*rdev
)
3702 enum r600_td td
= R600_TD_DFLT
;
3704 for (i
= 0; i
< R600_PM_NUMBER_OF_TC
; i
++)
3705 WREG32(CG_FFCT_0
+ (i
* 4), (UTC_0(r600_utc
[i
]) | DTC_0(r600_dtc
[i
])));
3707 if (td
== R600_TD_AUTO
)
3708 WREG32_P(SCLK_PWRMGT_CNTL
, 0, ~FIR_FORCE_TREND_SEL
);
3710 WREG32_P(SCLK_PWRMGT_CNTL
, FIR_FORCE_TREND_SEL
, ~FIR_FORCE_TREND_SEL
);
3712 if (td
== R600_TD_UP
)
3713 WREG32_P(SCLK_PWRMGT_CNTL
, 0, ~FIR_TREND_MODE
);
3715 if (td
== R600_TD_DOWN
)
3716 WREG32_P(SCLK_PWRMGT_CNTL
, FIR_TREND_MODE
, ~FIR_TREND_MODE
);
3719 static void si_program_tpp(struct radeon_device
*rdev
)
3721 WREG32(CG_TPC
, R600_TPC_DFLT
);
3724 static void si_program_sstp(struct radeon_device
*rdev
)
3726 WREG32(CG_SSP
, (SSTU(R600_SSTU_DFLT
) | SST(R600_SST_DFLT
)));
3729 static void si_enable_display_gap(struct radeon_device
*rdev
)
3731 u32 tmp
= RREG32(CG_DISPLAY_GAP_CNTL
);
3733 tmp
&= ~(DISP1_GAP_MASK
| DISP2_GAP_MASK
);
3734 tmp
|= (DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE
) |
3735 DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE
));
3737 tmp
&= ~(DISP1_GAP_MCHG_MASK
| DISP2_GAP_MCHG_MASK
);
3738 tmp
|= (DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK
) |
3739 DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE
));
3740 WREG32(CG_DISPLAY_GAP_CNTL
, tmp
);
3743 static void si_program_vc(struct radeon_device
*rdev
)
3745 struct rv7xx_power_info
*pi
= rv770_get_pi(rdev
);
3747 WREG32(CG_FTV
, pi
->vrc
);
3750 static void si_clear_vc(struct radeon_device
*rdev
)
3755 u8
si_get_ddr3_mclk_frequency_ratio(u32 memory_clock
)
3759 if (memory_clock
< 10000)
3761 else if (memory_clock
>= 80000)
3762 mc_para_index
= 0x0f;
3764 mc_para_index
= (u8
)((memory_clock
- 10000) / 5000 + 1);
3765 return mc_para_index
;
3768 u8
si_get_mclk_frequency_ratio(u32 memory_clock
, bool strobe_mode
)
3773 if (memory_clock
< 12500)
3774 mc_para_index
= 0x00;
3775 else if (memory_clock
> 47500)
3776 mc_para_index
= 0x0f;
3778 mc_para_index
= (u8
)((memory_clock
- 10000) / 2500);
3780 if (memory_clock
< 65000)
3781 mc_para_index
= 0x00;
3782 else if (memory_clock
> 135000)
3783 mc_para_index
= 0x0f;
3785 mc_para_index
= (u8
)((memory_clock
- 60000) / 5000);
3787 return mc_para_index
;
3790 static u8
si_get_strobe_mode_settings(struct radeon_device
*rdev
, u32 mclk
)
3792 struct rv7xx_power_info
*pi
= rv770_get_pi(rdev
);
3793 bool strobe_mode
= false;
3796 if (mclk
<= pi
->mclk_strobe_mode_threshold
)
3800 result
= si_get_mclk_frequency_ratio(mclk
, strobe_mode
);
3802 result
= si_get_ddr3_mclk_frequency_ratio(mclk
);
3805 result
|= SISLANDS_SMC_STROBE_ENABLE
;
3810 static int si_upload_firmware(struct radeon_device
*rdev
)
3812 struct si_power_info
*si_pi
= si_get_pi(rdev
);
3816 si_stop_smc_clock(rdev
);
3818 ret
= si_load_smc_ucode(rdev
, si_pi
->sram_end
);
3823 static bool si_validate_phase_shedding_tables(struct radeon_device
*rdev
,
3824 const struct atom_voltage_table
*table
,
3825 const struct radeon_phase_shedding_limits_table
*limits
)
3827 u32 data
, num_bits
, num_levels
;
3829 if ((table
== NULL
) || (limits
== NULL
))
3832 data
= table
->mask_low
;
3834 num_bits
= hweight32(data
);
3839 num_levels
= (1 << num_bits
);
3841 if (table
->count
!= num_levels
)
3844 if (limits
->count
!= (num_levels
- 1))
3850 void si_trim_voltage_table_to_fit_state_table(struct radeon_device
*rdev
,
3851 u32 max_voltage_steps
,
3852 struct atom_voltage_table
*voltage_table
)
3854 unsigned int i
, diff
;
3856 if (voltage_table
->count
<= max_voltage_steps
)
3859 diff
= voltage_table
->count
- max_voltage_steps
;
3861 for (i
= 0; i
< max_voltage_steps
; i
++)
3862 voltage_table
->entries
[i
] = voltage_table
->entries
[i
+ diff
];
3864 voltage_table
->count
= max_voltage_steps
;
3867 static int si_get_svi2_voltage_table(struct radeon_device
*rdev
,
3868 struct radeon_clock_voltage_dependency_table
*voltage_dependency_table
,
3869 struct atom_voltage_table
*voltage_table
)
3873 if (voltage_dependency_table
== NULL
)
3876 voltage_table
->mask_low
= 0;
3877 voltage_table
->phase_delay
= 0;
3879 voltage_table
->count
= voltage_dependency_table
->count
;
3880 for (i
= 0; i
< voltage_table
->count
; i
++) {
3881 voltage_table
->entries
[i
].value
= voltage_dependency_table
->entries
[i
].v
;
3882 voltage_table
->entries
[i
].smio_low
= 0;
3888 static int si_construct_voltage_tables(struct radeon_device
*rdev
)
3890 struct rv7xx_power_info
*pi
= rv770_get_pi(rdev
);
3891 struct evergreen_power_info
*eg_pi
= evergreen_get_pi(rdev
);
3892 struct si_power_info
*si_pi
= si_get_pi(rdev
);
3895 if (pi
->voltage_control
) {
3896 ret
= radeon_atom_get_voltage_table(rdev
, VOLTAGE_TYPE_VDDC
,
3897 VOLTAGE_OBJ_GPIO_LUT
, &eg_pi
->vddc_voltage_table
);
3901 if (eg_pi
->vddc_voltage_table
.count
> SISLANDS_MAX_NO_VREG_STEPS
)
3902 si_trim_voltage_table_to_fit_state_table(rdev
,
3903 SISLANDS_MAX_NO_VREG_STEPS
,
3904 &eg_pi
->vddc_voltage_table
);
3905 } else if (si_pi
->voltage_control_svi2
) {
3906 ret
= si_get_svi2_voltage_table(rdev
,
3907 &rdev
->pm
.dpm
.dyn_state
.vddc_dependency_on_mclk
,
3908 &eg_pi
->vddc_voltage_table
);
3915 if (eg_pi
->vddci_control
) {
3916 ret
= radeon_atom_get_voltage_table(rdev
, VOLTAGE_TYPE_VDDCI
,
3917 VOLTAGE_OBJ_GPIO_LUT
, &eg_pi
->vddci_voltage_table
);
3921 if (eg_pi
->vddci_voltage_table
.count
> SISLANDS_MAX_NO_VREG_STEPS
)
3922 si_trim_voltage_table_to_fit_state_table(rdev
,
3923 SISLANDS_MAX_NO_VREG_STEPS
,
3924 &eg_pi
->vddci_voltage_table
);
3926 if (si_pi
->vddci_control_svi2
) {
3927 ret
= si_get_svi2_voltage_table(rdev
,
3928 &rdev
->pm
.dpm
.dyn_state
.vddci_dependency_on_mclk
,
3929 &eg_pi
->vddci_voltage_table
);
3934 if (pi
->mvdd_control
) {
3935 ret
= radeon_atom_get_voltage_table(rdev
, VOLTAGE_TYPE_MVDDC
,
3936 VOLTAGE_OBJ_GPIO_LUT
, &si_pi
->mvdd_voltage_table
);
3939 pi
->mvdd_control
= false;
3943 if (si_pi
->mvdd_voltage_table
.count
== 0) {
3944 pi
->mvdd_control
= false;
3948 if (si_pi
->mvdd_voltage_table
.count
> SISLANDS_MAX_NO_VREG_STEPS
)
3949 si_trim_voltage_table_to_fit_state_table(rdev
,
3950 SISLANDS_MAX_NO_VREG_STEPS
,
3951 &si_pi
->mvdd_voltage_table
);
3954 if (si_pi
->vddc_phase_shed_control
) {
3955 ret
= radeon_atom_get_voltage_table(rdev
, VOLTAGE_TYPE_VDDC
,
3956 VOLTAGE_OBJ_PHASE_LUT
, &si_pi
->vddc_phase_shed_table
);
3958 si_pi
->vddc_phase_shed_control
= false;
3960 if ((si_pi
->vddc_phase_shed_table
.count
== 0) ||
3961 (si_pi
->vddc_phase_shed_table
.count
> SISLANDS_MAX_NO_VREG_STEPS
))
3962 si_pi
->vddc_phase_shed_control
= false;
3968 static void si_populate_smc_voltage_table(struct radeon_device
*rdev
,
3969 const struct atom_voltage_table
*voltage_table
,
3970 SISLANDS_SMC_STATETABLE
*table
)
3974 for (i
= 0; i
< voltage_table
->count
; i
++)
3975 table
->lowSMIO
[i
] |= cpu_to_be32(voltage_table
->entries
[i
].smio_low
);
3978 static int si_populate_smc_voltage_tables(struct radeon_device
*rdev
,
3979 SISLANDS_SMC_STATETABLE
*table
)
3981 struct rv7xx_power_info
*pi
= rv770_get_pi(rdev
);
3982 struct evergreen_power_info
*eg_pi
= evergreen_get_pi(rdev
);
3983 struct si_power_info
*si_pi
= si_get_pi(rdev
);
3986 if (si_pi
->voltage_control_svi2
) {
3987 si_write_smc_soft_register(rdev
, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svc
,
3988 si_pi
->svc_gpio_id
);
3989 si_write_smc_soft_register(rdev
, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svd
,
3990 si_pi
->svd_gpio_id
);
3991 si_write_smc_soft_register(rdev
, SI_SMC_SOFT_REGISTER_svi_rework_plat_type
,
3994 if (eg_pi
->vddc_voltage_table
.count
) {
3995 si_populate_smc_voltage_table(rdev
, &eg_pi
->vddc_voltage_table
, table
);
3996 table
->voltageMaskTable
.lowMask
[SISLANDS_SMC_VOLTAGEMASK_VDDC
] =
3997 cpu_to_be32(eg_pi
->vddc_voltage_table
.mask_low
);
3999 for (i
= 0; i
< eg_pi
->vddc_voltage_table
.count
; i
++) {
4000 if (pi
->max_vddc_in_table
<= eg_pi
->vddc_voltage_table
.entries
[i
].value
) {
4001 table
->maxVDDCIndexInPPTable
= i
;
4007 if (eg_pi
->vddci_voltage_table
.count
) {
4008 si_populate_smc_voltage_table(rdev
, &eg_pi
->vddci_voltage_table
, table
);
4010 table
->voltageMaskTable
.lowMask
[SISLANDS_SMC_VOLTAGEMASK_VDDCI
] =
4011 cpu_to_be32(eg_pi
->vddci_voltage_table
.mask_low
);
4015 if (si_pi
->mvdd_voltage_table
.count
) {
4016 si_populate_smc_voltage_table(rdev
, &si_pi
->mvdd_voltage_table
, table
);
4018 table
->voltageMaskTable
.lowMask
[SISLANDS_SMC_VOLTAGEMASK_MVDD
] =
4019 cpu_to_be32(si_pi
->mvdd_voltage_table
.mask_low
);
4022 if (si_pi
->vddc_phase_shed_control
) {
4023 if (si_validate_phase_shedding_tables(rdev
, &si_pi
->vddc_phase_shed_table
,
4024 &rdev
->pm
.dpm
.dyn_state
.phase_shedding_limits_table
)) {
4025 si_populate_smc_voltage_table(rdev
, &si_pi
->vddc_phase_shed_table
, table
);
4027 table
->phaseMaskTable
.lowMask
[SISLANDS_SMC_VOLTAGEMASK_VDDC
] =
4028 cpu_to_be32(si_pi
->vddc_phase_shed_table
.mask_low
);
4030 si_write_smc_soft_register(rdev
, SI_SMC_SOFT_REGISTER_phase_shedding_delay
,
4031 (u32
)si_pi
->vddc_phase_shed_table
.phase_delay
);
4033 si_pi
->vddc_phase_shed_control
= false;
4041 static int si_populate_voltage_value(struct radeon_device
*rdev
,
4042 const struct atom_voltage_table
*table
,
4043 u16 value
, SISLANDS_SMC_VOLTAGE_VALUE
*voltage
)
4047 for (i
= 0; i
< table
->count
; i
++) {
4048 if (value
<= table
->entries
[i
].value
) {
4049 voltage
->index
= (u8
)i
;
4050 voltage
->value
= cpu_to_be16(table
->entries
[i
].value
);
4055 if (i
>= table
->count
)
4061 static int si_populate_mvdd_value(struct radeon_device
*rdev
, u32 mclk
,
4062 SISLANDS_SMC_VOLTAGE_VALUE
*voltage
)
4064 struct rv7xx_power_info
*pi
= rv770_get_pi(rdev
);
4065 struct si_power_info
*si_pi
= si_get_pi(rdev
);
4067 if (pi
->mvdd_control
) {
4068 if (mclk
<= pi
->mvdd_split_frequency
)
4071 voltage
->index
= (u8
)(si_pi
->mvdd_voltage_table
.count
) - 1;
4073 voltage
->value
= cpu_to_be16(si_pi
->mvdd_voltage_table
.entries
[voltage
->index
].value
);
4078 static int si_get_std_voltage_value(struct radeon_device
*rdev
,
4079 SISLANDS_SMC_VOLTAGE_VALUE
*voltage
,
4083 bool voltage_found
= false;
4084 *std_voltage
= be16_to_cpu(voltage
->value
);
4086 if (rdev
->pm
.dpm
.dyn_state
.cac_leakage_table
.entries
) {
4087 if (rdev
->pm
.dpm
.platform_caps
& ATOM_PP_PLATFORM_CAP_NEW_CAC_VOLTAGE
) {
4088 if (rdev
->pm
.dpm
.dyn_state
.vddc_dependency_on_sclk
.entries
== NULL
)
4091 for (v_index
= 0; (u32
)v_index
< rdev
->pm
.dpm
.dyn_state
.vddc_dependency_on_sclk
.count
; v_index
++) {
4092 if (be16_to_cpu(voltage
->value
) ==
4093 (u16
)rdev
->pm
.dpm
.dyn_state
.vddc_dependency_on_sclk
.entries
[v_index
].v
) {
4094 voltage_found
= true;
4095 if ((u32
)v_index
< rdev
->pm
.dpm
.dyn_state
.cac_leakage_table
.count
)
4097 rdev
->pm
.dpm
.dyn_state
.cac_leakage_table
.entries
[v_index
].vddc
;
4100 rdev
->pm
.dpm
.dyn_state
.cac_leakage_table
.entries
[rdev
->pm
.dpm
.dyn_state
.cac_leakage_table
.count
-1].vddc
;
4105 if (!voltage_found
) {
4106 for (v_index
= 0; (u32
)v_index
< rdev
->pm
.dpm
.dyn_state
.vddc_dependency_on_sclk
.count
; v_index
++) {
4107 if (be16_to_cpu(voltage
->value
) <=
4108 (u16
)rdev
->pm
.dpm
.dyn_state
.vddc_dependency_on_sclk
.entries
[v_index
].v
) {
4109 voltage_found
= true;
4110 if ((u32
)v_index
< rdev
->pm
.dpm
.dyn_state
.cac_leakage_table
.count
)
4112 rdev
->pm
.dpm
.dyn_state
.cac_leakage_table
.entries
[v_index
].vddc
;
4115 rdev
->pm
.dpm
.dyn_state
.cac_leakage_table
.entries
[rdev
->pm
.dpm
.dyn_state
.cac_leakage_table
.count
-1].vddc
;
4121 if ((u32
)voltage
->index
< rdev
->pm
.dpm
.dyn_state
.cac_leakage_table
.count
)
4122 *std_voltage
= rdev
->pm
.dpm
.dyn_state
.cac_leakage_table
.entries
[voltage
->index
].vddc
;
4129 static int si_populate_std_voltage_value(struct radeon_device
*rdev
,
4130 u16 value
, u8 index
,
4131 SISLANDS_SMC_VOLTAGE_VALUE
*voltage
)
4133 voltage
->index
= index
;
4134 voltage
->value
= cpu_to_be16(value
);
4139 static int si_populate_phase_shedding_value(struct radeon_device
*rdev
,
4140 const struct radeon_phase_shedding_limits_table
*limits
,
4141 u16 voltage
, u32 sclk
, u32 mclk
,
4142 SISLANDS_SMC_VOLTAGE_VALUE
*smc_voltage
)
4146 for (i
= 0; i
< limits
->count
; i
++) {
4147 if ((voltage
<= limits
->entries
[i
].voltage
) &&
4148 (sclk
<= limits
->entries
[i
].sclk
) &&
4149 (mclk
<= limits
->entries
[i
].mclk
))
4153 smc_voltage
->phase_settings
= (u8
)i
;
4158 static int si_init_arb_table_index(struct radeon_device
*rdev
)
4160 struct si_power_info
*si_pi
= si_get_pi(rdev
);
4164 ret
= si_read_smc_sram_dword(rdev
, si_pi
->arb_table_start
, &tmp
, si_pi
->sram_end
);
4169 tmp
|= MC_CG_ARB_FREQ_F1
<< 24;
4171 return si_write_smc_sram_dword(rdev
, si_pi
->arb_table_start
, tmp
, si_pi
->sram_end
);
4174 static int si_initial_switch_from_arb_f0_to_f1(struct radeon_device
*rdev
)
4176 return ni_copy_and_switch_arb_sets(rdev
, MC_CG_ARB_FREQ_F0
, MC_CG_ARB_FREQ_F1
);
4179 static int si_reset_to_default(struct radeon_device
*rdev
)
4181 return (si_send_msg_to_smc(rdev
, PPSMC_MSG_ResetToDefaults
) == PPSMC_Result_OK
) ?
4185 static int si_force_switch_to_arb_f0(struct radeon_device
*rdev
)
4187 struct si_power_info
*si_pi
= si_get_pi(rdev
);
4191 ret
= si_read_smc_sram_dword(rdev
, si_pi
->arb_table_start
,
4192 &tmp
, si_pi
->sram_end
);
4196 tmp
= (tmp
>> 24) & 0xff;
4198 if (tmp
== MC_CG_ARB_FREQ_F0
)
4201 return ni_copy_and_switch_arb_sets(rdev
, tmp
, MC_CG_ARB_FREQ_F0
);
4204 static u32
si_calculate_memory_refresh_rate(struct radeon_device
*rdev
,
4208 u32 dram_refresh_rate
;
4209 u32 mc_arb_rfsh_rate
;
4210 u32 tmp
= (RREG32(MC_ARB_RAMCFG
) & NOOFROWS_MASK
) >> NOOFROWS_SHIFT
;
4215 dram_rows
= 1 << (tmp
+ 10);
4217 dram_refresh_rate
= 1 << ((RREG32(MC_SEQ_MISC0
) & 0x3) + 3);
4218 mc_arb_rfsh_rate
= ((engine_clock
* 10) * dram_refresh_rate
/ dram_rows
- 32) / 64;
4220 return mc_arb_rfsh_rate
;
4223 static int si_populate_memory_timing_parameters(struct radeon_device
*rdev
,
4224 struct rv7xx_pl
*pl
,
4225 SMC_SIslands_MCArbDramTimingRegisterSet
*arb_regs
)
4231 arb_regs
->mc_arb_rfsh_rate
=
4232 (u8
)si_calculate_memory_refresh_rate(rdev
, pl
->sclk
);
4234 radeon_atom_set_engine_dram_timings(rdev
,
4238 dram_timing
= RREG32(MC_ARB_DRAM_TIMING
);
4239 dram_timing2
= RREG32(MC_ARB_DRAM_TIMING2
);
4240 burst_time
= RREG32(MC_ARB_BURST_TIME
) & STATE0_MASK
;
4242 arb_regs
->mc_arb_dram_timing
= cpu_to_be32(dram_timing
);
4243 arb_regs
->mc_arb_dram_timing2
= cpu_to_be32(dram_timing2
);
4244 arb_regs
->mc_arb_burst_time
= (u8
)burst_time
;
4249 static int si_do_program_memory_timing_parameters(struct radeon_device
*rdev
,
4250 struct radeon_ps
*radeon_state
,
4251 unsigned int first_arb_set
)
4253 struct si_power_info
*si_pi
= si_get_pi(rdev
);
4254 struct ni_ps
*state
= ni_get_ps(radeon_state
);
4255 SMC_SIslands_MCArbDramTimingRegisterSet arb_regs
= { 0 };
4258 for (i
= 0; i
< state
->performance_level_count
; i
++) {
4259 ret
= si_populate_memory_timing_parameters(rdev
, &state
->performance_levels
[i
], &arb_regs
);
4262 ret
= si_copy_bytes_to_smc(rdev
,
4263 si_pi
->arb_table_start
+
4264 offsetof(SMC_SIslands_MCArbDramTimingRegisters
, data
) +
4265 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet
) * (first_arb_set
+ i
),
4267 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet
),
4276 static int si_program_memory_timing_parameters(struct radeon_device
*rdev
,
4277 struct radeon_ps
*radeon_new_state
)
4279 return si_do_program_memory_timing_parameters(rdev
, radeon_new_state
,
4280 SISLANDS_DRIVER_STATE_ARB_INDEX
);
4283 static int si_populate_initial_mvdd_value(struct radeon_device
*rdev
,
4284 struct SISLANDS_SMC_VOLTAGE_VALUE
*voltage
)
4286 struct rv7xx_power_info
*pi
= rv770_get_pi(rdev
);
4287 struct si_power_info
*si_pi
= si_get_pi(rdev
);
4289 if (pi
->mvdd_control
)
4290 return si_populate_voltage_value(rdev
, &si_pi
->mvdd_voltage_table
,
4291 si_pi
->mvdd_bootup_value
, voltage
);
4296 static int si_populate_smc_initial_state(struct radeon_device
*rdev
,
4297 struct radeon_ps
*radeon_initial_state
,
4298 SISLANDS_SMC_STATETABLE
*table
)
4300 struct ni_ps
*initial_state
= ni_get_ps(radeon_initial_state
);
4301 struct rv7xx_power_info
*pi
= rv770_get_pi(rdev
);
4302 struct evergreen_power_info
*eg_pi
= evergreen_get_pi(rdev
);
4303 struct si_power_info
*si_pi
= si_get_pi(rdev
);
4307 table
->initialState
.levels
[0].mclk
.vDLL_CNTL
=
4308 cpu_to_be32(si_pi
->clock_registers
.dll_cntl
);
4309 table
->initialState
.levels
[0].mclk
.vMCLK_PWRMGT_CNTL
=
4310 cpu_to_be32(si_pi
->clock_registers
.mclk_pwrmgt_cntl
);
4311 table
->initialState
.levels
[0].mclk
.vMPLL_AD_FUNC_CNTL
=
4312 cpu_to_be32(si_pi
->clock_registers
.mpll_ad_func_cntl
);
4313 table
->initialState
.levels
[0].mclk
.vMPLL_DQ_FUNC_CNTL
=
4314 cpu_to_be32(si_pi
->clock_registers
.mpll_dq_func_cntl
);
4315 table
->initialState
.levels
[0].mclk
.vMPLL_FUNC_CNTL
=
4316 cpu_to_be32(si_pi
->clock_registers
.mpll_func_cntl
);
4317 table
->initialState
.levels
[0].mclk
.vMPLL_FUNC_CNTL_1
=
4318 cpu_to_be32(si_pi
->clock_registers
.mpll_func_cntl_1
);
4319 table
->initialState
.levels
[0].mclk
.vMPLL_FUNC_CNTL_2
=
4320 cpu_to_be32(si_pi
->clock_registers
.mpll_func_cntl_2
);
4321 table
->initialState
.levels
[0].mclk
.vMPLL_SS
=
4322 cpu_to_be32(si_pi
->clock_registers
.mpll_ss1
);
4323 table
->initialState
.levels
[0].mclk
.vMPLL_SS2
=
4324 cpu_to_be32(si_pi
->clock_registers
.mpll_ss2
);
4326 table
->initialState
.levels
[0].mclk
.mclk_value
=
4327 cpu_to_be32(initial_state
->performance_levels
[0].mclk
);
4329 table
->initialState
.levels
[0].sclk
.vCG_SPLL_FUNC_CNTL
=
4330 cpu_to_be32(si_pi
->clock_registers
.cg_spll_func_cntl
);
4331 table
->initialState
.levels
[0].sclk
.vCG_SPLL_FUNC_CNTL_2
=
4332 cpu_to_be32(si_pi
->clock_registers
.cg_spll_func_cntl_2
);
4333 table
->initialState
.levels
[0].sclk
.vCG_SPLL_FUNC_CNTL_3
=
4334 cpu_to_be32(si_pi
->clock_registers
.cg_spll_func_cntl_3
);
4335 table
->initialState
.levels
[0].sclk
.vCG_SPLL_FUNC_CNTL_4
=
4336 cpu_to_be32(si_pi
->clock_registers
.cg_spll_func_cntl_4
);
4337 table
->initialState
.levels
[0].sclk
.vCG_SPLL_SPREAD_SPECTRUM
=
4338 cpu_to_be32(si_pi
->clock_registers
.cg_spll_spread_spectrum
);
4339 table
->initialState
.levels
[0].sclk
.vCG_SPLL_SPREAD_SPECTRUM_2
=
4340 cpu_to_be32(si_pi
->clock_registers
.cg_spll_spread_spectrum_2
);
4342 table
->initialState
.levels
[0].sclk
.sclk_value
=
4343 cpu_to_be32(initial_state
->performance_levels
[0].sclk
);
4345 table
->initialState
.levels
[0].arbRefreshState
=
4346 SISLANDS_INITIAL_STATE_ARB_INDEX
;
4348 table
->initialState
.levels
[0].ACIndex
= 0;
4350 ret
= si_populate_voltage_value(rdev
, &eg_pi
->vddc_voltage_table
,
4351 initial_state
->performance_levels
[0].vddc
,
4352 &table
->initialState
.levels
[0].vddc
);
4357 ret
= si_get_std_voltage_value(rdev
,
4358 &table
->initialState
.levels
[0].vddc
,
4361 si_populate_std_voltage_value(rdev
, std_vddc
,
4362 table
->initialState
.levels
[0].vddc
.index
,
4363 &table
->initialState
.levels
[0].std_vddc
);
4366 if (eg_pi
->vddci_control
)
4367 si_populate_voltage_value(rdev
,
4368 &eg_pi
->vddci_voltage_table
,
4369 initial_state
->performance_levels
[0].vddci
,
4370 &table
->initialState
.levels
[0].vddci
);
4372 if (si_pi
->vddc_phase_shed_control
)
4373 si_populate_phase_shedding_value(rdev
,
4374 &rdev
->pm
.dpm
.dyn_state
.phase_shedding_limits_table
,
4375 initial_state
->performance_levels
[0].vddc
,
4376 initial_state
->performance_levels
[0].sclk
,
4377 initial_state
->performance_levels
[0].mclk
,
4378 &table
->initialState
.levels
[0].vddc
);
4380 si_populate_initial_mvdd_value(rdev
, &table
->initialState
.levels
[0].mvdd
);
4382 reg
= CG_R(0xffff) | CG_L(0);
4383 table
->initialState
.levels
[0].aT
= cpu_to_be32(reg
);
4385 table
->initialState
.levels
[0].bSP
= cpu_to_be32(pi
->dsp
);
4387 table
->initialState
.levels
[0].gen2PCIE
= (u8
)si_pi
->boot_pcie_gen
;
4389 if (pi
->mem_gddr5
) {
4390 table
->initialState
.levels
[0].strobeMode
=
4391 si_get_strobe_mode_settings(rdev
,
4392 initial_state
->performance_levels
[0].mclk
);
4394 if (initial_state
->performance_levels
[0].mclk
> pi
->mclk_edc_enable_threshold
)
4395 table
->initialState
.levels
[0].mcFlags
= SISLANDS_SMC_MC_EDC_RD_FLAG
| SISLANDS_SMC_MC_EDC_WR_FLAG
;
4397 table
->initialState
.levels
[0].mcFlags
= 0;
4400 table
->initialState
.levelCount
= 1;
4402 table
->initialState
.flags
|= PPSMC_SWSTATE_FLAG_DC
;
4404 table
->initialState
.levels
[0].dpm2
.MaxPS
= 0;
4405 table
->initialState
.levels
[0].dpm2
.NearTDPDec
= 0;
4406 table
->initialState
.levels
[0].dpm2
.AboveSafeInc
= 0;
4407 table
->initialState
.levels
[0].dpm2
.BelowSafeInc
= 0;
4408 table
->initialState
.levels
[0].dpm2
.PwrEfficiencyRatio
= 0;
4410 reg
= MIN_POWER_MASK
| MAX_POWER_MASK
;
4411 table
->initialState
.levels
[0].SQPowerThrottle
= cpu_to_be32(reg
);
4413 reg
= MAX_POWER_DELTA_MASK
| STI_SIZE_MASK
| LTI_RATIO_MASK
;
4414 table
->initialState
.levels
[0].SQPowerThrottle_2
= cpu_to_be32(reg
);
4419 static int si_populate_smc_acpi_state(struct radeon_device
*rdev
,
4420 SISLANDS_SMC_STATETABLE
*table
)
4422 struct rv7xx_power_info
*pi
= rv770_get_pi(rdev
);
4423 struct evergreen_power_info
*eg_pi
= evergreen_get_pi(rdev
);
4424 struct si_power_info
*si_pi
= si_get_pi(rdev
);
4425 u32 spll_func_cntl
= si_pi
->clock_registers
.cg_spll_func_cntl
;
4426 u32 spll_func_cntl_2
= si_pi
->clock_registers
.cg_spll_func_cntl_2
;
4427 u32 spll_func_cntl_3
= si_pi
->clock_registers
.cg_spll_func_cntl_3
;
4428 u32 spll_func_cntl_4
= si_pi
->clock_registers
.cg_spll_func_cntl_4
;
4429 u32 dll_cntl
= si_pi
->clock_registers
.dll_cntl
;
4430 u32 mclk_pwrmgt_cntl
= si_pi
->clock_registers
.mclk_pwrmgt_cntl
;
4431 u32 mpll_ad_func_cntl
= si_pi
->clock_registers
.mpll_ad_func_cntl
;
4432 u32 mpll_dq_func_cntl
= si_pi
->clock_registers
.mpll_dq_func_cntl
;
4433 u32 mpll_func_cntl
= si_pi
->clock_registers
.mpll_func_cntl
;
4434 u32 mpll_func_cntl_1
= si_pi
->clock_registers
.mpll_func_cntl_1
;
4435 u32 mpll_func_cntl_2
= si_pi
->clock_registers
.mpll_func_cntl_2
;
4439 table
->ACPIState
= table
->initialState
;
4441 table
->ACPIState
.flags
&= ~PPSMC_SWSTATE_FLAG_DC
;
4443 if (pi
->acpi_vddc
) {
4444 ret
= si_populate_voltage_value(rdev
, &eg_pi
->vddc_voltage_table
,
4445 pi
->acpi_vddc
, &table
->ACPIState
.levels
[0].vddc
);
4449 ret
= si_get_std_voltage_value(rdev
,
4450 &table
->ACPIState
.levels
[0].vddc
, &std_vddc
);
4452 si_populate_std_voltage_value(rdev
, std_vddc
,
4453 table
->ACPIState
.levels
[0].vddc
.index
,
4454 &table
->ACPIState
.levels
[0].std_vddc
);
4456 table
->ACPIState
.levels
[0].gen2PCIE
= si_pi
->acpi_pcie_gen
;
4458 if (si_pi
->vddc_phase_shed_control
) {
4459 si_populate_phase_shedding_value(rdev
,
4460 &rdev
->pm
.dpm
.dyn_state
.phase_shedding_limits_table
,
4464 &table
->ACPIState
.levels
[0].vddc
);
4467 ret
= si_populate_voltage_value(rdev
, &eg_pi
->vddc_voltage_table
,
4468 pi
->min_vddc_in_table
, &table
->ACPIState
.levels
[0].vddc
);
4472 ret
= si_get_std_voltage_value(rdev
,
4473 &table
->ACPIState
.levels
[0].vddc
, &std_vddc
);
4476 si_populate_std_voltage_value(rdev
, std_vddc
,
4477 table
->ACPIState
.levels
[0].vddc
.index
,
4478 &table
->ACPIState
.levels
[0].std_vddc
);
4480 table
->ACPIState
.levels
[0].gen2PCIE
= (u8
)r600_get_pcie_gen_support(rdev
,
4481 si_pi
->sys_pcie_mask
,
4482 si_pi
->boot_pcie_gen
,
4485 if (si_pi
->vddc_phase_shed_control
)
4486 si_populate_phase_shedding_value(rdev
,
4487 &rdev
->pm
.dpm
.dyn_state
.phase_shedding_limits_table
,
4488 pi
->min_vddc_in_table
,
4491 &table
->ACPIState
.levels
[0].vddc
);
4494 if (pi
->acpi_vddc
) {
4495 if (eg_pi
->acpi_vddci
)
4496 si_populate_voltage_value(rdev
, &eg_pi
->vddci_voltage_table
,
4498 &table
->ACPIState
.levels
[0].vddci
);
4501 mclk_pwrmgt_cntl
|= MRDCK0_RESET
| MRDCK1_RESET
;
4502 mclk_pwrmgt_cntl
&= ~(MRDCK0_PDNB
| MRDCK1_PDNB
);
4504 dll_cntl
&= ~(MRDCK0_BYPASS
| MRDCK1_BYPASS
);
4506 spll_func_cntl_2
&= ~SCLK_MUX_SEL_MASK
;
4507 spll_func_cntl_2
|= SCLK_MUX_SEL(4);
4509 table
->ACPIState
.levels
[0].mclk
.vDLL_CNTL
=
4510 cpu_to_be32(dll_cntl
);
4511 table
->ACPIState
.levels
[0].mclk
.vMCLK_PWRMGT_CNTL
=
4512 cpu_to_be32(mclk_pwrmgt_cntl
);
4513 table
->ACPIState
.levels
[0].mclk
.vMPLL_AD_FUNC_CNTL
=
4514 cpu_to_be32(mpll_ad_func_cntl
);
4515 table
->ACPIState
.levels
[0].mclk
.vMPLL_DQ_FUNC_CNTL
=
4516 cpu_to_be32(mpll_dq_func_cntl
);
4517 table
->ACPIState
.levels
[0].mclk
.vMPLL_FUNC_CNTL
=
4518 cpu_to_be32(mpll_func_cntl
);
4519 table
->ACPIState
.levels
[0].mclk
.vMPLL_FUNC_CNTL_1
=
4520 cpu_to_be32(mpll_func_cntl_1
);
4521 table
->ACPIState
.levels
[0].mclk
.vMPLL_FUNC_CNTL_2
=
4522 cpu_to_be32(mpll_func_cntl_2
);
4523 table
->ACPIState
.levels
[0].mclk
.vMPLL_SS
=
4524 cpu_to_be32(si_pi
->clock_registers
.mpll_ss1
);
4525 table
->ACPIState
.levels
[0].mclk
.vMPLL_SS2
=
4526 cpu_to_be32(si_pi
->clock_registers
.mpll_ss2
);
4528 table
->ACPIState
.levels
[0].sclk
.vCG_SPLL_FUNC_CNTL
=
4529 cpu_to_be32(spll_func_cntl
);
4530 table
->ACPIState
.levels
[0].sclk
.vCG_SPLL_FUNC_CNTL_2
=
4531 cpu_to_be32(spll_func_cntl_2
);
4532 table
->ACPIState
.levels
[0].sclk
.vCG_SPLL_FUNC_CNTL_3
=
4533 cpu_to_be32(spll_func_cntl_3
);
4534 table
->ACPIState
.levels
[0].sclk
.vCG_SPLL_FUNC_CNTL_4
=
4535 cpu_to_be32(spll_func_cntl_4
);
4537 table
->ACPIState
.levels
[0].mclk
.mclk_value
= 0;
4538 table
->ACPIState
.levels
[0].sclk
.sclk_value
= 0;
4540 si_populate_mvdd_value(rdev
, 0, &table
->ACPIState
.levels
[0].mvdd
);
4542 if (eg_pi
->dynamic_ac_timing
)
4543 table
->ACPIState
.levels
[0].ACIndex
= 0;
4545 table
->ACPIState
.levels
[0].dpm2
.MaxPS
= 0;
4546 table
->ACPIState
.levels
[0].dpm2
.NearTDPDec
= 0;
4547 table
->ACPIState
.levels
[0].dpm2
.AboveSafeInc
= 0;
4548 table
->ACPIState
.levels
[0].dpm2
.BelowSafeInc
= 0;
4549 table
->ACPIState
.levels
[0].dpm2
.PwrEfficiencyRatio
= 0;
4551 reg
= MIN_POWER_MASK
| MAX_POWER_MASK
;
4552 table
->ACPIState
.levels
[0].SQPowerThrottle
= cpu_to_be32(reg
);
4554 reg
= MAX_POWER_DELTA_MASK
| STI_SIZE_MASK
| LTI_RATIO_MASK
;
4555 table
->ACPIState
.levels
[0].SQPowerThrottle_2
= cpu_to_be32(reg
);
4560 static int si_populate_ulv_state(struct radeon_device
*rdev
,
4561 SISLANDS_SMC_SWSTATE
*state
)
4563 struct evergreen_power_info
*eg_pi
= evergreen_get_pi(rdev
);
4564 struct si_power_info
*si_pi
= si_get_pi(rdev
);
4565 struct si_ulv_param
*ulv
= &si_pi
->ulv
;
4566 u32 sclk_in_sr
= 1350; /* ??? */
4569 ret
= si_convert_power_level_to_smc(rdev
, &ulv
->pl
,
4572 if (eg_pi
->sclk_deep_sleep
) {
4573 if (sclk_in_sr
<= SCLK_MIN_DEEPSLEEP_FREQ
)
4574 state
->levels
[0].stateFlags
|= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS
;
4576 state
->levels
[0].stateFlags
|= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE
;
4578 if (ulv
->one_pcie_lane_in_ulv
)
4579 state
->flags
|= PPSMC_SWSTATE_FLAG_PCIE_X1
;
4580 state
->levels
[0].arbRefreshState
= (u8
)(SISLANDS_ULV_STATE_ARB_INDEX
);
4581 state
->levels
[0].ACIndex
= 1;
4582 state
->levels
[0].std_vddc
= state
->levels
[0].vddc
;
4583 state
->levelCount
= 1;
4585 state
->flags
|= PPSMC_SWSTATE_FLAG_DC
;
4591 static int si_program_ulv_memory_timing_parameters(struct radeon_device
*rdev
)
4593 struct si_power_info
*si_pi
= si_get_pi(rdev
);
4594 struct si_ulv_param
*ulv
= &si_pi
->ulv
;
4595 SMC_SIslands_MCArbDramTimingRegisterSet arb_regs
= { 0 };
4598 ret
= si_populate_memory_timing_parameters(rdev
, &ulv
->pl
,
4603 si_write_smc_soft_register(rdev
, SI_SMC_SOFT_REGISTER_ulv_volt_change_delay
,
4604 ulv
->volt_change_delay
);
4606 ret
= si_copy_bytes_to_smc(rdev
,
4607 si_pi
->arb_table_start
+
4608 offsetof(SMC_SIslands_MCArbDramTimingRegisters
, data
) +
4609 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet
) * SISLANDS_ULV_STATE_ARB_INDEX
,
4611 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet
),
4617 static void si_get_mvdd_configuration(struct radeon_device
*rdev
)
4619 struct rv7xx_power_info
*pi
= rv770_get_pi(rdev
);
4621 pi
->mvdd_split_frequency
= 30000;
4624 static int si_init_smc_table(struct radeon_device
*rdev
)
4626 struct rv7xx_power_info
*pi
= rv770_get_pi(rdev
);
4627 struct si_power_info
*si_pi
= si_get_pi(rdev
);
4628 struct radeon_ps
*radeon_boot_state
= rdev
->pm
.dpm
.boot_ps
;
4629 const struct si_ulv_param
*ulv
= &si_pi
->ulv
;
4630 SISLANDS_SMC_STATETABLE
*table
= &si_pi
->smc_statetable
;
4635 si_populate_smc_voltage_tables(rdev
, table
);
4637 switch (rdev
->pm
.int_thermal_type
) {
4638 case THERMAL_TYPE_SI
:
4639 case THERMAL_TYPE_EMC2103_WITH_INTERNAL
:
4640 table
->thermalProtectType
= PPSMC_THERMAL_PROTECT_TYPE_INTERNAL
;
4642 case THERMAL_TYPE_NONE
:
4643 table
->thermalProtectType
= PPSMC_THERMAL_PROTECT_TYPE_NONE
;
4646 table
->thermalProtectType
= PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL
;
4650 if (rdev
->pm
.dpm
.platform_caps
& ATOM_PP_PLATFORM_CAP_HARDWAREDC
)
4651 table
->systemFlags
|= PPSMC_SYSTEMFLAG_GPIO_DC
;
4653 if (rdev
->pm
.dpm
.platform_caps
& ATOM_PP_PLATFORM_CAP_REGULATOR_HOT
) {
4654 if ((rdev
->pdev
->device
!= 0x6818) && (rdev
->pdev
->device
!= 0x6819))
4655 table
->systemFlags
|= PPSMC_SYSTEMFLAG_REGULATOR_HOT
;
4658 if (rdev
->pm
.dpm
.platform_caps
& ATOM_PP_PLATFORM_CAP_STEPVDDC
)
4659 table
->systemFlags
|= PPSMC_SYSTEMFLAG_STEPVDDC
;
4662 table
->systemFlags
|= PPSMC_SYSTEMFLAG_GDDR5
;
4664 if (rdev
->pm
.dpm
.platform_caps
& ATOM_PP_PLATFORM_CAP_REVERT_GPIO5_POLARITY
)
4665 table
->extraFlags
|= PPSMC_EXTRAFLAGS_AC2DC_GPIO5_POLARITY_HIGH
;
4667 if (rdev
->pm
.dpm
.platform_caps
& ATOM_PP_PLATFORM_CAP_VRHOT_GPIO_CONFIGURABLE
) {
4668 table
->systemFlags
|= PPSMC_SYSTEMFLAG_REGULATOR_HOT_PROG_GPIO
;
4669 vr_hot_gpio
= rdev
->pm
.dpm
.backbias_response_time
;
4670 si_write_smc_soft_register(rdev
, SI_SMC_SOFT_REGISTER_vr_hot_gpio
,
4674 ret
= si_populate_smc_initial_state(rdev
, radeon_boot_state
, table
);
4678 ret
= si_populate_smc_acpi_state(rdev
, table
);
4682 table
->driverState
= table
->initialState
;
4684 ret
= si_do_program_memory_timing_parameters(rdev
, radeon_boot_state
,
4685 SISLANDS_INITIAL_STATE_ARB_INDEX
);
4689 if (ulv
->supported
&& ulv
->pl
.vddc
) {
4690 ret
= si_populate_ulv_state(rdev
, &table
->ULVState
);
4694 ret
= si_program_ulv_memory_timing_parameters(rdev
);
4698 WREG32(CG_ULV_CONTROL
, ulv
->cg_ulv_control
);
4699 WREG32(CG_ULV_PARAMETER
, ulv
->cg_ulv_parameter
);
4701 lane_width
= radeon_get_pcie_lanes(rdev
);
4702 si_write_smc_soft_register(rdev
, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width
, lane_width
);
4704 table
->ULVState
= table
->initialState
;
4707 return si_copy_bytes_to_smc(rdev
, si_pi
->state_table_start
,
4708 (u8
*)table
, sizeof(SISLANDS_SMC_STATETABLE
),
4712 static int si_calculate_sclk_params(struct radeon_device
*rdev
,
4714 SISLANDS_SMC_SCLK_VALUE
*sclk
)
4716 struct rv7xx_power_info
*pi
= rv770_get_pi(rdev
);
4717 struct si_power_info
*si_pi
= si_get_pi(rdev
);
4718 struct atom_clock_dividers dividers
;
4719 u32 spll_func_cntl
= si_pi
->clock_registers
.cg_spll_func_cntl
;
4720 u32 spll_func_cntl_2
= si_pi
->clock_registers
.cg_spll_func_cntl_2
;
4721 u32 spll_func_cntl_3
= si_pi
->clock_registers
.cg_spll_func_cntl_3
;
4722 u32 spll_func_cntl_4
= si_pi
->clock_registers
.cg_spll_func_cntl_4
;
4723 u32 cg_spll_spread_spectrum
= si_pi
->clock_registers
.cg_spll_spread_spectrum
;
4724 u32 cg_spll_spread_spectrum_2
= si_pi
->clock_registers
.cg_spll_spread_spectrum_2
;
4726 u32 reference_clock
= rdev
->clock
.spll
.reference_freq
;
4727 u32 reference_divider
;
4731 ret
= radeon_atom_get_clock_dividers(rdev
, COMPUTE_ENGINE_PLL_PARAM
,
4732 engine_clock
, false, ÷rs
);
4736 reference_divider
= 1 + dividers
.ref_div
;
4738 tmp
= (u64
) engine_clock
* reference_divider
* dividers
.post_div
* 16384;
4739 do_div(tmp
, reference_clock
);
4742 spll_func_cntl
&= ~(SPLL_PDIV_A_MASK
| SPLL_REF_DIV_MASK
);
4743 spll_func_cntl
|= SPLL_REF_DIV(dividers
.ref_div
);
4744 spll_func_cntl
|= SPLL_PDIV_A(dividers
.post_div
);
4746 spll_func_cntl_2
&= ~SCLK_MUX_SEL_MASK
;
4747 spll_func_cntl_2
|= SCLK_MUX_SEL(2);
4749 spll_func_cntl_3
&= ~SPLL_FB_DIV_MASK
;
4750 spll_func_cntl_3
|= SPLL_FB_DIV(fbdiv
);
4751 spll_func_cntl_3
|= SPLL_DITHEN
;
4754 struct radeon_atom_ss ss
;
4755 u32 vco_freq
= engine_clock
* dividers
.post_div
;
4757 if (radeon_atombios_get_asic_ss_info(rdev
, &ss
,
4758 ASIC_INTERNAL_ENGINE_SS
, vco_freq
)) {
4759 u32 clk_s
= reference_clock
* 5 / (reference_divider
* ss
.rate
);
4760 u32 clk_v
= 4 * ss
.percentage
* fbdiv
/ (clk_s
* 10000);
4762 cg_spll_spread_spectrum
&= ~CLK_S_MASK
;
4763 cg_spll_spread_spectrum
|= CLK_S(clk_s
);
4764 cg_spll_spread_spectrum
|= SSEN
;
4766 cg_spll_spread_spectrum_2
&= ~CLK_V_MASK
;
4767 cg_spll_spread_spectrum_2
|= CLK_V(clk_v
);
4771 sclk
->sclk_value
= engine_clock
;
4772 sclk
->vCG_SPLL_FUNC_CNTL
= spll_func_cntl
;
4773 sclk
->vCG_SPLL_FUNC_CNTL_2
= spll_func_cntl_2
;
4774 sclk
->vCG_SPLL_FUNC_CNTL_3
= spll_func_cntl_3
;
4775 sclk
->vCG_SPLL_FUNC_CNTL_4
= spll_func_cntl_4
;
4776 sclk
->vCG_SPLL_SPREAD_SPECTRUM
= cg_spll_spread_spectrum
;
4777 sclk
->vCG_SPLL_SPREAD_SPECTRUM_2
= cg_spll_spread_spectrum_2
;
4782 static int si_populate_sclk_value(struct radeon_device
*rdev
,
4784 SISLANDS_SMC_SCLK_VALUE
*sclk
)
4786 SISLANDS_SMC_SCLK_VALUE sclk_tmp
;
4789 ret
= si_calculate_sclk_params(rdev
, engine_clock
, &sclk_tmp
);
4791 sclk
->sclk_value
= cpu_to_be32(sclk_tmp
.sclk_value
);
4792 sclk
->vCG_SPLL_FUNC_CNTL
= cpu_to_be32(sclk_tmp
.vCG_SPLL_FUNC_CNTL
);
4793 sclk
->vCG_SPLL_FUNC_CNTL_2
= cpu_to_be32(sclk_tmp
.vCG_SPLL_FUNC_CNTL_2
);
4794 sclk
->vCG_SPLL_FUNC_CNTL_3
= cpu_to_be32(sclk_tmp
.vCG_SPLL_FUNC_CNTL_3
);
4795 sclk
->vCG_SPLL_FUNC_CNTL_4
= cpu_to_be32(sclk_tmp
.vCG_SPLL_FUNC_CNTL_4
);
4796 sclk
->vCG_SPLL_SPREAD_SPECTRUM
= cpu_to_be32(sclk_tmp
.vCG_SPLL_SPREAD_SPECTRUM
);
4797 sclk
->vCG_SPLL_SPREAD_SPECTRUM_2
= cpu_to_be32(sclk_tmp
.vCG_SPLL_SPREAD_SPECTRUM_2
);
4803 static int si_populate_mclk_value(struct radeon_device
*rdev
,
4806 SISLANDS_SMC_MCLK_VALUE
*mclk
,
4810 struct rv7xx_power_info
*pi
= rv770_get_pi(rdev
);
4811 struct si_power_info
*si_pi
= si_get_pi(rdev
);
4812 u32 dll_cntl
= si_pi
->clock_registers
.dll_cntl
;
4813 u32 mclk_pwrmgt_cntl
= si_pi
->clock_registers
.mclk_pwrmgt_cntl
;
4814 u32 mpll_ad_func_cntl
= si_pi
->clock_registers
.mpll_ad_func_cntl
;
4815 u32 mpll_dq_func_cntl
= si_pi
->clock_registers
.mpll_dq_func_cntl
;
4816 u32 mpll_func_cntl
= si_pi
->clock_registers
.mpll_func_cntl
;
4817 u32 mpll_func_cntl_1
= si_pi
->clock_registers
.mpll_func_cntl_1
;
4818 u32 mpll_func_cntl_2
= si_pi
->clock_registers
.mpll_func_cntl_2
;
4819 u32 mpll_ss1
= si_pi
->clock_registers
.mpll_ss1
;
4820 u32 mpll_ss2
= si_pi
->clock_registers
.mpll_ss2
;
4821 struct atom_mpll_param mpll_param
;
4824 ret
= radeon_atom_get_memory_pll_dividers(rdev
, memory_clock
, strobe_mode
, &mpll_param
);
4828 mpll_func_cntl
&= ~BWCTRL_MASK
;
4829 mpll_func_cntl
|= BWCTRL(mpll_param
.bwcntl
);
4831 mpll_func_cntl_1
&= ~(CLKF_MASK
| CLKFRAC_MASK
| VCO_MODE_MASK
);
4832 mpll_func_cntl_1
|= CLKF(mpll_param
.clkf
) |
4833 CLKFRAC(mpll_param
.clkfrac
) | VCO_MODE(mpll_param
.vco_mode
);
4835 mpll_ad_func_cntl
&= ~YCLK_POST_DIV_MASK
;
4836 mpll_ad_func_cntl
|= YCLK_POST_DIV(mpll_param
.post_div
);
4838 if (pi
->mem_gddr5
) {
4839 mpll_dq_func_cntl
&= ~(YCLK_SEL_MASK
| YCLK_POST_DIV_MASK
);
4840 mpll_dq_func_cntl
|= YCLK_SEL(mpll_param
.yclk_sel
) |
4841 YCLK_POST_DIV(mpll_param
.post_div
);
4845 struct radeon_atom_ss ss
;
4848 u32 reference_clock
= rdev
->clock
.mpll
.reference_freq
;
4851 freq_nom
= memory_clock
* 4;
4853 freq_nom
= memory_clock
* 2;
4855 tmp
= freq_nom
/ reference_clock
;
4857 if (radeon_atombios_get_asic_ss_info(rdev
, &ss
,
4858 ASIC_INTERNAL_MEMORY_SS
, freq_nom
)) {
4859 u32 clks
= reference_clock
* 5 / ss
.rate
;
4860 u32 clkv
= (u32
)((((131 * ss
.percentage
* ss
.rate
) / 100) * tmp
) / freq_nom
);
4862 mpll_ss1
&= ~CLKV_MASK
;
4863 mpll_ss1
|= CLKV(clkv
);
4865 mpll_ss2
&= ~CLKS_MASK
;
4866 mpll_ss2
|= CLKS(clks
);
4870 mclk_pwrmgt_cntl
&= ~DLL_SPEED_MASK
;
4871 mclk_pwrmgt_cntl
|= DLL_SPEED(mpll_param
.dll_speed
);
4874 mclk_pwrmgt_cntl
|= MRDCK0_PDNB
| MRDCK1_PDNB
;
4876 mclk_pwrmgt_cntl
&= ~(MRDCK0_PDNB
| MRDCK1_PDNB
);
4878 mclk
->mclk_value
= cpu_to_be32(memory_clock
);
4879 mclk
->vMPLL_FUNC_CNTL
= cpu_to_be32(mpll_func_cntl
);
4880 mclk
->vMPLL_FUNC_CNTL_1
= cpu_to_be32(mpll_func_cntl_1
);
4881 mclk
->vMPLL_FUNC_CNTL_2
= cpu_to_be32(mpll_func_cntl_2
);
4882 mclk
->vMPLL_AD_FUNC_CNTL
= cpu_to_be32(mpll_ad_func_cntl
);
4883 mclk
->vMPLL_DQ_FUNC_CNTL
= cpu_to_be32(mpll_dq_func_cntl
);
4884 mclk
->vMCLK_PWRMGT_CNTL
= cpu_to_be32(mclk_pwrmgt_cntl
);
4885 mclk
->vDLL_CNTL
= cpu_to_be32(dll_cntl
);
4886 mclk
->vMPLL_SS
= cpu_to_be32(mpll_ss1
);
4887 mclk
->vMPLL_SS2
= cpu_to_be32(mpll_ss2
);
4892 static void si_populate_smc_sp(struct radeon_device
*rdev
,
4893 struct radeon_ps
*radeon_state
,
4894 SISLANDS_SMC_SWSTATE
*smc_state
)
4896 struct ni_ps
*ps
= ni_get_ps(radeon_state
);
4897 struct rv7xx_power_info
*pi
= rv770_get_pi(rdev
);
4900 for (i
= 0; i
< ps
->performance_level_count
- 1; i
++)
4901 smc_state
->levels
[i
].bSP
= cpu_to_be32(pi
->dsp
);
4903 smc_state
->levels
[ps
->performance_level_count
- 1].bSP
=
4904 cpu_to_be32(pi
->psp
);
4907 static int si_convert_power_level_to_smc(struct radeon_device
*rdev
,
4908 struct rv7xx_pl
*pl
,
4909 SISLANDS_SMC_HW_PERFORMANCE_LEVEL
*level
)
4911 struct rv7xx_power_info
*pi
= rv770_get_pi(rdev
);
4912 struct evergreen_power_info
*eg_pi
= evergreen_get_pi(rdev
);
4913 struct si_power_info
*si_pi
= si_get_pi(rdev
);
4917 bool gmc_pg
= false;
4919 if (eg_pi
->pcie_performance_request
&&
4920 (si_pi
->force_pcie_gen
!= RADEON_PCIE_GEN_INVALID
))
4921 level
->gen2PCIE
= (u8
)si_pi
->force_pcie_gen
;
4923 level
->gen2PCIE
= (u8
)pl
->pcie_gen
;
4925 ret
= si_populate_sclk_value(rdev
, pl
->sclk
, &level
->sclk
);
4931 if (pi
->mclk_stutter_mode_threshold
&&
4932 (pl
->mclk
<= pi
->mclk_stutter_mode_threshold
) &&
4933 !eg_pi
->uvd_enabled
&&
4934 (RREG32(DPG_PIPE_STUTTER_CONTROL
) & STUTTER_ENABLE
) &&
4935 (rdev
->pm
.dpm
.new_active_crtc_count
<= 2)) {
4936 level
->mcFlags
|= SISLANDS_SMC_MC_STUTTER_EN
;
4939 level
->mcFlags
|= SISLANDS_SMC_MC_PG_EN
;
4942 if (pi
->mem_gddr5
) {
4943 if (pl
->mclk
> pi
->mclk_edc_enable_threshold
)
4944 level
->mcFlags
|= SISLANDS_SMC_MC_EDC_RD_FLAG
;
4946 if (pl
->mclk
> eg_pi
->mclk_edc_wr_enable_threshold
)
4947 level
->mcFlags
|= SISLANDS_SMC_MC_EDC_WR_FLAG
;
4949 level
->strobeMode
= si_get_strobe_mode_settings(rdev
, pl
->mclk
);
4951 if (level
->strobeMode
& SISLANDS_SMC_STROBE_ENABLE
) {
4952 if (si_get_mclk_frequency_ratio(pl
->mclk
, true) >=
4953 ((RREG32(MC_SEQ_MISC7
) >> 16) & 0xf))
4954 dll_state_on
= ((RREG32(MC_SEQ_MISC5
) >> 1) & 0x1) ? true : false;
4956 dll_state_on
= ((RREG32(MC_SEQ_MISC6
) >> 1) & 0x1) ? true : false;
4958 dll_state_on
= false;
4961 level
->strobeMode
= si_get_strobe_mode_settings(rdev
,
4964 dll_state_on
= ((RREG32(MC_SEQ_MISC5
) >> 1) & 0x1) ? true : false;
4967 ret
= si_populate_mclk_value(rdev
,
4971 (level
->strobeMode
& SISLANDS_SMC_STROBE_ENABLE
) != 0, dll_state_on
);
4975 ret
= si_populate_voltage_value(rdev
,
4976 &eg_pi
->vddc_voltage_table
,
4977 pl
->vddc
, &level
->vddc
);
4982 ret
= si_get_std_voltage_value(rdev
, &level
->vddc
, &std_vddc
);
4986 ret
= si_populate_std_voltage_value(rdev
, std_vddc
,
4987 level
->vddc
.index
, &level
->std_vddc
);
4991 if (eg_pi
->vddci_control
) {
4992 ret
= si_populate_voltage_value(rdev
, &eg_pi
->vddci_voltage_table
,
4993 pl
->vddci
, &level
->vddci
);
4998 if (si_pi
->vddc_phase_shed_control
) {
4999 ret
= si_populate_phase_shedding_value(rdev
,
5000 &rdev
->pm
.dpm
.dyn_state
.phase_shedding_limits_table
,
5009 level
->MaxPoweredUpCU
= si_pi
->max_cu
;
5011 ret
= si_populate_mvdd_value(rdev
, pl
->mclk
, &level
->mvdd
);
5016 static int si_populate_smc_t(struct radeon_device
*rdev
,
5017 struct radeon_ps
*radeon_state
,
5018 SISLANDS_SMC_SWSTATE
*smc_state
)
5020 struct rv7xx_power_info
*pi
= rv770_get_pi(rdev
);
5021 struct ni_ps
*state
= ni_get_ps(radeon_state
);
5027 if (state
->performance_level_count
>= 9)
5030 if (state
->performance_level_count
< 2) {
5031 a_t
= CG_R(0xffff) | CG_L(0);
5032 smc_state
->levels
[0].aT
= cpu_to_be32(a_t
);
5036 smc_state
->levels
[0].aT
= cpu_to_be32(0);
5038 for (i
= 0; i
<= state
->performance_level_count
- 2; i
++) {
5039 ret
= r600_calculate_at(
5040 (50 / SISLANDS_MAX_HARDWARE_POWERLEVELS
) * 100 * (i
+ 1),
5042 state
->performance_levels
[i
+ 1].sclk
,
5043 state
->performance_levels
[i
].sclk
,
5048 t_h
= (i
+ 1) * 1000 - 50 * R600_AH_DFLT
;
5049 t_l
= (i
+ 1) * 1000 + 50 * R600_AH_DFLT
;
5052 a_t
= be32_to_cpu(smc_state
->levels
[i
].aT
) & ~CG_R_MASK
;
5053 a_t
|= CG_R(t_l
* pi
->bsp
/ 20000);
5054 smc_state
->levels
[i
].aT
= cpu_to_be32(a_t
);
5056 high_bsp
= (i
== state
->performance_level_count
- 2) ?
5058 a_t
= CG_R(0xffff) | CG_L(t_h
* high_bsp
/ 20000);
5059 smc_state
->levels
[i
+ 1].aT
= cpu_to_be32(a_t
);
5065 static int si_disable_ulv(struct radeon_device
*rdev
)
5067 struct si_power_info
*si_pi
= si_get_pi(rdev
);
5068 struct si_ulv_param
*ulv
= &si_pi
->ulv
;
5071 return (si_send_msg_to_smc(rdev
, PPSMC_MSG_DisableULV
) == PPSMC_Result_OK
) ?
5077 static bool si_is_state_ulv_compatible(struct radeon_device
*rdev
,
5078 struct radeon_ps
*radeon_state
)
5080 const struct si_power_info
*si_pi
= si_get_pi(rdev
);
5081 const struct si_ulv_param
*ulv
= &si_pi
->ulv
;
5082 const struct ni_ps
*state
= ni_get_ps(radeon_state
);
5085 if (state
->performance_levels
[0].mclk
!= ulv
->pl
.mclk
)
5088 /* XXX validate against display requirements! */
5090 for (i
= 0; i
< rdev
->pm
.dpm
.dyn_state
.vddc_dependency_on_dispclk
.count
; i
++) {
5091 if (rdev
->clock
.current_dispclk
<=
5092 rdev
->pm
.dpm
.dyn_state
.vddc_dependency_on_dispclk
.entries
[i
].clk
) {
5094 rdev
->pm
.dpm
.dyn_state
.vddc_dependency_on_dispclk
.entries
[i
].v
)
5099 if ((radeon_state
->vclk
!= 0) || (radeon_state
->dclk
!= 0))
5105 static int si_set_power_state_conditionally_enable_ulv(struct radeon_device
*rdev
,
5106 struct radeon_ps
*radeon_new_state
)
5108 const struct si_power_info
*si_pi
= si_get_pi(rdev
);
5109 const struct si_ulv_param
*ulv
= &si_pi
->ulv
;
5111 if (ulv
->supported
) {
5112 if (si_is_state_ulv_compatible(rdev
, radeon_new_state
))
5113 return (si_send_msg_to_smc(rdev
, PPSMC_MSG_EnableULV
) == PPSMC_Result_OK
) ?
5119 static int si_convert_power_state_to_smc(struct radeon_device
*rdev
,
5120 struct radeon_ps
*radeon_state
,
5121 SISLANDS_SMC_SWSTATE
*smc_state
)
5123 struct evergreen_power_info
*eg_pi
= evergreen_get_pi(rdev
);
5124 struct ni_power_info
*ni_pi
= ni_get_pi(rdev
);
5125 struct si_power_info
*si_pi
= si_get_pi(rdev
);
5126 struct ni_ps
*state
= ni_get_ps(radeon_state
);
5129 u32 sclk_in_sr
= 1350; /* ??? */
5131 if (state
->performance_level_count
> SISLANDS_MAX_HARDWARE_POWERLEVELS
)
5134 threshold
= state
->performance_levels
[state
->performance_level_count
-1].sclk
* 100 / 100;
5136 if (radeon_state
->vclk
&& radeon_state
->dclk
) {
5137 eg_pi
->uvd_enabled
= true;
5138 if (eg_pi
->smu_uvd_hs
)
5139 smc_state
->flags
|= PPSMC_SWSTATE_FLAG_UVD
;
5141 eg_pi
->uvd_enabled
= false;
5144 if (state
->dc_compatible
)
5145 smc_state
->flags
|= PPSMC_SWSTATE_FLAG_DC
;
5147 smc_state
->levelCount
= 0;
5148 for (i
= 0; i
< state
->performance_level_count
; i
++) {
5149 if (eg_pi
->sclk_deep_sleep
) {
5150 if ((i
== 0) || si_pi
->sclk_deep_sleep_above_low
) {
5151 if (sclk_in_sr
<= SCLK_MIN_DEEPSLEEP_FREQ
)
5152 smc_state
->levels
[i
].stateFlags
|= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS
;
5154 smc_state
->levels
[i
].stateFlags
|= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE
;
5158 ret
= si_convert_power_level_to_smc(rdev
, &state
->performance_levels
[i
],
5159 &smc_state
->levels
[i
]);
5160 smc_state
->levels
[i
].arbRefreshState
=
5161 (u8
)(SISLANDS_DRIVER_STATE_ARB_INDEX
+ i
);
5166 if (ni_pi
->enable_power_containment
)
5167 smc_state
->levels
[i
].displayWatermark
=
5168 (state
->performance_levels
[i
].sclk
< threshold
) ?
5169 PPSMC_DISPLAY_WATERMARK_LOW
: PPSMC_DISPLAY_WATERMARK_HIGH
;
5171 smc_state
->levels
[i
].displayWatermark
= (i
< 2) ?
5172 PPSMC_DISPLAY_WATERMARK_LOW
: PPSMC_DISPLAY_WATERMARK_HIGH
;
5174 if (eg_pi
->dynamic_ac_timing
)
5175 smc_state
->levels
[i
].ACIndex
= SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT
+ i
;
5177 smc_state
->levels
[i
].ACIndex
= 0;
5179 smc_state
->levelCount
++;
5182 si_write_smc_soft_register(rdev
,
5183 SI_SMC_SOFT_REGISTER_watermark_threshold
,
5186 si_populate_smc_sp(rdev
, radeon_state
, smc_state
);
5188 ret
= si_populate_power_containment_values(rdev
, radeon_state
, smc_state
);
5190 ni_pi
->enable_power_containment
= false;
5192 ret
= si_populate_sq_ramping_values(rdev
, radeon_state
, smc_state
);
5194 ni_pi
->enable_sq_ramping
= false;
5196 return si_populate_smc_t(rdev
, radeon_state
, smc_state
);
5199 static int si_upload_sw_state(struct radeon_device
*rdev
,
5200 struct radeon_ps
*radeon_new_state
)
5202 struct si_power_info
*si_pi
= si_get_pi(rdev
);
5203 struct ni_ps
*new_state
= ni_get_ps(radeon_new_state
);
5205 u32 address
= si_pi
->state_table_start
+
5206 offsetof(SISLANDS_SMC_STATETABLE
, driverState
);
5207 u32 state_size
= sizeof(SISLANDS_SMC_SWSTATE
) +
5208 ((new_state
->performance_level_count
- 1) *
5209 sizeof(SISLANDS_SMC_HW_PERFORMANCE_LEVEL
));
5210 SISLANDS_SMC_SWSTATE
*smc_state
= &si_pi
->smc_statetable
.driverState
;
5212 memset(smc_state
, 0, state_size
);
5214 ret
= si_convert_power_state_to_smc(rdev
, radeon_new_state
, smc_state
);
5218 ret
= si_copy_bytes_to_smc(rdev
, address
, (u8
*)smc_state
,
5219 state_size
, si_pi
->sram_end
);
5224 static int si_upload_ulv_state(struct radeon_device
*rdev
)
5226 struct si_power_info
*si_pi
= si_get_pi(rdev
);
5227 struct si_ulv_param
*ulv
= &si_pi
->ulv
;
5230 if (ulv
->supported
&& ulv
->pl
.vddc
) {
5231 u32 address
= si_pi
->state_table_start
+
5232 offsetof(SISLANDS_SMC_STATETABLE
, ULVState
);
5233 SISLANDS_SMC_SWSTATE
*smc_state
= &si_pi
->smc_statetable
.ULVState
;
5234 u32 state_size
= sizeof(SISLANDS_SMC_SWSTATE
);
5236 memset(smc_state
, 0, state_size
);
5238 ret
= si_populate_ulv_state(rdev
, smc_state
);
5240 ret
= si_copy_bytes_to_smc(rdev
, address
, (u8
*)smc_state
,
5241 state_size
, si_pi
->sram_end
);
5247 static int si_upload_smc_data(struct radeon_device
*rdev
)
5249 struct radeon_crtc
*radeon_crtc
= NULL
;
5252 if (rdev
->pm
.dpm
.new_active_crtc_count
== 0)
5255 for (i
= 0; i
< rdev
->num_crtc
; i
++) {
5256 if (rdev
->pm
.dpm
.new_active_crtcs
& (1 << i
)) {
5257 radeon_crtc
= rdev
->mode_info
.crtcs
[i
];
5262 if (radeon_crtc
== NULL
)
5265 if (radeon_crtc
->line_time
<= 0)
5268 if (si_write_smc_soft_register(rdev
,
5269 SI_SMC_SOFT_REGISTER_crtc_index
,
5270 radeon_crtc
->crtc_id
) != PPSMC_Result_OK
)
5273 if (si_write_smc_soft_register(rdev
,
5274 SI_SMC_SOFT_REGISTER_mclk_change_block_cp_min
,
5275 radeon_crtc
->wm_high
/ radeon_crtc
->line_time
) != PPSMC_Result_OK
)
5278 if (si_write_smc_soft_register(rdev
,
5279 SI_SMC_SOFT_REGISTER_mclk_change_block_cp_max
,
5280 radeon_crtc
->wm_low
/ radeon_crtc
->line_time
) != PPSMC_Result_OK
)
5286 static int si_set_mc_special_registers(struct radeon_device
*rdev
,
5287 struct si_mc_reg_table
*table
)
5289 struct rv7xx_power_info
*pi
= rv770_get_pi(rdev
);
5293 for (i
= 0, j
= table
->last
; i
< table
->last
; i
++) {
5294 if (j
>= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE
)
5296 switch (table
->mc_reg_address
[i
].s1
<< 2) {
5298 temp_reg
= RREG32(MC_PMG_CMD_EMRS
);
5299 table
->mc_reg_address
[j
].s1
= MC_PMG_CMD_EMRS
>> 2;
5300 table
->mc_reg_address
[j
].s0
= MC_SEQ_PMG_CMD_EMRS_LP
>> 2;
5301 for (k
= 0; k
< table
->num_entries
; k
++)
5302 table
->mc_reg_table_entry
[k
].mc_data
[j
] =
5303 ((temp_reg
& 0xffff0000)) |
5304 ((table
->mc_reg_table_entry
[k
].mc_data
[i
] & 0xffff0000) >> 16);
5306 if (j
>= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE
)
5309 temp_reg
= RREG32(MC_PMG_CMD_MRS
);
5310 table
->mc_reg_address
[j
].s1
= MC_PMG_CMD_MRS
>> 2;
5311 table
->mc_reg_address
[j
].s0
= MC_SEQ_PMG_CMD_MRS_LP
>> 2;
5312 for (k
= 0; k
< table
->num_entries
; k
++) {
5313 table
->mc_reg_table_entry
[k
].mc_data
[j
] =
5314 (temp_reg
& 0xffff0000) |
5315 (table
->mc_reg_table_entry
[k
].mc_data
[i
] & 0x0000ffff);
5317 table
->mc_reg_table_entry
[k
].mc_data
[j
] |= 0x100;
5320 if (j
>= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE
)
5323 if (!pi
->mem_gddr5
) {
5324 table
->mc_reg_address
[j
].s1
= MC_PMG_AUTO_CMD
>> 2;
5325 table
->mc_reg_address
[j
].s0
= MC_PMG_AUTO_CMD
>> 2;
5326 for (k
= 0; k
< table
->num_entries
; k
++)
5327 table
->mc_reg_table_entry
[k
].mc_data
[j
] =
5328 (table
->mc_reg_table_entry
[k
].mc_data
[i
] & 0xffff0000) >> 16;
5330 if (j
>= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE
)
5334 case MC_SEQ_RESERVE_M
:
5335 temp_reg
= RREG32(MC_PMG_CMD_MRS1
);
5336 table
->mc_reg_address
[j
].s1
= MC_PMG_CMD_MRS1
>> 2;
5337 table
->mc_reg_address
[j
].s0
= MC_SEQ_PMG_CMD_MRS1_LP
>> 2;
5338 for(k
= 0; k
< table
->num_entries
; k
++)
5339 table
->mc_reg_table_entry
[k
].mc_data
[j
] =
5340 (temp_reg
& 0xffff0000) |
5341 (table
->mc_reg_table_entry
[k
].mc_data
[i
] & 0x0000ffff);
5343 if (j
>= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE
)
5356 static bool si_check_s0_mc_reg_index(u16 in_reg
, u16
*out_reg
)
5361 case MC_SEQ_RAS_TIMING
>> 2:
5362 *out_reg
= MC_SEQ_RAS_TIMING_LP
>> 2;
5364 case MC_SEQ_CAS_TIMING
>> 2:
5365 *out_reg
= MC_SEQ_CAS_TIMING_LP
>> 2;
5367 case MC_SEQ_MISC_TIMING
>> 2:
5368 *out_reg
= MC_SEQ_MISC_TIMING_LP
>> 2;
5370 case MC_SEQ_MISC_TIMING2
>> 2:
5371 *out_reg
= MC_SEQ_MISC_TIMING2_LP
>> 2;
5373 case MC_SEQ_RD_CTL_D0
>> 2:
5374 *out_reg
= MC_SEQ_RD_CTL_D0_LP
>> 2;
5376 case MC_SEQ_RD_CTL_D1
>> 2:
5377 *out_reg
= MC_SEQ_RD_CTL_D1_LP
>> 2;
5379 case MC_SEQ_WR_CTL_D0
>> 2:
5380 *out_reg
= MC_SEQ_WR_CTL_D0_LP
>> 2;
5382 case MC_SEQ_WR_CTL_D1
>> 2:
5383 *out_reg
= MC_SEQ_WR_CTL_D1_LP
>> 2;
5385 case MC_PMG_CMD_EMRS
>> 2:
5386 *out_reg
= MC_SEQ_PMG_CMD_EMRS_LP
>> 2;
5388 case MC_PMG_CMD_MRS
>> 2:
5389 *out_reg
= MC_SEQ_PMG_CMD_MRS_LP
>> 2;
5391 case MC_PMG_CMD_MRS1
>> 2:
5392 *out_reg
= MC_SEQ_PMG_CMD_MRS1_LP
>> 2;
5394 case MC_SEQ_PMG_TIMING
>> 2:
5395 *out_reg
= MC_SEQ_PMG_TIMING_LP
>> 2;
5397 case MC_PMG_CMD_MRS2
>> 2:
5398 *out_reg
= MC_SEQ_PMG_CMD_MRS2_LP
>> 2;
5400 case MC_SEQ_WR_CTL_2
>> 2:
5401 *out_reg
= MC_SEQ_WR_CTL_2_LP
>> 2;
5411 static void si_set_valid_flag(struct si_mc_reg_table
*table
)
5415 for (i
= 0; i
< table
->last
; i
++) {
5416 for (j
= 1; j
< table
->num_entries
; j
++) {
5417 if (table
->mc_reg_table_entry
[j
-1].mc_data
[i
] != table
->mc_reg_table_entry
[j
].mc_data
[i
]) {
5418 table
->valid_flag
|= 1 << i
;
5425 static void si_set_s0_mc_reg_index(struct si_mc_reg_table
*table
)
5430 for (i
= 0; i
< table
->last
; i
++)
5431 table
->mc_reg_address
[i
].s0
= si_check_s0_mc_reg_index(table
->mc_reg_address
[i
].s1
, &address
) ?
5432 address
: table
->mc_reg_address
[i
].s1
;
5436 static int si_copy_vbios_mc_reg_table(struct atom_mc_reg_table
*table
,
5437 struct si_mc_reg_table
*si_table
)
5441 if (table
->last
> SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE
)
5443 if (table
->num_entries
> MAX_AC_TIMING_ENTRIES
)
5446 for (i
= 0; i
< table
->last
; i
++)
5447 si_table
->mc_reg_address
[i
].s1
= table
->mc_reg_address
[i
].s1
;
5448 si_table
->last
= table
->last
;
5450 for (i
= 0; i
< table
->num_entries
; i
++) {
5451 si_table
->mc_reg_table_entry
[i
].mclk_max
=
5452 table
->mc_reg_table_entry
[i
].mclk_max
;
5453 for (j
= 0; j
< table
->last
; j
++) {
5454 si_table
->mc_reg_table_entry
[i
].mc_data
[j
] =
5455 table
->mc_reg_table_entry
[i
].mc_data
[j
];
5458 si_table
->num_entries
= table
->num_entries
;
5463 static int si_initialize_mc_reg_table(struct radeon_device
*rdev
)
5465 struct si_power_info
*si_pi
= si_get_pi(rdev
);
5466 struct atom_mc_reg_table
*table
;
5467 struct si_mc_reg_table
*si_table
= &si_pi
->mc_reg_table
;
5468 u8 module_index
= rv770_get_memory_module_index(rdev
);
5471 table
= kzalloc(sizeof(struct atom_mc_reg_table
), GFP_KERNEL
);
5475 WREG32(MC_SEQ_RAS_TIMING_LP
, RREG32(MC_SEQ_RAS_TIMING
));
5476 WREG32(MC_SEQ_CAS_TIMING_LP
, RREG32(MC_SEQ_CAS_TIMING
));
5477 WREG32(MC_SEQ_MISC_TIMING_LP
, RREG32(MC_SEQ_MISC_TIMING
));
5478 WREG32(MC_SEQ_MISC_TIMING2_LP
, RREG32(MC_SEQ_MISC_TIMING2
));
5479 WREG32(MC_SEQ_PMG_CMD_EMRS_LP
, RREG32(MC_PMG_CMD_EMRS
));
5480 WREG32(MC_SEQ_PMG_CMD_MRS_LP
, RREG32(MC_PMG_CMD_MRS
));
5481 WREG32(MC_SEQ_PMG_CMD_MRS1_LP
, RREG32(MC_PMG_CMD_MRS1
));
5482 WREG32(MC_SEQ_WR_CTL_D0_LP
, RREG32(MC_SEQ_WR_CTL_D0
));
5483 WREG32(MC_SEQ_WR_CTL_D1_LP
, RREG32(MC_SEQ_WR_CTL_D1
));
5484 WREG32(MC_SEQ_RD_CTL_D0_LP
, RREG32(MC_SEQ_RD_CTL_D0
));
5485 WREG32(MC_SEQ_RD_CTL_D1_LP
, RREG32(MC_SEQ_RD_CTL_D1
));
5486 WREG32(MC_SEQ_PMG_TIMING_LP
, RREG32(MC_SEQ_PMG_TIMING
));
5487 WREG32(MC_SEQ_PMG_CMD_MRS2_LP
, RREG32(MC_PMG_CMD_MRS2
));
5488 WREG32(MC_SEQ_WR_CTL_2_LP
, RREG32(MC_SEQ_WR_CTL_2
));
5490 ret
= radeon_atom_init_mc_reg_table(rdev
, module_index
, table
);
5494 ret
= si_copy_vbios_mc_reg_table(table
, si_table
);
5498 si_set_s0_mc_reg_index(si_table
);
5500 ret
= si_set_mc_special_registers(rdev
, si_table
);
5504 si_set_valid_flag(si_table
);
5513 static void si_populate_mc_reg_addresses(struct radeon_device
*rdev
,
5514 SMC_SIslands_MCRegisters
*mc_reg_table
)
5516 struct si_power_info
*si_pi
= si_get_pi(rdev
);
5519 for (i
= 0, j
= 0; j
< si_pi
->mc_reg_table
.last
; j
++) {
5520 if (si_pi
->mc_reg_table
.valid_flag
& (1 << j
)) {
5521 if (i
>= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE
)
5523 mc_reg_table
->address
[i
].s0
=
5524 cpu_to_be16(si_pi
->mc_reg_table
.mc_reg_address
[j
].s0
);
5525 mc_reg_table
->address
[i
].s1
=
5526 cpu_to_be16(si_pi
->mc_reg_table
.mc_reg_address
[j
].s1
);
5530 mc_reg_table
->last
= (u8
)i
;
5533 static void si_convert_mc_registers(const struct si_mc_reg_entry
*entry
,
5534 SMC_SIslands_MCRegisterSet
*data
,
5535 u32 num_entries
, u32 valid_flag
)
5539 for(i
= 0, j
= 0; j
< num_entries
; j
++) {
5540 if (valid_flag
& (1 << j
)) {
5541 data
->value
[i
] = cpu_to_be32(entry
->mc_data
[j
]);
5547 static void si_convert_mc_reg_table_entry_to_smc(struct radeon_device
*rdev
,
5548 struct rv7xx_pl
*pl
,
5549 SMC_SIslands_MCRegisterSet
*mc_reg_table_data
)
5551 struct si_power_info
*si_pi
= si_get_pi(rdev
);
5554 for (i
= 0; i
< si_pi
->mc_reg_table
.num_entries
; i
++) {
5555 if (pl
->mclk
<= si_pi
->mc_reg_table
.mc_reg_table_entry
[i
].mclk_max
)
5559 if ((i
== si_pi
->mc_reg_table
.num_entries
) && (i
> 0))
5562 si_convert_mc_registers(&si_pi
->mc_reg_table
.mc_reg_table_entry
[i
],
5563 mc_reg_table_data
, si_pi
->mc_reg_table
.last
,
5564 si_pi
->mc_reg_table
.valid_flag
);
5567 static void si_convert_mc_reg_table_to_smc(struct radeon_device
*rdev
,
5568 struct radeon_ps
*radeon_state
,
5569 SMC_SIslands_MCRegisters
*mc_reg_table
)
5571 struct ni_ps
*state
= ni_get_ps(radeon_state
);
5574 for (i
= 0; i
< state
->performance_level_count
; i
++) {
5575 si_convert_mc_reg_table_entry_to_smc(rdev
,
5576 &state
->performance_levels
[i
],
5577 &mc_reg_table
->data
[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT
+ i
]);
5581 static int si_populate_mc_reg_table(struct radeon_device
*rdev
,
5582 struct radeon_ps
*radeon_boot_state
)
5584 struct ni_ps
*boot_state
= ni_get_ps(radeon_boot_state
);
5585 struct si_power_info
*si_pi
= si_get_pi(rdev
);
5586 struct si_ulv_param
*ulv
= &si_pi
->ulv
;
5587 SMC_SIslands_MCRegisters
*smc_mc_reg_table
= &si_pi
->smc_mc_reg_table
;
5589 memset(smc_mc_reg_table
, 0, sizeof(SMC_SIslands_MCRegisters
));
5591 si_write_smc_soft_register(rdev
, SI_SMC_SOFT_REGISTER_seq_index
, 1);
5593 si_populate_mc_reg_addresses(rdev
, smc_mc_reg_table
);
5595 si_convert_mc_reg_table_entry_to_smc(rdev
, &boot_state
->performance_levels
[0],
5596 &smc_mc_reg_table
->data
[SISLANDS_MCREGISTERTABLE_INITIAL_SLOT
]);
5598 si_convert_mc_registers(&si_pi
->mc_reg_table
.mc_reg_table_entry
[0],
5599 &smc_mc_reg_table
->data
[SISLANDS_MCREGISTERTABLE_ACPI_SLOT
],
5600 si_pi
->mc_reg_table
.last
,
5601 si_pi
->mc_reg_table
.valid_flag
);
5603 if (ulv
->supported
&& ulv
->pl
.vddc
!= 0)
5604 si_convert_mc_reg_table_entry_to_smc(rdev
, &ulv
->pl
,
5605 &smc_mc_reg_table
->data
[SISLANDS_MCREGISTERTABLE_ULV_SLOT
]);
5607 si_convert_mc_registers(&si_pi
->mc_reg_table
.mc_reg_table_entry
[0],
5608 &smc_mc_reg_table
->data
[SISLANDS_MCREGISTERTABLE_ULV_SLOT
],
5609 si_pi
->mc_reg_table
.last
,
5610 si_pi
->mc_reg_table
.valid_flag
);
5612 si_convert_mc_reg_table_to_smc(rdev
, radeon_boot_state
, smc_mc_reg_table
);
5614 return si_copy_bytes_to_smc(rdev
, si_pi
->mc_reg_table_start
,
5615 (u8
*)smc_mc_reg_table
,
5616 sizeof(SMC_SIslands_MCRegisters
), si_pi
->sram_end
);
5619 static int si_upload_mc_reg_table(struct radeon_device
*rdev
,
5620 struct radeon_ps
*radeon_new_state
)
5622 struct ni_ps
*new_state
= ni_get_ps(radeon_new_state
);
5623 struct si_power_info
*si_pi
= si_get_pi(rdev
);
5624 u32 address
= si_pi
->mc_reg_table_start
+
5625 offsetof(SMC_SIslands_MCRegisters
,
5626 data
[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT
]);
5627 SMC_SIslands_MCRegisters
*smc_mc_reg_table
= &si_pi
->smc_mc_reg_table
;
5629 memset(smc_mc_reg_table
, 0, sizeof(SMC_SIslands_MCRegisters
));
5631 si_convert_mc_reg_table_to_smc(rdev
, radeon_new_state
, smc_mc_reg_table
);
5634 return si_copy_bytes_to_smc(rdev
, address
,
5635 (u8
*)&smc_mc_reg_table
->data
[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT
],
5636 sizeof(SMC_SIslands_MCRegisterSet
) * new_state
->performance_level_count
,
5641 static void si_enable_voltage_control(struct radeon_device
*rdev
, bool enable
)
5644 WREG32_P(GENERAL_PWRMGT
, VOLT_PWRMGT_EN
, ~VOLT_PWRMGT_EN
);
5646 WREG32_P(GENERAL_PWRMGT
, 0, ~VOLT_PWRMGT_EN
);
5649 static enum radeon_pcie_gen
si_get_maximum_link_speed(struct radeon_device
*rdev
,
5650 struct radeon_ps
*radeon_state
)
5652 struct ni_ps
*state
= ni_get_ps(radeon_state
);
5654 u16 pcie_speed
, max_speed
= 0;
5656 for (i
= 0; i
< state
->performance_level_count
; i
++) {
5657 pcie_speed
= state
->performance_levels
[i
].pcie_gen
;
5658 if (max_speed
< pcie_speed
)
5659 max_speed
= pcie_speed
;
5664 static u16
si_get_current_pcie_speed(struct radeon_device
*rdev
)
5668 speed_cntl
= RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL
) & LC_CURRENT_DATA_RATE_MASK
;
5669 speed_cntl
>>= LC_CURRENT_DATA_RATE_SHIFT
;
5671 return (u16
)speed_cntl
;
5674 static void si_request_link_speed_change_before_state_change(struct radeon_device
*rdev
,
5675 struct radeon_ps
*radeon_new_state
,
5676 struct radeon_ps
*radeon_current_state
)
5678 struct si_power_info
*si_pi
= si_get_pi(rdev
);
5679 enum radeon_pcie_gen target_link_speed
= si_get_maximum_link_speed(rdev
, radeon_new_state
);
5680 enum radeon_pcie_gen current_link_speed
;
5682 if (si_pi
->force_pcie_gen
== RADEON_PCIE_GEN_INVALID
)
5683 current_link_speed
= si_get_maximum_link_speed(rdev
, radeon_current_state
);
5685 current_link_speed
= si_pi
->force_pcie_gen
;
5687 si_pi
->force_pcie_gen
= RADEON_PCIE_GEN_INVALID
;
5688 si_pi
->pspp_notify_required
= false;
5689 if (target_link_speed
> current_link_speed
) {
5690 switch (target_link_speed
) {
5691 #if defined(CONFIG_ACPI)
5692 case RADEON_PCIE_GEN3
:
5693 if (radeon_acpi_pcie_performance_request(rdev
, PCIE_PERF_REQ_PECI_GEN3
, false) == 0)
5695 si_pi
->force_pcie_gen
= RADEON_PCIE_GEN2
;
5696 if (current_link_speed
== RADEON_PCIE_GEN2
)
5698 case RADEON_PCIE_GEN2
:
5699 if (radeon_acpi_pcie_performance_request(rdev
, PCIE_PERF_REQ_PECI_GEN2
, false) == 0)
5703 si_pi
->force_pcie_gen
= si_get_current_pcie_speed(rdev
);
5707 if (target_link_speed
< current_link_speed
)
5708 si_pi
->pspp_notify_required
= true;
5712 static void si_notify_link_speed_change_after_state_change(struct radeon_device
*rdev
,
5713 struct radeon_ps
*radeon_new_state
,
5714 struct radeon_ps
*radeon_current_state
)
5716 struct si_power_info
*si_pi
= si_get_pi(rdev
);
5717 enum radeon_pcie_gen target_link_speed
= si_get_maximum_link_speed(rdev
, radeon_new_state
);
5720 if (si_pi
->pspp_notify_required
) {
5721 if (target_link_speed
== RADEON_PCIE_GEN3
)
5722 request
= PCIE_PERF_REQ_PECI_GEN3
;
5723 else if (target_link_speed
== RADEON_PCIE_GEN2
)
5724 request
= PCIE_PERF_REQ_PECI_GEN2
;
5726 request
= PCIE_PERF_REQ_PECI_GEN1
;
5728 if ((request
== PCIE_PERF_REQ_PECI_GEN1
) &&
5729 (si_get_current_pcie_speed(rdev
) > 0))
5732 #if defined(CONFIG_ACPI)
5733 radeon_acpi_pcie_performance_request(rdev
, request
, false);
5739 static int si_ds_request(struct radeon_device
*rdev
,
5740 bool ds_status_on
, u32 count_write
)
5742 struct evergreen_power_info
*eg_pi
= evergreen_get_pi(rdev
);
5744 if (eg_pi
->sclk_deep_sleep
) {
5746 return (si_send_msg_to_smc(rdev
, PPSMC_MSG_CancelThrottleOVRDSCLKDS
) ==
5750 return (si_send_msg_to_smc(rdev
, PPSMC_MSG_ThrottleOVRDSCLKDS
) ==
5751 PPSMC_Result_OK
) ? 0 : -EINVAL
;
5757 static void si_set_max_cu_value(struct radeon_device
*rdev
)
5759 struct si_power_info
*si_pi
= si_get_pi(rdev
);
5761 if (rdev
->family
== CHIP_VERDE
) {
5762 switch (rdev
->pdev
->device
) {
5798 static int si_patch_single_dependency_table_based_on_leakage(struct radeon_device
*rdev
,
5799 struct radeon_clock_voltage_dependency_table
*table
)
5803 u16 leakage_voltage
;
5806 for (i
= 0; i
< table
->count
; i
++) {
5807 switch (si_get_leakage_voltage_from_leakage_index(rdev
,
5808 table
->entries
[i
].v
,
5809 &leakage_voltage
)) {
5811 table
->entries
[i
].v
= leakage_voltage
;
5821 for (j
= (table
->count
- 2); j
>= 0; j
--) {
5822 table
->entries
[j
].v
= (table
->entries
[j
].v
<= table
->entries
[j
+ 1].v
) ?
5823 table
->entries
[j
].v
: table
->entries
[j
+ 1].v
;
5829 static int si_patch_dependency_tables_based_on_leakage(struct radeon_device
*rdev
)
5833 ret
= si_patch_single_dependency_table_based_on_leakage(rdev
,
5834 &rdev
->pm
.dpm
.dyn_state
.vddc_dependency_on_sclk
);
5835 ret
= si_patch_single_dependency_table_based_on_leakage(rdev
,
5836 &rdev
->pm
.dpm
.dyn_state
.vddc_dependency_on_mclk
);
5837 ret
= si_patch_single_dependency_table_based_on_leakage(rdev
,
5838 &rdev
->pm
.dpm
.dyn_state
.vddci_dependency_on_mclk
);
5842 static void si_set_pcie_lane_width_in_smc(struct radeon_device
*rdev
,
5843 struct radeon_ps
*radeon_new_state
,
5844 struct radeon_ps
*radeon_current_state
)
5847 u32 new_lane_width
=
5848 (radeon_new_state
->caps
& ATOM_PPLIB_PCIE_LINK_WIDTH_MASK
) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT
;
5849 u32 current_lane_width
=
5850 (radeon_current_state
->caps
& ATOM_PPLIB_PCIE_LINK_WIDTH_MASK
) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT
;
5852 if (new_lane_width
!= current_lane_width
) {
5853 radeon_set_pcie_lanes(rdev
, new_lane_width
);
5854 lane_width
= radeon_get_pcie_lanes(rdev
);
5855 si_write_smc_soft_register(rdev
, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width
, lane_width
);
5859 void si_dpm_setup_asic(struct radeon_device
*rdev
)
5863 r
= si_mc_load_microcode(rdev
);
5865 DRM_ERROR("Failed to load MC firmware!\n");
5866 rv770_get_memory_type(rdev
);
5867 si_read_clock_registers(rdev
);
5868 si_enable_acpi_power_management(rdev
);
5871 static int si_thermal_enable_alert(struct radeon_device
*rdev
,
5874 u32 thermal_int
= RREG32(CG_THERMAL_INT
);
5877 PPSMC_Result result
;
5879 thermal_int
&= ~(THERM_INT_MASK_HIGH
| THERM_INT_MASK_LOW
);
5880 WREG32(CG_THERMAL_INT
, thermal_int
);
5881 rdev
->irq
.dpm_thermal
= false;
5882 result
= si_send_msg_to_smc(rdev
, PPSMC_MSG_EnableThermalInterrupt
);
5883 if (result
!= PPSMC_Result_OK
) {
5884 DRM_DEBUG_KMS("Could not enable thermal interrupts.\n");
5888 thermal_int
|= THERM_INT_MASK_HIGH
| THERM_INT_MASK_LOW
;
5889 WREG32(CG_THERMAL_INT
, thermal_int
);
5890 rdev
->irq
.dpm_thermal
= true;
5896 static int si_thermal_set_temperature_range(struct radeon_device
*rdev
,
5897 int min_temp
, int max_temp
)
5899 int low_temp
= 0 * 1000;
5900 int high_temp
= 255 * 1000;
5902 if (low_temp
< min_temp
)
5903 low_temp
= min_temp
;
5904 if (high_temp
> max_temp
)
5905 high_temp
= max_temp
;
5906 if (high_temp
< low_temp
) {
5907 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp
, high_temp
);
5911 WREG32_P(CG_THERMAL_INT
, DIG_THERM_INTH(high_temp
/ 1000), ~DIG_THERM_INTH_MASK
);
5912 WREG32_P(CG_THERMAL_INT
, DIG_THERM_INTL(low_temp
/ 1000), ~DIG_THERM_INTL_MASK
);
5913 WREG32_P(CG_THERMAL_CTRL
, DIG_THERM_DPM(high_temp
/ 1000), ~DIG_THERM_DPM_MASK
);
5915 rdev
->pm
.dpm
.thermal
.min_temp
= low_temp
;
5916 rdev
->pm
.dpm
.thermal
.max_temp
= high_temp
;
5921 static void si_fan_ctrl_set_static_mode(struct radeon_device
*rdev
, u32 mode
)
5923 struct si_power_info
*si_pi
= si_get_pi(rdev
);
5926 if (si_pi
->fan_ctrl_is_in_default_mode
) {
5927 tmp
= (RREG32(CG_FDO_CTRL2
) & FDO_PWM_MODE_MASK
) >> FDO_PWM_MODE_SHIFT
;
5928 si_pi
->fan_ctrl_default_mode
= tmp
;
5929 tmp
= (RREG32(CG_FDO_CTRL2
) & TMIN_MASK
) >> TMIN_SHIFT
;
5931 si_pi
->fan_ctrl_is_in_default_mode
= false;
5934 tmp
= RREG32(CG_FDO_CTRL2
) & ~TMIN_MASK
;
5936 WREG32(CG_FDO_CTRL2
, tmp
);
5938 tmp
= RREG32(CG_FDO_CTRL2
) & ~FDO_PWM_MODE_MASK
;
5939 tmp
|= FDO_PWM_MODE(mode
);
5940 WREG32(CG_FDO_CTRL2
, tmp
);
5943 static int si_thermal_setup_fan_table(struct radeon_device
*rdev
)
5945 struct si_power_info
*si_pi
= si_get_pi(rdev
);
5946 PP_SIslands_FanTable fan_table
= { FDO_MODE_HARDWARE
};
5948 u32 t_diff1
, t_diff2
, pwm_diff1
, pwm_diff2
;
5949 u16 fdo_min
, slope1
, slope2
;
5950 u32 reference_clock
, tmp
;
5954 if (!si_pi
->fan_table_start
) {
5955 rdev
->pm
.dpm
.fan
.ucode_fan_control
= false;
5959 duty100
= (RREG32(CG_FDO_CTRL1
) & FMAX_DUTY100_MASK
) >> FMAX_DUTY100_SHIFT
;
5962 rdev
->pm
.dpm
.fan
.ucode_fan_control
= false;
5966 tmp64
= (u64
)rdev
->pm
.dpm
.fan
.pwm_min
* duty100
;
5967 do_div(tmp64
, 10000);
5968 fdo_min
= (u16
)tmp64
;
5970 t_diff1
= rdev
->pm
.dpm
.fan
.t_med
- rdev
->pm
.dpm
.fan
.t_min
;
5971 t_diff2
= rdev
->pm
.dpm
.fan
.t_high
- rdev
->pm
.dpm
.fan
.t_med
;
5973 pwm_diff1
= rdev
->pm
.dpm
.fan
.pwm_med
- rdev
->pm
.dpm
.fan
.pwm_min
;
5974 pwm_diff2
= rdev
->pm
.dpm
.fan
.pwm_high
- rdev
->pm
.dpm
.fan
.pwm_med
;
5976 slope1
= (u16
)((50 + ((16 * duty100
* pwm_diff1
) / t_diff1
)) / 100);
5977 slope2
= (u16
)((50 + ((16 * duty100
* pwm_diff2
) / t_diff2
)) / 100);
5979 fan_table
.slope1
= cpu_to_be16(slope1
);
5980 fan_table
.slope2
= cpu_to_be16(slope2
);
5982 fan_table
.fdo_min
= cpu_to_be16(fdo_min
);
5984 fan_table
.hys_down
= cpu_to_be16(rdev
->pm
.dpm
.fan
.t_hyst
);
5986 fan_table
.hys_up
= cpu_to_be16(1);
5988 fan_table
.hys_slope
= cpu_to_be16(1);
5990 fan_table
.temp_resp_lim
= cpu_to_be16(5);
5992 reference_clock
= radeon_get_xclk(rdev
);
5994 fan_table
.refresh_period
= cpu_to_be32((rdev
->pm
.dpm
.fan
.cycle_delay
*
5995 reference_clock
) / 1600);
5997 fan_table
.fdo_max
= cpu_to_be16((u16
)duty100
);
5999 tmp
= (RREG32(CG_MULT_THERMAL_CTRL
) & TEMP_SEL_MASK
) >> TEMP_SEL_SHIFT
;
6000 fan_table
.temp_src
= (uint8_t)tmp
;
6002 ret
= si_copy_bytes_to_smc(rdev
,
6003 si_pi
->fan_table_start
,
6009 DRM_ERROR("Failed to load fan table to the SMC.");
6010 rdev
->pm
.dpm
.fan
.ucode_fan_control
= false;
6016 static int si_fan_ctrl_start_smc_fan_control(struct radeon_device
*rdev
)
6018 struct si_power_info
*si_pi
= si_get_pi(rdev
);
6021 ret
= si_send_msg_to_smc(rdev
, PPSMC_StartFanControl
);
6022 if (ret
== PPSMC_Result_OK
) {
6023 si_pi
->fan_is_controlled_by_smc
= true;
6030 static int si_fan_ctrl_stop_smc_fan_control(struct radeon_device
*rdev
)
6032 struct si_power_info
*si_pi
= si_get_pi(rdev
);
6035 ret
= si_send_msg_to_smc(rdev
, PPSMC_StopFanControl
);
6037 if (ret
== PPSMC_Result_OK
) {
6038 si_pi
->fan_is_controlled_by_smc
= false;
6045 int si_fan_ctrl_get_fan_speed_percent(struct radeon_device
*rdev
,
6048 struct si_power_info
*si_pi
= si_get_pi(rdev
);
6052 if (rdev
->pm
.no_fan
)
6055 if (si_pi
->fan_is_controlled_by_smc
)
6058 duty100
= (RREG32(CG_FDO_CTRL1
) & FMAX_DUTY100_MASK
) >> FMAX_DUTY100_SHIFT
;
6059 duty
= (RREG32(CG_THERMAL_STATUS
) & FDO_PWM_DUTY_MASK
) >> FDO_PWM_DUTY_SHIFT
;
6064 tmp64
= (u64
)duty
* 100;
6065 do_div(tmp64
, duty100
);
6066 *speed
= (u32
)tmp64
;
6074 int si_fan_ctrl_set_fan_speed_percent(struct radeon_device
*rdev
,
6081 if (rdev
->pm
.no_fan
)
6087 duty100
= (RREG32(CG_FDO_CTRL1
) & FMAX_DUTY100_MASK
) >> FMAX_DUTY100_SHIFT
;
6092 tmp64
= (u64
)speed
* duty100
;
6096 tmp
= RREG32(CG_FDO_CTRL0
) & ~FDO_STATIC_DUTY_MASK
;
6097 tmp
|= FDO_STATIC_DUTY(duty
);
6098 WREG32(CG_FDO_CTRL0
, tmp
);
6103 void si_fan_ctrl_set_mode(struct radeon_device
*rdev
, u32 mode
)
6106 /* stop auto-manage */
6107 if (rdev
->pm
.dpm
.fan
.ucode_fan_control
)
6108 si_fan_ctrl_stop_smc_fan_control(rdev
);
6109 si_fan_ctrl_set_static_mode(rdev
, mode
);
6111 /* restart auto-manage */
6112 if (rdev
->pm
.dpm
.fan
.ucode_fan_control
)
6113 si_thermal_start_smc_fan_control(rdev
);
6115 si_fan_ctrl_set_default_mode(rdev
);
6119 u32
si_fan_ctrl_get_mode(struct radeon_device
*rdev
)
6121 struct si_power_info
*si_pi
= si_get_pi(rdev
);
6124 if (si_pi
->fan_is_controlled_by_smc
)
6127 tmp
= RREG32(CG_FDO_CTRL2
) & FDO_PWM_MODE_MASK
;
6128 return (tmp
>> FDO_PWM_MODE_SHIFT
);
6132 static int si_fan_ctrl_get_fan_speed_rpm(struct radeon_device
*rdev
,
6136 u32 xclk
= radeon_get_xclk(rdev
);
6138 if (rdev
->pm
.no_fan
)
6141 if (rdev
->pm
.fan_pulses_per_revolution
== 0)
6144 tach_period
= (RREG32(CG_TACH_STATUS
) & TACH_PERIOD_MASK
) >> TACH_PERIOD_SHIFT
;
6145 if (tach_period
== 0)
6148 *speed
= 60 * xclk
* 10000 / tach_period
;
6153 static int si_fan_ctrl_set_fan_speed_rpm(struct radeon_device
*rdev
,
6156 u32 tach_period
, tmp
;
6157 u32 xclk
= radeon_get_xclk(rdev
);
6159 if (rdev
->pm
.no_fan
)
6162 if (rdev
->pm
.fan_pulses_per_revolution
== 0)
6165 if ((speed
< rdev
->pm
.fan_min_rpm
) ||
6166 (speed
> rdev
->pm
.fan_max_rpm
))
6169 if (rdev
->pm
.dpm
.fan
.ucode_fan_control
)
6170 si_fan_ctrl_stop_smc_fan_control(rdev
);
6172 tach_period
= 60 * xclk
* 10000 / (8 * speed
);
6173 tmp
= RREG32(CG_TACH_CTRL
) & ~TARGET_PERIOD_MASK
;
6174 tmp
|= TARGET_PERIOD(tach_period
);
6175 WREG32(CG_TACH_CTRL
, tmp
);
6177 si_fan_ctrl_set_static_mode(rdev
, FDO_PWM_MODE_STATIC_RPM
);
6183 static void si_fan_ctrl_set_default_mode(struct radeon_device
*rdev
)
6185 struct si_power_info
*si_pi
= si_get_pi(rdev
);
6188 if (!si_pi
->fan_ctrl_is_in_default_mode
) {
6189 tmp
= RREG32(CG_FDO_CTRL2
) & ~FDO_PWM_MODE_MASK
;
6190 tmp
|= FDO_PWM_MODE(si_pi
->fan_ctrl_default_mode
);
6191 WREG32(CG_FDO_CTRL2
, tmp
);
6193 tmp
= RREG32(CG_FDO_CTRL2
) & ~TMIN_MASK
;
6194 tmp
|= TMIN(si_pi
->t_min
);
6195 WREG32(CG_FDO_CTRL2
, tmp
);
6196 si_pi
->fan_ctrl_is_in_default_mode
= true;
6200 static void si_thermal_start_smc_fan_control(struct radeon_device
*rdev
)
6202 if (rdev
->pm
.dpm
.fan
.ucode_fan_control
) {
6203 si_fan_ctrl_start_smc_fan_control(rdev
);
6204 si_fan_ctrl_set_static_mode(rdev
, FDO_PWM_MODE_STATIC
);
6208 static void si_thermal_initialize(struct radeon_device
*rdev
)
6212 if (rdev
->pm
.fan_pulses_per_revolution
) {
6213 tmp
= RREG32(CG_TACH_CTRL
) & ~EDGE_PER_REV_MASK
;
6214 tmp
|= EDGE_PER_REV(rdev
->pm
.fan_pulses_per_revolution
-1);
6215 WREG32(CG_TACH_CTRL
, tmp
);
6218 tmp
= RREG32(CG_FDO_CTRL2
) & ~TACH_PWM_RESP_RATE_MASK
;
6219 tmp
|= TACH_PWM_RESP_RATE(0x28);
6220 WREG32(CG_FDO_CTRL2
, tmp
);
6223 static int si_thermal_start_thermal_controller(struct radeon_device
*rdev
)
6227 si_thermal_initialize(rdev
);
6228 ret
= si_thermal_set_temperature_range(rdev
, R600_TEMP_RANGE_MIN
, R600_TEMP_RANGE_MAX
);
6231 ret
= si_thermal_enable_alert(rdev
, true);
6234 if (rdev
->pm
.dpm
.fan
.ucode_fan_control
) {
6235 ret
= si_halt_smc(rdev
);
6238 ret
= si_thermal_setup_fan_table(rdev
);
6241 ret
= si_resume_smc(rdev
);
6244 si_thermal_start_smc_fan_control(rdev
);
6250 static void si_thermal_stop_thermal_controller(struct radeon_device
*rdev
)
6252 if (!rdev
->pm
.no_fan
) {
6253 si_fan_ctrl_set_default_mode(rdev
);
6254 si_fan_ctrl_stop_smc_fan_control(rdev
);
6258 int si_dpm_enable(struct radeon_device
*rdev
)
6260 struct rv7xx_power_info
*pi
= rv770_get_pi(rdev
);
6261 struct evergreen_power_info
*eg_pi
= evergreen_get_pi(rdev
);
6262 struct si_power_info
*si_pi
= si_get_pi(rdev
);
6263 struct radeon_ps
*boot_ps
= rdev
->pm
.dpm
.boot_ps
;
6266 if (si_is_smc_running(rdev
))
6268 if (pi
->voltage_control
|| si_pi
->voltage_control_svi2
)
6269 si_enable_voltage_control(rdev
, true);
6270 if (pi
->mvdd_control
)
6271 si_get_mvdd_configuration(rdev
);
6272 if (pi
->voltage_control
|| si_pi
->voltage_control_svi2
) {
6273 ret
= si_construct_voltage_tables(rdev
);
6275 DRM_ERROR("si_construct_voltage_tables failed\n");
6279 if (eg_pi
->dynamic_ac_timing
) {
6280 ret
= si_initialize_mc_reg_table(rdev
);
6282 eg_pi
->dynamic_ac_timing
= false;
6285 si_enable_spread_spectrum(rdev
, true);
6286 if (pi
->thermal_protection
)
6287 si_enable_thermal_protection(rdev
, true);
6289 si_program_git(rdev
);
6290 si_program_tp(rdev
);
6291 si_program_tpp(rdev
);
6292 si_program_sstp(rdev
);
6293 si_enable_display_gap(rdev
);
6294 si_program_vc(rdev
);
6295 ret
= si_upload_firmware(rdev
);
6297 DRM_ERROR("si_upload_firmware failed\n");
6300 ret
= si_process_firmware_header(rdev
);
6302 DRM_ERROR("si_process_firmware_header failed\n");
6305 ret
= si_initial_switch_from_arb_f0_to_f1(rdev
);
6307 DRM_ERROR("si_initial_switch_from_arb_f0_to_f1 failed\n");
6310 ret
= si_init_smc_table(rdev
);
6312 DRM_ERROR("si_init_smc_table failed\n");
6315 ret
= si_init_smc_spll_table(rdev
);
6317 DRM_ERROR("si_init_smc_spll_table failed\n");
6320 ret
= si_init_arb_table_index(rdev
);
6322 DRM_ERROR("si_init_arb_table_index failed\n");
6325 if (eg_pi
->dynamic_ac_timing
) {
6326 ret
= si_populate_mc_reg_table(rdev
, boot_ps
);
6328 DRM_ERROR("si_populate_mc_reg_table failed\n");
6332 ret
= si_initialize_smc_cac_tables(rdev
);
6334 DRM_ERROR("si_initialize_smc_cac_tables failed\n");
6337 ret
= si_initialize_hardware_cac_manager(rdev
);
6339 DRM_ERROR("si_initialize_hardware_cac_manager failed\n");
6342 ret
= si_initialize_smc_dte_tables(rdev
);
6344 DRM_ERROR("si_initialize_smc_dte_tables failed\n");
6347 ret
= si_populate_smc_tdp_limits(rdev
, boot_ps
);
6349 DRM_ERROR("si_populate_smc_tdp_limits failed\n");
6352 ret
= si_populate_smc_tdp_limits_2(rdev
, boot_ps
);
6354 DRM_ERROR("si_populate_smc_tdp_limits_2 failed\n");
6357 si_program_response_times(rdev
);
6358 si_program_ds_registers(rdev
);
6359 si_dpm_start_smc(rdev
);
6360 ret
= si_notify_smc_display_change(rdev
, false);
6362 DRM_ERROR("si_notify_smc_display_change failed\n");
6365 si_enable_sclk_control(rdev
, true);
6368 si_enable_auto_throttle_source(rdev
, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL
, true);
6370 si_thermal_start_thermal_controller(rdev
);
6372 ni_update_current_ps(rdev
, boot_ps
);
6377 static int si_set_temperature_range(struct radeon_device
*rdev
)
6381 ret
= si_thermal_enable_alert(rdev
, false);
6384 ret
= si_thermal_set_temperature_range(rdev
, R600_TEMP_RANGE_MIN
, R600_TEMP_RANGE_MAX
);
6387 ret
= si_thermal_enable_alert(rdev
, true);
6394 int si_dpm_late_enable(struct radeon_device
*rdev
)
6398 ret
= si_set_temperature_range(rdev
);
6405 void si_dpm_disable(struct radeon_device
*rdev
)
6407 struct rv7xx_power_info
*pi
= rv770_get_pi(rdev
);
6408 struct radeon_ps
*boot_ps
= rdev
->pm
.dpm
.boot_ps
;
6410 if (!si_is_smc_running(rdev
))
6412 si_thermal_stop_thermal_controller(rdev
);
6413 si_disable_ulv(rdev
);
6415 if (pi
->thermal_protection
)
6416 si_enable_thermal_protection(rdev
, false);
6417 si_enable_power_containment(rdev
, boot_ps
, false);
6418 si_enable_smc_cac(rdev
, boot_ps
, false);
6419 si_enable_spread_spectrum(rdev
, false);
6420 si_enable_auto_throttle_source(rdev
, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL
, false);
6422 si_reset_to_default(rdev
);
6423 si_dpm_stop_smc(rdev
);
6424 si_force_switch_to_arb_f0(rdev
);
6426 ni_update_current_ps(rdev
, boot_ps
);
6429 int si_dpm_pre_set_power_state(struct radeon_device
*rdev
)
6431 struct evergreen_power_info
*eg_pi
= evergreen_get_pi(rdev
);
6432 struct radeon_ps requested_ps
= *rdev
->pm
.dpm
.requested_ps
;
6433 struct radeon_ps
*new_ps
= &requested_ps
;
6435 ni_update_requested_ps(rdev
, new_ps
);
6437 si_apply_state_adjust_rules(rdev
, &eg_pi
->requested_rps
);
6442 static int si_power_control_set_level(struct radeon_device
*rdev
)
6444 struct radeon_ps
*new_ps
= rdev
->pm
.dpm
.requested_ps
;
6447 ret
= si_restrict_performance_levels_before_switch(rdev
);
6450 ret
= si_halt_smc(rdev
);
6453 ret
= si_populate_smc_tdp_limits(rdev
, new_ps
);
6456 ret
= si_populate_smc_tdp_limits_2(rdev
, new_ps
);
6459 ret
= si_resume_smc(rdev
);
6462 ret
= si_set_sw_state(rdev
);
6468 int si_dpm_set_power_state(struct radeon_device
*rdev
)
6470 struct evergreen_power_info
*eg_pi
= evergreen_get_pi(rdev
);
6471 struct radeon_ps
*new_ps
= &eg_pi
->requested_rps
;
6472 struct radeon_ps
*old_ps
= &eg_pi
->current_rps
;
6475 ret
= si_disable_ulv(rdev
);
6477 DRM_ERROR("si_disable_ulv failed\n");
6480 ret
= si_restrict_performance_levels_before_switch(rdev
);
6482 DRM_ERROR("si_restrict_performance_levels_before_switch failed\n");
6485 if (eg_pi
->pcie_performance_request
)
6486 si_request_link_speed_change_before_state_change(rdev
, new_ps
, old_ps
);
6487 ni_set_uvd_clock_before_set_eng_clock(rdev
, new_ps
, old_ps
);
6488 ret
= si_enable_power_containment(rdev
, new_ps
, false);
6490 DRM_ERROR("si_enable_power_containment failed\n");
6493 ret
= si_enable_smc_cac(rdev
, new_ps
, false);
6495 DRM_ERROR("si_enable_smc_cac failed\n");
6498 ret
= si_halt_smc(rdev
);
6500 DRM_ERROR("si_halt_smc failed\n");
6503 ret
= si_upload_sw_state(rdev
, new_ps
);
6505 DRM_ERROR("si_upload_sw_state failed\n");
6508 ret
= si_upload_smc_data(rdev
);
6510 DRM_ERROR("si_upload_smc_data failed\n");
6513 ret
= si_upload_ulv_state(rdev
);
6515 DRM_ERROR("si_upload_ulv_state failed\n");
6518 if (eg_pi
->dynamic_ac_timing
) {
6519 ret
= si_upload_mc_reg_table(rdev
, new_ps
);
6521 DRM_ERROR("si_upload_mc_reg_table failed\n");
6525 ret
= si_program_memory_timing_parameters(rdev
, new_ps
);
6527 DRM_ERROR("si_program_memory_timing_parameters failed\n");
6530 si_set_pcie_lane_width_in_smc(rdev
, new_ps
, old_ps
);
6532 ret
= si_resume_smc(rdev
);
6534 DRM_ERROR("si_resume_smc failed\n");
6537 ret
= si_set_sw_state(rdev
);
6539 DRM_ERROR("si_set_sw_state failed\n");
6542 ni_set_uvd_clock_after_set_eng_clock(rdev
, new_ps
, old_ps
);
6543 if (eg_pi
->pcie_performance_request
)
6544 si_notify_link_speed_change_after_state_change(rdev
, new_ps
, old_ps
);
6545 ret
= si_set_power_state_conditionally_enable_ulv(rdev
, new_ps
);
6547 DRM_ERROR("si_set_power_state_conditionally_enable_ulv failed\n");
6550 ret
= si_enable_smc_cac(rdev
, new_ps
, true);
6552 DRM_ERROR("si_enable_smc_cac failed\n");
6555 ret
= si_enable_power_containment(rdev
, new_ps
, true);
6557 DRM_ERROR("si_enable_power_containment failed\n");
6561 ret
= si_power_control_set_level(rdev
);
6563 DRM_ERROR("si_power_control_set_level failed\n");
6570 void si_dpm_post_set_power_state(struct radeon_device
*rdev
)
6572 struct evergreen_power_info
*eg_pi
= evergreen_get_pi(rdev
);
6573 struct radeon_ps
*new_ps
= &eg_pi
->requested_rps
;
6575 ni_update_current_ps(rdev
, new_ps
);
6579 void si_dpm_reset_asic(struct radeon_device
*rdev
)
6581 si_restrict_performance_levels_before_switch(rdev
);
6582 si_disable_ulv(rdev
);
6583 si_set_boot_state(rdev
);
6586 void si_dpm_display_configuration_changed(struct radeon_device
*rdev
)
6588 si_program_display_gap(rdev
);
6592 struct _ATOM_POWERPLAY_INFO info
;
6593 struct _ATOM_POWERPLAY_INFO_V2 info_2
;
6594 struct _ATOM_POWERPLAY_INFO_V3 info_3
;
6595 struct _ATOM_PPLIB_POWERPLAYTABLE pplib
;
6596 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2
;
6597 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3
;
6600 union pplib_clock_info
{
6601 struct _ATOM_PPLIB_R600_CLOCK_INFO r600
;
6602 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780
;
6603 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen
;
6604 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo
;
6605 struct _ATOM_PPLIB_SI_CLOCK_INFO si
;
6608 union pplib_power_state
{
6609 struct _ATOM_PPLIB_STATE v1
;
6610 struct _ATOM_PPLIB_STATE_V2 v2
;
6613 static void si_parse_pplib_non_clock_info(struct radeon_device
*rdev
,
6614 struct radeon_ps
*rps
,
6615 struct _ATOM_PPLIB_NONCLOCK_INFO
*non_clock_info
,
6618 rps
->caps
= le32_to_cpu(non_clock_info
->ulCapsAndSettings
);
6619 rps
->class = le16_to_cpu(non_clock_info
->usClassification
);
6620 rps
->class2
= le16_to_cpu(non_clock_info
->usClassification2
);
6622 if (ATOM_PPLIB_NONCLOCKINFO_VER1
< table_rev
) {
6623 rps
->vclk
= le32_to_cpu(non_clock_info
->ulVCLK
);
6624 rps
->dclk
= le32_to_cpu(non_clock_info
->ulDCLK
);
6625 } else if (r600_is_uvd_state(rps
->class, rps
->class2
)) {
6626 rps
->vclk
= RV770_DEFAULT_VCLK_FREQ
;
6627 rps
->dclk
= RV770_DEFAULT_DCLK_FREQ
;
6633 if (rps
->class & ATOM_PPLIB_CLASSIFICATION_BOOT
)
6634 rdev
->pm
.dpm
.boot_ps
= rps
;
6635 if (rps
->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE
)
6636 rdev
->pm
.dpm
.uvd_ps
= rps
;
6639 static void si_parse_pplib_clock_info(struct radeon_device
*rdev
,
6640 struct radeon_ps
*rps
, int index
,
6641 union pplib_clock_info
*clock_info
)
6643 struct rv7xx_power_info
*pi
= rv770_get_pi(rdev
);
6644 struct evergreen_power_info
*eg_pi
= evergreen_get_pi(rdev
);
6645 struct si_power_info
*si_pi
= si_get_pi(rdev
);
6646 struct ni_ps
*ps
= ni_get_ps(rps
);
6647 u16 leakage_voltage
;
6648 struct rv7xx_pl
*pl
= &ps
->performance_levels
[index
];
6651 ps
->performance_level_count
= index
+ 1;
6653 pl
->sclk
= le16_to_cpu(clock_info
->si
.usEngineClockLow
);
6654 pl
->sclk
|= clock_info
->si
.ucEngineClockHigh
<< 16;
6655 pl
->mclk
= le16_to_cpu(clock_info
->si
.usMemoryClockLow
);
6656 pl
->mclk
|= clock_info
->si
.ucMemoryClockHigh
<< 16;
6658 pl
->vddc
= le16_to_cpu(clock_info
->si
.usVDDC
);
6659 pl
->vddci
= le16_to_cpu(clock_info
->si
.usVDDCI
);
6660 pl
->flags
= le32_to_cpu(clock_info
->si
.ulFlags
);
6661 pl
->pcie_gen
= r600_get_pcie_gen_support(rdev
,
6662 si_pi
->sys_pcie_mask
,
6663 si_pi
->boot_pcie_gen
,
6664 clock_info
->si
.ucPCIEGen
);
6666 /* patch up vddc if necessary */
6667 ret
= si_get_leakage_voltage_from_leakage_index(rdev
, pl
->vddc
,
6670 pl
->vddc
= leakage_voltage
;
6672 if (rps
->class & ATOM_PPLIB_CLASSIFICATION_ACPI
) {
6673 pi
->acpi_vddc
= pl
->vddc
;
6674 eg_pi
->acpi_vddci
= pl
->vddci
;
6675 si_pi
->acpi_pcie_gen
= pl
->pcie_gen
;
6678 if ((rps
->class2
& ATOM_PPLIB_CLASSIFICATION2_ULV
) &&
6680 /* XXX disable for A0 tahiti */
6681 si_pi
->ulv
.supported
= false;
6682 si_pi
->ulv
.pl
= *pl
;
6683 si_pi
->ulv
.one_pcie_lane_in_ulv
= false;
6684 si_pi
->ulv
.volt_change_delay
= SISLANDS_ULVVOLTAGECHANGEDELAY_DFLT
;
6685 si_pi
->ulv
.cg_ulv_parameter
= SISLANDS_CGULVPARAMETER_DFLT
;
6686 si_pi
->ulv
.cg_ulv_control
= SISLANDS_CGULVCONTROL_DFLT
;
6689 if (pi
->min_vddc_in_table
> pl
->vddc
)
6690 pi
->min_vddc_in_table
= pl
->vddc
;
6692 if (pi
->max_vddc_in_table
< pl
->vddc
)
6693 pi
->max_vddc_in_table
= pl
->vddc
;
6695 /* patch up boot state */
6696 if (rps
->class & ATOM_PPLIB_CLASSIFICATION_BOOT
) {
6697 u16 vddc
, vddci
, mvdd
;
6698 radeon_atombios_get_default_voltages(rdev
, &vddc
, &vddci
, &mvdd
);
6699 pl
->mclk
= rdev
->clock
.default_mclk
;
6700 pl
->sclk
= rdev
->clock
.default_sclk
;
6703 si_pi
->mvdd_bootup_value
= mvdd
;
6706 if ((rps
->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK
) ==
6707 ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE
) {
6708 rdev
->pm
.dpm
.dyn_state
.max_clock_voltage_on_ac
.sclk
= pl
->sclk
;
6709 rdev
->pm
.dpm
.dyn_state
.max_clock_voltage_on_ac
.mclk
= pl
->mclk
;
6710 rdev
->pm
.dpm
.dyn_state
.max_clock_voltage_on_ac
.vddc
= pl
->vddc
;
6711 rdev
->pm
.dpm
.dyn_state
.max_clock_voltage_on_ac
.vddci
= pl
->vddci
;
6715 static int si_parse_power_table(struct radeon_device
*rdev
)
6717 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
6718 struct _ATOM_PPLIB_NONCLOCK_INFO
*non_clock_info
;
6719 union pplib_power_state
*power_state
;
6720 int i
, j
, k
, non_clock_array_index
, clock_array_index
;
6721 union pplib_clock_info
*clock_info
;
6722 struct _StateArray
*state_array
;
6723 struct _ClockInfoArray
*clock_info_array
;
6724 struct _NonClockInfoArray
*non_clock_info_array
;
6725 union power_info
*power_info
;
6726 int index
= GetIndexIntoMasterTable(DATA
, PowerPlayInfo
);
6729 u8
*power_state_offset
;
6732 if (!atom_parse_data_header(mode_info
->atom_context
, index
, NULL
,
6733 &frev
, &crev
, &data_offset
))
6735 power_info
= (union power_info
*)(mode_info
->atom_context
->bios
+ data_offset
);
6737 state_array
= (struct _StateArray
*)
6738 (mode_info
->atom_context
->bios
+ data_offset
+
6739 le16_to_cpu(power_info
->pplib
.usStateArrayOffset
));
6740 clock_info_array
= (struct _ClockInfoArray
*)
6741 (mode_info
->atom_context
->bios
+ data_offset
+
6742 le16_to_cpu(power_info
->pplib
.usClockInfoArrayOffset
));
6743 non_clock_info_array
= (struct _NonClockInfoArray
*)
6744 (mode_info
->atom_context
->bios
+ data_offset
+
6745 le16_to_cpu(power_info
->pplib
.usNonClockInfoArrayOffset
));
6747 rdev
->pm
.dpm
.ps
= kzalloc(sizeof(struct radeon_ps
) *
6748 state_array
->ucNumEntries
, GFP_KERNEL
);
6749 if (!rdev
->pm
.dpm
.ps
)
6751 power_state_offset
= (u8
*)state_array
->states
;
6752 for (i
= 0; i
< state_array
->ucNumEntries
; i
++) {
6754 power_state
= (union pplib_power_state
*)power_state_offset
;
6755 non_clock_array_index
= power_state
->v2
.nonClockInfoIndex
;
6756 non_clock_info
= (struct _ATOM_PPLIB_NONCLOCK_INFO
*)
6757 &non_clock_info_array
->nonClockInfo
[non_clock_array_index
];
6758 if (!rdev
->pm
.power_state
[i
].clock_info
)
6760 ps
= kzalloc(sizeof(struct ni_ps
), GFP_KERNEL
);
6762 kfree(rdev
->pm
.dpm
.ps
);
6765 rdev
->pm
.dpm
.ps
[i
].ps_priv
= ps
;
6766 si_parse_pplib_non_clock_info(rdev
, &rdev
->pm
.dpm
.ps
[i
],
6768 non_clock_info_array
->ucEntrySize
);
6770 idx
= (u8
*)&power_state
->v2
.clockInfoIndex
[0];
6771 for (j
= 0; j
< power_state
->v2
.ucNumDPMLevels
; j
++) {
6772 clock_array_index
= idx
[j
];
6773 if (clock_array_index
>= clock_info_array
->ucNumEntries
)
6775 if (k
>= SISLANDS_MAX_HARDWARE_POWERLEVELS
)
6777 clock_info
= (union pplib_clock_info
*)
6778 ((u8
*)&clock_info_array
->clockInfo
[0] +
6779 (clock_array_index
* clock_info_array
->ucEntrySize
));
6780 si_parse_pplib_clock_info(rdev
,
6781 &rdev
->pm
.dpm
.ps
[i
], k
,
6785 power_state_offset
+= 2 + power_state
->v2
.ucNumDPMLevels
;
6787 rdev
->pm
.dpm
.num_ps
= state_array
->ucNumEntries
;
6791 int si_dpm_init(struct radeon_device
*rdev
)
6793 struct rv7xx_power_info
*pi
;
6794 struct evergreen_power_info
*eg_pi
;
6795 struct ni_power_info
*ni_pi
;
6796 struct si_power_info
*si_pi
;
6797 struct atom_clock_dividers dividers
;
6801 si_pi
= kzalloc(sizeof(struct si_power_info
), GFP_KERNEL
);
6804 rdev
->pm
.dpm
.priv
= si_pi
;
6809 ret
= drm_pcie_get_speed_cap_mask(rdev
->ddev
, &mask
);
6811 si_pi
->sys_pcie_mask
= 0;
6813 si_pi
->sys_pcie_mask
= mask
;
6814 si_pi
->force_pcie_gen
= RADEON_PCIE_GEN_INVALID
;
6815 si_pi
->boot_pcie_gen
= si_get_current_pcie_speed(rdev
);
6817 si_set_max_cu_value(rdev
);
6819 rv770_get_max_vddc(rdev
);
6820 si_get_leakage_vddc(rdev
);
6821 si_patch_dependency_tables_based_on_leakage(rdev
);
6824 eg_pi
->acpi_vddci
= 0;
6825 pi
->min_vddc_in_table
= 0;
6826 pi
->max_vddc_in_table
= 0;
6828 ret
= r600_get_platform_caps(rdev
);
6832 ret
= si_parse_power_table(rdev
);
6835 ret
= r600_parse_extended_power_table(rdev
);
6839 rdev
->pm
.dpm
.dyn_state
.vddc_dependency_on_dispclk
.entries
=
6840 kzalloc(4 * sizeof(struct radeon_clock_voltage_dependency_entry
), GFP_KERNEL
);
6841 if (!rdev
->pm
.dpm
.dyn_state
.vddc_dependency_on_dispclk
.entries
) {
6842 r600_free_extended_power_table(rdev
);
6845 rdev
->pm
.dpm
.dyn_state
.vddc_dependency_on_dispclk
.count
= 4;
6846 rdev
->pm
.dpm
.dyn_state
.vddc_dependency_on_dispclk
.entries
[0].clk
= 0;
6847 rdev
->pm
.dpm
.dyn_state
.vddc_dependency_on_dispclk
.entries
[0].v
= 0;
6848 rdev
->pm
.dpm
.dyn_state
.vddc_dependency_on_dispclk
.entries
[1].clk
= 36000;
6849 rdev
->pm
.dpm
.dyn_state
.vddc_dependency_on_dispclk
.entries
[1].v
= 720;
6850 rdev
->pm
.dpm
.dyn_state
.vddc_dependency_on_dispclk
.entries
[2].clk
= 54000;
6851 rdev
->pm
.dpm
.dyn_state
.vddc_dependency_on_dispclk
.entries
[2].v
= 810;
6852 rdev
->pm
.dpm
.dyn_state
.vddc_dependency_on_dispclk
.entries
[3].clk
= 72000;
6853 rdev
->pm
.dpm
.dyn_state
.vddc_dependency_on_dispclk
.entries
[3].v
= 900;
6855 if (rdev
->pm
.dpm
.voltage_response_time
== 0)
6856 rdev
->pm
.dpm
.voltage_response_time
= R600_VOLTAGERESPONSETIME_DFLT
;
6857 if (rdev
->pm
.dpm
.backbias_response_time
== 0)
6858 rdev
->pm
.dpm
.backbias_response_time
= R600_BACKBIASRESPONSETIME_DFLT
;
6860 ret
= radeon_atom_get_clock_dividers(rdev
, COMPUTE_ENGINE_PLL_PARAM
,
6861 0, false, ÷rs
);
6863 pi
->ref_div
= dividers
.ref_div
+ 1;
6865 pi
->ref_div
= R600_REFERENCEDIVIDER_DFLT
;
6867 eg_pi
->smu_uvd_hs
= false;
6869 pi
->mclk_strobe_mode_threshold
= 40000;
6870 if (si_is_special_1gb_platform(rdev
))
6871 pi
->mclk_stutter_mode_threshold
= 0;
6873 pi
->mclk_stutter_mode_threshold
= pi
->mclk_strobe_mode_threshold
;
6874 pi
->mclk_edc_enable_threshold
= 40000;
6875 eg_pi
->mclk_edc_wr_enable_threshold
= 40000;
6877 ni_pi
->mclk_rtt_mode_threshold
= eg_pi
->mclk_edc_wr_enable_threshold
;
6879 pi
->voltage_control
=
6880 radeon_atom_is_voltage_gpio(rdev
, SET_VOLTAGE_TYPE_ASIC_VDDC
,
6881 VOLTAGE_OBJ_GPIO_LUT
);
6882 if (!pi
->voltage_control
) {
6883 si_pi
->voltage_control_svi2
=
6884 radeon_atom_is_voltage_gpio(rdev
, SET_VOLTAGE_TYPE_ASIC_VDDC
,
6886 if (si_pi
->voltage_control_svi2
)
6887 radeon_atom_get_svi2_info(rdev
, SET_VOLTAGE_TYPE_ASIC_VDDC
,
6888 &si_pi
->svd_gpio_id
, &si_pi
->svc_gpio_id
);
6892 radeon_atom_is_voltage_gpio(rdev
, SET_VOLTAGE_TYPE_ASIC_MVDDC
,
6893 VOLTAGE_OBJ_GPIO_LUT
);
6895 eg_pi
->vddci_control
=
6896 radeon_atom_is_voltage_gpio(rdev
, SET_VOLTAGE_TYPE_ASIC_VDDCI
,
6897 VOLTAGE_OBJ_GPIO_LUT
);
6898 if (!eg_pi
->vddci_control
)
6899 si_pi
->vddci_control_svi2
=
6900 radeon_atom_is_voltage_gpio(rdev
, SET_VOLTAGE_TYPE_ASIC_VDDCI
,
6903 si_pi
->vddc_phase_shed_control
=
6904 radeon_atom_is_voltage_gpio(rdev
, SET_VOLTAGE_TYPE_ASIC_VDDC
,
6905 VOLTAGE_OBJ_PHASE_LUT
);
6907 rv770_get_engine_memory_ss(rdev
);
6909 pi
->asi
= RV770_ASI_DFLT
;
6910 pi
->pasi
= CYPRESS_HASI_DFLT
;
6911 pi
->vrc
= SISLANDS_VRC_DFLT
;
6913 pi
->gfx_clock_gating
= true;
6915 eg_pi
->sclk_deep_sleep
= true;
6916 si_pi
->sclk_deep_sleep_above_low
= false;
6918 if (rdev
->pm
.int_thermal_type
!= THERMAL_TYPE_NONE
)
6919 pi
->thermal_protection
= true;
6921 pi
->thermal_protection
= false;
6923 eg_pi
->dynamic_ac_timing
= true;
6925 eg_pi
->light_sleep
= true;
6926 #if defined(CONFIG_ACPI)
6927 eg_pi
->pcie_performance_request
=
6928 radeon_acpi_is_pcie_performance_request_supported(rdev
);
6930 eg_pi
->pcie_performance_request
= false;
6933 si_pi
->sram_end
= SMC_RAM_END
;
6935 rdev
->pm
.dpm
.dyn_state
.mclk_sclk_ratio
= 4;
6936 rdev
->pm
.dpm
.dyn_state
.sclk_mclk_delta
= 15000;
6937 rdev
->pm
.dpm
.dyn_state
.vddc_vddci_delta
= 200;
6938 rdev
->pm
.dpm
.dyn_state
.valid_sclk_values
.count
= 0;
6939 rdev
->pm
.dpm
.dyn_state
.valid_sclk_values
.values
= NULL
;
6940 rdev
->pm
.dpm
.dyn_state
.valid_mclk_values
.count
= 0;
6941 rdev
->pm
.dpm
.dyn_state
.valid_mclk_values
.values
= NULL
;
6943 si_initialize_powertune_defaults(rdev
);
6945 /* make sure dc limits are valid */
6946 if ((rdev
->pm
.dpm
.dyn_state
.max_clock_voltage_on_dc
.sclk
== 0) ||
6947 (rdev
->pm
.dpm
.dyn_state
.max_clock_voltage_on_dc
.mclk
== 0))
6948 rdev
->pm
.dpm
.dyn_state
.max_clock_voltage_on_dc
=
6949 rdev
->pm
.dpm
.dyn_state
.max_clock_voltage_on_ac
;
6951 si_pi
->fan_ctrl_is_in_default_mode
= true;
6952 rdev
->pm
.dpm
.fan
.ucode_fan_control
= false;
6957 void si_dpm_fini(struct radeon_device
*rdev
)
6961 for (i
= 0; i
< rdev
->pm
.dpm
.num_ps
; i
++) {
6962 kfree(rdev
->pm
.dpm
.ps
[i
].ps_priv
);
6964 kfree(rdev
->pm
.dpm
.ps
);
6965 kfree(rdev
->pm
.dpm
.priv
);
6966 kfree(rdev
->pm
.dpm
.dyn_state
.vddc_dependency_on_dispclk
.entries
);
6967 r600_free_extended_power_table(rdev
);
6970 void si_dpm_debugfs_print_current_performance_level(struct radeon_device
*rdev
,
6973 struct evergreen_power_info
*eg_pi
= evergreen_get_pi(rdev
);
6974 struct radeon_ps
*rps
= &eg_pi
->current_rps
;
6975 struct ni_ps
*ps
= ni_get_ps(rps
);
6976 struct rv7xx_pl
*pl
;
6978 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX
) & CURRENT_STATE_INDEX_MASK
) >>
6979 CURRENT_STATE_INDEX_SHIFT
;
6981 if (current_index
>= ps
->performance_level_count
) {
6982 seq_printf(m
, "invalid dpm profile %d\n", current_index
);
6984 pl
= &ps
->performance_levels
[current_index
];
6985 seq_printf(m
, "uvd vclk: %d dclk: %d\n", rps
->vclk
, rps
->dclk
);
6986 seq_printf(m
, "power level %d sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n",
6987 current_index
, pl
->sclk
, pl
->mclk
, pl
->vddc
, pl
->vddci
, pl
->pcie_gen
+ 1);