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drm/radeon/pm: move pm handling into the asic specific code
[deliverable/linux.git] / drivers / gpu / drm / radeon / si_dpm.c
1 /*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #include "drmP.h"
25 #include "radeon.h"
26 #include "sid.h"
27 #include "r600_dpm.h"
28 #include "si_dpm.h"
29 #include "atom.h"
30 #include <linux/math64.h>
31 #include <linux/seq_file.h>
32
33 #define MC_CG_ARB_FREQ_F0 0x0a
34 #define MC_CG_ARB_FREQ_F1 0x0b
35 #define MC_CG_ARB_FREQ_F2 0x0c
36 #define MC_CG_ARB_FREQ_F3 0x0d
37
38 #define SMC_RAM_END 0x20000
39
40 #define SCLK_MIN_DEEPSLEEP_FREQ 1350
41
42 static const struct si_cac_config_reg cac_weights_tahiti[] =
43 {
44 { 0x0, 0x0000ffff, 0, 0xc, SISLANDS_CACCONFIG_CGIND },
45 { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
46 { 0x1, 0x0000ffff, 0, 0x101, SISLANDS_CACCONFIG_CGIND },
47 { 0x1, 0xffff0000, 16, 0xc, SISLANDS_CACCONFIG_CGIND },
48 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
49 { 0x3, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
50 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
51 { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
52 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
53 { 0x5, 0x0000ffff, 0, 0x8fc, SISLANDS_CACCONFIG_CGIND },
54 { 0x5, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
55 { 0x6, 0x0000ffff, 0, 0x95, SISLANDS_CACCONFIG_CGIND },
56 { 0x6, 0xffff0000, 16, 0x34e, SISLANDS_CACCONFIG_CGIND },
57 { 0x18f, 0x0000ffff, 0, 0x1a1, SISLANDS_CACCONFIG_CGIND },
58 { 0x7, 0x0000ffff, 0, 0xda, SISLANDS_CACCONFIG_CGIND },
59 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
60 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
61 { 0x8, 0xffff0000, 16, 0x46, SISLANDS_CACCONFIG_CGIND },
62 { 0x9, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
63 { 0xa, 0x0000ffff, 0, 0x208, SISLANDS_CACCONFIG_CGIND },
64 { 0xb, 0x0000ffff, 0, 0xe7, SISLANDS_CACCONFIG_CGIND },
65 { 0xb, 0xffff0000, 16, 0x948, SISLANDS_CACCONFIG_CGIND },
66 { 0xc, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
67 { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
68 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
69 { 0xe, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
70 { 0xf, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
71 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
72 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
73 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
74 { 0x11, 0x0000ffff, 0, 0x167, SISLANDS_CACCONFIG_CGIND },
75 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
76 { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
77 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
78 { 0x13, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
79 { 0x14, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
80 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
81 { 0x15, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
82 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
83 { 0x16, 0x0000ffff, 0, 0x31, SISLANDS_CACCONFIG_CGIND },
84 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
85 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
86 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
87 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
88 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
89 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
90 { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
91 { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
92 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
93 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
94 { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
95 { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
96 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
97 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
98 { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
99 { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
100 { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
101 { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
102 { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
103 { 0x6d, 0x0000ffff, 0, 0x18e, SISLANDS_CACCONFIG_CGIND },
104 { 0xFFFFFFFF }
105 };
106
107 static const struct si_cac_config_reg lcac_tahiti[] =
108 {
109 { 0x143, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
110 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
111 { 0x146, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
112 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
113 { 0x149, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
114 { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
115 { 0x14c, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
116 { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
117 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
118 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
119 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
120 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
121 { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
122 { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
123 { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
124 { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
125 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
126 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
127 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
128 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
129 { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
130 { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
131 { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
132 { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
133 { 0x8c, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
134 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
135 { 0x8f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
136 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
137 { 0x92, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
138 { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
139 { 0x95, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
140 { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
141 { 0x14f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
142 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
143 { 0x152, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
144 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
145 { 0x155, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
146 { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
147 { 0x158, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
148 { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
149 { 0x110, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
150 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
151 { 0x113, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
152 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
153 { 0x116, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
154 { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
155 { 0x119, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
156 { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
157 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
158 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
159 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
160 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
161 { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
162 { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
163 { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
164 { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
165 { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
166 { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
167 { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
168 { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
169 { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
170 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
171 { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
172 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
173 { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
174 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
175 { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
176 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
177 { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
178 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
179 { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
180 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
181 { 0x16d, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
182 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
183 { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
184 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
185 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
186 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
187 { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
188 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
189 { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
190 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
191 { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
192 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
193 { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
194 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
195 { 0xFFFFFFFF }
196
197 };
198
199 static const struct si_cac_config_reg cac_override_tahiti[] =
200 {
201 { 0xFFFFFFFF }
202 };
203
204 static const struct si_powertune_data powertune_data_tahiti =
205 {
206 ((1 << 16) | 27027),
207 6,
208 0,
209 4,
210 95,
211 {
212 0UL,
213 0UL,
214 4521550UL,
215 309631529UL,
216 -1270850L,
217 4513710L,
218 40
219 },
220 595000000UL,
221 12,
222 {
223 0,
224 0,
225 0,
226 0,
227 0,
228 0,
229 0,
230 0
231 },
232 true
233 };
234
235 static const struct si_dte_data dte_data_tahiti =
236 {
237 { 1159409, 0, 0, 0, 0 },
238 { 777, 0, 0, 0, 0 },
239 2,
240 54000,
241 127000,
242 25,
243 2,
244 10,
245 13,
246 { 27, 31, 35, 39, 43, 47, 54, 61, 67, 74, 81, 88, 95, 0, 0, 0 },
247 { 240888759, 221057860, 235370597, 162287531, 158510299, 131423027, 116673180, 103067515, 87941937, 76209048, 68209175, 64090048, 58301890, 0, 0, 0 },
248 { 12024, 11189, 11451, 8411, 7939, 6666, 5681, 4905, 4241, 3720, 3354, 3122, 2890, 0, 0, 0 },
249 85,
250 false
251 };
252
253 static const struct si_dte_data dte_data_tahiti_le =
254 {
255 { 0x1E8480, 0x7A1200, 0x2160EC0, 0x3938700, 0 },
256 { 0x7D, 0x7D, 0x4E4, 0xB00, 0 },
257 0x5,
258 0xAFC8,
259 0x64,
260 0x32,
261 1,
262 0,
263 0x10,
264 { 0x78, 0x7C, 0x82, 0x88, 0x8E, 0x94, 0x9A, 0xA0, 0xA6, 0xAC, 0xB0, 0xB4, 0xB8, 0xBC, 0xC0, 0xC4 },
265 { 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700 },
266 { 0x2AF8, 0x2AF8, 0x29BB, 0x27F9, 0x2637, 0x2475, 0x22B3, 0x20F1, 0x1F2F, 0x1D6D, 0x1734, 0x1414, 0x10F4, 0xDD4, 0xAB4, 0x794 },
267 85,
268 true
269 };
270
271 static const struct si_dte_data dte_data_tahiti_pro =
272 {
273 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
274 { 0x0, 0x0, 0x0, 0x0, 0x0 },
275 5,
276 45000,
277 100,
278 0xA,
279 1,
280 0,
281 0x10,
282 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
283 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
284 { 0x7D0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
285 90,
286 true
287 };
288
289 static const struct si_dte_data dte_data_new_zealand =
290 {
291 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0 },
292 { 0x29B, 0x3E9, 0x537, 0x7D2, 0 },
293 0x5,
294 0xAFC8,
295 0x69,
296 0x32,
297 1,
298 0,
299 0x10,
300 { 0x82, 0xA0, 0xB4, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE },
301 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
302 { 0xDAC, 0x1388, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685 },
303 85,
304 true
305 };
306
307 static const struct si_dte_data dte_data_aruba_pro =
308 {
309 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
310 { 0x0, 0x0, 0x0, 0x0, 0x0 },
311 5,
312 45000,
313 100,
314 0xA,
315 1,
316 0,
317 0x10,
318 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
319 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
320 { 0x1000, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
321 90,
322 true
323 };
324
325 static const struct si_dte_data dte_data_malta =
326 {
327 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
328 { 0x0, 0x0, 0x0, 0x0, 0x0 },
329 5,
330 45000,
331 100,
332 0xA,
333 1,
334 0,
335 0x10,
336 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
337 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
338 { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
339 90,
340 true
341 };
342
343 struct si_cac_config_reg cac_weights_pitcairn[] =
344 {
345 { 0x0, 0x0000ffff, 0, 0x8a, SISLANDS_CACCONFIG_CGIND },
346 { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
347 { 0x1, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
348 { 0x1, 0xffff0000, 16, 0x24d, SISLANDS_CACCONFIG_CGIND },
349 { 0x2, 0x0000ffff, 0, 0x19, SISLANDS_CACCONFIG_CGIND },
350 { 0x3, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
351 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
352 { 0x4, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
353 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
354 { 0x5, 0x0000ffff, 0, 0xc11, SISLANDS_CACCONFIG_CGIND },
355 { 0x5, 0xffff0000, 16, 0x7f3, SISLANDS_CACCONFIG_CGIND },
356 { 0x6, 0x0000ffff, 0, 0x403, SISLANDS_CACCONFIG_CGIND },
357 { 0x6, 0xffff0000, 16, 0x367, SISLANDS_CACCONFIG_CGIND },
358 { 0x18f, 0x0000ffff, 0, 0x4c9, SISLANDS_CACCONFIG_CGIND },
359 { 0x7, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
360 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
361 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
362 { 0x8, 0xffff0000, 16, 0x45d, SISLANDS_CACCONFIG_CGIND },
363 { 0x9, 0x0000ffff, 0, 0x36d, SISLANDS_CACCONFIG_CGIND },
364 { 0xa, 0x0000ffff, 0, 0x534, SISLANDS_CACCONFIG_CGIND },
365 { 0xb, 0x0000ffff, 0, 0x5da, SISLANDS_CACCONFIG_CGIND },
366 { 0xb, 0xffff0000, 16, 0x880, SISLANDS_CACCONFIG_CGIND },
367 { 0xc, 0x0000ffff, 0, 0x201, SISLANDS_CACCONFIG_CGIND },
368 { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
369 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
370 { 0xe, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND },
371 { 0xf, 0x0000ffff, 0, 0x1f, SISLANDS_CACCONFIG_CGIND },
372 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
373 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
374 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
375 { 0x11, 0x0000ffff, 0, 0x5de, SISLANDS_CACCONFIG_CGIND },
376 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
377 { 0x12, 0x0000ffff, 0, 0x7b, SISLANDS_CACCONFIG_CGIND },
378 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
379 { 0x13, 0xffff0000, 16, 0x13, SISLANDS_CACCONFIG_CGIND },
380 { 0x14, 0x0000ffff, 0, 0xf9, SISLANDS_CACCONFIG_CGIND },
381 { 0x15, 0x0000ffff, 0, 0x66, SISLANDS_CACCONFIG_CGIND },
382 { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
383 { 0x4e, 0x0000ffff, 0, 0x13, SISLANDS_CACCONFIG_CGIND },
384 { 0x16, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
385 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
386 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
387 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
388 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
389 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
390 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
391 { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
392 { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
393 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
394 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
395 { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
396 { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
397 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
398 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
399 { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
400 { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
401 { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
402 { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
403 { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
404 { 0x6d, 0x0000ffff, 0, 0x186, SISLANDS_CACCONFIG_CGIND },
405 { 0xFFFFFFFF }
406 };
407
408 static const struct si_cac_config_reg lcac_pitcairn[] =
409 {
410 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
411 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
412 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
413 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
414 { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
415 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
416 { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
417 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
418 { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
419 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
420 { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
421 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
422 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
423 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
424 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
425 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
426 { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
427 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
428 { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
429 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
430 { 0x8f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
431 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
432 { 0x146, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
433 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
434 { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
435 { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
436 { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
437 { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
438 { 0x116, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
439 { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
440 { 0x155, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
441 { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
442 { 0x92, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
443 { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
444 { 0x149, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
445 { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
446 { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
447 { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
448 { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
449 { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
450 { 0x119, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
451 { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
452 { 0x158, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
453 { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
454 { 0x95, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
455 { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
456 { 0x14c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
457 { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
458 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
459 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
460 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
461 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
462 { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
463 { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
464 { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
465 { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
466 { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
467 { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
468 { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
469 { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
470 { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
471 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
472 { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
473 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
474 { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
475 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
476 { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
477 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
478 { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
479 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
480 { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
481 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
482 { 0x16d, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
483 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
484 { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
485 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
486 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
487 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
488 { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
489 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
490 { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
491 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
492 { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
493 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
494 { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
495 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
496 { 0xFFFFFFFF }
497 };
498
499 static const struct si_cac_config_reg cac_override_pitcairn[] =
500 {
501 { 0xFFFFFFFF }
502 };
503
504 static const struct si_powertune_data powertune_data_pitcairn =
505 {
506 ((1 << 16) | 27027),
507 5,
508 0,
509 6,
510 100,
511 {
512 51600000UL,
513 1800000UL,
514 7194395UL,
515 309631529UL,
516 -1270850L,
517 4513710L,
518 100
519 },
520 117830498UL,
521 12,
522 {
523 0,
524 0,
525 0,
526 0,
527 0,
528 0,
529 0,
530 0
531 },
532 true
533 };
534
535 static const struct si_dte_data dte_data_pitcairn =
536 {
537 { 0, 0, 0, 0, 0 },
538 { 0, 0, 0, 0, 0 },
539 0,
540 0,
541 0,
542 0,
543 0,
544 0,
545 0,
546 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
547 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
548 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
549 0,
550 false
551 };
552
553 static const struct si_dte_data dte_data_curacao_xt =
554 {
555 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
556 { 0x0, 0x0, 0x0, 0x0, 0x0 },
557 5,
558 45000,
559 100,
560 0xA,
561 1,
562 0,
563 0x10,
564 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
565 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
566 { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
567 90,
568 true
569 };
570
571 static const struct si_dte_data dte_data_curacao_pro =
572 {
573 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
574 { 0x0, 0x0, 0x0, 0x0, 0x0 },
575 5,
576 45000,
577 100,
578 0xA,
579 1,
580 0,
581 0x10,
582 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
583 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
584 { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
585 90,
586 true
587 };
588
589 static const struct si_dte_data dte_data_neptune_xt =
590 {
591 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
592 { 0x0, 0x0, 0x0, 0x0, 0x0 },
593 5,
594 45000,
595 100,
596 0xA,
597 1,
598 0,
599 0x10,
600 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
601 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
602 { 0x3A2F, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
603 90,
604 true
605 };
606
607 static const struct si_cac_config_reg cac_weights_chelsea_pro[] =
608 {
609 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
610 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
611 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
612 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
613 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
614 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
615 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
616 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
617 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
618 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
619 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
620 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
621 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
622 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
623 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
624 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
625 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
626 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
627 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
628 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
629 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
630 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
631 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
632 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
633 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
634 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
635 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
636 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
637 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
638 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
639 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
640 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
641 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
642 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
643 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
644 { 0x14, 0x0000ffff, 0, 0x2BD, SISLANDS_CACCONFIG_CGIND },
645 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
646 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
647 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
648 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
649 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
650 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
651 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
652 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
653 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
654 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
655 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
656 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
657 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
658 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
659 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
660 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
661 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
662 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
663 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
664 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
665 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
666 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
667 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
668 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
669 { 0xFFFFFFFF }
670 };
671
672 static const struct si_cac_config_reg cac_weights_chelsea_xt[] =
673 {
674 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
675 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
676 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
677 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
678 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
679 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
680 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
681 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
682 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
683 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
684 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
685 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
686 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
687 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
688 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
689 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
690 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
691 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
692 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
693 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
694 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
695 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
696 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
697 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
698 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
699 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
700 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
701 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
702 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
703 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
704 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
705 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
706 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
707 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
708 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
709 { 0x14, 0x0000ffff, 0, 0x30A, SISLANDS_CACCONFIG_CGIND },
710 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
711 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
712 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
713 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
714 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
715 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
716 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
717 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
718 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
719 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
720 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
721 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
722 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
723 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
724 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
725 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
726 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
727 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
728 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
729 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
730 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
731 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
732 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
733 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
734 { 0xFFFFFFFF }
735 };
736
737 static const struct si_cac_config_reg cac_weights_heathrow[] =
738 {
739 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
740 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
741 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
742 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
743 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
744 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
745 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
746 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
747 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
748 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
749 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
750 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
751 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
752 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
753 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
754 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
755 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
756 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
757 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
758 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
759 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
760 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
761 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
762 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
763 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
764 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
765 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
766 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
767 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
768 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
769 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
770 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
771 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
772 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
773 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
774 { 0x14, 0x0000ffff, 0, 0x362, SISLANDS_CACCONFIG_CGIND },
775 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
776 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
777 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
778 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
779 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
780 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
781 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
782 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
783 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
784 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
785 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
786 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
787 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
788 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
789 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
790 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
791 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
792 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
793 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
794 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
795 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
796 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
797 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
798 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
799 { 0xFFFFFFFF }
800 };
801
802 static const struct si_cac_config_reg cac_weights_cape_verde_pro[] =
803 {
804 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
805 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
806 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
807 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
808 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
809 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
810 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
811 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
812 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
813 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
814 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
815 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
816 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
817 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
818 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
819 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
820 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
821 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
822 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
823 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
824 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
825 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
826 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
827 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
828 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
829 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
830 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
831 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
832 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
833 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
834 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
835 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
836 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
837 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
838 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
839 { 0x14, 0x0000ffff, 0, 0x315, SISLANDS_CACCONFIG_CGIND },
840 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
841 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
842 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
843 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
844 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
845 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
846 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
847 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
848 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
849 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
850 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
851 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
852 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
853 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
854 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
855 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
856 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
857 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
858 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
859 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
860 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
861 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
862 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
863 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
864 { 0xFFFFFFFF }
865 };
866
867 static const struct si_cac_config_reg cac_weights_cape_verde[] =
868 {
869 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
870 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
871 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
872 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
873 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
874 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
875 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
876 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
877 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
878 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
879 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
880 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
881 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
882 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
883 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
884 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
885 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
886 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
887 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
888 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
889 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
890 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
891 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
892 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
893 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
894 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
895 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
896 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
897 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
898 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
899 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
900 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
901 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
902 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
903 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
904 { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND },
905 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
906 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
907 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
908 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
909 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
910 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
911 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
912 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
913 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
914 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
915 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
916 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
917 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
918 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
919 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
920 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
921 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
922 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
923 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
924 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
925 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
926 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
927 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
928 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
929 { 0xFFFFFFFF }
930 };
931
932 static const struct si_cac_config_reg lcac_cape_verde[] =
933 {
934 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
935 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
936 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
937 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
938 { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
939 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
940 { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
941 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
942 { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
943 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
944 { 0x143, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
945 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
946 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
947 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
948 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
949 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
950 { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
951 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
952 { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
953 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
954 { 0x8f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
955 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
956 { 0x146, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
957 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
958 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
959 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
960 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
961 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
962 { 0x164, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
963 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
964 { 0x167, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
965 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
966 { 0x16a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
967 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
968 { 0x15e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
969 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
970 { 0x161, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
971 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
972 { 0x15b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
973 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
974 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
975 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
976 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
977 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
978 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
979 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
980 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
981 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
982 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
983 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
984 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
985 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
986 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
987 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
988 { 0xFFFFFFFF }
989 };
990
991 static const struct si_cac_config_reg cac_override_cape_verde[] =
992 {
993 { 0xFFFFFFFF }
994 };
995
996 static const struct si_powertune_data powertune_data_cape_verde =
997 {
998 ((1 << 16) | 0x6993),
999 5,
1000 0,
1001 7,
1002 105,
1003 {
1004 0UL,
1005 0UL,
1006 7194395UL,
1007 309631529UL,
1008 -1270850L,
1009 4513710L,
1010 100
1011 },
1012 117830498UL,
1013 12,
1014 {
1015 0,
1016 0,
1017 0,
1018 0,
1019 0,
1020 0,
1021 0,
1022 0
1023 },
1024 true
1025 };
1026
1027 static const struct si_dte_data dte_data_cape_verde =
1028 {
1029 { 0, 0, 0, 0, 0 },
1030 { 0, 0, 0, 0, 0 },
1031 0,
1032 0,
1033 0,
1034 0,
1035 0,
1036 0,
1037 0,
1038 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1039 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1040 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1041 0,
1042 false
1043 };
1044
1045 static const struct si_dte_data dte_data_venus_xtx =
1046 {
1047 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1048 { 0x71C, 0xAAB, 0xE39, 0x11C7, 0x0 },
1049 5,
1050 55000,
1051 0x69,
1052 0xA,
1053 1,
1054 0,
1055 0x3,
1056 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1057 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1058 { 0xD6D8, 0x88B8, 0x1555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1059 90,
1060 true
1061 };
1062
1063 static const struct si_dte_data dte_data_venus_xt =
1064 {
1065 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1066 { 0xBDA, 0x11C7, 0x17B4, 0x1DA1, 0x0 },
1067 5,
1068 55000,
1069 0x69,
1070 0xA,
1071 1,
1072 0,
1073 0x3,
1074 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1075 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1076 { 0xAFC8, 0x88B8, 0x238E, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1077 90,
1078 true
1079 };
1080
1081 static const struct si_dte_data dte_data_venus_pro =
1082 {
1083 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1084 { 0x11C7, 0x1AAB, 0x238E, 0x2C72, 0x0 },
1085 5,
1086 55000,
1087 0x69,
1088 0xA,
1089 1,
1090 0,
1091 0x3,
1092 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1093 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1094 { 0x88B8, 0x88B8, 0x3555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1095 90,
1096 true
1097 };
1098
1099 struct si_cac_config_reg cac_weights_oland[] =
1100 {
1101 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
1102 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
1103 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
1104 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
1105 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1106 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
1107 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
1108 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
1109 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
1110 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
1111 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
1112 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
1113 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
1114 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
1115 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
1116 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
1117 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
1118 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
1119 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
1120 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
1121 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
1122 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
1123 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
1124 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
1125 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
1126 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1127 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1128 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1129 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1130 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
1131 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1132 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
1133 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
1134 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
1135 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1136 { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND },
1137 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1138 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1139 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1140 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
1141 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
1142 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1143 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1144 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1145 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1146 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1147 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1148 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1149 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1150 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1151 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1152 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1153 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1154 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1155 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1156 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1157 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1158 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1159 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1160 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
1161 { 0xFFFFFFFF }
1162 };
1163
1164 static const struct si_cac_config_reg cac_weights_mars_pro[] =
1165 {
1166 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1167 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1168 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1169 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1170 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1171 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1172 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1173 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1174 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1175 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1176 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1177 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1178 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1179 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1180 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1181 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1182 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1183 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1184 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1185 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1186 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1187 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1188 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1189 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1190 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1191 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1192 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1193 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1194 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1195 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1196 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1197 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1198 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1199 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1200 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1201 { 0x14, 0x0000ffff, 0, 0x2, SISLANDS_CACCONFIG_CGIND },
1202 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1203 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1204 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1205 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1206 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1207 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1208 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1209 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1210 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1211 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1212 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1213 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1214 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1215 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1216 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1217 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1218 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1219 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1220 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1221 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1222 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1223 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1224 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1225 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1226 { 0xFFFFFFFF }
1227 };
1228
1229 static const struct si_cac_config_reg cac_weights_mars_xt[] =
1230 {
1231 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1232 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1233 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1234 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1235 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1236 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1237 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1238 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1239 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1240 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1241 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1242 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1243 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1244 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1245 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1246 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1247 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1248 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1249 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1250 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1251 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1252 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1253 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1254 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1255 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1256 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1257 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1258 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1259 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1260 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1261 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1262 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1263 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1264 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1265 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1266 { 0x14, 0x0000ffff, 0, 0x60, SISLANDS_CACCONFIG_CGIND },
1267 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1268 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1269 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1270 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1271 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1272 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1273 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1274 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1275 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1276 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1277 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1278 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1279 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1280 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1281 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1282 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1283 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1284 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1285 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1286 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1287 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1288 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1289 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1290 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1291 { 0xFFFFFFFF }
1292 };
1293
1294 static const struct si_cac_config_reg cac_weights_oland_pro[] =
1295 {
1296 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1297 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1298 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1299 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1300 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1301 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1302 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1303 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1304 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1305 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1306 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1307 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1308 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1309 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1310 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1311 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1312 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1313 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1314 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1315 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1316 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1317 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1318 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1319 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1320 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1321 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1322 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1323 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1324 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1325 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1326 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1327 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1328 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1329 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1330 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1331 { 0x14, 0x0000ffff, 0, 0x90, SISLANDS_CACCONFIG_CGIND },
1332 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1333 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1334 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1335 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1336 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1337 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1338 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1339 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1340 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1341 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1342 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1343 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1344 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1345 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1346 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1347 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1348 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1349 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1350 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1351 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1352 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1353 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1354 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1355 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1356 { 0xFFFFFFFF }
1357 };
1358
1359 static const struct si_cac_config_reg cac_weights_oland_xt[] =
1360 {
1361 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1362 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1363 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1364 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1365 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1366 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1367 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1368 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1369 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1370 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1371 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1372 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1373 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1374 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1375 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1376 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1377 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1378 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1379 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1380 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1381 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1382 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1383 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1384 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1385 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1386 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1387 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1388 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1389 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1390 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1391 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1392 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1393 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1394 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1395 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1396 { 0x14, 0x0000ffff, 0, 0x120, SISLANDS_CACCONFIG_CGIND },
1397 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1398 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1399 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1400 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1401 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1402 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1403 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1404 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1405 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1406 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1407 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1408 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1409 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1410 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1411 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1412 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1413 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1414 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1415 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1416 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1417 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1418 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1419 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1420 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1421 { 0xFFFFFFFF }
1422 };
1423
1424 static const struct si_cac_config_reg lcac_oland[] =
1425 {
1426 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1427 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1428 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1429 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1430 { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1431 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1432 { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1433 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1434 { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1435 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1436 { 0x143, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
1437 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1438 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1439 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1440 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1441 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1442 { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1443 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1444 { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1445 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1446 { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1447 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1448 { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1449 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1450 { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1451 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1452 { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1453 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1454 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1455 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1456 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1457 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1458 { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1459 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1460 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1461 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1462 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1463 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1464 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1465 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1466 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1467 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1468 { 0xFFFFFFFF }
1469 };
1470
1471 static const struct si_cac_config_reg lcac_mars_pro[] =
1472 {
1473 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1474 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1475 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1476 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1477 { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1478 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1479 { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1480 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1481 { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1482 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1483 { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1484 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1485 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1486 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1487 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1488 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1489 { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1490 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1491 { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1492 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1493 { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1494 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1495 { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1496 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1497 { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1498 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1499 { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1500 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1501 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1502 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1503 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1504 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1505 { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1506 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1507 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1508 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1509 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1510 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1511 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1512 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1513 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1514 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1515 { 0xFFFFFFFF }
1516 };
1517
1518 static const struct si_cac_config_reg cac_override_oland[] =
1519 {
1520 { 0xFFFFFFFF }
1521 };
1522
1523 static const struct si_powertune_data powertune_data_oland =
1524 {
1525 ((1 << 16) | 0x6993),
1526 5,
1527 0,
1528 7,
1529 105,
1530 {
1531 0UL,
1532 0UL,
1533 7194395UL,
1534 309631529UL,
1535 -1270850L,
1536 4513710L,
1537 100
1538 },
1539 117830498UL,
1540 12,
1541 {
1542 0,
1543 0,
1544 0,
1545 0,
1546 0,
1547 0,
1548 0,
1549 0
1550 },
1551 true
1552 };
1553
1554 static const struct si_powertune_data powertune_data_mars_pro =
1555 {
1556 ((1 << 16) | 0x6993),
1557 5,
1558 0,
1559 7,
1560 105,
1561 {
1562 0UL,
1563 0UL,
1564 7194395UL,
1565 309631529UL,
1566 -1270850L,
1567 4513710L,
1568 100
1569 },
1570 117830498UL,
1571 12,
1572 {
1573 0,
1574 0,
1575 0,
1576 0,
1577 0,
1578 0,
1579 0,
1580 0
1581 },
1582 true
1583 };
1584
1585 static const struct si_dte_data dte_data_oland =
1586 {
1587 { 0, 0, 0, 0, 0 },
1588 { 0, 0, 0, 0, 0 },
1589 0,
1590 0,
1591 0,
1592 0,
1593 0,
1594 0,
1595 0,
1596 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1597 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1598 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1599 0,
1600 false
1601 };
1602
1603 static const struct si_dte_data dte_data_mars_pro =
1604 {
1605 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1606 { 0x0, 0x0, 0x0, 0x0, 0x0 },
1607 5,
1608 55000,
1609 105,
1610 0xA,
1611 1,
1612 0,
1613 0x10,
1614 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
1615 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
1616 { 0xF627, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1617 90,
1618 true
1619 };
1620
1621 static const struct si_dte_data dte_data_sun_xt =
1622 {
1623 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1624 { 0x0, 0x0, 0x0, 0x0, 0x0 },
1625 5,
1626 55000,
1627 105,
1628 0xA,
1629 1,
1630 0,
1631 0x10,
1632 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
1633 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
1634 { 0xD555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1635 90,
1636 true
1637 };
1638
1639
1640 static const struct si_cac_config_reg cac_weights_hainan[] =
1641 {
1642 { 0x0, 0x0000ffff, 0, 0x2d9, SISLANDS_CACCONFIG_CGIND },
1643 { 0x0, 0xffff0000, 16, 0x22b, SISLANDS_CACCONFIG_CGIND },
1644 { 0x1, 0x0000ffff, 0, 0x21c, SISLANDS_CACCONFIG_CGIND },
1645 { 0x1, 0xffff0000, 16, 0x1dc, SISLANDS_CACCONFIG_CGIND },
1646 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1647 { 0x3, 0x0000ffff, 0, 0x24e, SISLANDS_CACCONFIG_CGIND },
1648 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1649 { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1650 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1651 { 0x5, 0x0000ffff, 0, 0x35e, SISLANDS_CACCONFIG_CGIND },
1652 { 0x5, 0xffff0000, 16, 0x1143, SISLANDS_CACCONFIG_CGIND },
1653 { 0x6, 0x0000ffff, 0, 0xe17, SISLANDS_CACCONFIG_CGIND },
1654 { 0x6, 0xffff0000, 16, 0x441, SISLANDS_CACCONFIG_CGIND },
1655 { 0x18f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1656 { 0x7, 0x0000ffff, 0, 0x28b, SISLANDS_CACCONFIG_CGIND },
1657 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1658 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1659 { 0x8, 0xffff0000, 16, 0xabe, SISLANDS_CACCONFIG_CGIND },
1660 { 0x9, 0x0000ffff, 0, 0xf11, SISLANDS_CACCONFIG_CGIND },
1661 { 0xa, 0x0000ffff, 0, 0x907, SISLANDS_CACCONFIG_CGIND },
1662 { 0xb, 0x0000ffff, 0, 0xb45, SISLANDS_CACCONFIG_CGIND },
1663 { 0xb, 0xffff0000, 16, 0xd1e, SISLANDS_CACCONFIG_CGIND },
1664 { 0xc, 0x0000ffff, 0, 0xa2c, SISLANDS_CACCONFIG_CGIND },
1665 { 0xd, 0x0000ffff, 0, 0x62, SISLANDS_CACCONFIG_CGIND },
1666 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1667 { 0xe, 0x0000ffff, 0, 0x1f3, SISLANDS_CACCONFIG_CGIND },
1668 { 0xf, 0x0000ffff, 0, 0x42, SISLANDS_CACCONFIG_CGIND },
1669 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1670 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1671 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1672 { 0x11, 0x0000ffff, 0, 0x709, SISLANDS_CACCONFIG_CGIND },
1673 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1674 { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1675 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1676 { 0x13, 0xffff0000, 16, 0x3a, SISLANDS_CACCONFIG_CGIND },
1677 { 0x14, 0x0000ffff, 0, 0x357, SISLANDS_CACCONFIG_CGIND },
1678 { 0x15, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND },
1679 { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1680 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1681 { 0x16, 0x0000ffff, 0, 0x314, SISLANDS_CACCONFIG_CGIND },
1682 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1683 { 0x17, 0x0000ffff, 0, 0x6d, SISLANDS_CACCONFIG_CGIND },
1684 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1685 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1686 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1687 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1688 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1689 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1690 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1691 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1692 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1693 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1694 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1695 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1696 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1697 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1698 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1699 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1700 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1701 { 0x6d, 0x0000ffff, 0, 0x1b9, SISLANDS_CACCONFIG_CGIND },
1702 { 0xFFFFFFFF }
1703 };
1704
1705 static const struct si_powertune_data powertune_data_hainan =
1706 {
1707 ((1 << 16) | 0x6993),
1708 5,
1709 0,
1710 9,
1711 105,
1712 {
1713 0UL,
1714 0UL,
1715 7194395UL,
1716 309631529UL,
1717 -1270850L,
1718 4513710L,
1719 100
1720 },
1721 117830498UL,
1722 12,
1723 {
1724 0,
1725 0,
1726 0,
1727 0,
1728 0,
1729 0,
1730 0,
1731 0
1732 },
1733 true
1734 };
1735
1736 struct rv7xx_power_info *rv770_get_pi(struct radeon_device *rdev);
1737 struct evergreen_power_info *evergreen_get_pi(struct radeon_device *rdev);
1738 struct ni_power_info *ni_get_pi(struct radeon_device *rdev);
1739 struct ni_ps *ni_get_ps(struct radeon_ps *rps);
1740
1741 extern int si_mc_load_microcode(struct radeon_device *rdev);
1742
1743 static int si_populate_voltage_value(struct radeon_device *rdev,
1744 const struct atom_voltage_table *table,
1745 u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage);
1746 static int si_get_std_voltage_value(struct radeon_device *rdev,
1747 SISLANDS_SMC_VOLTAGE_VALUE *voltage,
1748 u16 *std_voltage);
1749 static int si_write_smc_soft_register(struct radeon_device *rdev,
1750 u16 reg_offset, u32 value);
1751 static int si_convert_power_level_to_smc(struct radeon_device *rdev,
1752 struct rv7xx_pl *pl,
1753 SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level);
1754 static int si_calculate_sclk_params(struct radeon_device *rdev,
1755 u32 engine_clock,
1756 SISLANDS_SMC_SCLK_VALUE *sclk);
1757
1758 static struct si_power_info *si_get_pi(struct radeon_device *rdev)
1759 {
1760 struct si_power_info *pi = rdev->pm.dpm.priv;
1761
1762 return pi;
1763 }
1764
1765 static void si_calculate_leakage_for_v_and_t_formula(const struct ni_leakage_coeffients *coeff,
1766 u16 v, s32 t, u32 ileakage, u32 *leakage)
1767 {
1768 s64 kt, kv, leakage_w, i_leakage, vddc;
1769 s64 temperature, t_slope, t_intercept, av, bv, t_ref;
1770 s64 tmp;
1771
1772 i_leakage = div64_s64(drm_int2fixp(ileakage), 100);
1773 vddc = div64_s64(drm_int2fixp(v), 1000);
1774 temperature = div64_s64(drm_int2fixp(t), 1000);
1775
1776 t_slope = div64_s64(drm_int2fixp(coeff->t_slope), 100000000);
1777 t_intercept = div64_s64(drm_int2fixp(coeff->t_intercept), 100000000);
1778 av = div64_s64(drm_int2fixp(coeff->av), 100000000);
1779 bv = div64_s64(drm_int2fixp(coeff->bv), 100000000);
1780 t_ref = drm_int2fixp(coeff->t_ref);
1781
1782 tmp = drm_fixp_mul(t_slope, vddc) + t_intercept;
1783 kt = drm_fixp_exp(drm_fixp_mul(tmp, temperature));
1784 kt = drm_fixp_div(kt, drm_fixp_exp(drm_fixp_mul(tmp, t_ref)));
1785 kv = drm_fixp_mul(av, drm_fixp_exp(drm_fixp_mul(bv, vddc)));
1786
1787 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc);
1788
1789 *leakage = drm_fixp2int(leakage_w * 1000);
1790 }
1791
1792 static void si_calculate_leakage_for_v_and_t(struct radeon_device *rdev,
1793 const struct ni_leakage_coeffients *coeff,
1794 u16 v,
1795 s32 t,
1796 u32 i_leakage,
1797 u32 *leakage)
1798 {
1799 si_calculate_leakage_for_v_and_t_formula(coeff, v, t, i_leakage, leakage);
1800 }
1801
1802 static void si_calculate_leakage_for_v_formula(const struct ni_leakage_coeffients *coeff,
1803 const u32 fixed_kt, u16 v,
1804 u32 ileakage, u32 *leakage)
1805 {
1806 s64 kt, kv, leakage_w, i_leakage, vddc;
1807
1808 i_leakage = div64_s64(drm_int2fixp(ileakage), 100);
1809 vddc = div64_s64(drm_int2fixp(v), 1000);
1810
1811 kt = div64_s64(drm_int2fixp(fixed_kt), 100000000);
1812 kv = drm_fixp_mul(div64_s64(drm_int2fixp(coeff->av), 100000000),
1813 drm_fixp_exp(drm_fixp_mul(div64_s64(drm_int2fixp(coeff->bv), 100000000), vddc)));
1814
1815 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc);
1816
1817 *leakage = drm_fixp2int(leakage_w * 1000);
1818 }
1819
1820 static void si_calculate_leakage_for_v(struct radeon_device *rdev,
1821 const struct ni_leakage_coeffients *coeff,
1822 const u32 fixed_kt,
1823 u16 v,
1824 u32 i_leakage,
1825 u32 *leakage)
1826 {
1827 si_calculate_leakage_for_v_formula(coeff, fixed_kt, v, i_leakage, leakage);
1828 }
1829
1830
1831 static void si_update_dte_from_pl2(struct radeon_device *rdev,
1832 struct si_dte_data *dte_data)
1833 {
1834 u32 p_limit1 = rdev->pm.dpm.tdp_limit;
1835 u32 p_limit2 = rdev->pm.dpm.near_tdp_limit;
1836 u32 k = dte_data->k;
1837 u32 t_max = dte_data->max_t;
1838 u32 t_split[5] = { 10, 15, 20, 25, 30 };
1839 u32 t_0 = dte_data->t0;
1840 u32 i;
1841
1842 if (p_limit2 != 0 && p_limit2 <= p_limit1) {
1843 dte_data->tdep_count = 3;
1844
1845 for (i = 0; i < k; i++) {
1846 dte_data->r[i] =
1847 (t_split[i] * (t_max - t_0/(u32)1000) * (1 << 14)) /
1848 (p_limit2 * (u32)100);
1849 }
1850
1851 dte_data->tdep_r[1] = dte_data->r[4] * 2;
1852
1853 for (i = 2; i < SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE; i++) {
1854 dte_data->tdep_r[i] = dte_data->r[4];
1855 }
1856 } else {
1857 DRM_ERROR("Invalid PL2! DTE will not be updated.\n");
1858 }
1859 }
1860
1861 static void si_initialize_powertune_defaults(struct radeon_device *rdev)
1862 {
1863 struct ni_power_info *ni_pi = ni_get_pi(rdev);
1864 struct si_power_info *si_pi = si_get_pi(rdev);
1865 bool update_dte_from_pl2 = false;
1866
1867 if (rdev->family == CHIP_TAHITI) {
1868 si_pi->cac_weights = cac_weights_tahiti;
1869 si_pi->lcac_config = lcac_tahiti;
1870 si_pi->cac_override = cac_override_tahiti;
1871 si_pi->powertune_data = &powertune_data_tahiti;
1872 si_pi->dte_data = dte_data_tahiti;
1873
1874 switch (rdev->pdev->device) {
1875 case 0x6798:
1876 si_pi->dte_data.enable_dte_by_default = true;
1877 break;
1878 case 0x6799:
1879 si_pi->dte_data = dte_data_new_zealand;
1880 break;
1881 case 0x6790:
1882 case 0x6791:
1883 case 0x6792:
1884 case 0x679E:
1885 si_pi->dte_data = dte_data_aruba_pro;
1886 update_dte_from_pl2 = true;
1887 break;
1888 case 0x679B:
1889 si_pi->dte_data = dte_data_malta;
1890 update_dte_from_pl2 = true;
1891 break;
1892 case 0x679A:
1893 si_pi->dte_data = dte_data_tahiti_pro;
1894 update_dte_from_pl2 = true;
1895 break;
1896 default:
1897 if (si_pi->dte_data.enable_dte_by_default == true)
1898 DRM_ERROR("DTE is not enabled!\n");
1899 break;
1900 }
1901 } else if (rdev->family == CHIP_PITCAIRN) {
1902 switch (rdev->pdev->device) {
1903 case 0x6810:
1904 case 0x6818:
1905 si_pi->cac_weights = cac_weights_pitcairn;
1906 si_pi->lcac_config = lcac_pitcairn;
1907 si_pi->cac_override = cac_override_pitcairn;
1908 si_pi->powertune_data = &powertune_data_pitcairn;
1909 si_pi->dte_data = dte_data_curacao_xt;
1910 update_dte_from_pl2 = true;
1911 break;
1912 case 0x6819:
1913 case 0x6811:
1914 si_pi->cac_weights = cac_weights_pitcairn;
1915 si_pi->lcac_config = lcac_pitcairn;
1916 si_pi->cac_override = cac_override_pitcairn;
1917 si_pi->powertune_data = &powertune_data_pitcairn;
1918 si_pi->dte_data = dte_data_curacao_pro;
1919 update_dte_from_pl2 = true;
1920 break;
1921 case 0x6800:
1922 case 0x6806:
1923 si_pi->cac_weights = cac_weights_pitcairn;
1924 si_pi->lcac_config = lcac_pitcairn;
1925 si_pi->cac_override = cac_override_pitcairn;
1926 si_pi->powertune_data = &powertune_data_pitcairn;
1927 si_pi->dte_data = dte_data_neptune_xt;
1928 update_dte_from_pl2 = true;
1929 break;
1930 default:
1931 si_pi->cac_weights = cac_weights_pitcairn;
1932 si_pi->lcac_config = lcac_pitcairn;
1933 si_pi->cac_override = cac_override_pitcairn;
1934 si_pi->powertune_data = &powertune_data_pitcairn;
1935 si_pi->dte_data = dte_data_pitcairn;
1936 break;
1937 }
1938 } else if (rdev->family == CHIP_VERDE) {
1939 si_pi->lcac_config = lcac_cape_verde;
1940 si_pi->cac_override = cac_override_cape_verde;
1941 si_pi->powertune_data = &powertune_data_cape_verde;
1942
1943 switch (rdev->pdev->device) {
1944 case 0x683B:
1945 case 0x683F:
1946 case 0x6829:
1947 case 0x6835:
1948 si_pi->cac_weights = cac_weights_cape_verde_pro;
1949 si_pi->dte_data = dte_data_cape_verde;
1950 break;
1951 case 0x6825:
1952 case 0x6827:
1953 si_pi->cac_weights = cac_weights_heathrow;
1954 si_pi->dte_data = dte_data_cape_verde;
1955 break;
1956 case 0x6824:
1957 case 0x682D:
1958 si_pi->cac_weights = cac_weights_chelsea_xt;
1959 si_pi->dte_data = dte_data_cape_verde;
1960 break;
1961 case 0x682F:
1962 si_pi->cac_weights = cac_weights_chelsea_pro;
1963 si_pi->dte_data = dte_data_cape_verde;
1964 break;
1965 case 0x6820:
1966 si_pi->cac_weights = cac_weights_heathrow;
1967 si_pi->dte_data = dte_data_venus_xtx;
1968 break;
1969 case 0x6821:
1970 si_pi->cac_weights = cac_weights_heathrow;
1971 si_pi->dte_data = dte_data_venus_xt;
1972 break;
1973 case 0x6823:
1974 si_pi->cac_weights = cac_weights_chelsea_pro;
1975 si_pi->dte_data = dte_data_venus_pro;
1976 break;
1977 case 0x682B:
1978 si_pi->cac_weights = cac_weights_chelsea_pro;
1979 si_pi->dte_data = dte_data_venus_pro;
1980 break;
1981 default:
1982 si_pi->cac_weights = cac_weights_cape_verde;
1983 si_pi->dte_data = dte_data_cape_verde;
1984 break;
1985 }
1986 } else if (rdev->family == CHIP_OLAND) {
1987 switch (rdev->pdev->device) {
1988 case 0x6601:
1989 case 0x6621:
1990 case 0x6603:
1991 si_pi->cac_weights = cac_weights_mars_pro;
1992 si_pi->lcac_config = lcac_mars_pro;
1993 si_pi->cac_override = cac_override_oland;
1994 si_pi->powertune_data = &powertune_data_mars_pro;
1995 si_pi->dte_data = dte_data_mars_pro;
1996 update_dte_from_pl2 = true;
1997 break;
1998 case 0x6600:
1999 case 0x6606:
2000 case 0x6620:
2001 si_pi->cac_weights = cac_weights_mars_xt;
2002 si_pi->lcac_config = lcac_mars_pro;
2003 si_pi->cac_override = cac_override_oland;
2004 si_pi->powertune_data = &powertune_data_mars_pro;
2005 si_pi->dte_data = dte_data_mars_pro;
2006 update_dte_from_pl2 = true;
2007 break;
2008 case 0x6611:
2009 si_pi->cac_weights = cac_weights_oland_pro;
2010 si_pi->lcac_config = lcac_mars_pro;
2011 si_pi->cac_override = cac_override_oland;
2012 si_pi->powertune_data = &powertune_data_mars_pro;
2013 si_pi->dte_data = dte_data_mars_pro;
2014 update_dte_from_pl2 = true;
2015 break;
2016 case 0x6610:
2017 si_pi->cac_weights = cac_weights_oland_xt;
2018 si_pi->lcac_config = lcac_mars_pro;
2019 si_pi->cac_override = cac_override_oland;
2020 si_pi->powertune_data = &powertune_data_mars_pro;
2021 si_pi->dte_data = dte_data_mars_pro;
2022 update_dte_from_pl2 = true;
2023 break;
2024 default:
2025 si_pi->cac_weights = cac_weights_oland;
2026 si_pi->lcac_config = lcac_oland;
2027 si_pi->cac_override = cac_override_oland;
2028 si_pi->powertune_data = &powertune_data_oland;
2029 si_pi->dte_data = dte_data_oland;
2030 break;
2031 }
2032 } else if (rdev->family == CHIP_HAINAN) {
2033 si_pi->cac_weights = cac_weights_hainan;
2034 si_pi->lcac_config = lcac_oland;
2035 si_pi->cac_override = cac_override_oland;
2036 si_pi->powertune_data = &powertune_data_hainan;
2037 si_pi->dte_data = dte_data_sun_xt;
2038 update_dte_from_pl2 = true;
2039 } else {
2040 DRM_ERROR("Unknown SI asic revision, failed to initialize PowerTune!\n");
2041 return;
2042 }
2043
2044 ni_pi->enable_power_containment = false;
2045 ni_pi->enable_cac = false;
2046 ni_pi->enable_sq_ramping = false;
2047 si_pi->enable_dte = false;
2048
2049 if (si_pi->powertune_data->enable_powertune_by_default) {
2050 ni_pi->enable_power_containment= true;
2051 ni_pi->enable_cac = true;
2052 if (si_pi->dte_data.enable_dte_by_default) {
2053 si_pi->enable_dte = true;
2054 if (update_dte_from_pl2)
2055 si_update_dte_from_pl2(rdev, &si_pi->dte_data);
2056
2057 }
2058 ni_pi->enable_sq_ramping = true;
2059 }
2060
2061 ni_pi->driver_calculate_cac_leakage = true;
2062 ni_pi->cac_configuration_required = true;
2063
2064 if (ni_pi->cac_configuration_required) {
2065 ni_pi->support_cac_long_term_average = true;
2066 si_pi->dyn_powertune_data.l2_lta_window_size =
2067 si_pi->powertune_data->l2_lta_window_size_default;
2068 si_pi->dyn_powertune_data.lts_truncate =
2069 si_pi->powertune_data->lts_truncate_default;
2070 } else {
2071 ni_pi->support_cac_long_term_average = false;
2072 si_pi->dyn_powertune_data.l2_lta_window_size = 0;
2073 si_pi->dyn_powertune_data.lts_truncate = 0;
2074 }
2075
2076 si_pi->dyn_powertune_data.disable_uvd_powertune = false;
2077 }
2078
2079 static u32 si_get_smc_power_scaling_factor(struct radeon_device *rdev)
2080 {
2081 return 1;
2082 }
2083
2084 static u32 si_calculate_cac_wintime(struct radeon_device *rdev)
2085 {
2086 u32 xclk;
2087 u32 wintime;
2088 u32 cac_window;
2089 u32 cac_window_size;
2090
2091 xclk = radeon_get_xclk(rdev);
2092
2093 if (xclk == 0)
2094 return 0;
2095
2096 cac_window = RREG32(CG_CAC_CTRL) & CAC_WINDOW_MASK;
2097 cac_window_size = ((cac_window & 0xFFFF0000) >> 16) * (cac_window & 0x0000FFFF);
2098
2099 wintime = (cac_window_size * 100) / xclk;
2100
2101 return wintime;
2102 }
2103
2104 static u32 si_scale_power_for_smc(u32 power_in_watts, u32 scaling_factor)
2105 {
2106 return power_in_watts;
2107 }
2108
2109 static int si_calculate_adjusted_tdp_limits(struct radeon_device *rdev,
2110 bool adjust_polarity,
2111 u32 tdp_adjustment,
2112 u32 *tdp_limit,
2113 u32 *near_tdp_limit)
2114 {
2115 u32 adjustment_delta, max_tdp_limit;
2116
2117 if (tdp_adjustment > (u32)rdev->pm.dpm.tdp_od_limit)
2118 return -EINVAL;
2119
2120 max_tdp_limit = ((100 + 100) * rdev->pm.dpm.tdp_limit) / 100;
2121
2122 if (adjust_polarity) {
2123 *tdp_limit = ((100 + tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100;
2124 *near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted + (*tdp_limit - rdev->pm.dpm.tdp_limit);
2125 } else {
2126 *tdp_limit = ((100 - tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100;
2127 adjustment_delta = rdev->pm.dpm.tdp_limit - *tdp_limit;
2128 if (adjustment_delta < rdev->pm.dpm.near_tdp_limit_adjusted)
2129 *near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted - adjustment_delta;
2130 else
2131 *near_tdp_limit = 0;
2132 }
2133
2134 if ((*tdp_limit <= 0) || (*tdp_limit > max_tdp_limit))
2135 return -EINVAL;
2136 if ((*near_tdp_limit <= 0) || (*near_tdp_limit > *tdp_limit))
2137 return -EINVAL;
2138
2139 return 0;
2140 }
2141
2142 static int si_populate_smc_tdp_limits(struct radeon_device *rdev,
2143 struct radeon_ps *radeon_state)
2144 {
2145 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2146 struct si_power_info *si_pi = si_get_pi(rdev);
2147
2148 if (ni_pi->enable_power_containment) {
2149 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable;
2150 PP_SIslands_PAPMParameters *papm_parm;
2151 struct radeon_ppm_table *ppm = rdev->pm.dpm.dyn_state.ppm_table;
2152 u32 scaling_factor = si_get_smc_power_scaling_factor(rdev);
2153 u32 tdp_limit;
2154 u32 near_tdp_limit;
2155 int ret;
2156
2157 if (scaling_factor == 0)
2158 return -EINVAL;
2159
2160 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE));
2161
2162 ret = si_calculate_adjusted_tdp_limits(rdev,
2163 false, /* ??? */
2164 rdev->pm.dpm.tdp_adjustment,
2165 &tdp_limit,
2166 &near_tdp_limit);
2167 if (ret)
2168 return ret;
2169
2170 smc_table->dpm2Params.TDPLimit =
2171 cpu_to_be32(si_scale_power_for_smc(tdp_limit, scaling_factor) * 1000);
2172 smc_table->dpm2Params.NearTDPLimit =
2173 cpu_to_be32(si_scale_power_for_smc(near_tdp_limit, scaling_factor) * 1000);
2174 smc_table->dpm2Params.SafePowerLimit =
2175 cpu_to_be32(si_scale_power_for_smc((near_tdp_limit * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000);
2176
2177 ret = si_copy_bytes_to_smc(rdev,
2178 (si_pi->state_table_start + offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) +
2179 offsetof(PP_SIslands_DPM2Parameters, TDPLimit)),
2180 (u8 *)(&(smc_table->dpm2Params.TDPLimit)),
2181 sizeof(u32) * 3,
2182 si_pi->sram_end);
2183 if (ret)
2184 return ret;
2185
2186 if (si_pi->enable_ppm) {
2187 papm_parm = &si_pi->papm_parm;
2188 memset(papm_parm, 0, sizeof(PP_SIslands_PAPMParameters));
2189 papm_parm->NearTDPLimitTherm = cpu_to_be32(ppm->dgpu_tdp);
2190 papm_parm->dGPU_T_Limit = cpu_to_be32(ppm->tj_max);
2191 papm_parm->dGPU_T_Warning = cpu_to_be32(95);
2192 papm_parm->dGPU_T_Hysteresis = cpu_to_be32(5);
2193 papm_parm->PlatformPowerLimit = 0xffffffff;
2194 papm_parm->NearTDPLimitPAPM = 0xffffffff;
2195
2196 ret = si_copy_bytes_to_smc(rdev, si_pi->papm_cfg_table_start,
2197 (u8 *)papm_parm,
2198 sizeof(PP_SIslands_PAPMParameters),
2199 si_pi->sram_end);
2200 if (ret)
2201 return ret;
2202 }
2203 }
2204 return 0;
2205 }
2206
2207 static int si_populate_smc_tdp_limits_2(struct radeon_device *rdev,
2208 struct radeon_ps *radeon_state)
2209 {
2210 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2211 struct si_power_info *si_pi = si_get_pi(rdev);
2212
2213 if (ni_pi->enable_power_containment) {
2214 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable;
2215 u32 scaling_factor = si_get_smc_power_scaling_factor(rdev);
2216 int ret;
2217
2218 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE));
2219
2220 smc_table->dpm2Params.NearTDPLimit =
2221 cpu_to_be32(si_scale_power_for_smc(rdev->pm.dpm.near_tdp_limit_adjusted, scaling_factor) * 1000);
2222 smc_table->dpm2Params.SafePowerLimit =
2223 cpu_to_be32(si_scale_power_for_smc((rdev->pm.dpm.near_tdp_limit_adjusted * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000);
2224
2225 ret = si_copy_bytes_to_smc(rdev,
2226 (si_pi->state_table_start +
2227 offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) +
2228 offsetof(PP_SIslands_DPM2Parameters, NearTDPLimit)),
2229 (u8 *)(&(smc_table->dpm2Params.NearTDPLimit)),
2230 sizeof(u32) * 2,
2231 si_pi->sram_end);
2232 if (ret)
2233 return ret;
2234 }
2235
2236 return 0;
2237 }
2238
2239 static u16 si_calculate_power_efficiency_ratio(struct radeon_device *rdev,
2240 const u16 prev_std_vddc,
2241 const u16 curr_std_vddc)
2242 {
2243 u64 margin = (u64)SISLANDS_DPM2_PWREFFICIENCYRATIO_MARGIN;
2244 u64 prev_vddc = (u64)prev_std_vddc;
2245 u64 curr_vddc = (u64)curr_std_vddc;
2246 u64 pwr_efficiency_ratio, n, d;
2247
2248 if ((prev_vddc == 0) || (curr_vddc == 0))
2249 return 0;
2250
2251 n = div64_u64((u64)1024 * curr_vddc * curr_vddc * ((u64)1000 + margin), (u64)1000);
2252 d = prev_vddc * prev_vddc;
2253 pwr_efficiency_ratio = div64_u64(n, d);
2254
2255 if (pwr_efficiency_ratio > (u64)0xFFFF)
2256 return 0;
2257
2258 return (u16)pwr_efficiency_ratio;
2259 }
2260
2261 static bool si_should_disable_uvd_powertune(struct radeon_device *rdev,
2262 struct radeon_ps *radeon_state)
2263 {
2264 struct si_power_info *si_pi = si_get_pi(rdev);
2265
2266 if (si_pi->dyn_powertune_data.disable_uvd_powertune &&
2267 radeon_state->vclk && radeon_state->dclk)
2268 return true;
2269
2270 return false;
2271 }
2272
2273 static int si_populate_power_containment_values(struct radeon_device *rdev,
2274 struct radeon_ps *radeon_state,
2275 SISLANDS_SMC_SWSTATE *smc_state)
2276 {
2277 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
2278 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2279 struct ni_ps *state = ni_get_ps(radeon_state);
2280 SISLANDS_SMC_VOLTAGE_VALUE vddc;
2281 u32 prev_sclk;
2282 u32 max_sclk;
2283 u32 min_sclk;
2284 u16 prev_std_vddc;
2285 u16 curr_std_vddc;
2286 int i;
2287 u16 pwr_efficiency_ratio;
2288 u8 max_ps_percent;
2289 bool disable_uvd_power_tune;
2290 int ret;
2291
2292 if (ni_pi->enable_power_containment == false)
2293 return 0;
2294
2295 if (state->performance_level_count == 0)
2296 return -EINVAL;
2297
2298 if (smc_state->levelCount != state->performance_level_count)
2299 return -EINVAL;
2300
2301 disable_uvd_power_tune = si_should_disable_uvd_powertune(rdev, radeon_state);
2302
2303 smc_state->levels[0].dpm2.MaxPS = 0;
2304 smc_state->levels[0].dpm2.NearTDPDec = 0;
2305 smc_state->levels[0].dpm2.AboveSafeInc = 0;
2306 smc_state->levels[0].dpm2.BelowSafeInc = 0;
2307 smc_state->levels[0].dpm2.PwrEfficiencyRatio = 0;
2308
2309 for (i = 1; i < state->performance_level_count; i++) {
2310 prev_sclk = state->performance_levels[i-1].sclk;
2311 max_sclk = state->performance_levels[i].sclk;
2312 if (i == 1)
2313 max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_M;
2314 else
2315 max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_H;
2316
2317 if (prev_sclk > max_sclk)
2318 return -EINVAL;
2319
2320 if ((max_ps_percent == 0) ||
2321 (prev_sclk == max_sclk) ||
2322 disable_uvd_power_tune) {
2323 min_sclk = max_sclk;
2324 } else if (i == 1) {
2325 min_sclk = prev_sclk;
2326 } else {
2327 min_sclk = (prev_sclk * (u32)max_ps_percent) / 100;
2328 }
2329
2330 if (min_sclk < state->performance_levels[0].sclk)
2331 min_sclk = state->performance_levels[0].sclk;
2332
2333 if (min_sclk == 0)
2334 return -EINVAL;
2335
2336 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
2337 state->performance_levels[i-1].vddc, &vddc);
2338 if (ret)
2339 return ret;
2340
2341 ret = si_get_std_voltage_value(rdev, &vddc, &prev_std_vddc);
2342 if (ret)
2343 return ret;
2344
2345 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
2346 state->performance_levels[i].vddc, &vddc);
2347 if (ret)
2348 return ret;
2349
2350 ret = si_get_std_voltage_value(rdev, &vddc, &curr_std_vddc);
2351 if (ret)
2352 return ret;
2353
2354 pwr_efficiency_ratio = si_calculate_power_efficiency_ratio(rdev,
2355 prev_std_vddc, curr_std_vddc);
2356
2357 smc_state->levels[i].dpm2.MaxPS = (u8)((SISLANDS_DPM2_MAX_PULSE_SKIP * (max_sclk - min_sclk)) / max_sclk);
2358 smc_state->levels[i].dpm2.NearTDPDec = SISLANDS_DPM2_NEAR_TDP_DEC;
2359 smc_state->levels[i].dpm2.AboveSafeInc = SISLANDS_DPM2_ABOVE_SAFE_INC;
2360 smc_state->levels[i].dpm2.BelowSafeInc = SISLANDS_DPM2_BELOW_SAFE_INC;
2361 smc_state->levels[i].dpm2.PwrEfficiencyRatio = cpu_to_be16(pwr_efficiency_ratio);
2362 }
2363
2364 return 0;
2365 }
2366
2367 static int si_populate_sq_ramping_values(struct radeon_device *rdev,
2368 struct radeon_ps *radeon_state,
2369 SISLANDS_SMC_SWSTATE *smc_state)
2370 {
2371 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2372 struct ni_ps *state = ni_get_ps(radeon_state);
2373 u32 sq_power_throttle, sq_power_throttle2;
2374 bool enable_sq_ramping = ni_pi->enable_sq_ramping;
2375 int i;
2376
2377 if (state->performance_level_count == 0)
2378 return -EINVAL;
2379
2380 if (smc_state->levelCount != state->performance_level_count)
2381 return -EINVAL;
2382
2383 if (rdev->pm.dpm.sq_ramping_threshold == 0)
2384 return -EINVAL;
2385
2386 if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER > (MAX_POWER_MASK >> MAX_POWER_SHIFT))
2387 enable_sq_ramping = false;
2388
2389 if (SISLANDS_DPM2_SQ_RAMP_MIN_POWER > (MIN_POWER_MASK >> MIN_POWER_SHIFT))
2390 enable_sq_ramping = false;
2391
2392 if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA > (MAX_POWER_DELTA_MASK >> MAX_POWER_DELTA_SHIFT))
2393 enable_sq_ramping = false;
2394
2395 if (SISLANDS_DPM2_SQ_RAMP_STI_SIZE > (STI_SIZE_MASK >> STI_SIZE_SHIFT))
2396 enable_sq_ramping = false;
2397
2398 if (NISLANDS_DPM2_SQ_RAMP_LTI_RATIO <= (LTI_RATIO_MASK >> LTI_RATIO_SHIFT))
2399 enable_sq_ramping = false;
2400
2401 for (i = 0; i < state->performance_level_count; i++) {
2402 sq_power_throttle = 0;
2403 sq_power_throttle2 = 0;
2404
2405 if ((state->performance_levels[i].sclk >= rdev->pm.dpm.sq_ramping_threshold) &&
2406 enable_sq_ramping) {
2407 sq_power_throttle |= MAX_POWER(SISLANDS_DPM2_SQ_RAMP_MAX_POWER);
2408 sq_power_throttle |= MIN_POWER(SISLANDS_DPM2_SQ_RAMP_MIN_POWER);
2409 sq_power_throttle2 |= MAX_POWER_DELTA(SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA);
2410 sq_power_throttle2 |= STI_SIZE(SISLANDS_DPM2_SQ_RAMP_STI_SIZE);
2411 sq_power_throttle2 |= LTI_RATIO(SISLANDS_DPM2_SQ_RAMP_LTI_RATIO);
2412 } else {
2413 sq_power_throttle |= MAX_POWER_MASK | MIN_POWER_MASK;
2414 sq_power_throttle2 |= MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
2415 }
2416
2417 smc_state->levels[i].SQPowerThrottle = cpu_to_be32(sq_power_throttle);
2418 smc_state->levels[i].SQPowerThrottle_2 = cpu_to_be32(sq_power_throttle2);
2419 }
2420
2421 return 0;
2422 }
2423
2424 static int si_enable_power_containment(struct radeon_device *rdev,
2425 struct radeon_ps *radeon_new_state,
2426 bool enable)
2427 {
2428 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2429 PPSMC_Result smc_result;
2430 int ret = 0;
2431
2432 if (ni_pi->enable_power_containment) {
2433 if (enable) {
2434 if (!si_should_disable_uvd_powertune(rdev, radeon_new_state)) {
2435 smc_result = si_send_msg_to_smc(rdev, PPSMC_TDPClampingActive);
2436 if (smc_result != PPSMC_Result_OK) {
2437 ret = -EINVAL;
2438 ni_pi->pc_enabled = false;
2439 } else {
2440 ni_pi->pc_enabled = true;
2441 }
2442 }
2443 } else {
2444 smc_result = si_send_msg_to_smc(rdev, PPSMC_TDPClampingInactive);
2445 if (smc_result != PPSMC_Result_OK)
2446 ret = -EINVAL;
2447 ni_pi->pc_enabled = false;
2448 }
2449 }
2450
2451 return ret;
2452 }
2453
2454 static int si_initialize_smc_dte_tables(struct radeon_device *rdev)
2455 {
2456 struct si_power_info *si_pi = si_get_pi(rdev);
2457 int ret = 0;
2458 struct si_dte_data *dte_data = &si_pi->dte_data;
2459 Smc_SIslands_DTE_Configuration *dte_tables = NULL;
2460 u32 table_size;
2461 u8 tdep_count;
2462 u32 i;
2463
2464 if (dte_data == NULL)
2465 si_pi->enable_dte = false;
2466
2467 if (si_pi->enable_dte == false)
2468 return 0;
2469
2470 if (dte_data->k <= 0)
2471 return -EINVAL;
2472
2473 dte_tables = kzalloc(sizeof(Smc_SIslands_DTE_Configuration), GFP_KERNEL);
2474 if (dte_tables == NULL) {
2475 si_pi->enable_dte = false;
2476 return -ENOMEM;
2477 }
2478
2479 table_size = dte_data->k;
2480
2481 if (table_size > SMC_SISLANDS_DTE_MAX_FILTER_STAGES)
2482 table_size = SMC_SISLANDS_DTE_MAX_FILTER_STAGES;
2483
2484 tdep_count = dte_data->tdep_count;
2485 if (tdep_count > SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE)
2486 tdep_count = SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE;
2487
2488 dte_tables->K = cpu_to_be32(table_size);
2489 dte_tables->T0 = cpu_to_be32(dte_data->t0);
2490 dte_tables->MaxT = cpu_to_be32(dte_data->max_t);
2491 dte_tables->WindowSize = dte_data->window_size;
2492 dte_tables->temp_select = dte_data->temp_select;
2493 dte_tables->DTE_mode = dte_data->dte_mode;
2494 dte_tables->Tthreshold = cpu_to_be32(dte_data->t_threshold);
2495
2496 if (tdep_count > 0)
2497 table_size--;
2498
2499 for (i = 0; i < table_size; i++) {
2500 dte_tables->tau[i] = cpu_to_be32(dte_data->tau[i]);
2501 dte_tables->R[i] = cpu_to_be32(dte_data->r[i]);
2502 }
2503
2504 dte_tables->Tdep_count = tdep_count;
2505
2506 for (i = 0; i < (u32)tdep_count; i++) {
2507 dte_tables->T_limits[i] = dte_data->t_limits[i];
2508 dte_tables->Tdep_tau[i] = cpu_to_be32(dte_data->tdep_tau[i]);
2509 dte_tables->Tdep_R[i] = cpu_to_be32(dte_data->tdep_r[i]);
2510 }
2511
2512 ret = si_copy_bytes_to_smc(rdev, si_pi->dte_table_start, (u8 *)dte_tables,
2513 sizeof(Smc_SIslands_DTE_Configuration), si_pi->sram_end);
2514 kfree(dte_tables);
2515
2516 return ret;
2517 }
2518
2519 static int si_get_cac_std_voltage_max_min(struct radeon_device *rdev,
2520 u16 *max, u16 *min)
2521 {
2522 struct si_power_info *si_pi = si_get_pi(rdev);
2523 struct radeon_cac_leakage_table *table =
2524 &rdev->pm.dpm.dyn_state.cac_leakage_table;
2525 u32 i;
2526 u32 v0_loadline;
2527
2528
2529 if (table == NULL)
2530 return -EINVAL;
2531
2532 *max = 0;
2533 *min = 0xFFFF;
2534
2535 for (i = 0; i < table->count; i++) {
2536 if (table->entries[i].vddc > *max)
2537 *max = table->entries[i].vddc;
2538 if (table->entries[i].vddc < *min)
2539 *min = table->entries[i].vddc;
2540 }
2541
2542 if (si_pi->powertune_data->lkge_lut_v0_percent > 100)
2543 return -EINVAL;
2544
2545 v0_loadline = (*min) * (100 - si_pi->powertune_data->lkge_lut_v0_percent) / 100;
2546
2547 if (v0_loadline > 0xFFFFUL)
2548 return -EINVAL;
2549
2550 *min = (u16)v0_loadline;
2551
2552 if ((*min > *max) || (*max == 0) || (*min == 0))
2553 return -EINVAL;
2554
2555 return 0;
2556 }
2557
2558 static u16 si_get_cac_std_voltage_step(u16 max, u16 min)
2559 {
2560 return ((max - min) + (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1)) /
2561 SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES;
2562 }
2563
2564 static int si_init_dte_leakage_table(struct radeon_device *rdev,
2565 PP_SIslands_CacConfig *cac_tables,
2566 u16 vddc_max, u16 vddc_min, u16 vddc_step,
2567 u16 t0, u16 t_step)
2568 {
2569 struct si_power_info *si_pi = si_get_pi(rdev);
2570 u32 leakage;
2571 unsigned int i, j;
2572 s32 t;
2573 u32 smc_leakage;
2574 u32 scaling_factor;
2575 u16 voltage;
2576
2577 scaling_factor = si_get_smc_power_scaling_factor(rdev);
2578
2579 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++) {
2580 t = (1000 * (i * t_step + t0));
2581
2582 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) {
2583 voltage = vddc_max - (vddc_step * j);
2584
2585 si_calculate_leakage_for_v_and_t(rdev,
2586 &si_pi->powertune_data->leakage_coefficients,
2587 voltage,
2588 t,
2589 si_pi->dyn_powertune_data.cac_leakage,
2590 &leakage);
2591
2592 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4;
2593
2594 if (smc_leakage > 0xFFFF)
2595 smc_leakage = 0xFFFF;
2596
2597 cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] =
2598 cpu_to_be16((u16)smc_leakage);
2599 }
2600 }
2601 return 0;
2602 }
2603
2604 static int si_init_simplified_leakage_table(struct radeon_device *rdev,
2605 PP_SIslands_CacConfig *cac_tables,
2606 u16 vddc_max, u16 vddc_min, u16 vddc_step)
2607 {
2608 struct si_power_info *si_pi = si_get_pi(rdev);
2609 u32 leakage;
2610 unsigned int i, j;
2611 u32 smc_leakage;
2612 u32 scaling_factor;
2613 u16 voltage;
2614
2615 scaling_factor = si_get_smc_power_scaling_factor(rdev);
2616
2617 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) {
2618 voltage = vddc_max - (vddc_step * j);
2619
2620 si_calculate_leakage_for_v(rdev,
2621 &si_pi->powertune_data->leakage_coefficients,
2622 si_pi->powertune_data->fixed_kt,
2623 voltage,
2624 si_pi->dyn_powertune_data.cac_leakage,
2625 &leakage);
2626
2627 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4;
2628
2629 if (smc_leakage > 0xFFFF)
2630 smc_leakage = 0xFFFF;
2631
2632 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++)
2633 cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] =
2634 cpu_to_be16((u16)smc_leakage);
2635 }
2636 return 0;
2637 }
2638
2639 static int si_initialize_smc_cac_tables(struct radeon_device *rdev)
2640 {
2641 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2642 struct si_power_info *si_pi = si_get_pi(rdev);
2643 PP_SIslands_CacConfig *cac_tables = NULL;
2644 u16 vddc_max, vddc_min, vddc_step;
2645 u16 t0, t_step;
2646 u32 load_line_slope, reg;
2647 int ret = 0;
2648 u32 ticks_per_us = radeon_get_xclk(rdev) / 100;
2649
2650 if (ni_pi->enable_cac == false)
2651 return 0;
2652
2653 cac_tables = kzalloc(sizeof(PP_SIslands_CacConfig), GFP_KERNEL);
2654 if (!cac_tables)
2655 return -ENOMEM;
2656
2657 reg = RREG32(CG_CAC_CTRL) & ~CAC_WINDOW_MASK;
2658 reg |= CAC_WINDOW(si_pi->powertune_data->cac_window);
2659 WREG32(CG_CAC_CTRL, reg);
2660
2661 si_pi->dyn_powertune_data.cac_leakage = rdev->pm.dpm.cac_leakage;
2662 si_pi->dyn_powertune_data.dc_pwr_value =
2663 si_pi->powertune_data->dc_cac[NISLANDS_DCCAC_LEVEL_0];
2664 si_pi->dyn_powertune_data.wintime = si_calculate_cac_wintime(rdev);
2665 si_pi->dyn_powertune_data.shift_n = si_pi->powertune_data->shift_n_default;
2666
2667 si_pi->dyn_powertune_data.leakage_minimum_temperature = 80 * 1000;
2668
2669 ret = si_get_cac_std_voltage_max_min(rdev, &vddc_max, &vddc_min);
2670 if (ret)
2671 goto done_free;
2672
2673 vddc_step = si_get_cac_std_voltage_step(vddc_max, vddc_min);
2674 vddc_min = vddc_max - (vddc_step * (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1));
2675 t_step = 4;
2676 t0 = 60;
2677
2678 if (si_pi->enable_dte || ni_pi->driver_calculate_cac_leakage)
2679 ret = si_init_dte_leakage_table(rdev, cac_tables,
2680 vddc_max, vddc_min, vddc_step,
2681 t0, t_step);
2682 else
2683 ret = si_init_simplified_leakage_table(rdev, cac_tables,
2684 vddc_max, vddc_min, vddc_step);
2685 if (ret)
2686 goto done_free;
2687
2688 load_line_slope = ((u32)rdev->pm.dpm.load_line_slope << SMC_SISLANDS_SCALE_R) / 100;
2689
2690 cac_tables->l2numWin_TDP = cpu_to_be32(si_pi->dyn_powertune_data.l2_lta_window_size);
2691 cac_tables->lts_truncate_n = si_pi->dyn_powertune_data.lts_truncate;
2692 cac_tables->SHIFT_N = si_pi->dyn_powertune_data.shift_n;
2693 cac_tables->lkge_lut_V0 = cpu_to_be32((u32)vddc_min);
2694 cac_tables->lkge_lut_Vstep = cpu_to_be32((u32)vddc_step);
2695 cac_tables->R_LL = cpu_to_be32(load_line_slope);
2696 cac_tables->WinTime = cpu_to_be32(si_pi->dyn_powertune_data.wintime);
2697 cac_tables->calculation_repeats = cpu_to_be32(2);
2698 cac_tables->dc_cac = cpu_to_be32(0);
2699 cac_tables->log2_PG_LKG_SCALE = 12;
2700 cac_tables->cac_temp = si_pi->powertune_data->operating_temp;
2701 cac_tables->lkge_lut_T0 = cpu_to_be32((u32)t0);
2702 cac_tables->lkge_lut_Tstep = cpu_to_be32((u32)t_step);
2703
2704 ret = si_copy_bytes_to_smc(rdev, si_pi->cac_table_start, (u8 *)cac_tables,
2705 sizeof(PP_SIslands_CacConfig), si_pi->sram_end);
2706
2707 if (ret)
2708 goto done_free;
2709
2710 ret = si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_ticks_per_us, ticks_per_us);
2711
2712 done_free:
2713 if (ret) {
2714 ni_pi->enable_cac = false;
2715 ni_pi->enable_power_containment = false;
2716 }
2717
2718 kfree(cac_tables);
2719
2720 return 0;
2721 }
2722
2723 static int si_program_cac_config_registers(struct radeon_device *rdev,
2724 const struct si_cac_config_reg *cac_config_regs)
2725 {
2726 const struct si_cac_config_reg *config_regs = cac_config_regs;
2727 u32 data = 0, offset;
2728
2729 if (!config_regs)
2730 return -EINVAL;
2731
2732 while (config_regs->offset != 0xFFFFFFFF) {
2733 switch (config_regs->type) {
2734 case SISLANDS_CACCONFIG_CGIND:
2735 offset = SMC_CG_IND_START + config_regs->offset;
2736 if (offset < SMC_CG_IND_END)
2737 data = RREG32_SMC(offset);
2738 break;
2739 default:
2740 data = RREG32(config_regs->offset << 2);
2741 break;
2742 }
2743
2744 data &= ~config_regs->mask;
2745 data |= ((config_regs->value << config_regs->shift) & config_regs->mask);
2746
2747 switch (config_regs->type) {
2748 case SISLANDS_CACCONFIG_CGIND:
2749 offset = SMC_CG_IND_START + config_regs->offset;
2750 if (offset < SMC_CG_IND_END)
2751 WREG32_SMC(offset, data);
2752 break;
2753 default:
2754 WREG32(config_regs->offset << 2, data);
2755 break;
2756 }
2757 config_regs++;
2758 }
2759 return 0;
2760 }
2761
2762 static int si_initialize_hardware_cac_manager(struct radeon_device *rdev)
2763 {
2764 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2765 struct si_power_info *si_pi = si_get_pi(rdev);
2766 int ret;
2767
2768 if ((ni_pi->enable_cac == false) ||
2769 (ni_pi->cac_configuration_required == false))
2770 return 0;
2771
2772 ret = si_program_cac_config_registers(rdev, si_pi->lcac_config);
2773 if (ret)
2774 return ret;
2775 ret = si_program_cac_config_registers(rdev, si_pi->cac_override);
2776 if (ret)
2777 return ret;
2778 ret = si_program_cac_config_registers(rdev, si_pi->cac_weights);
2779 if (ret)
2780 return ret;
2781
2782 return 0;
2783 }
2784
2785 static int si_enable_smc_cac(struct radeon_device *rdev,
2786 struct radeon_ps *radeon_new_state,
2787 bool enable)
2788 {
2789 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2790 struct si_power_info *si_pi = si_get_pi(rdev);
2791 PPSMC_Result smc_result;
2792 int ret = 0;
2793
2794 if (ni_pi->enable_cac) {
2795 if (enable) {
2796 if (!si_should_disable_uvd_powertune(rdev, radeon_new_state)) {
2797 if (ni_pi->support_cac_long_term_average) {
2798 smc_result = si_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgEnable);
2799 if (smc_result != PPSMC_Result_OK)
2800 ni_pi->support_cac_long_term_average = false;
2801 }
2802
2803 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableCac);
2804 if (smc_result != PPSMC_Result_OK) {
2805 ret = -EINVAL;
2806 ni_pi->cac_enabled = false;
2807 } else {
2808 ni_pi->cac_enabled = true;
2809 }
2810
2811 if (si_pi->enable_dte) {
2812 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableDTE);
2813 if (smc_result != PPSMC_Result_OK)
2814 ret = -EINVAL;
2815 }
2816 }
2817 } else if (ni_pi->cac_enabled) {
2818 if (si_pi->enable_dte)
2819 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_DisableDTE);
2820
2821 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_DisableCac);
2822
2823 ni_pi->cac_enabled = false;
2824
2825 if (ni_pi->support_cac_long_term_average)
2826 smc_result = si_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgDisable);
2827 }
2828 }
2829 return ret;
2830 }
2831
2832 static int si_init_smc_spll_table(struct radeon_device *rdev)
2833 {
2834 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2835 struct si_power_info *si_pi = si_get_pi(rdev);
2836 SMC_SISLANDS_SPLL_DIV_TABLE *spll_table;
2837 SISLANDS_SMC_SCLK_VALUE sclk_params;
2838 u32 fb_div, p_div;
2839 u32 clk_s, clk_v;
2840 u32 sclk = 0;
2841 int ret = 0;
2842 u32 tmp;
2843 int i;
2844
2845 if (si_pi->spll_table_start == 0)
2846 return -EINVAL;
2847
2848 spll_table = kzalloc(sizeof(SMC_SISLANDS_SPLL_DIV_TABLE), GFP_KERNEL);
2849 if (spll_table == NULL)
2850 return -ENOMEM;
2851
2852 for (i = 0; i < 256; i++) {
2853 ret = si_calculate_sclk_params(rdev, sclk, &sclk_params);
2854 if (ret)
2855 break;
2856
2857 p_div = (sclk_params.vCG_SPLL_FUNC_CNTL & SPLL_PDIV_A_MASK) >> SPLL_PDIV_A_SHIFT;
2858 fb_div = (sclk_params.vCG_SPLL_FUNC_CNTL_3 & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT;
2859 clk_s = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM & CLK_S_MASK) >> CLK_S_SHIFT;
2860 clk_v = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM_2 & CLK_V_MASK) >> CLK_V_SHIFT;
2861
2862 fb_div &= ~0x00001FFF;
2863 fb_div >>= 1;
2864 clk_v >>= 6;
2865
2866 if (p_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT))
2867 ret = -EINVAL;
2868 if (fb_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT))
2869 ret = -EINVAL;
2870 if (clk_s & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT))
2871 ret = -EINVAL;
2872 if (clk_v & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT))
2873 ret = -EINVAL;
2874
2875 if (ret)
2876 break;
2877
2878 tmp = ((fb_div << SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK) |
2879 ((p_div << SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK);
2880 spll_table->freq[i] = cpu_to_be32(tmp);
2881
2882 tmp = ((clk_v << SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK) |
2883 ((clk_s << SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK);
2884 spll_table->ss[i] = cpu_to_be32(tmp);
2885
2886 sclk += 512;
2887 }
2888
2889
2890 if (!ret)
2891 ret = si_copy_bytes_to_smc(rdev, si_pi->spll_table_start,
2892 (u8 *)spll_table, sizeof(SMC_SISLANDS_SPLL_DIV_TABLE),
2893 si_pi->sram_end);
2894
2895 if (ret)
2896 ni_pi->enable_power_containment = false;
2897
2898 kfree(spll_table);
2899
2900 return ret;
2901 }
2902
2903 static void si_apply_state_adjust_rules(struct radeon_device *rdev,
2904 struct radeon_ps *rps)
2905 {
2906 struct ni_ps *ps = ni_get_ps(rps);
2907 struct radeon_clock_and_voltage_limits *max_limits;
2908 bool disable_mclk_switching = false;
2909 bool disable_sclk_switching = false;
2910 u32 mclk, sclk;
2911 u16 vddc, vddci;
2912 u32 max_sclk_vddc, max_mclk_vddci, max_mclk_vddc;
2913 int i;
2914
2915 if ((rdev->pm.dpm.new_active_crtc_count > 1) ||
2916 ni_dpm_vblank_too_short(rdev))
2917 disable_mclk_switching = true;
2918
2919 if (rps->vclk || rps->dclk) {
2920 disable_mclk_switching = true;
2921 disable_sclk_switching = true;
2922 }
2923
2924 if (rdev->pm.dpm.ac_power)
2925 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
2926 else
2927 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
2928
2929 for (i = ps->performance_level_count - 2; i >= 0; i--) {
2930 if (ps->performance_levels[i].vddc > ps->performance_levels[i+1].vddc)
2931 ps->performance_levels[i].vddc = ps->performance_levels[i+1].vddc;
2932 }
2933 if (rdev->pm.dpm.ac_power == false) {
2934 for (i = 0; i < ps->performance_level_count; i++) {
2935 if (ps->performance_levels[i].mclk > max_limits->mclk)
2936 ps->performance_levels[i].mclk = max_limits->mclk;
2937 if (ps->performance_levels[i].sclk > max_limits->sclk)
2938 ps->performance_levels[i].sclk = max_limits->sclk;
2939 if (ps->performance_levels[i].vddc > max_limits->vddc)
2940 ps->performance_levels[i].vddc = max_limits->vddc;
2941 if (ps->performance_levels[i].vddci > max_limits->vddci)
2942 ps->performance_levels[i].vddci = max_limits->vddci;
2943 }
2944 }
2945
2946 /* limit clocks to max supported clocks based on voltage dependency tables */
2947 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
2948 &max_sclk_vddc);
2949 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
2950 &max_mclk_vddci);
2951 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
2952 &max_mclk_vddc);
2953
2954 for (i = 0; i < ps->performance_level_count; i++) {
2955 if (max_sclk_vddc) {
2956 if (ps->performance_levels[i].sclk > max_sclk_vddc)
2957 ps->performance_levels[i].sclk = max_sclk_vddc;
2958 }
2959 if (max_mclk_vddci) {
2960 if (ps->performance_levels[i].mclk > max_mclk_vddci)
2961 ps->performance_levels[i].mclk = max_mclk_vddci;
2962 }
2963 if (max_mclk_vddc) {
2964 if (ps->performance_levels[i].mclk > max_mclk_vddc)
2965 ps->performance_levels[i].mclk = max_mclk_vddc;
2966 }
2967 }
2968
2969 /* XXX validate the min clocks required for display */
2970
2971 if (disable_mclk_switching) {
2972 mclk = ps->performance_levels[ps->performance_level_count - 1].mclk;
2973 vddci = ps->performance_levels[ps->performance_level_count - 1].vddci;
2974 } else {
2975 mclk = ps->performance_levels[0].mclk;
2976 vddci = ps->performance_levels[0].vddci;
2977 }
2978
2979 if (disable_sclk_switching) {
2980 sclk = ps->performance_levels[ps->performance_level_count - 1].sclk;
2981 vddc = ps->performance_levels[ps->performance_level_count - 1].vddc;
2982 } else {
2983 sclk = ps->performance_levels[0].sclk;
2984 vddc = ps->performance_levels[0].vddc;
2985 }
2986
2987 /* adjusted low state */
2988 ps->performance_levels[0].sclk = sclk;
2989 ps->performance_levels[0].mclk = mclk;
2990 ps->performance_levels[0].vddc = vddc;
2991 ps->performance_levels[0].vddci = vddci;
2992
2993 if (disable_sclk_switching) {
2994 sclk = ps->performance_levels[0].sclk;
2995 for (i = 1; i < ps->performance_level_count; i++) {
2996 if (sclk < ps->performance_levels[i].sclk)
2997 sclk = ps->performance_levels[i].sclk;
2998 }
2999 for (i = 0; i < ps->performance_level_count; i++) {
3000 ps->performance_levels[i].sclk = sclk;
3001 ps->performance_levels[i].vddc = vddc;
3002 }
3003 } else {
3004 for (i = 1; i < ps->performance_level_count; i++) {
3005 if (ps->performance_levels[i].sclk < ps->performance_levels[i - 1].sclk)
3006 ps->performance_levels[i].sclk = ps->performance_levels[i - 1].sclk;
3007 if (ps->performance_levels[i].vddc < ps->performance_levels[i - 1].vddc)
3008 ps->performance_levels[i].vddc = ps->performance_levels[i - 1].vddc;
3009 }
3010 }
3011
3012 if (disable_mclk_switching) {
3013 mclk = ps->performance_levels[0].mclk;
3014 for (i = 1; i < ps->performance_level_count; i++) {
3015 if (mclk < ps->performance_levels[i].mclk)
3016 mclk = ps->performance_levels[i].mclk;
3017 }
3018 for (i = 0; i < ps->performance_level_count; i++) {
3019 ps->performance_levels[i].mclk = mclk;
3020 ps->performance_levels[i].vddci = vddci;
3021 }
3022 } else {
3023 for (i = 1; i < ps->performance_level_count; i++) {
3024 if (ps->performance_levels[i].mclk < ps->performance_levels[i - 1].mclk)
3025 ps->performance_levels[i].mclk = ps->performance_levels[i - 1].mclk;
3026 if (ps->performance_levels[i].vddci < ps->performance_levels[i - 1].vddci)
3027 ps->performance_levels[i].vddci = ps->performance_levels[i - 1].vddci;
3028 }
3029 }
3030
3031 for (i = 0; i < ps->performance_level_count; i++)
3032 btc_adjust_clock_combinations(rdev, max_limits,
3033 &ps->performance_levels[i]);
3034
3035 for (i = 0; i < ps->performance_level_count; i++) {
3036 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
3037 ps->performance_levels[i].sclk,
3038 max_limits->vddc, &ps->performance_levels[i].vddc);
3039 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
3040 ps->performance_levels[i].mclk,
3041 max_limits->vddci, &ps->performance_levels[i].vddci);
3042 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
3043 ps->performance_levels[i].mclk,
3044 max_limits->vddc, &ps->performance_levels[i].vddc);
3045 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk,
3046 rdev->clock.current_dispclk,
3047 max_limits->vddc, &ps->performance_levels[i].vddc);
3048 }
3049
3050 for (i = 0; i < ps->performance_level_count; i++) {
3051 btc_apply_voltage_delta_rules(rdev,
3052 max_limits->vddc, max_limits->vddci,
3053 &ps->performance_levels[i].vddc,
3054 &ps->performance_levels[i].vddci);
3055 }
3056
3057 ps->dc_compatible = true;
3058 for (i = 0; i < ps->performance_level_count; i++) {
3059 if (ps->performance_levels[i].vddc > rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc)
3060 ps->dc_compatible = false;
3061 }
3062
3063 }
3064
3065 #if 0
3066 static int si_read_smc_soft_register(struct radeon_device *rdev,
3067 u16 reg_offset, u32 *value)
3068 {
3069 struct si_power_info *si_pi = si_get_pi(rdev);
3070
3071 return si_read_smc_sram_dword(rdev,
3072 si_pi->soft_regs_start + reg_offset, value,
3073 si_pi->sram_end);
3074 }
3075 #endif
3076
3077 static int si_write_smc_soft_register(struct radeon_device *rdev,
3078 u16 reg_offset, u32 value)
3079 {
3080 struct si_power_info *si_pi = si_get_pi(rdev);
3081
3082 return si_write_smc_sram_dword(rdev,
3083 si_pi->soft_regs_start + reg_offset,
3084 value, si_pi->sram_end);
3085 }
3086
3087 static bool si_is_special_1gb_platform(struct radeon_device *rdev)
3088 {
3089 bool ret = false;
3090 u32 tmp, width, row, column, bank, density;
3091 bool is_memory_gddr5, is_special;
3092
3093 tmp = RREG32(MC_SEQ_MISC0);
3094 is_memory_gddr5 = (MC_SEQ_MISC0_GDDR5_VALUE == ((tmp & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT));
3095 is_special = (MC_SEQ_MISC0_REV_ID_VALUE == ((tmp & MC_SEQ_MISC0_REV_ID_MASK) >> MC_SEQ_MISC0_REV_ID_SHIFT))
3096 & (MC_SEQ_MISC0_VEN_ID_VALUE == ((tmp & MC_SEQ_MISC0_VEN_ID_MASK) >> MC_SEQ_MISC0_VEN_ID_SHIFT));
3097
3098 WREG32(MC_SEQ_IO_DEBUG_INDEX, 0xb);
3099 width = ((RREG32(MC_SEQ_IO_DEBUG_DATA) >> 1) & 1) ? 16 : 32;
3100
3101 tmp = RREG32(MC_ARB_RAMCFG);
3102 row = ((tmp & NOOFROWS_MASK) >> NOOFROWS_SHIFT) + 10;
3103 column = ((tmp & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT) + 8;
3104 bank = ((tmp & NOOFBANK_MASK) >> NOOFBANK_SHIFT) + 2;
3105
3106 density = (1 << (row + column - 20 + bank)) * width;
3107
3108 if ((rdev->pdev->device == 0x6819) &&
3109 is_memory_gddr5 && is_special && (density == 0x400))
3110 ret = true;
3111
3112 return ret;
3113 }
3114
3115 static void si_get_leakage_vddc(struct radeon_device *rdev)
3116 {
3117 struct si_power_info *si_pi = si_get_pi(rdev);
3118 u16 vddc, count = 0;
3119 int i, ret;
3120
3121 for (i = 0; i < SISLANDS_MAX_LEAKAGE_COUNT; i++) {
3122 ret = radeon_atom_get_leakage_vddc_based_on_leakage_idx(rdev, &vddc, SISLANDS_LEAKAGE_INDEX0 + i);
3123
3124 if (!ret && (vddc > 0) && (vddc != (SISLANDS_LEAKAGE_INDEX0 + i))) {
3125 si_pi->leakage_voltage.entries[count].voltage = vddc;
3126 si_pi->leakage_voltage.entries[count].leakage_index =
3127 SISLANDS_LEAKAGE_INDEX0 + i;
3128 count++;
3129 }
3130 }
3131 si_pi->leakage_voltage.count = count;
3132 }
3133
3134 static int si_get_leakage_voltage_from_leakage_index(struct radeon_device *rdev,
3135 u32 index, u16 *leakage_voltage)
3136 {
3137 struct si_power_info *si_pi = si_get_pi(rdev);
3138 int i;
3139
3140 if (leakage_voltage == NULL)
3141 return -EINVAL;
3142
3143 if ((index & 0xff00) != 0xff00)
3144 return -EINVAL;
3145
3146 if ((index & 0xff) > SISLANDS_MAX_LEAKAGE_COUNT + 1)
3147 return -EINVAL;
3148
3149 if (index < SISLANDS_LEAKAGE_INDEX0)
3150 return -EINVAL;
3151
3152 for (i = 0; i < si_pi->leakage_voltage.count; i++) {
3153 if (si_pi->leakage_voltage.entries[i].leakage_index == index) {
3154 *leakage_voltage = si_pi->leakage_voltage.entries[i].voltage;
3155 return 0;
3156 }
3157 }
3158 return -EAGAIN;
3159 }
3160
3161 static void si_set_dpm_event_sources(struct radeon_device *rdev, u32 sources)
3162 {
3163 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3164 bool want_thermal_protection;
3165 enum radeon_dpm_event_src dpm_event_src;
3166
3167 switch (sources) {
3168 case 0:
3169 default:
3170 want_thermal_protection = false;
3171 break;
3172 case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL):
3173 want_thermal_protection = true;
3174 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGITAL;
3175 break;
3176 case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL):
3177 want_thermal_protection = true;
3178 dpm_event_src = RADEON_DPM_EVENT_SRC_EXTERNAL;
3179 break;
3180 case ((1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL) |
3181 (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL)):
3182 want_thermal_protection = true;
3183 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL;
3184 break;
3185 }
3186
3187 if (want_thermal_protection) {
3188 WREG32_P(CG_THERMAL_CTRL, DPM_EVENT_SRC(dpm_event_src), ~DPM_EVENT_SRC_MASK);
3189 if (pi->thermal_protection)
3190 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS);
3191 } else {
3192 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS);
3193 }
3194 }
3195
3196 static void si_enable_auto_throttle_source(struct radeon_device *rdev,
3197 enum radeon_dpm_auto_throttle_src source,
3198 bool enable)
3199 {
3200 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3201
3202 if (enable) {
3203 if (!(pi->active_auto_throttle_sources & (1 << source))) {
3204 pi->active_auto_throttle_sources |= 1 << source;
3205 si_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);
3206 }
3207 } else {
3208 if (pi->active_auto_throttle_sources & (1 << source)) {
3209 pi->active_auto_throttle_sources &= ~(1 << source);
3210 si_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);
3211 }
3212 }
3213 }
3214
3215 static void si_start_dpm(struct radeon_device *rdev)
3216 {
3217 WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN);
3218 }
3219
3220 static void si_stop_dpm(struct radeon_device *rdev)
3221 {
3222 WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN);
3223 }
3224
3225 static void si_enable_sclk_control(struct radeon_device *rdev, bool enable)
3226 {
3227 if (enable)
3228 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF);
3229 else
3230 WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF);
3231
3232 }
3233
3234 #if 0
3235 static int si_notify_hardware_of_thermal_state(struct radeon_device *rdev,
3236 u32 thermal_level)
3237 {
3238 PPSMC_Result ret;
3239
3240 if (thermal_level == 0) {
3241 ret = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt);
3242 if (ret == PPSMC_Result_OK)
3243 return 0;
3244 else
3245 return -EINVAL;
3246 }
3247 return 0;
3248 }
3249
3250 static void si_notify_hardware_vpu_recovery_event(struct radeon_device *rdev)
3251 {
3252 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_tdr_is_about_to_happen, true);
3253 }
3254 #endif
3255
3256 #if 0
3257 static int si_notify_hw_of_powersource(struct radeon_device *rdev, bool ac_power)
3258 {
3259 if (ac_power)
3260 return (si_send_msg_to_smc(rdev, PPSMC_MSG_RunningOnAC) == PPSMC_Result_OK) ?
3261 0 : -EINVAL;
3262
3263 return 0;
3264 }
3265 #endif
3266
3267 static PPSMC_Result si_send_msg_to_smc_with_parameter(struct radeon_device *rdev,
3268 PPSMC_Msg msg, u32 parameter)
3269 {
3270 WREG32(SMC_SCRATCH0, parameter);
3271 return si_send_msg_to_smc(rdev, msg);
3272 }
3273
3274 static int si_restrict_performance_levels_before_switch(struct radeon_device *rdev)
3275 {
3276 if (si_send_msg_to_smc(rdev, PPSMC_MSG_NoForcedLevel) != PPSMC_Result_OK)
3277 return -EINVAL;
3278
3279 return (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) == PPSMC_Result_OK) ?
3280 0 : -EINVAL;
3281 }
3282
3283 int si_dpm_force_performance_level(struct radeon_device *rdev,
3284 enum radeon_dpm_forced_level level)
3285 {
3286 struct radeon_ps *rps = rdev->pm.dpm.current_ps;
3287 struct ni_ps *ps = ni_get_ps(rps);
3288 u32 levels = ps->performance_level_count;
3289
3290 if (level == RADEON_DPM_FORCED_LEVEL_HIGH) {
3291 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK)
3292 return -EINVAL;
3293
3294 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 1) != PPSMC_Result_OK)
3295 return -EINVAL;
3296 } else if (level == RADEON_DPM_FORCED_LEVEL_LOW) {
3297 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK)
3298 return -EINVAL;
3299
3300 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) != PPSMC_Result_OK)
3301 return -EINVAL;
3302 } else if (level == RADEON_DPM_FORCED_LEVEL_AUTO) {
3303 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK)
3304 return -EINVAL;
3305
3306 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK)
3307 return -EINVAL;
3308 }
3309
3310 rdev->pm.dpm.forced_level = level;
3311
3312 return 0;
3313 }
3314
3315 static int si_set_boot_state(struct radeon_device *rdev)
3316 {
3317 return (si_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToInitialState) == PPSMC_Result_OK) ?
3318 0 : -EINVAL;
3319 }
3320
3321 static int si_set_sw_state(struct radeon_device *rdev)
3322 {
3323 return (si_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToSwState) == PPSMC_Result_OK) ?
3324 0 : -EINVAL;
3325 }
3326
3327 static int si_halt_smc(struct radeon_device *rdev)
3328 {
3329 if (si_send_msg_to_smc(rdev, PPSMC_MSG_Halt) != PPSMC_Result_OK)
3330 return -EINVAL;
3331
3332 return (si_wait_for_smc_inactive(rdev) == PPSMC_Result_OK) ?
3333 0 : -EINVAL;
3334 }
3335
3336 static int si_resume_smc(struct radeon_device *rdev)
3337 {
3338 if (si_send_msg_to_smc(rdev, PPSMC_FlushDataCache) != PPSMC_Result_OK)
3339 return -EINVAL;
3340
3341 return (si_send_msg_to_smc(rdev, PPSMC_MSG_Resume) == PPSMC_Result_OK) ?
3342 0 : -EINVAL;
3343 }
3344
3345 static void si_dpm_start_smc(struct radeon_device *rdev)
3346 {
3347 si_program_jump_on_start(rdev);
3348 si_start_smc(rdev);
3349 si_start_smc_clock(rdev);
3350 }
3351
3352 static void si_dpm_stop_smc(struct radeon_device *rdev)
3353 {
3354 si_reset_smc(rdev);
3355 si_stop_smc_clock(rdev);
3356 }
3357
3358 static int si_process_firmware_header(struct radeon_device *rdev)
3359 {
3360 struct si_power_info *si_pi = si_get_pi(rdev);
3361 u32 tmp;
3362 int ret;
3363
3364 ret = si_read_smc_sram_dword(rdev,
3365 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3366 SISLANDS_SMC_FIRMWARE_HEADER_stateTable,
3367 &tmp, si_pi->sram_end);
3368 if (ret)
3369 return ret;
3370
3371 si_pi->state_table_start = tmp;
3372
3373 ret = si_read_smc_sram_dword(rdev,
3374 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3375 SISLANDS_SMC_FIRMWARE_HEADER_softRegisters,
3376 &tmp, si_pi->sram_end);
3377 if (ret)
3378 return ret;
3379
3380 si_pi->soft_regs_start = tmp;
3381
3382 ret = si_read_smc_sram_dword(rdev,
3383 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3384 SISLANDS_SMC_FIRMWARE_HEADER_mcRegisterTable,
3385 &tmp, si_pi->sram_end);
3386 if (ret)
3387 return ret;
3388
3389 si_pi->mc_reg_table_start = tmp;
3390
3391 ret = si_read_smc_sram_dword(rdev,
3392 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3393 SISLANDS_SMC_FIRMWARE_HEADER_mcArbDramAutoRefreshTable,
3394 &tmp, si_pi->sram_end);
3395 if (ret)
3396 return ret;
3397
3398 si_pi->arb_table_start = tmp;
3399
3400 ret = si_read_smc_sram_dword(rdev,
3401 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3402 SISLANDS_SMC_FIRMWARE_HEADER_CacConfigTable,
3403 &tmp, si_pi->sram_end);
3404 if (ret)
3405 return ret;
3406
3407 si_pi->cac_table_start = tmp;
3408
3409 ret = si_read_smc_sram_dword(rdev,
3410 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3411 SISLANDS_SMC_FIRMWARE_HEADER_DteConfiguration,
3412 &tmp, si_pi->sram_end);
3413 if (ret)
3414 return ret;
3415
3416 si_pi->dte_table_start = tmp;
3417
3418 ret = si_read_smc_sram_dword(rdev,
3419 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3420 SISLANDS_SMC_FIRMWARE_HEADER_spllTable,
3421 &tmp, si_pi->sram_end);
3422 if (ret)
3423 return ret;
3424
3425 si_pi->spll_table_start = tmp;
3426
3427 ret = si_read_smc_sram_dword(rdev,
3428 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3429 SISLANDS_SMC_FIRMWARE_HEADER_PAPMParameters,
3430 &tmp, si_pi->sram_end);
3431 if (ret)
3432 return ret;
3433
3434 si_pi->papm_cfg_table_start = tmp;
3435
3436 return ret;
3437 }
3438
3439 static void si_read_clock_registers(struct radeon_device *rdev)
3440 {
3441 struct si_power_info *si_pi = si_get_pi(rdev);
3442
3443 si_pi->clock_registers.cg_spll_func_cntl = RREG32(CG_SPLL_FUNC_CNTL);
3444 si_pi->clock_registers.cg_spll_func_cntl_2 = RREG32(CG_SPLL_FUNC_CNTL_2);
3445 si_pi->clock_registers.cg_spll_func_cntl_3 = RREG32(CG_SPLL_FUNC_CNTL_3);
3446 si_pi->clock_registers.cg_spll_func_cntl_4 = RREG32(CG_SPLL_FUNC_CNTL_4);
3447 si_pi->clock_registers.cg_spll_spread_spectrum = RREG32(CG_SPLL_SPREAD_SPECTRUM);
3448 si_pi->clock_registers.cg_spll_spread_spectrum_2 = RREG32(CG_SPLL_SPREAD_SPECTRUM_2);
3449 si_pi->clock_registers.dll_cntl = RREG32(DLL_CNTL);
3450 si_pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL);
3451 si_pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL);
3452 si_pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL);
3453 si_pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL);
3454 si_pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1);
3455 si_pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2);
3456 si_pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1);
3457 si_pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2);
3458 }
3459
3460 static void si_enable_thermal_protection(struct radeon_device *rdev,
3461 bool enable)
3462 {
3463 if (enable)
3464 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS);
3465 else
3466 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS);
3467 }
3468
3469 static void si_enable_acpi_power_management(struct radeon_device *rdev)
3470 {
3471 WREG32_P(GENERAL_PWRMGT, STATIC_PM_EN, ~STATIC_PM_EN);
3472 }
3473
3474 #if 0
3475 static int si_enter_ulp_state(struct radeon_device *rdev)
3476 {
3477 WREG32(SMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower);
3478
3479 udelay(25000);
3480
3481 return 0;
3482 }
3483
3484 static int si_exit_ulp_state(struct radeon_device *rdev)
3485 {
3486 int i;
3487
3488 WREG32(SMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower);
3489
3490 udelay(7000);
3491
3492 for (i = 0; i < rdev->usec_timeout; i++) {
3493 if (RREG32(SMC_RESP_0) == 1)
3494 break;
3495 udelay(1000);
3496 }
3497
3498 return 0;
3499 }
3500 #endif
3501
3502 static int si_notify_smc_display_change(struct radeon_device *rdev,
3503 bool has_display)
3504 {
3505 PPSMC_Msg msg = has_display ?
3506 PPSMC_MSG_HasDisplay : PPSMC_MSG_NoDisplay;
3507
3508 return (si_send_msg_to_smc(rdev, msg) == PPSMC_Result_OK) ?
3509 0 : -EINVAL;
3510 }
3511
3512 static void si_program_response_times(struct radeon_device *rdev)
3513 {
3514 u32 voltage_response_time, backbias_response_time, acpi_delay_time, vbi_time_out;
3515 u32 vddc_dly, acpi_dly, vbi_dly;
3516 u32 reference_clock;
3517
3518 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mvdd_chg_time, 1);
3519
3520 voltage_response_time = (u32)rdev->pm.dpm.voltage_response_time;
3521 backbias_response_time = (u32)rdev->pm.dpm.backbias_response_time;
3522
3523 if (voltage_response_time == 0)
3524 voltage_response_time = 1000;
3525
3526 acpi_delay_time = 15000;
3527 vbi_time_out = 100000;
3528
3529 reference_clock = radeon_get_xclk(rdev);
3530
3531 vddc_dly = (voltage_response_time * reference_clock) / 100;
3532 acpi_dly = (acpi_delay_time * reference_clock) / 100;
3533 vbi_dly = (vbi_time_out * reference_clock) / 100;
3534
3535 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_delay_vreg, vddc_dly);
3536 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_delay_acpi, acpi_dly);
3537 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mclk_chg_timeout, vbi_dly);
3538 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mc_block_delay, 0xAA);
3539 }
3540
3541 static void si_program_ds_registers(struct radeon_device *rdev)
3542 {
3543 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
3544 u32 tmp = 1; /* XXX: 0x10 on tahiti A0 */
3545
3546 if (eg_pi->sclk_deep_sleep) {
3547 WREG32_P(MISC_CLK_CNTL, DEEP_SLEEP_CLK_SEL(tmp), ~DEEP_SLEEP_CLK_SEL_MASK);
3548 WREG32_P(CG_SPLL_AUTOSCALE_CNTL, AUTOSCALE_ON_SS_CLEAR,
3549 ~AUTOSCALE_ON_SS_CLEAR);
3550 }
3551 }
3552
3553 static void si_program_display_gap(struct radeon_device *rdev)
3554 {
3555 u32 tmp, pipe;
3556 int i;
3557
3558 tmp = RREG32(CG_DISPLAY_GAP_CNTL) & ~(DISP1_GAP_MASK | DISP2_GAP_MASK);
3559 if (rdev->pm.dpm.new_active_crtc_count > 0)
3560 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
3561 else
3562 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE);
3563
3564 if (rdev->pm.dpm.new_active_crtc_count > 1)
3565 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
3566 else
3567 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE);
3568
3569 WREG32(CG_DISPLAY_GAP_CNTL, tmp);
3570
3571 tmp = RREG32(DCCG_DISP_SLOW_SELECT_REG);
3572 pipe = (tmp & DCCG_DISP1_SLOW_SELECT_MASK) >> DCCG_DISP1_SLOW_SELECT_SHIFT;
3573
3574 if ((rdev->pm.dpm.new_active_crtc_count > 0) &&
3575 (!(rdev->pm.dpm.new_active_crtcs & (1 << pipe)))) {
3576 /* find the first active crtc */
3577 for (i = 0; i < rdev->num_crtc; i++) {
3578 if (rdev->pm.dpm.new_active_crtcs & (1 << i))
3579 break;
3580 }
3581 if (i == rdev->num_crtc)
3582 pipe = 0;
3583 else
3584 pipe = i;
3585
3586 tmp &= ~DCCG_DISP1_SLOW_SELECT_MASK;
3587 tmp |= DCCG_DISP1_SLOW_SELECT(pipe);
3588 WREG32(DCCG_DISP_SLOW_SELECT_REG, tmp);
3589 }
3590
3591 /* Setting this to false forces the performance state to low if the crtcs are disabled.
3592 * This can be a problem on PowerXpress systems or if you want to use the card
3593 * for offscreen rendering or compute if there are no crtcs enabled. Set it to
3594 * true for now so that performance scales even if the displays are off.
3595 */
3596 si_notify_smc_display_change(rdev, true /*rdev->pm.dpm.new_active_crtc_count > 0*/);
3597 }
3598
3599 static void si_enable_spread_spectrum(struct radeon_device *rdev, bool enable)
3600 {
3601 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3602
3603 if (enable) {
3604 if (pi->sclk_ss)
3605 WREG32_P(GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, ~DYN_SPREAD_SPECTRUM_EN);
3606 } else {
3607 WREG32_P(CG_SPLL_SPREAD_SPECTRUM, 0, ~SSEN);
3608 WREG32_P(GENERAL_PWRMGT, 0, ~DYN_SPREAD_SPECTRUM_EN);
3609 }
3610 }
3611
3612 static void si_setup_bsp(struct radeon_device *rdev)
3613 {
3614 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3615 u32 xclk = radeon_get_xclk(rdev);
3616
3617 r600_calculate_u_and_p(pi->asi,
3618 xclk,
3619 16,
3620 &pi->bsp,
3621 &pi->bsu);
3622
3623 r600_calculate_u_and_p(pi->pasi,
3624 xclk,
3625 16,
3626 &pi->pbsp,
3627 &pi->pbsu);
3628
3629
3630 pi->dsp = BSP(pi->bsp) | BSU(pi->bsu);
3631 pi->psp = BSP(pi->pbsp) | BSU(pi->pbsu);
3632
3633 WREG32(CG_BSP, pi->dsp);
3634 }
3635
3636 static void si_program_git(struct radeon_device *rdev)
3637 {
3638 WREG32_P(CG_GIT, CG_GICST(R600_GICST_DFLT), ~CG_GICST_MASK);
3639 }
3640
3641 static void si_program_tp(struct radeon_device *rdev)
3642 {
3643 int i;
3644 enum r600_td td = R600_TD_DFLT;
3645
3646 for (i = 0; i < R600_PM_NUMBER_OF_TC; i++)
3647 WREG32(CG_FFCT_0 + (i * 4), (UTC_0(r600_utc[i]) | DTC_0(r600_dtc[i])));
3648
3649 if (td == R600_TD_AUTO)
3650 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL);
3651 else
3652 WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL);
3653
3654 if (td == R600_TD_UP)
3655 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE);
3656
3657 if (td == R600_TD_DOWN)
3658 WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE);
3659 }
3660
3661 static void si_program_tpp(struct radeon_device *rdev)
3662 {
3663 WREG32(CG_TPC, R600_TPC_DFLT);
3664 }
3665
3666 static void si_program_sstp(struct radeon_device *rdev)
3667 {
3668 WREG32(CG_SSP, (SSTU(R600_SSTU_DFLT) | SST(R600_SST_DFLT)));
3669 }
3670
3671 static void si_enable_display_gap(struct radeon_device *rdev)
3672 {
3673 u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL);
3674
3675 tmp &= ~(DISP1_GAP_MASK | DISP2_GAP_MASK);
3676 tmp |= (DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE) |
3677 DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE));
3678
3679 tmp &= ~(DISP1_GAP_MCHG_MASK | DISP2_GAP_MCHG_MASK);
3680 tmp |= (DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK) |
3681 DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE));
3682 WREG32(CG_DISPLAY_GAP_CNTL, tmp);
3683 }
3684
3685 static void si_program_vc(struct radeon_device *rdev)
3686 {
3687 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3688
3689 WREG32(CG_FTV, pi->vrc);
3690 }
3691
3692 static void si_clear_vc(struct radeon_device *rdev)
3693 {
3694 WREG32(CG_FTV, 0);
3695 }
3696
3697 u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock)
3698 {
3699 u8 mc_para_index;
3700
3701 if (memory_clock < 10000)
3702 mc_para_index = 0;
3703 else if (memory_clock >= 80000)
3704 mc_para_index = 0x0f;
3705 else
3706 mc_para_index = (u8)((memory_clock - 10000) / 5000 + 1);
3707 return mc_para_index;
3708 }
3709
3710 u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode)
3711 {
3712 u8 mc_para_index;
3713
3714 if (strobe_mode) {
3715 if (memory_clock < 12500)
3716 mc_para_index = 0x00;
3717 else if (memory_clock > 47500)
3718 mc_para_index = 0x0f;
3719 else
3720 mc_para_index = (u8)((memory_clock - 10000) / 2500);
3721 } else {
3722 if (memory_clock < 65000)
3723 mc_para_index = 0x00;
3724 else if (memory_clock > 135000)
3725 mc_para_index = 0x0f;
3726 else
3727 mc_para_index = (u8)((memory_clock - 60000) / 5000);
3728 }
3729 return mc_para_index;
3730 }
3731
3732 static u8 si_get_strobe_mode_settings(struct radeon_device *rdev, u32 mclk)
3733 {
3734 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3735 bool strobe_mode = false;
3736 u8 result = 0;
3737
3738 if (mclk <= pi->mclk_strobe_mode_threshold)
3739 strobe_mode = true;
3740
3741 if (pi->mem_gddr5)
3742 result = si_get_mclk_frequency_ratio(mclk, strobe_mode);
3743 else
3744 result = si_get_ddr3_mclk_frequency_ratio(mclk);
3745
3746 if (strobe_mode)
3747 result |= SISLANDS_SMC_STROBE_ENABLE;
3748
3749 return result;
3750 }
3751
3752 static int si_upload_firmware(struct radeon_device *rdev)
3753 {
3754 struct si_power_info *si_pi = si_get_pi(rdev);
3755 int ret;
3756
3757 si_reset_smc(rdev);
3758 si_stop_smc_clock(rdev);
3759
3760 ret = si_load_smc_ucode(rdev, si_pi->sram_end);
3761
3762 return ret;
3763 }
3764
3765 static bool si_validate_phase_shedding_tables(struct radeon_device *rdev,
3766 const struct atom_voltage_table *table,
3767 const struct radeon_phase_shedding_limits_table *limits)
3768 {
3769 u32 data, num_bits, num_levels;
3770
3771 if ((table == NULL) || (limits == NULL))
3772 return false;
3773
3774 data = table->mask_low;
3775
3776 num_bits = hweight32(data);
3777
3778 if (num_bits == 0)
3779 return false;
3780
3781 num_levels = (1 << num_bits);
3782
3783 if (table->count != num_levels)
3784 return false;
3785
3786 if (limits->count != (num_levels - 1))
3787 return false;
3788
3789 return true;
3790 }
3791
3792 void si_trim_voltage_table_to_fit_state_table(struct radeon_device *rdev,
3793 u32 max_voltage_steps,
3794 struct atom_voltage_table *voltage_table)
3795 {
3796 unsigned int i, diff;
3797
3798 if (voltage_table->count <= max_voltage_steps)
3799 return;
3800
3801 diff = voltage_table->count - max_voltage_steps;
3802
3803 for (i= 0; i < max_voltage_steps; i++)
3804 voltage_table->entries[i] = voltage_table->entries[i + diff];
3805
3806 voltage_table->count = max_voltage_steps;
3807 }
3808
3809 static int si_construct_voltage_tables(struct radeon_device *rdev)
3810 {
3811 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3812 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
3813 struct si_power_info *si_pi = si_get_pi(rdev);
3814 int ret;
3815
3816 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC,
3817 VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddc_voltage_table);
3818 if (ret)
3819 return ret;
3820
3821 if (eg_pi->vddc_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
3822 si_trim_voltage_table_to_fit_state_table(rdev,
3823 SISLANDS_MAX_NO_VREG_STEPS,
3824 &eg_pi->vddc_voltage_table);
3825
3826 if (eg_pi->vddci_control) {
3827 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDCI,
3828 VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddci_voltage_table);
3829 if (ret)
3830 return ret;
3831
3832 if (eg_pi->vddci_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
3833 si_trim_voltage_table_to_fit_state_table(rdev,
3834 SISLANDS_MAX_NO_VREG_STEPS,
3835 &eg_pi->vddci_voltage_table);
3836 }
3837
3838 if (pi->mvdd_control) {
3839 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_MVDDC,
3840 VOLTAGE_OBJ_GPIO_LUT, &si_pi->mvdd_voltage_table);
3841
3842 if (ret) {
3843 pi->mvdd_control = false;
3844 return ret;
3845 }
3846
3847 if (si_pi->mvdd_voltage_table.count == 0) {
3848 pi->mvdd_control = false;
3849 return -EINVAL;
3850 }
3851
3852 if (si_pi->mvdd_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
3853 si_trim_voltage_table_to_fit_state_table(rdev,
3854 SISLANDS_MAX_NO_VREG_STEPS,
3855 &si_pi->mvdd_voltage_table);
3856 }
3857
3858 if (si_pi->vddc_phase_shed_control) {
3859 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC,
3860 VOLTAGE_OBJ_PHASE_LUT, &si_pi->vddc_phase_shed_table);
3861 if (ret)
3862 si_pi->vddc_phase_shed_control = false;
3863
3864 if ((si_pi->vddc_phase_shed_table.count == 0) ||
3865 (si_pi->vddc_phase_shed_table.count > SISLANDS_MAX_NO_VREG_STEPS))
3866 si_pi->vddc_phase_shed_control = false;
3867 }
3868
3869 return 0;
3870 }
3871
3872 static void si_populate_smc_voltage_table(struct radeon_device *rdev,
3873 const struct atom_voltage_table *voltage_table,
3874 SISLANDS_SMC_STATETABLE *table)
3875 {
3876 unsigned int i;
3877
3878 for (i = 0; i < voltage_table->count; i++)
3879 table->lowSMIO[i] |= cpu_to_be32(voltage_table->entries[i].smio_low);
3880 }
3881
3882 static int si_populate_smc_voltage_tables(struct radeon_device *rdev,
3883 SISLANDS_SMC_STATETABLE *table)
3884 {
3885 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3886 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
3887 struct si_power_info *si_pi = si_get_pi(rdev);
3888 u8 i;
3889
3890 if (eg_pi->vddc_voltage_table.count) {
3891 si_populate_smc_voltage_table(rdev, &eg_pi->vddc_voltage_table, table);
3892 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC] =
3893 cpu_to_be32(eg_pi->vddc_voltage_table.mask_low);
3894
3895 for (i = 0; i < eg_pi->vddc_voltage_table.count; i++) {
3896 if (pi->max_vddc_in_table <= eg_pi->vddc_voltage_table.entries[i].value) {
3897 table->maxVDDCIndexInPPTable = i;
3898 break;
3899 }
3900 }
3901 }
3902
3903 if (eg_pi->vddci_voltage_table.count) {
3904 si_populate_smc_voltage_table(rdev, &eg_pi->vddci_voltage_table, table);
3905
3906 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDCI] =
3907 cpu_to_be32(eg_pi->vddci_voltage_table.mask_low);
3908 }
3909
3910
3911 if (si_pi->mvdd_voltage_table.count) {
3912 si_populate_smc_voltage_table(rdev, &si_pi->mvdd_voltage_table, table);
3913
3914 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_MVDD] =
3915 cpu_to_be32(si_pi->mvdd_voltage_table.mask_low);
3916 }
3917
3918 if (si_pi->vddc_phase_shed_control) {
3919 if (si_validate_phase_shedding_tables(rdev, &si_pi->vddc_phase_shed_table,
3920 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table)) {
3921 si_populate_smc_voltage_table(rdev, &si_pi->vddc_phase_shed_table, table);
3922
3923 table->phaseMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC] =
3924 cpu_to_be32(si_pi->vddc_phase_shed_table.mask_low);
3925
3926 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_phase_shedding_delay,
3927 (u32)si_pi->vddc_phase_shed_table.phase_delay);
3928 } else {
3929 si_pi->vddc_phase_shed_control = false;
3930 }
3931 }
3932
3933 return 0;
3934 }
3935
3936 static int si_populate_voltage_value(struct radeon_device *rdev,
3937 const struct atom_voltage_table *table,
3938 u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage)
3939 {
3940 unsigned int i;
3941
3942 for (i = 0; i < table->count; i++) {
3943 if (value <= table->entries[i].value) {
3944 voltage->index = (u8)i;
3945 voltage->value = cpu_to_be16(table->entries[i].value);
3946 break;
3947 }
3948 }
3949
3950 if (i >= table->count)
3951 return -EINVAL;
3952
3953 return 0;
3954 }
3955
3956 static int si_populate_mvdd_value(struct radeon_device *rdev, u32 mclk,
3957 SISLANDS_SMC_VOLTAGE_VALUE *voltage)
3958 {
3959 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3960 struct si_power_info *si_pi = si_get_pi(rdev);
3961
3962 if (pi->mvdd_control) {
3963 if (mclk <= pi->mvdd_split_frequency)
3964 voltage->index = 0;
3965 else
3966 voltage->index = (u8)(si_pi->mvdd_voltage_table.count) - 1;
3967
3968 voltage->value = cpu_to_be16(si_pi->mvdd_voltage_table.entries[voltage->index].value);
3969 }
3970 return 0;
3971 }
3972
3973 static int si_get_std_voltage_value(struct radeon_device *rdev,
3974 SISLANDS_SMC_VOLTAGE_VALUE *voltage,
3975 u16 *std_voltage)
3976 {
3977 u16 v_index;
3978 bool voltage_found = false;
3979 *std_voltage = be16_to_cpu(voltage->value);
3980
3981 if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries) {
3982 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_NEW_CAC_VOLTAGE) {
3983 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL)
3984 return -EINVAL;
3985
3986 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
3987 if (be16_to_cpu(voltage->value) ==
3988 (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
3989 voltage_found = true;
3990 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)
3991 *std_voltage =
3992 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc;
3993 else
3994 *std_voltage =
3995 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc;
3996 break;
3997 }
3998 }
3999
4000 if (!voltage_found) {
4001 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
4002 if (be16_to_cpu(voltage->value) <=
4003 (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
4004 voltage_found = true;
4005 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)
4006 *std_voltage =
4007 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc;
4008 else
4009 *std_voltage =
4010 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc;
4011 break;
4012 }
4013 }
4014 }
4015 } else {
4016 if ((u32)voltage->index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)
4017 *std_voltage = rdev->pm.dpm.dyn_state.cac_leakage_table.entries[voltage->index].vddc;
4018 }
4019 }
4020
4021 return 0;
4022 }
4023
4024 static int si_populate_std_voltage_value(struct radeon_device *rdev,
4025 u16 value, u8 index,
4026 SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4027 {
4028 voltage->index = index;
4029 voltage->value = cpu_to_be16(value);
4030
4031 return 0;
4032 }
4033
4034 static int si_populate_phase_shedding_value(struct radeon_device *rdev,
4035 const struct radeon_phase_shedding_limits_table *limits,
4036 u16 voltage, u32 sclk, u32 mclk,
4037 SISLANDS_SMC_VOLTAGE_VALUE *smc_voltage)
4038 {
4039 unsigned int i;
4040
4041 for (i = 0; i < limits->count; i++) {
4042 if ((voltage <= limits->entries[i].voltage) &&
4043 (sclk <= limits->entries[i].sclk) &&
4044 (mclk <= limits->entries[i].mclk))
4045 break;
4046 }
4047
4048 smc_voltage->phase_settings = (u8)i;
4049
4050 return 0;
4051 }
4052
4053 static int si_init_arb_table_index(struct radeon_device *rdev)
4054 {
4055 struct si_power_info *si_pi = si_get_pi(rdev);
4056 u32 tmp;
4057 int ret;
4058
4059 ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start, &tmp, si_pi->sram_end);
4060 if (ret)
4061 return ret;
4062
4063 tmp &= 0x00FFFFFF;
4064 tmp |= MC_CG_ARB_FREQ_F1 << 24;
4065
4066 return si_write_smc_sram_dword(rdev, si_pi->arb_table_start, tmp, si_pi->sram_end);
4067 }
4068
4069 static int si_initial_switch_from_arb_f0_to_f1(struct radeon_device *rdev)
4070 {
4071 return ni_copy_and_switch_arb_sets(rdev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
4072 }
4073
4074 static int si_reset_to_default(struct radeon_device *rdev)
4075 {
4076 return (si_send_msg_to_smc(rdev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ?
4077 0 : -EINVAL;
4078 }
4079
4080 static int si_force_switch_to_arb_f0(struct radeon_device *rdev)
4081 {
4082 struct si_power_info *si_pi = si_get_pi(rdev);
4083 u32 tmp;
4084 int ret;
4085
4086 ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start,
4087 &tmp, si_pi->sram_end);
4088 if (ret)
4089 return ret;
4090
4091 tmp = (tmp >> 24) & 0xff;
4092
4093 if (tmp == MC_CG_ARB_FREQ_F0)
4094 return 0;
4095
4096 return ni_copy_and_switch_arb_sets(rdev, tmp, MC_CG_ARB_FREQ_F0);
4097 }
4098
4099 static u32 si_calculate_memory_refresh_rate(struct radeon_device *rdev,
4100 u32 engine_clock)
4101 {
4102 u32 dram_rows;
4103 u32 dram_refresh_rate;
4104 u32 mc_arb_rfsh_rate;
4105 u32 tmp = (RREG32(MC_ARB_RAMCFG) & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
4106
4107 if (tmp >= 4)
4108 dram_rows = 16384;
4109 else
4110 dram_rows = 1 << (tmp + 10);
4111
4112 dram_refresh_rate = 1 << ((RREG32(MC_SEQ_MISC0) & 0x3) + 3);
4113 mc_arb_rfsh_rate = ((engine_clock * 10) * dram_refresh_rate / dram_rows - 32) / 64;
4114
4115 return mc_arb_rfsh_rate;
4116 }
4117
4118 static int si_populate_memory_timing_parameters(struct radeon_device *rdev,
4119 struct rv7xx_pl *pl,
4120 SMC_SIslands_MCArbDramTimingRegisterSet *arb_regs)
4121 {
4122 u32 dram_timing;
4123 u32 dram_timing2;
4124 u32 burst_time;
4125
4126 arb_regs->mc_arb_rfsh_rate =
4127 (u8)si_calculate_memory_refresh_rate(rdev, pl->sclk);
4128
4129 radeon_atom_set_engine_dram_timings(rdev,
4130 pl->sclk,
4131 pl->mclk);
4132
4133 dram_timing = RREG32(MC_ARB_DRAM_TIMING);
4134 dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
4135 burst_time = RREG32(MC_ARB_BURST_TIME) & STATE0_MASK;
4136
4137 arb_regs->mc_arb_dram_timing = cpu_to_be32(dram_timing);
4138 arb_regs->mc_arb_dram_timing2 = cpu_to_be32(dram_timing2);
4139 arb_regs->mc_arb_burst_time = (u8)burst_time;
4140
4141 return 0;
4142 }
4143
4144 static int si_do_program_memory_timing_parameters(struct radeon_device *rdev,
4145 struct radeon_ps *radeon_state,
4146 unsigned int first_arb_set)
4147 {
4148 struct si_power_info *si_pi = si_get_pi(rdev);
4149 struct ni_ps *state = ni_get_ps(radeon_state);
4150 SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 };
4151 int i, ret = 0;
4152
4153 for (i = 0; i < state->performance_level_count; i++) {
4154 ret = si_populate_memory_timing_parameters(rdev, &state->performance_levels[i], &arb_regs);
4155 if (ret)
4156 break;
4157 ret = si_copy_bytes_to_smc(rdev,
4158 si_pi->arb_table_start +
4159 offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) +
4160 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * (first_arb_set + i),
4161 (u8 *)&arb_regs,
4162 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet),
4163 si_pi->sram_end);
4164 if (ret)
4165 break;
4166 }
4167
4168 return ret;
4169 }
4170
4171 static int si_program_memory_timing_parameters(struct radeon_device *rdev,
4172 struct radeon_ps *radeon_new_state)
4173 {
4174 return si_do_program_memory_timing_parameters(rdev, radeon_new_state,
4175 SISLANDS_DRIVER_STATE_ARB_INDEX);
4176 }
4177
4178 static int si_populate_initial_mvdd_value(struct radeon_device *rdev,
4179 struct SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4180 {
4181 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4182 struct si_power_info *si_pi = si_get_pi(rdev);
4183
4184 if (pi->mvdd_control)
4185 return si_populate_voltage_value(rdev, &si_pi->mvdd_voltage_table,
4186 si_pi->mvdd_bootup_value, voltage);
4187
4188 return 0;
4189 }
4190
4191 static int si_populate_smc_initial_state(struct radeon_device *rdev,
4192 struct radeon_ps *radeon_initial_state,
4193 SISLANDS_SMC_STATETABLE *table)
4194 {
4195 struct ni_ps *initial_state = ni_get_ps(radeon_initial_state);
4196 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4197 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4198 struct si_power_info *si_pi = si_get_pi(rdev);
4199 u32 reg;
4200 int ret;
4201
4202 table->initialState.levels[0].mclk.vDLL_CNTL =
4203 cpu_to_be32(si_pi->clock_registers.dll_cntl);
4204 table->initialState.levels[0].mclk.vMCLK_PWRMGT_CNTL =
4205 cpu_to_be32(si_pi->clock_registers.mclk_pwrmgt_cntl);
4206 table->initialState.levels[0].mclk.vMPLL_AD_FUNC_CNTL =
4207 cpu_to_be32(si_pi->clock_registers.mpll_ad_func_cntl);
4208 table->initialState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL =
4209 cpu_to_be32(si_pi->clock_registers.mpll_dq_func_cntl);
4210 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL =
4211 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl);
4212 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_1 =
4213 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_1);
4214 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_2 =
4215 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_2);
4216 table->initialState.levels[0].mclk.vMPLL_SS =
4217 cpu_to_be32(si_pi->clock_registers.mpll_ss1);
4218 table->initialState.levels[0].mclk.vMPLL_SS2 =
4219 cpu_to_be32(si_pi->clock_registers.mpll_ss2);
4220
4221 table->initialState.levels[0].mclk.mclk_value =
4222 cpu_to_be32(initial_state->performance_levels[0].mclk);
4223
4224 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
4225 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl);
4226 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
4227 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_2);
4228 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
4229 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_3);
4230 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 =
4231 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_4);
4232 table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM =
4233 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum);
4234 table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM_2 =
4235 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum_2);
4236
4237 table->initialState.levels[0].sclk.sclk_value =
4238 cpu_to_be32(initial_state->performance_levels[0].sclk);
4239
4240 table->initialState.levels[0].arbRefreshState =
4241 SISLANDS_INITIAL_STATE_ARB_INDEX;
4242
4243 table->initialState.levels[0].ACIndex = 0;
4244
4245 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
4246 initial_state->performance_levels[0].vddc,
4247 &table->initialState.levels[0].vddc);
4248
4249 if (!ret) {
4250 u16 std_vddc;
4251
4252 ret = si_get_std_voltage_value(rdev,
4253 &table->initialState.levels[0].vddc,
4254 &std_vddc);
4255 if (!ret)
4256 si_populate_std_voltage_value(rdev, std_vddc,
4257 table->initialState.levels[0].vddc.index,
4258 &table->initialState.levels[0].std_vddc);
4259 }
4260
4261 if (eg_pi->vddci_control)
4262 si_populate_voltage_value(rdev,
4263 &eg_pi->vddci_voltage_table,
4264 initial_state->performance_levels[0].vddci,
4265 &table->initialState.levels[0].vddci);
4266
4267 if (si_pi->vddc_phase_shed_control)
4268 si_populate_phase_shedding_value(rdev,
4269 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
4270 initial_state->performance_levels[0].vddc,
4271 initial_state->performance_levels[0].sclk,
4272 initial_state->performance_levels[0].mclk,
4273 &table->initialState.levels[0].vddc);
4274
4275 si_populate_initial_mvdd_value(rdev, &table->initialState.levels[0].mvdd);
4276
4277 reg = CG_R(0xffff) | CG_L(0);
4278 table->initialState.levels[0].aT = cpu_to_be32(reg);
4279
4280 table->initialState.levels[0].bSP = cpu_to_be32(pi->dsp);
4281
4282 table->initialState.levels[0].gen2PCIE = (u8)si_pi->boot_pcie_gen;
4283
4284 if (pi->mem_gddr5) {
4285 table->initialState.levels[0].strobeMode =
4286 si_get_strobe_mode_settings(rdev,
4287 initial_state->performance_levels[0].mclk);
4288
4289 if (initial_state->performance_levels[0].mclk > pi->mclk_edc_enable_threshold)
4290 table->initialState.levels[0].mcFlags = SISLANDS_SMC_MC_EDC_RD_FLAG | SISLANDS_SMC_MC_EDC_WR_FLAG;
4291 else
4292 table->initialState.levels[0].mcFlags = 0;
4293 }
4294
4295 table->initialState.levelCount = 1;
4296
4297 table->initialState.flags |= PPSMC_SWSTATE_FLAG_DC;
4298
4299 table->initialState.levels[0].dpm2.MaxPS = 0;
4300 table->initialState.levels[0].dpm2.NearTDPDec = 0;
4301 table->initialState.levels[0].dpm2.AboveSafeInc = 0;
4302 table->initialState.levels[0].dpm2.BelowSafeInc = 0;
4303 table->initialState.levels[0].dpm2.PwrEfficiencyRatio = 0;
4304
4305 reg = MIN_POWER_MASK | MAX_POWER_MASK;
4306 table->initialState.levels[0].SQPowerThrottle = cpu_to_be32(reg);
4307
4308 reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
4309 table->initialState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg);
4310
4311 return 0;
4312 }
4313
4314 static int si_populate_smc_acpi_state(struct radeon_device *rdev,
4315 SISLANDS_SMC_STATETABLE *table)
4316 {
4317 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4318 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4319 struct si_power_info *si_pi = si_get_pi(rdev);
4320 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl;
4321 u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2;
4322 u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3;
4323 u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4;
4324 u32 dll_cntl = si_pi->clock_registers.dll_cntl;
4325 u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl;
4326 u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl;
4327 u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl;
4328 u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl;
4329 u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1;
4330 u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2;
4331 u32 reg;
4332 int ret;
4333
4334 table->ACPIState = table->initialState;
4335
4336 table->ACPIState.flags &= ~PPSMC_SWSTATE_FLAG_DC;
4337
4338 if (pi->acpi_vddc) {
4339 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
4340 pi->acpi_vddc, &table->ACPIState.levels[0].vddc);
4341 if (!ret) {
4342 u16 std_vddc;
4343
4344 ret = si_get_std_voltage_value(rdev,
4345 &table->ACPIState.levels[0].vddc, &std_vddc);
4346 if (!ret)
4347 si_populate_std_voltage_value(rdev, std_vddc,
4348 table->ACPIState.levels[0].vddc.index,
4349 &table->ACPIState.levels[0].std_vddc);
4350 }
4351 table->ACPIState.levels[0].gen2PCIE = si_pi->acpi_pcie_gen;
4352
4353 if (si_pi->vddc_phase_shed_control) {
4354 si_populate_phase_shedding_value(rdev,
4355 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
4356 pi->acpi_vddc,
4357 0,
4358 0,
4359 &table->ACPIState.levels[0].vddc);
4360 }
4361 } else {
4362 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
4363 pi->min_vddc_in_table, &table->ACPIState.levels[0].vddc);
4364 if (!ret) {
4365 u16 std_vddc;
4366
4367 ret = si_get_std_voltage_value(rdev,
4368 &table->ACPIState.levels[0].vddc, &std_vddc);
4369
4370 if (!ret)
4371 si_populate_std_voltage_value(rdev, std_vddc,
4372 table->ACPIState.levels[0].vddc.index,
4373 &table->ACPIState.levels[0].std_vddc);
4374 }
4375 table->ACPIState.levels[0].gen2PCIE = (u8)r600_get_pcie_gen_support(rdev,
4376 si_pi->sys_pcie_mask,
4377 si_pi->boot_pcie_gen,
4378 RADEON_PCIE_GEN1);
4379
4380 if (si_pi->vddc_phase_shed_control)
4381 si_populate_phase_shedding_value(rdev,
4382 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
4383 pi->min_vddc_in_table,
4384 0,
4385 0,
4386 &table->ACPIState.levels[0].vddc);
4387 }
4388
4389 if (pi->acpi_vddc) {
4390 if (eg_pi->acpi_vddci)
4391 si_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table,
4392 eg_pi->acpi_vddci,
4393 &table->ACPIState.levels[0].vddci);
4394 }
4395
4396 mclk_pwrmgt_cntl |= MRDCK0_RESET | MRDCK1_RESET;
4397 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
4398
4399 dll_cntl &= ~(MRDCK0_BYPASS | MRDCK1_BYPASS);
4400
4401 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
4402 spll_func_cntl_2 |= SCLK_MUX_SEL(4);
4403
4404 table->ACPIState.levels[0].mclk.vDLL_CNTL =
4405 cpu_to_be32(dll_cntl);
4406 table->ACPIState.levels[0].mclk.vMCLK_PWRMGT_CNTL =
4407 cpu_to_be32(mclk_pwrmgt_cntl);
4408 table->ACPIState.levels[0].mclk.vMPLL_AD_FUNC_CNTL =
4409 cpu_to_be32(mpll_ad_func_cntl);
4410 table->ACPIState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL =
4411 cpu_to_be32(mpll_dq_func_cntl);
4412 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL =
4413 cpu_to_be32(mpll_func_cntl);
4414 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_1 =
4415 cpu_to_be32(mpll_func_cntl_1);
4416 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_2 =
4417 cpu_to_be32(mpll_func_cntl_2);
4418 table->ACPIState.levels[0].mclk.vMPLL_SS =
4419 cpu_to_be32(si_pi->clock_registers.mpll_ss1);
4420 table->ACPIState.levels[0].mclk.vMPLL_SS2 =
4421 cpu_to_be32(si_pi->clock_registers.mpll_ss2);
4422
4423 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
4424 cpu_to_be32(spll_func_cntl);
4425 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
4426 cpu_to_be32(spll_func_cntl_2);
4427 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
4428 cpu_to_be32(spll_func_cntl_3);
4429 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 =
4430 cpu_to_be32(spll_func_cntl_4);
4431
4432 table->ACPIState.levels[0].mclk.mclk_value = 0;
4433 table->ACPIState.levels[0].sclk.sclk_value = 0;
4434
4435 si_populate_mvdd_value(rdev, 0, &table->ACPIState.levels[0].mvdd);
4436
4437 if (eg_pi->dynamic_ac_timing)
4438 table->ACPIState.levels[0].ACIndex = 0;
4439
4440 table->ACPIState.levels[0].dpm2.MaxPS = 0;
4441 table->ACPIState.levels[0].dpm2.NearTDPDec = 0;
4442 table->ACPIState.levels[0].dpm2.AboveSafeInc = 0;
4443 table->ACPIState.levels[0].dpm2.BelowSafeInc = 0;
4444 table->ACPIState.levels[0].dpm2.PwrEfficiencyRatio = 0;
4445
4446 reg = MIN_POWER_MASK | MAX_POWER_MASK;
4447 table->ACPIState.levels[0].SQPowerThrottle = cpu_to_be32(reg);
4448
4449 reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
4450 table->ACPIState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg);
4451
4452 return 0;
4453 }
4454
4455 static int si_populate_ulv_state(struct radeon_device *rdev,
4456 SISLANDS_SMC_SWSTATE *state)
4457 {
4458 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4459 struct si_power_info *si_pi = si_get_pi(rdev);
4460 struct si_ulv_param *ulv = &si_pi->ulv;
4461 u32 sclk_in_sr = 1350; /* ??? */
4462 int ret;
4463
4464 ret = si_convert_power_level_to_smc(rdev, &ulv->pl,
4465 &state->levels[0]);
4466 if (!ret) {
4467 if (eg_pi->sclk_deep_sleep) {
4468 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ)
4469 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS;
4470 else
4471 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE;
4472 }
4473 if (ulv->one_pcie_lane_in_ulv)
4474 state->flags |= PPSMC_SWSTATE_FLAG_PCIE_X1;
4475 state->levels[0].arbRefreshState = (u8)(SISLANDS_ULV_STATE_ARB_INDEX);
4476 state->levels[0].ACIndex = 1;
4477 state->levels[0].std_vddc = state->levels[0].vddc;
4478 state->levelCount = 1;
4479
4480 state->flags |= PPSMC_SWSTATE_FLAG_DC;
4481 }
4482
4483 return ret;
4484 }
4485
4486 static int si_program_ulv_memory_timing_parameters(struct radeon_device *rdev)
4487 {
4488 struct si_power_info *si_pi = si_get_pi(rdev);
4489 struct si_ulv_param *ulv = &si_pi->ulv;
4490 SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 };
4491 int ret;
4492
4493 ret = si_populate_memory_timing_parameters(rdev, &ulv->pl,
4494 &arb_regs);
4495 if (ret)
4496 return ret;
4497
4498 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_ulv_volt_change_delay,
4499 ulv->volt_change_delay);
4500
4501 ret = si_copy_bytes_to_smc(rdev,
4502 si_pi->arb_table_start +
4503 offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) +
4504 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * SISLANDS_ULV_STATE_ARB_INDEX,
4505 (u8 *)&arb_regs,
4506 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet),
4507 si_pi->sram_end);
4508
4509 return ret;
4510 }
4511
4512 static void si_get_mvdd_configuration(struct radeon_device *rdev)
4513 {
4514 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4515
4516 pi->mvdd_split_frequency = 30000;
4517 }
4518
4519 static int si_init_smc_table(struct radeon_device *rdev)
4520 {
4521 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4522 struct si_power_info *si_pi = si_get_pi(rdev);
4523 struct radeon_ps *radeon_boot_state = rdev->pm.dpm.boot_ps;
4524 const struct si_ulv_param *ulv = &si_pi->ulv;
4525 SISLANDS_SMC_STATETABLE *table = &si_pi->smc_statetable;
4526 int ret;
4527 u32 lane_width;
4528 u32 vr_hot_gpio;
4529
4530 si_populate_smc_voltage_tables(rdev, table);
4531
4532 switch (rdev->pm.int_thermal_type) {
4533 case THERMAL_TYPE_SI:
4534 case THERMAL_TYPE_EMC2103_WITH_INTERNAL:
4535 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_INTERNAL;
4536 break;
4537 case THERMAL_TYPE_NONE:
4538 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_NONE;
4539 break;
4540 default:
4541 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL;
4542 break;
4543 }
4544
4545 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC)
4546 table->systemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
4547
4548 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT) {
4549 if ((rdev->pdev->device != 0x6818) && (rdev->pdev->device != 0x6819))
4550 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT;
4551 }
4552
4553 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC)
4554 table->systemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
4555
4556 if (pi->mem_gddr5)
4557 table->systemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
4558
4559 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REVERT_GPIO5_POLARITY)
4560 table->extraFlags |= PPSMC_EXTRAFLAGS_AC2DC_GPIO5_POLARITY_HIGH;
4561
4562 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VRHOT_GPIO_CONFIGURABLE) {
4563 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT_PROG_GPIO;
4564 vr_hot_gpio = rdev->pm.dpm.backbias_response_time;
4565 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_vr_hot_gpio,
4566 vr_hot_gpio);
4567 }
4568
4569 ret = si_populate_smc_initial_state(rdev, radeon_boot_state, table);
4570 if (ret)
4571 return ret;
4572
4573 ret = si_populate_smc_acpi_state(rdev, table);
4574 if (ret)
4575 return ret;
4576
4577 table->driverState = table->initialState;
4578
4579 ret = si_do_program_memory_timing_parameters(rdev, radeon_boot_state,
4580 SISLANDS_INITIAL_STATE_ARB_INDEX);
4581 if (ret)
4582 return ret;
4583
4584 if (ulv->supported && ulv->pl.vddc) {
4585 ret = si_populate_ulv_state(rdev, &table->ULVState);
4586 if (ret)
4587 return ret;
4588
4589 ret = si_program_ulv_memory_timing_parameters(rdev);
4590 if (ret)
4591 return ret;
4592
4593 WREG32(CG_ULV_CONTROL, ulv->cg_ulv_control);
4594 WREG32(CG_ULV_PARAMETER, ulv->cg_ulv_parameter);
4595
4596 lane_width = radeon_get_pcie_lanes(rdev);
4597 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width);
4598 } else {
4599 table->ULVState = table->initialState;
4600 }
4601
4602 return si_copy_bytes_to_smc(rdev, si_pi->state_table_start,
4603 (u8 *)table, sizeof(SISLANDS_SMC_STATETABLE),
4604 si_pi->sram_end);
4605 }
4606
4607 static int si_calculate_sclk_params(struct radeon_device *rdev,
4608 u32 engine_clock,
4609 SISLANDS_SMC_SCLK_VALUE *sclk)
4610 {
4611 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4612 struct si_power_info *si_pi = si_get_pi(rdev);
4613 struct atom_clock_dividers dividers;
4614 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl;
4615 u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2;
4616 u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3;
4617 u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4;
4618 u32 cg_spll_spread_spectrum = si_pi->clock_registers.cg_spll_spread_spectrum;
4619 u32 cg_spll_spread_spectrum_2 = si_pi->clock_registers.cg_spll_spread_spectrum_2;
4620 u64 tmp;
4621 u32 reference_clock = rdev->clock.spll.reference_freq;
4622 u32 reference_divider;
4623 u32 fbdiv;
4624 int ret;
4625
4626 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
4627 engine_clock, false, &dividers);
4628 if (ret)
4629 return ret;
4630
4631 reference_divider = 1 + dividers.ref_div;
4632
4633 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384;
4634 do_div(tmp, reference_clock);
4635 fbdiv = (u32) tmp;
4636
4637 spll_func_cntl &= ~(SPLL_PDIV_A_MASK | SPLL_REF_DIV_MASK);
4638 spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div);
4639 spll_func_cntl |= SPLL_PDIV_A(dividers.post_div);
4640
4641 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
4642 spll_func_cntl_2 |= SCLK_MUX_SEL(2);
4643
4644 spll_func_cntl_3 &= ~SPLL_FB_DIV_MASK;
4645 spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv);
4646 spll_func_cntl_3 |= SPLL_DITHEN;
4647
4648 if (pi->sclk_ss) {
4649 struct radeon_atom_ss ss;
4650 u32 vco_freq = engine_clock * dividers.post_div;
4651
4652 if (radeon_atombios_get_asic_ss_info(rdev, &ss,
4653 ASIC_INTERNAL_ENGINE_SS, vco_freq)) {
4654 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate);
4655 u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000);
4656
4657 cg_spll_spread_spectrum &= ~CLK_S_MASK;
4658 cg_spll_spread_spectrum |= CLK_S(clk_s);
4659 cg_spll_spread_spectrum |= SSEN;
4660
4661 cg_spll_spread_spectrum_2 &= ~CLK_V_MASK;
4662 cg_spll_spread_spectrum_2 |= CLK_V(clk_v);
4663 }
4664 }
4665
4666 sclk->sclk_value = engine_clock;
4667 sclk->vCG_SPLL_FUNC_CNTL = spll_func_cntl;
4668 sclk->vCG_SPLL_FUNC_CNTL_2 = spll_func_cntl_2;
4669 sclk->vCG_SPLL_FUNC_CNTL_3 = spll_func_cntl_3;
4670 sclk->vCG_SPLL_FUNC_CNTL_4 = spll_func_cntl_4;
4671 sclk->vCG_SPLL_SPREAD_SPECTRUM = cg_spll_spread_spectrum;
4672 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cg_spll_spread_spectrum_2;
4673
4674 return 0;
4675 }
4676
4677 static int si_populate_sclk_value(struct radeon_device *rdev,
4678 u32 engine_clock,
4679 SISLANDS_SMC_SCLK_VALUE *sclk)
4680 {
4681 SISLANDS_SMC_SCLK_VALUE sclk_tmp;
4682 int ret;
4683
4684 ret = si_calculate_sclk_params(rdev, engine_clock, &sclk_tmp);
4685 if (!ret) {
4686 sclk->sclk_value = cpu_to_be32(sclk_tmp.sclk_value);
4687 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL);
4688 sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_2);
4689 sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_3);
4690 sclk->vCG_SPLL_FUNC_CNTL_4 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_4);
4691 sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM);
4692 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM_2);
4693 }
4694
4695 return ret;
4696 }
4697
4698 static int si_populate_mclk_value(struct radeon_device *rdev,
4699 u32 engine_clock,
4700 u32 memory_clock,
4701 SISLANDS_SMC_MCLK_VALUE *mclk,
4702 bool strobe_mode,
4703 bool dll_state_on)
4704 {
4705 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4706 struct si_power_info *si_pi = si_get_pi(rdev);
4707 u32 dll_cntl = si_pi->clock_registers.dll_cntl;
4708 u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl;
4709 u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl;
4710 u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl;
4711 u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl;
4712 u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1;
4713 u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2;
4714 u32 mpll_ss1 = si_pi->clock_registers.mpll_ss1;
4715 u32 mpll_ss2 = si_pi->clock_registers.mpll_ss2;
4716 struct atom_mpll_param mpll_param;
4717 int ret;
4718
4719 ret = radeon_atom_get_memory_pll_dividers(rdev, memory_clock, strobe_mode, &mpll_param);
4720 if (ret)
4721 return ret;
4722
4723 mpll_func_cntl &= ~BWCTRL_MASK;
4724 mpll_func_cntl |= BWCTRL(mpll_param.bwcntl);
4725
4726 mpll_func_cntl_1 &= ~(CLKF_MASK | CLKFRAC_MASK | VCO_MODE_MASK);
4727 mpll_func_cntl_1 |= CLKF(mpll_param.clkf) |
4728 CLKFRAC(mpll_param.clkfrac) | VCO_MODE(mpll_param.vco_mode);
4729
4730 mpll_ad_func_cntl &= ~YCLK_POST_DIV_MASK;
4731 mpll_ad_func_cntl |= YCLK_POST_DIV(mpll_param.post_div);
4732
4733 if (pi->mem_gddr5) {
4734 mpll_dq_func_cntl &= ~(YCLK_SEL_MASK | YCLK_POST_DIV_MASK);
4735 mpll_dq_func_cntl |= YCLK_SEL(mpll_param.yclk_sel) |
4736 YCLK_POST_DIV(mpll_param.post_div);
4737 }
4738
4739 if (pi->mclk_ss) {
4740 struct radeon_atom_ss ss;
4741 u32 freq_nom;
4742 u32 tmp;
4743 u32 reference_clock = rdev->clock.mpll.reference_freq;
4744
4745 if (pi->mem_gddr5)
4746 freq_nom = memory_clock * 4;
4747 else
4748 freq_nom = memory_clock * 2;
4749
4750 tmp = freq_nom / reference_clock;
4751 tmp = tmp * tmp;
4752 if (radeon_atombios_get_asic_ss_info(rdev, &ss,
4753 ASIC_INTERNAL_MEMORY_SS, freq_nom)) {
4754 u32 clks = reference_clock * 5 / ss.rate;
4755 u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom);
4756
4757 mpll_ss1 &= ~CLKV_MASK;
4758 mpll_ss1 |= CLKV(clkv);
4759
4760 mpll_ss2 &= ~CLKS_MASK;
4761 mpll_ss2 |= CLKS(clks);
4762 }
4763 }
4764
4765 mclk_pwrmgt_cntl &= ~DLL_SPEED_MASK;
4766 mclk_pwrmgt_cntl |= DLL_SPEED(mpll_param.dll_speed);
4767
4768 if (dll_state_on)
4769 mclk_pwrmgt_cntl |= MRDCK0_PDNB | MRDCK1_PDNB;
4770 else
4771 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
4772
4773 mclk->mclk_value = cpu_to_be32(memory_clock);
4774 mclk->vMPLL_FUNC_CNTL = cpu_to_be32(mpll_func_cntl);
4775 mclk->vMPLL_FUNC_CNTL_1 = cpu_to_be32(mpll_func_cntl_1);
4776 mclk->vMPLL_FUNC_CNTL_2 = cpu_to_be32(mpll_func_cntl_2);
4777 mclk->vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl);
4778 mclk->vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl);
4779 mclk->vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl);
4780 mclk->vDLL_CNTL = cpu_to_be32(dll_cntl);
4781 mclk->vMPLL_SS = cpu_to_be32(mpll_ss1);
4782 mclk->vMPLL_SS2 = cpu_to_be32(mpll_ss2);
4783
4784 return 0;
4785 }
4786
4787 static void si_populate_smc_sp(struct radeon_device *rdev,
4788 struct radeon_ps *radeon_state,
4789 SISLANDS_SMC_SWSTATE *smc_state)
4790 {
4791 struct ni_ps *ps = ni_get_ps(radeon_state);
4792 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4793 int i;
4794
4795 for (i = 0; i < ps->performance_level_count - 1; i++)
4796 smc_state->levels[i].bSP = cpu_to_be32(pi->dsp);
4797
4798 smc_state->levels[ps->performance_level_count - 1].bSP =
4799 cpu_to_be32(pi->psp);
4800 }
4801
4802 static int si_convert_power_level_to_smc(struct radeon_device *rdev,
4803 struct rv7xx_pl *pl,
4804 SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level)
4805 {
4806 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4807 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4808 struct si_power_info *si_pi = si_get_pi(rdev);
4809 int ret;
4810 bool dll_state_on;
4811 u16 std_vddc;
4812 bool gmc_pg = false;
4813
4814 if (eg_pi->pcie_performance_request &&
4815 (si_pi->force_pcie_gen != RADEON_PCIE_GEN_INVALID))
4816 level->gen2PCIE = (u8)si_pi->force_pcie_gen;
4817 else
4818 level->gen2PCIE = (u8)pl->pcie_gen;
4819
4820 ret = si_populate_sclk_value(rdev, pl->sclk, &level->sclk);
4821 if (ret)
4822 return ret;
4823
4824 level->mcFlags = 0;
4825
4826 if (pi->mclk_stutter_mode_threshold &&
4827 (pl->mclk <= pi->mclk_stutter_mode_threshold) &&
4828 !eg_pi->uvd_enabled &&
4829 (RREG32(DPG_PIPE_STUTTER_CONTROL) & STUTTER_ENABLE) &&
4830 (rdev->pm.dpm.new_active_crtc_count <= 2)) {
4831 level->mcFlags |= SISLANDS_SMC_MC_STUTTER_EN;
4832
4833 if (gmc_pg)
4834 level->mcFlags |= SISLANDS_SMC_MC_PG_EN;
4835 }
4836
4837 if (pi->mem_gddr5) {
4838 if (pl->mclk > pi->mclk_edc_enable_threshold)
4839 level->mcFlags |= SISLANDS_SMC_MC_EDC_RD_FLAG;
4840
4841 if (pl->mclk > eg_pi->mclk_edc_wr_enable_threshold)
4842 level->mcFlags |= SISLANDS_SMC_MC_EDC_WR_FLAG;
4843
4844 level->strobeMode = si_get_strobe_mode_settings(rdev, pl->mclk);
4845
4846 if (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) {
4847 if (si_get_mclk_frequency_ratio(pl->mclk, true) >=
4848 ((RREG32(MC_SEQ_MISC7) >> 16) & 0xf))
4849 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
4850 else
4851 dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false;
4852 } else {
4853 dll_state_on = false;
4854 }
4855 } else {
4856 level->strobeMode = si_get_strobe_mode_settings(rdev,
4857 pl->mclk);
4858
4859 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
4860 }
4861
4862 ret = si_populate_mclk_value(rdev,
4863 pl->sclk,
4864 pl->mclk,
4865 &level->mclk,
4866 (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) != 0, dll_state_on);
4867 if (ret)
4868 return ret;
4869
4870 ret = si_populate_voltage_value(rdev,
4871 &eg_pi->vddc_voltage_table,
4872 pl->vddc, &level->vddc);
4873 if (ret)
4874 return ret;
4875
4876
4877 ret = si_get_std_voltage_value(rdev, &level->vddc, &std_vddc);
4878 if (ret)
4879 return ret;
4880
4881 ret = si_populate_std_voltage_value(rdev, std_vddc,
4882 level->vddc.index, &level->std_vddc);
4883 if (ret)
4884 return ret;
4885
4886 if (eg_pi->vddci_control) {
4887 ret = si_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table,
4888 pl->vddci, &level->vddci);
4889 if (ret)
4890 return ret;
4891 }
4892
4893 if (si_pi->vddc_phase_shed_control) {
4894 ret = si_populate_phase_shedding_value(rdev,
4895 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
4896 pl->vddc,
4897 pl->sclk,
4898 pl->mclk,
4899 &level->vddc);
4900 if (ret)
4901 return ret;
4902 }
4903
4904 level->MaxPoweredUpCU = si_pi->max_cu;
4905
4906 ret = si_populate_mvdd_value(rdev, pl->mclk, &level->mvdd);
4907
4908 return ret;
4909 }
4910
4911 static int si_populate_smc_t(struct radeon_device *rdev,
4912 struct radeon_ps *radeon_state,
4913 SISLANDS_SMC_SWSTATE *smc_state)
4914 {
4915 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4916 struct ni_ps *state = ni_get_ps(radeon_state);
4917 u32 a_t;
4918 u32 t_l, t_h;
4919 u32 high_bsp;
4920 int i, ret;
4921
4922 if (state->performance_level_count >= 9)
4923 return -EINVAL;
4924
4925 if (state->performance_level_count < 2) {
4926 a_t = CG_R(0xffff) | CG_L(0);
4927 smc_state->levels[0].aT = cpu_to_be32(a_t);
4928 return 0;
4929 }
4930
4931 smc_state->levels[0].aT = cpu_to_be32(0);
4932
4933 for (i = 0; i <= state->performance_level_count - 2; i++) {
4934 ret = r600_calculate_at(
4935 (50 / SISLANDS_MAX_HARDWARE_POWERLEVELS) * 100 * (i + 1),
4936 100 * R600_AH_DFLT,
4937 state->performance_levels[i + 1].sclk,
4938 state->performance_levels[i].sclk,
4939 &t_l,
4940 &t_h);
4941
4942 if (ret) {
4943 t_h = (i + 1) * 1000 - 50 * R600_AH_DFLT;
4944 t_l = (i + 1) * 1000 + 50 * R600_AH_DFLT;
4945 }
4946
4947 a_t = be32_to_cpu(smc_state->levels[i].aT) & ~CG_R_MASK;
4948 a_t |= CG_R(t_l * pi->bsp / 20000);
4949 smc_state->levels[i].aT = cpu_to_be32(a_t);
4950
4951 high_bsp = (i == state->performance_level_count - 2) ?
4952 pi->pbsp : pi->bsp;
4953 a_t = CG_R(0xffff) | CG_L(t_h * high_bsp / 20000);
4954 smc_state->levels[i + 1].aT = cpu_to_be32(a_t);
4955 }
4956
4957 return 0;
4958 }
4959
4960 static int si_disable_ulv(struct radeon_device *rdev)
4961 {
4962 struct si_power_info *si_pi = si_get_pi(rdev);
4963 struct si_ulv_param *ulv = &si_pi->ulv;
4964
4965 if (ulv->supported)
4966 return (si_send_msg_to_smc(rdev, PPSMC_MSG_DisableULV) == PPSMC_Result_OK) ?
4967 0 : -EINVAL;
4968
4969 return 0;
4970 }
4971
4972 static bool si_is_state_ulv_compatible(struct radeon_device *rdev,
4973 struct radeon_ps *radeon_state)
4974 {
4975 const struct si_power_info *si_pi = si_get_pi(rdev);
4976 const struct si_ulv_param *ulv = &si_pi->ulv;
4977 const struct ni_ps *state = ni_get_ps(radeon_state);
4978 int i;
4979
4980 if (state->performance_levels[0].mclk != ulv->pl.mclk)
4981 return false;
4982
4983 /* XXX validate against display requirements! */
4984
4985 for (i = 0; i < rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count; i++) {
4986 if (rdev->clock.current_dispclk <=
4987 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].clk) {
4988 if (ulv->pl.vddc <
4989 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].v)
4990 return false;
4991 }
4992 }
4993
4994 if ((radeon_state->vclk != 0) || (radeon_state->dclk != 0))
4995 return false;
4996
4997 return true;
4998 }
4999
5000 static int si_set_power_state_conditionally_enable_ulv(struct radeon_device *rdev,
5001 struct radeon_ps *radeon_new_state)
5002 {
5003 const struct si_power_info *si_pi = si_get_pi(rdev);
5004 const struct si_ulv_param *ulv = &si_pi->ulv;
5005
5006 if (ulv->supported) {
5007 if (si_is_state_ulv_compatible(rdev, radeon_new_state))
5008 return (si_send_msg_to_smc(rdev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ?
5009 0 : -EINVAL;
5010 }
5011 return 0;
5012 }
5013
5014 static int si_convert_power_state_to_smc(struct radeon_device *rdev,
5015 struct radeon_ps *radeon_state,
5016 SISLANDS_SMC_SWSTATE *smc_state)
5017 {
5018 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
5019 struct ni_power_info *ni_pi = ni_get_pi(rdev);
5020 struct si_power_info *si_pi = si_get_pi(rdev);
5021 struct ni_ps *state = ni_get_ps(radeon_state);
5022 int i, ret;
5023 u32 threshold;
5024 u32 sclk_in_sr = 1350; /* ??? */
5025
5026 if (state->performance_level_count > SISLANDS_MAX_HARDWARE_POWERLEVELS)
5027 return -EINVAL;
5028
5029 threshold = state->performance_levels[state->performance_level_count-1].sclk * 100 / 100;
5030
5031 if (radeon_state->vclk && radeon_state->dclk) {
5032 eg_pi->uvd_enabled = true;
5033 if (eg_pi->smu_uvd_hs)
5034 smc_state->flags |= PPSMC_SWSTATE_FLAG_UVD;
5035 } else {
5036 eg_pi->uvd_enabled = false;
5037 }
5038
5039 if (state->dc_compatible)
5040 smc_state->flags |= PPSMC_SWSTATE_FLAG_DC;
5041
5042 smc_state->levelCount = 0;
5043 for (i = 0; i < state->performance_level_count; i++) {
5044 if (eg_pi->sclk_deep_sleep) {
5045 if ((i == 0) || si_pi->sclk_deep_sleep_above_low) {
5046 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ)
5047 smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS;
5048 else
5049 smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE;
5050 }
5051 }
5052
5053 ret = si_convert_power_level_to_smc(rdev, &state->performance_levels[i],
5054 &smc_state->levels[i]);
5055 smc_state->levels[i].arbRefreshState =
5056 (u8)(SISLANDS_DRIVER_STATE_ARB_INDEX + i);
5057
5058 if (ret)
5059 return ret;
5060
5061 if (ni_pi->enable_power_containment)
5062 smc_state->levels[i].displayWatermark =
5063 (state->performance_levels[i].sclk < threshold) ?
5064 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH;
5065 else
5066 smc_state->levels[i].displayWatermark = (i < 2) ?
5067 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH;
5068
5069 if (eg_pi->dynamic_ac_timing)
5070 smc_state->levels[i].ACIndex = SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i;
5071 else
5072 smc_state->levels[i].ACIndex = 0;
5073
5074 smc_state->levelCount++;
5075 }
5076
5077 si_write_smc_soft_register(rdev,
5078 SI_SMC_SOFT_REGISTER_watermark_threshold,
5079 threshold / 512);
5080
5081 si_populate_smc_sp(rdev, radeon_state, smc_state);
5082
5083 ret = si_populate_power_containment_values(rdev, radeon_state, smc_state);
5084 if (ret)
5085 ni_pi->enable_power_containment = false;
5086
5087 ret = si_populate_sq_ramping_values(rdev, radeon_state, smc_state);
5088 if (ret)
5089 ni_pi->enable_sq_ramping = false;
5090
5091 return si_populate_smc_t(rdev, radeon_state, smc_state);
5092 }
5093
5094 static int si_upload_sw_state(struct radeon_device *rdev,
5095 struct radeon_ps *radeon_new_state)
5096 {
5097 struct si_power_info *si_pi = si_get_pi(rdev);
5098 struct ni_ps *new_state = ni_get_ps(radeon_new_state);
5099 int ret;
5100 u32 address = si_pi->state_table_start +
5101 offsetof(SISLANDS_SMC_STATETABLE, driverState);
5102 u32 state_size = sizeof(SISLANDS_SMC_SWSTATE) +
5103 ((new_state->performance_level_count - 1) *
5104 sizeof(SISLANDS_SMC_HW_PERFORMANCE_LEVEL));
5105 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.driverState;
5106
5107 memset(smc_state, 0, state_size);
5108
5109 ret = si_convert_power_state_to_smc(rdev, radeon_new_state, smc_state);
5110 if (ret)
5111 return ret;
5112
5113 ret = si_copy_bytes_to_smc(rdev, address, (u8 *)smc_state,
5114 state_size, si_pi->sram_end);
5115
5116 return ret;
5117 }
5118
5119 static int si_upload_ulv_state(struct radeon_device *rdev)
5120 {
5121 struct si_power_info *si_pi = si_get_pi(rdev);
5122 struct si_ulv_param *ulv = &si_pi->ulv;
5123 int ret = 0;
5124
5125 if (ulv->supported && ulv->pl.vddc) {
5126 u32 address = si_pi->state_table_start +
5127 offsetof(SISLANDS_SMC_STATETABLE, ULVState);
5128 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.ULVState;
5129 u32 state_size = sizeof(SISLANDS_SMC_SWSTATE);
5130
5131 memset(smc_state, 0, state_size);
5132
5133 ret = si_populate_ulv_state(rdev, smc_state);
5134 if (!ret)
5135 ret = si_copy_bytes_to_smc(rdev, address, (u8 *)smc_state,
5136 state_size, si_pi->sram_end);
5137 }
5138
5139 return ret;
5140 }
5141
5142 static int si_upload_smc_data(struct radeon_device *rdev)
5143 {
5144 struct radeon_crtc *radeon_crtc = NULL;
5145 int i;
5146
5147 if (rdev->pm.dpm.new_active_crtc_count == 0)
5148 return 0;
5149
5150 for (i = 0; i < rdev->num_crtc; i++) {
5151 if (rdev->pm.dpm.new_active_crtcs & (1 << i)) {
5152 radeon_crtc = rdev->mode_info.crtcs[i];
5153 break;
5154 }
5155 }
5156
5157 if (radeon_crtc == NULL)
5158 return 0;
5159
5160 if (radeon_crtc->line_time <= 0)
5161 return 0;
5162
5163 if (si_write_smc_soft_register(rdev,
5164 SI_SMC_SOFT_REGISTER_crtc_index,
5165 radeon_crtc->crtc_id) != PPSMC_Result_OK)
5166 return 0;
5167
5168 if (si_write_smc_soft_register(rdev,
5169 SI_SMC_SOFT_REGISTER_mclk_change_block_cp_min,
5170 radeon_crtc->wm_high / radeon_crtc->line_time) != PPSMC_Result_OK)
5171 return 0;
5172
5173 if (si_write_smc_soft_register(rdev,
5174 SI_SMC_SOFT_REGISTER_mclk_change_block_cp_max,
5175 radeon_crtc->wm_low / radeon_crtc->line_time) != PPSMC_Result_OK)
5176 return 0;
5177
5178 return 0;
5179 }
5180
5181 static int si_set_mc_special_registers(struct radeon_device *rdev,
5182 struct si_mc_reg_table *table)
5183 {
5184 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
5185 u8 i, j, k;
5186 u32 temp_reg;
5187
5188 for (i = 0, j = table->last; i < table->last; i++) {
5189 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5190 return -EINVAL;
5191 switch (table->mc_reg_address[i].s1 << 2) {
5192 case MC_SEQ_MISC1:
5193 temp_reg = RREG32(MC_PMG_CMD_EMRS);
5194 table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS >> 2;
5195 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2;
5196 for (k = 0; k < table->num_entries; k++)
5197 table->mc_reg_table_entry[k].mc_data[j] =
5198 ((temp_reg & 0xffff0000)) |
5199 ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
5200 j++;
5201 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5202 return -EINVAL;
5203
5204 temp_reg = RREG32(MC_PMG_CMD_MRS);
5205 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS >> 2;
5206 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2;
5207 for (k = 0; k < table->num_entries; k++) {
5208 table->mc_reg_table_entry[k].mc_data[j] =
5209 (temp_reg & 0xffff0000) |
5210 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
5211 if (!pi->mem_gddr5)
5212 table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
5213 }
5214 j++;
5215 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5216 return -EINVAL;
5217
5218 if (!pi->mem_gddr5) {
5219 table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD >> 2;
5220 table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD >> 2;
5221 for (k = 0; k < table->num_entries; k++)
5222 table->mc_reg_table_entry[k].mc_data[j] =
5223 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;
5224 j++;
5225 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5226 return -EINVAL;
5227 }
5228 break;
5229 case MC_SEQ_RESERVE_M:
5230 temp_reg = RREG32(MC_PMG_CMD_MRS1);
5231 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1 >> 2;
5232 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2;
5233 for(k = 0; k < table->num_entries; k++)
5234 table->mc_reg_table_entry[k].mc_data[j] =
5235 (temp_reg & 0xffff0000) |
5236 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
5237 j++;
5238 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5239 return -EINVAL;
5240 break;
5241 default:
5242 break;
5243 }
5244 }
5245
5246 table->last = j;
5247
5248 return 0;
5249 }
5250
5251 static bool si_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg)
5252 {
5253 bool result = true;
5254
5255 switch (in_reg) {
5256 case MC_SEQ_RAS_TIMING >> 2:
5257 *out_reg = MC_SEQ_RAS_TIMING_LP >> 2;
5258 break;
5259 case MC_SEQ_CAS_TIMING >> 2:
5260 *out_reg = MC_SEQ_CAS_TIMING_LP >> 2;
5261 break;
5262 case MC_SEQ_MISC_TIMING >> 2:
5263 *out_reg = MC_SEQ_MISC_TIMING_LP >> 2;
5264 break;
5265 case MC_SEQ_MISC_TIMING2 >> 2:
5266 *out_reg = MC_SEQ_MISC_TIMING2_LP >> 2;
5267 break;
5268 case MC_SEQ_RD_CTL_D0 >> 2:
5269 *out_reg = MC_SEQ_RD_CTL_D0_LP >> 2;
5270 break;
5271 case MC_SEQ_RD_CTL_D1 >> 2:
5272 *out_reg = MC_SEQ_RD_CTL_D1_LP >> 2;
5273 break;
5274 case MC_SEQ_WR_CTL_D0 >> 2:
5275 *out_reg = MC_SEQ_WR_CTL_D0_LP >> 2;
5276 break;
5277 case MC_SEQ_WR_CTL_D1 >> 2:
5278 *out_reg = MC_SEQ_WR_CTL_D1_LP >> 2;
5279 break;
5280 case MC_PMG_CMD_EMRS >> 2:
5281 *out_reg = MC_SEQ_PMG_CMD_EMRS_LP >> 2;
5282 break;
5283 case MC_PMG_CMD_MRS >> 2:
5284 *out_reg = MC_SEQ_PMG_CMD_MRS_LP >> 2;
5285 break;
5286 case MC_PMG_CMD_MRS1 >> 2:
5287 *out_reg = MC_SEQ_PMG_CMD_MRS1_LP >> 2;
5288 break;
5289 case MC_SEQ_PMG_TIMING >> 2:
5290 *out_reg = MC_SEQ_PMG_TIMING_LP >> 2;
5291 break;
5292 case MC_PMG_CMD_MRS2 >> 2:
5293 *out_reg = MC_SEQ_PMG_CMD_MRS2_LP >> 2;
5294 break;
5295 case MC_SEQ_WR_CTL_2 >> 2:
5296 *out_reg = MC_SEQ_WR_CTL_2_LP >> 2;
5297 break;
5298 default:
5299 result = false;
5300 break;
5301 }
5302
5303 return result;
5304 }
5305
5306 static void si_set_valid_flag(struct si_mc_reg_table *table)
5307 {
5308 u8 i, j;
5309
5310 for (i = 0; i < table->last; i++) {
5311 for (j = 1; j < table->num_entries; j++) {
5312 if (table->mc_reg_table_entry[j-1].mc_data[i] != table->mc_reg_table_entry[j].mc_data[i]) {
5313 table->valid_flag |= 1 << i;
5314 break;
5315 }
5316 }
5317 }
5318 }
5319
5320 static void si_set_s0_mc_reg_index(struct si_mc_reg_table *table)
5321 {
5322 u32 i;
5323 u16 address;
5324
5325 for (i = 0; i < table->last; i++)
5326 table->mc_reg_address[i].s0 = si_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ?
5327 address : table->mc_reg_address[i].s1;
5328
5329 }
5330
5331 static int si_copy_vbios_mc_reg_table(struct atom_mc_reg_table *table,
5332 struct si_mc_reg_table *si_table)
5333 {
5334 u8 i, j;
5335
5336 if (table->last > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5337 return -EINVAL;
5338 if (table->num_entries > MAX_AC_TIMING_ENTRIES)
5339 return -EINVAL;
5340
5341 for (i = 0; i < table->last; i++)
5342 si_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1;
5343 si_table->last = table->last;
5344
5345 for (i = 0; i < table->num_entries; i++) {
5346 si_table->mc_reg_table_entry[i].mclk_max =
5347 table->mc_reg_table_entry[i].mclk_max;
5348 for (j = 0; j < table->last; j++) {
5349 si_table->mc_reg_table_entry[i].mc_data[j] =
5350 table->mc_reg_table_entry[i].mc_data[j];
5351 }
5352 }
5353 si_table->num_entries = table->num_entries;
5354
5355 return 0;
5356 }
5357
5358 static int si_initialize_mc_reg_table(struct radeon_device *rdev)
5359 {
5360 struct si_power_info *si_pi = si_get_pi(rdev);
5361 struct atom_mc_reg_table *table;
5362 struct si_mc_reg_table *si_table = &si_pi->mc_reg_table;
5363 u8 module_index = rv770_get_memory_module_index(rdev);
5364 int ret;
5365
5366 table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL);
5367 if (!table)
5368 return -ENOMEM;
5369
5370 WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING));
5371 WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING));
5372 WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING));
5373 WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2));
5374 WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS));
5375 WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS));
5376 WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1));
5377 WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0));
5378 WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));
5379 WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0));
5380 WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1));
5381 WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING));
5382 WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2));
5383 WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2));
5384
5385 ret = radeon_atom_init_mc_reg_table(rdev, module_index, table);
5386 if (ret)
5387 goto init_mc_done;
5388
5389 ret = si_copy_vbios_mc_reg_table(table, si_table);
5390 if (ret)
5391 goto init_mc_done;
5392
5393 si_set_s0_mc_reg_index(si_table);
5394
5395 ret = si_set_mc_special_registers(rdev, si_table);
5396 if (ret)
5397 goto init_mc_done;
5398
5399 si_set_valid_flag(si_table);
5400
5401 init_mc_done:
5402 kfree(table);
5403
5404 return ret;
5405
5406 }
5407
5408 static void si_populate_mc_reg_addresses(struct radeon_device *rdev,
5409 SMC_SIslands_MCRegisters *mc_reg_table)
5410 {
5411 struct si_power_info *si_pi = si_get_pi(rdev);
5412 u32 i, j;
5413
5414 for (i = 0, j = 0; j < si_pi->mc_reg_table.last; j++) {
5415 if (si_pi->mc_reg_table.valid_flag & (1 << j)) {
5416 if (i >= SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE)
5417 break;
5418 mc_reg_table->address[i].s0 =
5419 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s0);
5420 mc_reg_table->address[i].s1 =
5421 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s1);
5422 i++;
5423 }
5424 }
5425 mc_reg_table->last = (u8)i;
5426 }
5427
5428 static void si_convert_mc_registers(const struct si_mc_reg_entry *entry,
5429 SMC_SIslands_MCRegisterSet *data,
5430 u32 num_entries, u32 valid_flag)
5431 {
5432 u32 i, j;
5433
5434 for(i = 0, j = 0; j < num_entries; j++) {
5435 if (valid_flag & (1 << j)) {
5436 data->value[i] = cpu_to_be32(entry->mc_data[j]);
5437 i++;
5438 }
5439 }
5440 }
5441
5442 static void si_convert_mc_reg_table_entry_to_smc(struct radeon_device *rdev,
5443 struct rv7xx_pl *pl,
5444 SMC_SIslands_MCRegisterSet *mc_reg_table_data)
5445 {
5446 struct si_power_info *si_pi = si_get_pi(rdev);
5447 u32 i = 0;
5448
5449 for (i = 0; i < si_pi->mc_reg_table.num_entries; i++) {
5450 if (pl->mclk <= si_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max)
5451 break;
5452 }
5453
5454 if ((i == si_pi->mc_reg_table.num_entries) && (i > 0))
5455 --i;
5456
5457 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[i],
5458 mc_reg_table_data, si_pi->mc_reg_table.last,
5459 si_pi->mc_reg_table.valid_flag);
5460 }
5461
5462 static void si_convert_mc_reg_table_to_smc(struct radeon_device *rdev,
5463 struct radeon_ps *radeon_state,
5464 SMC_SIslands_MCRegisters *mc_reg_table)
5465 {
5466 struct ni_ps *state = ni_get_ps(radeon_state);
5467 int i;
5468
5469 for (i = 0; i < state->performance_level_count; i++) {
5470 si_convert_mc_reg_table_entry_to_smc(rdev,
5471 &state->performance_levels[i],
5472 &mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i]);
5473 }
5474 }
5475
5476 static int si_populate_mc_reg_table(struct radeon_device *rdev,
5477 struct radeon_ps *radeon_boot_state)
5478 {
5479 struct ni_ps *boot_state = ni_get_ps(radeon_boot_state);
5480 struct si_power_info *si_pi = si_get_pi(rdev);
5481 struct si_ulv_param *ulv = &si_pi->ulv;
5482 SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table;
5483
5484 memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters));
5485
5486 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_seq_index, 1);
5487
5488 si_populate_mc_reg_addresses(rdev, smc_mc_reg_table);
5489
5490 si_convert_mc_reg_table_entry_to_smc(rdev, &boot_state->performance_levels[0],
5491 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_INITIAL_SLOT]);
5492
5493 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0],
5494 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ACPI_SLOT],
5495 si_pi->mc_reg_table.last,
5496 si_pi->mc_reg_table.valid_flag);
5497
5498 if (ulv->supported && ulv->pl.vddc != 0)
5499 si_convert_mc_reg_table_entry_to_smc(rdev, &ulv->pl,
5500 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT]);
5501 else
5502 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0],
5503 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT],
5504 si_pi->mc_reg_table.last,
5505 si_pi->mc_reg_table.valid_flag);
5506
5507 si_convert_mc_reg_table_to_smc(rdev, radeon_boot_state, smc_mc_reg_table);
5508
5509 return si_copy_bytes_to_smc(rdev, si_pi->mc_reg_table_start,
5510 (u8 *)smc_mc_reg_table,
5511 sizeof(SMC_SIslands_MCRegisters), si_pi->sram_end);
5512 }
5513
5514 static int si_upload_mc_reg_table(struct radeon_device *rdev,
5515 struct radeon_ps *radeon_new_state)
5516 {
5517 struct ni_ps *new_state = ni_get_ps(radeon_new_state);
5518 struct si_power_info *si_pi = si_get_pi(rdev);
5519 u32 address = si_pi->mc_reg_table_start +
5520 offsetof(SMC_SIslands_MCRegisters,
5521 data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT]);
5522 SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table;
5523
5524 memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters));
5525
5526 si_convert_mc_reg_table_to_smc(rdev, radeon_new_state, smc_mc_reg_table);
5527
5528
5529 return si_copy_bytes_to_smc(rdev, address,
5530 (u8 *)&smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT],
5531 sizeof(SMC_SIslands_MCRegisterSet) * new_state->performance_level_count,
5532 si_pi->sram_end);
5533
5534 }
5535
5536 static void si_enable_voltage_control(struct radeon_device *rdev, bool enable)
5537 {
5538 if (enable)
5539 WREG32_P(GENERAL_PWRMGT, VOLT_PWRMGT_EN, ~VOLT_PWRMGT_EN);
5540 else
5541 WREG32_P(GENERAL_PWRMGT, 0, ~VOLT_PWRMGT_EN);
5542 }
5543
5544 static enum radeon_pcie_gen si_get_maximum_link_speed(struct radeon_device *rdev,
5545 struct radeon_ps *radeon_state)
5546 {
5547 struct ni_ps *state = ni_get_ps(radeon_state);
5548 int i;
5549 u16 pcie_speed, max_speed = 0;
5550
5551 for (i = 0; i < state->performance_level_count; i++) {
5552 pcie_speed = state->performance_levels[i].pcie_gen;
5553 if (max_speed < pcie_speed)
5554 max_speed = pcie_speed;
5555 }
5556 return max_speed;
5557 }
5558
5559 static u16 si_get_current_pcie_speed(struct radeon_device *rdev)
5560 {
5561 u32 speed_cntl;
5562
5563 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL) & LC_CURRENT_DATA_RATE_MASK;
5564 speed_cntl >>= LC_CURRENT_DATA_RATE_SHIFT;
5565
5566 return (u16)speed_cntl;
5567 }
5568
5569 static void si_request_link_speed_change_before_state_change(struct radeon_device *rdev,
5570 struct radeon_ps *radeon_new_state,
5571 struct radeon_ps *radeon_current_state)
5572 {
5573 struct si_power_info *si_pi = si_get_pi(rdev);
5574 enum radeon_pcie_gen target_link_speed = si_get_maximum_link_speed(rdev, radeon_new_state);
5575 enum radeon_pcie_gen current_link_speed;
5576
5577 if (si_pi->force_pcie_gen == RADEON_PCIE_GEN_INVALID)
5578 current_link_speed = si_get_maximum_link_speed(rdev, radeon_current_state);
5579 else
5580 current_link_speed = si_pi->force_pcie_gen;
5581
5582 si_pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID;
5583 si_pi->pspp_notify_required = false;
5584 if (target_link_speed > current_link_speed) {
5585 switch (target_link_speed) {
5586 #if defined(CONFIG_ACPI)
5587 case RADEON_PCIE_GEN3:
5588 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN3, false) == 0)
5589 break;
5590 si_pi->force_pcie_gen = RADEON_PCIE_GEN2;
5591 if (current_link_speed == RADEON_PCIE_GEN2)
5592 break;
5593 case RADEON_PCIE_GEN2:
5594 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN2, false) == 0)
5595 break;
5596 #endif
5597 default:
5598 si_pi->force_pcie_gen = si_get_current_pcie_speed(rdev);
5599 break;
5600 }
5601 } else {
5602 if (target_link_speed < current_link_speed)
5603 si_pi->pspp_notify_required = true;
5604 }
5605 }
5606
5607 static void si_notify_link_speed_change_after_state_change(struct radeon_device *rdev,
5608 struct radeon_ps *radeon_new_state,
5609 struct radeon_ps *radeon_current_state)
5610 {
5611 struct si_power_info *si_pi = si_get_pi(rdev);
5612 enum radeon_pcie_gen target_link_speed = si_get_maximum_link_speed(rdev, radeon_new_state);
5613 u8 request;
5614
5615 if (si_pi->pspp_notify_required) {
5616 if (target_link_speed == RADEON_PCIE_GEN3)
5617 request = PCIE_PERF_REQ_PECI_GEN3;
5618 else if (target_link_speed == RADEON_PCIE_GEN2)
5619 request = PCIE_PERF_REQ_PECI_GEN2;
5620 else
5621 request = PCIE_PERF_REQ_PECI_GEN1;
5622
5623 if ((request == PCIE_PERF_REQ_PECI_GEN1) &&
5624 (si_get_current_pcie_speed(rdev) > 0))
5625 return;
5626
5627 #if defined(CONFIG_ACPI)
5628 radeon_acpi_pcie_performance_request(rdev, request, false);
5629 #endif
5630 }
5631 }
5632
5633 #if 0
5634 static int si_ds_request(struct radeon_device *rdev,
5635 bool ds_status_on, u32 count_write)
5636 {
5637 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
5638
5639 if (eg_pi->sclk_deep_sleep) {
5640 if (ds_status_on)
5641 return (si_send_msg_to_smc(rdev, PPSMC_MSG_CancelThrottleOVRDSCLKDS) ==
5642 PPSMC_Result_OK) ?
5643 0 : -EINVAL;
5644 else
5645 return (si_send_msg_to_smc(rdev, PPSMC_MSG_ThrottleOVRDSCLKDS) ==
5646 PPSMC_Result_OK) ? 0 : -EINVAL;
5647 }
5648 return 0;
5649 }
5650 #endif
5651
5652 static void si_set_max_cu_value(struct radeon_device *rdev)
5653 {
5654 struct si_power_info *si_pi = si_get_pi(rdev);
5655
5656 if (rdev->family == CHIP_VERDE) {
5657 switch (rdev->pdev->device) {
5658 case 0x6820:
5659 case 0x6825:
5660 case 0x6821:
5661 case 0x6823:
5662 case 0x6827:
5663 si_pi->max_cu = 10;
5664 break;
5665 case 0x682D:
5666 case 0x6824:
5667 case 0x682F:
5668 case 0x6826:
5669 si_pi->max_cu = 8;
5670 break;
5671 case 0x6828:
5672 case 0x6830:
5673 case 0x6831:
5674 case 0x6838:
5675 case 0x6839:
5676 case 0x683D:
5677 si_pi->max_cu = 10;
5678 break;
5679 case 0x683B:
5680 case 0x683F:
5681 case 0x6829:
5682 si_pi->max_cu = 8;
5683 break;
5684 default:
5685 si_pi->max_cu = 0;
5686 break;
5687 }
5688 } else {
5689 si_pi->max_cu = 0;
5690 }
5691 }
5692
5693 static int si_patch_single_dependency_table_based_on_leakage(struct radeon_device *rdev,
5694 struct radeon_clock_voltage_dependency_table *table)
5695 {
5696 u32 i;
5697 int j;
5698 u16 leakage_voltage;
5699
5700 if (table) {
5701 for (i = 0; i < table->count; i++) {
5702 switch (si_get_leakage_voltage_from_leakage_index(rdev,
5703 table->entries[i].v,
5704 &leakage_voltage)) {
5705 case 0:
5706 table->entries[i].v = leakage_voltage;
5707 break;
5708 case -EAGAIN:
5709 return -EINVAL;
5710 case -EINVAL:
5711 default:
5712 break;
5713 }
5714 }
5715
5716 for (j = (table->count - 2); j >= 0; j--) {
5717 table->entries[j].v = (table->entries[j].v <= table->entries[j + 1].v) ?
5718 table->entries[j].v : table->entries[j + 1].v;
5719 }
5720 }
5721 return 0;
5722 }
5723
5724 static int si_patch_dependency_tables_based_on_leakage(struct radeon_device *rdev)
5725 {
5726 int ret = 0;
5727
5728 ret = si_patch_single_dependency_table_based_on_leakage(rdev,
5729 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk);
5730 ret = si_patch_single_dependency_table_based_on_leakage(rdev,
5731 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk);
5732 ret = si_patch_single_dependency_table_based_on_leakage(rdev,
5733 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk);
5734 return ret;
5735 }
5736
5737 static void si_set_pcie_lane_width_in_smc(struct radeon_device *rdev,
5738 struct radeon_ps *radeon_new_state,
5739 struct radeon_ps *radeon_current_state)
5740 {
5741 u32 lane_width;
5742 u32 new_lane_width =
5743 (radeon_new_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT;
5744 u32 current_lane_width =
5745 (radeon_current_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT;
5746
5747 if (new_lane_width != current_lane_width) {
5748 radeon_set_pcie_lanes(rdev, new_lane_width);
5749 lane_width = radeon_get_pcie_lanes(rdev);
5750 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width);
5751 }
5752 }
5753
5754 void si_dpm_setup_asic(struct radeon_device *rdev)
5755 {
5756 int r;
5757
5758 r = si_mc_load_microcode(rdev);
5759 if (r)
5760 DRM_ERROR("Failed to load MC firmware!\n");
5761 rv770_get_memory_type(rdev);
5762 si_read_clock_registers(rdev);
5763 si_enable_acpi_power_management(rdev);
5764 }
5765
5766 static int si_set_thermal_temperature_range(struct radeon_device *rdev,
5767 int min_temp, int max_temp)
5768 {
5769 int low_temp = 0 * 1000;
5770 int high_temp = 255 * 1000;
5771
5772 if (low_temp < min_temp)
5773 low_temp = min_temp;
5774 if (high_temp > max_temp)
5775 high_temp = max_temp;
5776 if (high_temp < low_temp) {
5777 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp);
5778 return -EINVAL;
5779 }
5780
5781 WREG32_P(CG_THERMAL_INT, DIG_THERM_INTH(high_temp / 1000), ~DIG_THERM_INTH_MASK);
5782 WREG32_P(CG_THERMAL_INT, DIG_THERM_INTL(low_temp / 1000), ~DIG_THERM_INTL_MASK);
5783 WREG32_P(CG_THERMAL_CTRL, DIG_THERM_DPM(high_temp / 1000), ~DIG_THERM_DPM_MASK);
5784
5785 rdev->pm.dpm.thermal.min_temp = low_temp;
5786 rdev->pm.dpm.thermal.max_temp = high_temp;
5787
5788 return 0;
5789 }
5790
5791 int si_dpm_enable(struct radeon_device *rdev)
5792 {
5793 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
5794 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
5795 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
5796 int ret;
5797
5798 if (si_is_smc_running(rdev))
5799 return -EINVAL;
5800 if (pi->voltage_control)
5801 si_enable_voltage_control(rdev, true);
5802 if (pi->mvdd_control)
5803 si_get_mvdd_configuration(rdev);
5804 if (pi->voltage_control) {
5805 ret = si_construct_voltage_tables(rdev);
5806 if (ret) {
5807 DRM_ERROR("si_construct_voltage_tables failed\n");
5808 return ret;
5809 }
5810 }
5811 if (eg_pi->dynamic_ac_timing) {
5812 ret = si_initialize_mc_reg_table(rdev);
5813 if (ret)
5814 eg_pi->dynamic_ac_timing = false;
5815 }
5816 if (pi->dynamic_ss)
5817 si_enable_spread_spectrum(rdev, true);
5818 if (pi->thermal_protection)
5819 si_enable_thermal_protection(rdev, true);
5820 si_setup_bsp(rdev);
5821 si_program_git(rdev);
5822 si_program_tp(rdev);
5823 si_program_tpp(rdev);
5824 si_program_sstp(rdev);
5825 si_enable_display_gap(rdev);
5826 si_program_vc(rdev);
5827 ret = si_upload_firmware(rdev);
5828 if (ret) {
5829 DRM_ERROR("si_upload_firmware failed\n");
5830 return ret;
5831 }
5832 ret = si_process_firmware_header(rdev);
5833 if (ret) {
5834 DRM_ERROR("si_process_firmware_header failed\n");
5835 return ret;
5836 }
5837 ret = si_initial_switch_from_arb_f0_to_f1(rdev);
5838 if (ret) {
5839 DRM_ERROR("si_initial_switch_from_arb_f0_to_f1 failed\n");
5840 return ret;
5841 }
5842 ret = si_init_smc_table(rdev);
5843 if (ret) {
5844 DRM_ERROR("si_init_smc_table failed\n");
5845 return ret;
5846 }
5847 ret = si_init_smc_spll_table(rdev);
5848 if (ret) {
5849 DRM_ERROR("si_init_smc_spll_table failed\n");
5850 return ret;
5851 }
5852 ret = si_init_arb_table_index(rdev);
5853 if (ret) {
5854 DRM_ERROR("si_init_arb_table_index failed\n");
5855 return ret;
5856 }
5857 if (eg_pi->dynamic_ac_timing) {
5858 ret = si_populate_mc_reg_table(rdev, boot_ps);
5859 if (ret) {
5860 DRM_ERROR("si_populate_mc_reg_table failed\n");
5861 return ret;
5862 }
5863 }
5864 ret = si_initialize_smc_cac_tables(rdev);
5865 if (ret) {
5866 DRM_ERROR("si_initialize_smc_cac_tables failed\n");
5867 return ret;
5868 }
5869 ret = si_initialize_hardware_cac_manager(rdev);
5870 if (ret) {
5871 DRM_ERROR("si_initialize_hardware_cac_manager failed\n");
5872 return ret;
5873 }
5874 ret = si_initialize_smc_dte_tables(rdev);
5875 if (ret) {
5876 DRM_ERROR("si_initialize_smc_dte_tables failed\n");
5877 return ret;
5878 }
5879 ret = si_populate_smc_tdp_limits(rdev, boot_ps);
5880 if (ret) {
5881 DRM_ERROR("si_populate_smc_tdp_limits failed\n");
5882 return ret;
5883 }
5884 ret = si_populate_smc_tdp_limits_2(rdev, boot_ps);
5885 if (ret) {
5886 DRM_ERROR("si_populate_smc_tdp_limits_2 failed\n");
5887 return ret;
5888 }
5889 si_program_response_times(rdev);
5890 si_program_ds_registers(rdev);
5891 si_dpm_start_smc(rdev);
5892 ret = si_notify_smc_display_change(rdev, false);
5893 if (ret) {
5894 DRM_ERROR("si_notify_smc_display_change failed\n");
5895 return ret;
5896 }
5897 si_enable_sclk_control(rdev, true);
5898 si_start_dpm(rdev);
5899
5900 si_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true);
5901
5902 ni_update_current_ps(rdev, boot_ps);
5903
5904 return 0;
5905 }
5906
5907 int si_dpm_late_enable(struct radeon_device *rdev)
5908 {
5909 int ret;
5910
5911 if (rdev->irq.installed &&
5912 r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) {
5913 PPSMC_Result result;
5914
5915 ret = si_set_thermal_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
5916 if (ret)
5917 return ret;
5918 rdev->irq.dpm_thermal = true;
5919 radeon_irq_set(rdev);
5920 result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt);
5921
5922 if (result != PPSMC_Result_OK)
5923 DRM_DEBUG_KMS("Could not enable thermal interrupts.\n");
5924 }
5925
5926 return 0;
5927 }
5928
5929 void si_dpm_disable(struct radeon_device *rdev)
5930 {
5931 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
5932 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
5933
5934 if (!si_is_smc_running(rdev))
5935 return;
5936 si_disable_ulv(rdev);
5937 si_clear_vc(rdev);
5938 if (pi->thermal_protection)
5939 si_enable_thermal_protection(rdev, false);
5940 si_enable_power_containment(rdev, boot_ps, false);
5941 si_enable_smc_cac(rdev, boot_ps, false);
5942 si_enable_spread_spectrum(rdev, false);
5943 si_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, false);
5944 si_stop_dpm(rdev);
5945 si_reset_to_default(rdev);
5946 si_dpm_stop_smc(rdev);
5947 si_force_switch_to_arb_f0(rdev);
5948
5949 ni_update_current_ps(rdev, boot_ps);
5950 }
5951
5952 int si_dpm_pre_set_power_state(struct radeon_device *rdev)
5953 {
5954 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
5955 struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps;
5956 struct radeon_ps *new_ps = &requested_ps;
5957
5958 ni_update_requested_ps(rdev, new_ps);
5959
5960 si_apply_state_adjust_rules(rdev, &eg_pi->requested_rps);
5961
5962 return 0;
5963 }
5964
5965 static int si_power_control_set_level(struct radeon_device *rdev)
5966 {
5967 struct radeon_ps *new_ps = rdev->pm.dpm.requested_ps;
5968 int ret;
5969
5970 ret = si_restrict_performance_levels_before_switch(rdev);
5971 if (ret)
5972 return ret;
5973 ret = si_halt_smc(rdev);
5974 if (ret)
5975 return ret;
5976 ret = si_populate_smc_tdp_limits(rdev, new_ps);
5977 if (ret)
5978 return ret;
5979 ret = si_populate_smc_tdp_limits_2(rdev, new_ps);
5980 if (ret)
5981 return ret;
5982 ret = si_resume_smc(rdev);
5983 if (ret)
5984 return ret;
5985 ret = si_set_sw_state(rdev);
5986 if (ret)
5987 return ret;
5988 return 0;
5989 }
5990
5991 int si_dpm_set_power_state(struct radeon_device *rdev)
5992 {
5993 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
5994 struct radeon_ps *new_ps = &eg_pi->requested_rps;
5995 struct radeon_ps *old_ps = &eg_pi->current_rps;
5996 int ret;
5997
5998 ret = si_disable_ulv(rdev);
5999 if (ret) {
6000 DRM_ERROR("si_disable_ulv failed\n");
6001 return ret;
6002 }
6003 ret = si_restrict_performance_levels_before_switch(rdev);
6004 if (ret) {
6005 DRM_ERROR("si_restrict_performance_levels_before_switch failed\n");
6006 return ret;
6007 }
6008 if (eg_pi->pcie_performance_request)
6009 si_request_link_speed_change_before_state_change(rdev, new_ps, old_ps);
6010 ni_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps);
6011 ret = si_enable_power_containment(rdev, new_ps, false);
6012 if (ret) {
6013 DRM_ERROR("si_enable_power_containment failed\n");
6014 return ret;
6015 }
6016 ret = si_enable_smc_cac(rdev, new_ps, false);
6017 if (ret) {
6018 DRM_ERROR("si_enable_smc_cac failed\n");
6019 return ret;
6020 }
6021 ret = si_halt_smc(rdev);
6022 if (ret) {
6023 DRM_ERROR("si_halt_smc failed\n");
6024 return ret;
6025 }
6026 ret = si_upload_sw_state(rdev, new_ps);
6027 if (ret) {
6028 DRM_ERROR("si_upload_sw_state failed\n");
6029 return ret;
6030 }
6031 ret = si_upload_smc_data(rdev);
6032 if (ret) {
6033 DRM_ERROR("si_upload_smc_data failed\n");
6034 return ret;
6035 }
6036 ret = si_upload_ulv_state(rdev);
6037 if (ret) {
6038 DRM_ERROR("si_upload_ulv_state failed\n");
6039 return ret;
6040 }
6041 if (eg_pi->dynamic_ac_timing) {
6042 ret = si_upload_mc_reg_table(rdev, new_ps);
6043 if (ret) {
6044 DRM_ERROR("si_upload_mc_reg_table failed\n");
6045 return ret;
6046 }
6047 }
6048 ret = si_program_memory_timing_parameters(rdev, new_ps);
6049 if (ret) {
6050 DRM_ERROR("si_program_memory_timing_parameters failed\n");
6051 return ret;
6052 }
6053 si_set_pcie_lane_width_in_smc(rdev, new_ps, old_ps);
6054
6055 ret = si_resume_smc(rdev);
6056 if (ret) {
6057 DRM_ERROR("si_resume_smc failed\n");
6058 return ret;
6059 }
6060 ret = si_set_sw_state(rdev);
6061 if (ret) {
6062 DRM_ERROR("si_set_sw_state failed\n");
6063 return ret;
6064 }
6065 ni_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps);
6066 if (eg_pi->pcie_performance_request)
6067 si_notify_link_speed_change_after_state_change(rdev, new_ps, old_ps);
6068 ret = si_set_power_state_conditionally_enable_ulv(rdev, new_ps);
6069 if (ret) {
6070 DRM_ERROR("si_set_power_state_conditionally_enable_ulv failed\n");
6071 return ret;
6072 }
6073 ret = si_enable_smc_cac(rdev, new_ps, true);
6074 if (ret) {
6075 DRM_ERROR("si_enable_smc_cac failed\n");
6076 return ret;
6077 }
6078 ret = si_enable_power_containment(rdev, new_ps, true);
6079 if (ret) {
6080 DRM_ERROR("si_enable_power_containment failed\n");
6081 return ret;
6082 }
6083
6084 ret = si_power_control_set_level(rdev);
6085 if (ret) {
6086 DRM_ERROR("si_power_control_set_level failed\n");
6087 return ret;
6088 }
6089
6090 return 0;
6091 }
6092
6093 void si_dpm_post_set_power_state(struct radeon_device *rdev)
6094 {
6095 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6096 struct radeon_ps *new_ps = &eg_pi->requested_rps;
6097
6098 ni_update_current_ps(rdev, new_ps);
6099 }
6100
6101
6102 void si_dpm_reset_asic(struct radeon_device *rdev)
6103 {
6104 si_restrict_performance_levels_before_switch(rdev);
6105 si_disable_ulv(rdev);
6106 si_set_boot_state(rdev);
6107 }
6108
6109 void si_dpm_display_configuration_changed(struct radeon_device *rdev)
6110 {
6111 si_program_display_gap(rdev);
6112 }
6113
6114 union power_info {
6115 struct _ATOM_POWERPLAY_INFO info;
6116 struct _ATOM_POWERPLAY_INFO_V2 info_2;
6117 struct _ATOM_POWERPLAY_INFO_V3 info_3;
6118 struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
6119 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
6120 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
6121 };
6122
6123 union pplib_clock_info {
6124 struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
6125 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
6126 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
6127 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
6128 struct _ATOM_PPLIB_SI_CLOCK_INFO si;
6129 };
6130
6131 union pplib_power_state {
6132 struct _ATOM_PPLIB_STATE v1;
6133 struct _ATOM_PPLIB_STATE_V2 v2;
6134 };
6135
6136 static void si_parse_pplib_non_clock_info(struct radeon_device *rdev,
6137 struct radeon_ps *rps,
6138 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info,
6139 u8 table_rev)
6140 {
6141 rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);
6142 rps->class = le16_to_cpu(non_clock_info->usClassification);
6143 rps->class2 = le16_to_cpu(non_clock_info->usClassification2);
6144
6145 if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {
6146 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
6147 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
6148 } else if (r600_is_uvd_state(rps->class, rps->class2)) {
6149 rps->vclk = RV770_DEFAULT_VCLK_FREQ;
6150 rps->dclk = RV770_DEFAULT_DCLK_FREQ;
6151 } else {
6152 rps->vclk = 0;
6153 rps->dclk = 0;
6154 }
6155
6156 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT)
6157 rdev->pm.dpm.boot_ps = rps;
6158 if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
6159 rdev->pm.dpm.uvd_ps = rps;
6160 }
6161
6162 static void si_parse_pplib_clock_info(struct radeon_device *rdev,
6163 struct radeon_ps *rps, int index,
6164 union pplib_clock_info *clock_info)
6165 {
6166 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
6167 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6168 struct si_power_info *si_pi = si_get_pi(rdev);
6169 struct ni_ps *ps = ni_get_ps(rps);
6170 u16 leakage_voltage;
6171 struct rv7xx_pl *pl = &ps->performance_levels[index];
6172 int ret;
6173
6174 ps->performance_level_count = index + 1;
6175
6176 pl->sclk = le16_to_cpu(clock_info->si.usEngineClockLow);
6177 pl->sclk |= clock_info->si.ucEngineClockHigh << 16;
6178 pl->mclk = le16_to_cpu(clock_info->si.usMemoryClockLow);
6179 pl->mclk |= clock_info->si.ucMemoryClockHigh << 16;
6180
6181 pl->vddc = le16_to_cpu(clock_info->si.usVDDC);
6182 pl->vddci = le16_to_cpu(clock_info->si.usVDDCI);
6183 pl->flags = le32_to_cpu(clock_info->si.ulFlags);
6184 pl->pcie_gen = r600_get_pcie_gen_support(rdev,
6185 si_pi->sys_pcie_mask,
6186 si_pi->boot_pcie_gen,
6187 clock_info->si.ucPCIEGen);
6188
6189 /* patch up vddc if necessary */
6190 ret = si_get_leakage_voltage_from_leakage_index(rdev, pl->vddc,
6191 &leakage_voltage);
6192 if (ret == 0)
6193 pl->vddc = leakage_voltage;
6194
6195 if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) {
6196 pi->acpi_vddc = pl->vddc;
6197 eg_pi->acpi_vddci = pl->vddci;
6198 si_pi->acpi_pcie_gen = pl->pcie_gen;
6199 }
6200
6201 if ((rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) &&
6202 index == 0) {
6203 /* XXX disable for A0 tahiti */
6204 si_pi->ulv.supported = true;
6205 si_pi->ulv.pl = *pl;
6206 si_pi->ulv.one_pcie_lane_in_ulv = false;
6207 si_pi->ulv.volt_change_delay = SISLANDS_ULVVOLTAGECHANGEDELAY_DFLT;
6208 si_pi->ulv.cg_ulv_parameter = SISLANDS_CGULVPARAMETER_DFLT;
6209 si_pi->ulv.cg_ulv_control = SISLANDS_CGULVCONTROL_DFLT;
6210 }
6211
6212 if (pi->min_vddc_in_table > pl->vddc)
6213 pi->min_vddc_in_table = pl->vddc;
6214
6215 if (pi->max_vddc_in_table < pl->vddc)
6216 pi->max_vddc_in_table = pl->vddc;
6217
6218 /* patch up boot state */
6219 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {
6220 u16 vddc, vddci, mvdd;
6221 radeon_atombios_get_default_voltages(rdev, &vddc, &vddci, &mvdd);
6222 pl->mclk = rdev->clock.default_mclk;
6223 pl->sclk = rdev->clock.default_sclk;
6224 pl->vddc = vddc;
6225 pl->vddci = vddci;
6226 si_pi->mvdd_bootup_value = mvdd;
6227 }
6228
6229 if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) ==
6230 ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
6231 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk;
6232 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk;
6233 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc;
6234 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci;
6235 }
6236 }
6237
6238 static int si_parse_power_table(struct radeon_device *rdev)
6239 {
6240 struct radeon_mode_info *mode_info = &rdev->mode_info;
6241 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
6242 union pplib_power_state *power_state;
6243 int i, j, k, non_clock_array_index, clock_array_index;
6244 union pplib_clock_info *clock_info;
6245 struct _StateArray *state_array;
6246 struct _ClockInfoArray *clock_info_array;
6247 struct _NonClockInfoArray *non_clock_info_array;
6248 union power_info *power_info;
6249 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
6250 u16 data_offset;
6251 u8 frev, crev;
6252 u8 *power_state_offset;
6253 struct ni_ps *ps;
6254
6255 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
6256 &frev, &crev, &data_offset))
6257 return -EINVAL;
6258 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
6259
6260 state_array = (struct _StateArray *)
6261 (mode_info->atom_context->bios + data_offset +
6262 le16_to_cpu(power_info->pplib.usStateArrayOffset));
6263 clock_info_array = (struct _ClockInfoArray *)
6264 (mode_info->atom_context->bios + data_offset +
6265 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
6266 non_clock_info_array = (struct _NonClockInfoArray *)
6267 (mode_info->atom_context->bios + data_offset +
6268 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
6269
6270 rdev->pm.dpm.ps = kzalloc(sizeof(struct radeon_ps) *
6271 state_array->ucNumEntries, GFP_KERNEL);
6272 if (!rdev->pm.dpm.ps)
6273 return -ENOMEM;
6274 power_state_offset = (u8 *)state_array->states;
6275 rdev->pm.dpm.platform_caps = le32_to_cpu(power_info->pplib.ulPlatformCaps);
6276 rdev->pm.dpm.backbias_response_time = le16_to_cpu(power_info->pplib.usBackbiasTime);
6277 rdev->pm.dpm.voltage_response_time = le16_to_cpu(power_info->pplib.usVoltageTime);
6278 for (i = 0; i < state_array->ucNumEntries; i++) {
6279 u8 *idx;
6280 power_state = (union pplib_power_state *)power_state_offset;
6281 non_clock_array_index = power_state->v2.nonClockInfoIndex;
6282 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
6283 &non_clock_info_array->nonClockInfo[non_clock_array_index];
6284 if (!rdev->pm.power_state[i].clock_info)
6285 return -EINVAL;
6286 ps = kzalloc(sizeof(struct ni_ps), GFP_KERNEL);
6287 if (ps == NULL) {
6288 kfree(rdev->pm.dpm.ps);
6289 return -ENOMEM;
6290 }
6291 rdev->pm.dpm.ps[i].ps_priv = ps;
6292 si_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i],
6293 non_clock_info,
6294 non_clock_info_array->ucEntrySize);
6295 k = 0;
6296 idx = (u8 *)&power_state->v2.clockInfoIndex[0];
6297 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
6298 clock_array_index = idx[j];
6299 if (clock_array_index >= clock_info_array->ucNumEntries)
6300 continue;
6301 if (k >= SISLANDS_MAX_HARDWARE_POWERLEVELS)
6302 break;
6303 clock_info = (union pplib_clock_info *)
6304 ((u8 *)&clock_info_array->clockInfo[0] +
6305 (clock_array_index * clock_info_array->ucEntrySize));
6306 si_parse_pplib_clock_info(rdev,
6307 &rdev->pm.dpm.ps[i], k,
6308 clock_info);
6309 k++;
6310 }
6311 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
6312 }
6313 rdev->pm.dpm.num_ps = state_array->ucNumEntries;
6314 return 0;
6315 }
6316
6317 int si_dpm_init(struct radeon_device *rdev)
6318 {
6319 struct rv7xx_power_info *pi;
6320 struct evergreen_power_info *eg_pi;
6321 struct ni_power_info *ni_pi;
6322 struct si_power_info *si_pi;
6323 struct atom_clock_dividers dividers;
6324 int ret;
6325 u32 mask;
6326
6327 si_pi = kzalloc(sizeof(struct si_power_info), GFP_KERNEL);
6328 if (si_pi == NULL)
6329 return -ENOMEM;
6330 rdev->pm.dpm.priv = si_pi;
6331 ni_pi = &si_pi->ni;
6332 eg_pi = &ni_pi->eg;
6333 pi = &eg_pi->rv7xx;
6334
6335 ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask);
6336 if (ret)
6337 si_pi->sys_pcie_mask = 0;
6338 else
6339 si_pi->sys_pcie_mask = mask;
6340 si_pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID;
6341 si_pi->boot_pcie_gen = si_get_current_pcie_speed(rdev);
6342
6343 si_set_max_cu_value(rdev);
6344
6345 rv770_get_max_vddc(rdev);
6346 si_get_leakage_vddc(rdev);
6347 si_patch_dependency_tables_based_on_leakage(rdev);
6348
6349 pi->acpi_vddc = 0;
6350 eg_pi->acpi_vddci = 0;
6351 pi->min_vddc_in_table = 0;
6352 pi->max_vddc_in_table = 0;
6353
6354 ret = si_parse_power_table(rdev);
6355 if (ret)
6356 return ret;
6357 ret = r600_parse_extended_power_table(rdev);
6358 if (ret)
6359 return ret;
6360
6361 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries =
6362 kzalloc(4 * sizeof(struct radeon_clock_voltage_dependency_entry), GFP_KERNEL);
6363 if (!rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) {
6364 r600_free_extended_power_table(rdev);
6365 return -ENOMEM;
6366 }
6367 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4;
6368 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0;
6369 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0;
6370 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000;
6371 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720;
6372 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000;
6373 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810;
6374 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000;
6375 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900;
6376
6377 if (rdev->pm.dpm.voltage_response_time == 0)
6378 rdev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT;
6379 if (rdev->pm.dpm.backbias_response_time == 0)
6380 rdev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT;
6381
6382 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
6383 0, false, &dividers);
6384 if (ret)
6385 pi->ref_div = dividers.ref_div + 1;
6386 else
6387 pi->ref_div = R600_REFERENCEDIVIDER_DFLT;
6388
6389 eg_pi->smu_uvd_hs = false;
6390
6391 pi->mclk_strobe_mode_threshold = 40000;
6392 if (si_is_special_1gb_platform(rdev))
6393 pi->mclk_stutter_mode_threshold = 0;
6394 else
6395 pi->mclk_stutter_mode_threshold = pi->mclk_strobe_mode_threshold;
6396 pi->mclk_edc_enable_threshold = 40000;
6397 eg_pi->mclk_edc_wr_enable_threshold = 40000;
6398
6399 ni_pi->mclk_rtt_mode_threshold = eg_pi->mclk_edc_wr_enable_threshold;
6400
6401 pi->voltage_control =
6402 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, VOLTAGE_OBJ_GPIO_LUT);
6403
6404 pi->mvdd_control =
6405 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_MVDDC, VOLTAGE_OBJ_GPIO_LUT);
6406
6407 eg_pi->vddci_control =
6408 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI, VOLTAGE_OBJ_GPIO_LUT);
6409
6410 si_pi->vddc_phase_shed_control =
6411 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, VOLTAGE_OBJ_PHASE_LUT);
6412
6413 rv770_get_engine_memory_ss(rdev);
6414
6415 pi->asi = RV770_ASI_DFLT;
6416 pi->pasi = CYPRESS_HASI_DFLT;
6417 pi->vrc = SISLANDS_VRC_DFLT;
6418
6419 pi->gfx_clock_gating = true;
6420
6421 eg_pi->sclk_deep_sleep = true;
6422 si_pi->sclk_deep_sleep_above_low = false;
6423
6424 if (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE)
6425 pi->thermal_protection = true;
6426 else
6427 pi->thermal_protection = false;
6428
6429 eg_pi->dynamic_ac_timing = true;
6430
6431 eg_pi->light_sleep = true;
6432 #if defined(CONFIG_ACPI)
6433 eg_pi->pcie_performance_request =
6434 radeon_acpi_is_pcie_performance_request_supported(rdev);
6435 #else
6436 eg_pi->pcie_performance_request = false;
6437 #endif
6438
6439 si_pi->sram_end = SMC_RAM_END;
6440
6441 rdev->pm.dpm.dyn_state.mclk_sclk_ratio = 4;
6442 rdev->pm.dpm.dyn_state.sclk_mclk_delta = 15000;
6443 rdev->pm.dpm.dyn_state.vddc_vddci_delta = 200;
6444 rdev->pm.dpm.dyn_state.valid_sclk_values.count = 0;
6445 rdev->pm.dpm.dyn_state.valid_sclk_values.values = NULL;
6446 rdev->pm.dpm.dyn_state.valid_mclk_values.count = 0;
6447 rdev->pm.dpm.dyn_state.valid_mclk_values.values = NULL;
6448
6449 si_initialize_powertune_defaults(rdev);
6450
6451 /* make sure dc limits are valid */
6452 if ((rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) ||
6453 (rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0))
6454 rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc =
6455 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
6456
6457 return 0;
6458 }
6459
6460 void si_dpm_fini(struct radeon_device *rdev)
6461 {
6462 int i;
6463
6464 for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
6465 kfree(rdev->pm.dpm.ps[i].ps_priv);
6466 }
6467 kfree(rdev->pm.dpm.ps);
6468 kfree(rdev->pm.dpm.priv);
6469 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries);
6470 r600_free_extended_power_table(rdev);
6471 }
6472
6473 void si_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
6474 struct seq_file *m)
6475 {
6476 struct radeon_ps *rps = rdev->pm.dpm.current_ps;
6477 struct ni_ps *ps = ni_get_ps(rps);
6478 struct rv7xx_pl *pl;
6479 u32 current_index =
6480 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >>
6481 CURRENT_STATE_INDEX_SHIFT;
6482
6483 if (current_index >= ps->performance_level_count) {
6484 seq_printf(m, "invalid dpm profile %d\n", current_index);
6485 } else {
6486 pl = &ps->performance_levels[current_index];
6487 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
6488 seq_printf(m, "power level %d sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n",
6489 current_index, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1);
6490 }
6491 }
Linux kernel - Deliverables
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