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drm/radeon/dpm: fix typo in setting smc flag
[deliverable/linux.git] / drivers / gpu / drm / radeon / si_dpm.c
1 /*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #include "drmP.h"
25 #include "radeon.h"
26 #include "sid.h"
27 #include "r600_dpm.h"
28 #include "si_dpm.h"
29 #include "atom.h"
30 #include <linux/math64.h>
31 #include <linux/seq_file.h>
32
33 #define MC_CG_ARB_FREQ_F0 0x0a
34 #define MC_CG_ARB_FREQ_F1 0x0b
35 #define MC_CG_ARB_FREQ_F2 0x0c
36 #define MC_CG_ARB_FREQ_F3 0x0d
37
38 #define SMC_RAM_END 0x20000
39
40 #define SCLK_MIN_DEEPSLEEP_FREQ 1350
41
42 static const struct si_cac_config_reg cac_weights_tahiti[] =
43 {
44 { 0x0, 0x0000ffff, 0, 0xc, SISLANDS_CACCONFIG_CGIND },
45 { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
46 { 0x1, 0x0000ffff, 0, 0x101, SISLANDS_CACCONFIG_CGIND },
47 { 0x1, 0xffff0000, 16, 0xc, SISLANDS_CACCONFIG_CGIND },
48 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
49 { 0x3, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
50 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
51 { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
52 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
53 { 0x5, 0x0000ffff, 0, 0x8fc, SISLANDS_CACCONFIG_CGIND },
54 { 0x5, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
55 { 0x6, 0x0000ffff, 0, 0x95, SISLANDS_CACCONFIG_CGIND },
56 { 0x6, 0xffff0000, 16, 0x34e, SISLANDS_CACCONFIG_CGIND },
57 { 0x18f, 0x0000ffff, 0, 0x1a1, SISLANDS_CACCONFIG_CGIND },
58 { 0x7, 0x0000ffff, 0, 0xda, SISLANDS_CACCONFIG_CGIND },
59 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
60 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
61 { 0x8, 0xffff0000, 16, 0x46, SISLANDS_CACCONFIG_CGIND },
62 { 0x9, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
63 { 0xa, 0x0000ffff, 0, 0x208, SISLANDS_CACCONFIG_CGIND },
64 { 0xb, 0x0000ffff, 0, 0xe7, SISLANDS_CACCONFIG_CGIND },
65 { 0xb, 0xffff0000, 16, 0x948, SISLANDS_CACCONFIG_CGIND },
66 { 0xc, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
67 { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
68 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
69 { 0xe, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
70 { 0xf, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
71 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
72 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
73 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
74 { 0x11, 0x0000ffff, 0, 0x167, SISLANDS_CACCONFIG_CGIND },
75 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
76 { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
77 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
78 { 0x13, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
79 { 0x14, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
80 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
81 { 0x15, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
82 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
83 { 0x16, 0x0000ffff, 0, 0x31, SISLANDS_CACCONFIG_CGIND },
84 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
85 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
86 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
87 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
88 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
89 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
90 { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
91 { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
92 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
93 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
94 { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
95 { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
96 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
97 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
98 { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
99 { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
100 { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
101 { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
102 { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
103 { 0x6d, 0x0000ffff, 0, 0x18e, SISLANDS_CACCONFIG_CGIND },
104 { 0xFFFFFFFF }
105 };
106
107 static const struct si_cac_config_reg lcac_tahiti[] =
108 {
109 { 0x143, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
110 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
111 { 0x146, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
112 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
113 { 0x149, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
114 { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
115 { 0x14c, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
116 { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
117 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
118 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
119 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
120 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
121 { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
122 { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
123 { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
124 { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
125 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
126 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
127 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
128 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
129 { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
130 { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
131 { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
132 { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
133 { 0x8c, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
134 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
135 { 0x8f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
136 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
137 { 0x92, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
138 { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
139 { 0x95, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
140 { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
141 { 0x14f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
142 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
143 { 0x152, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
144 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
145 { 0x155, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
146 { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
147 { 0x158, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
148 { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
149 { 0x110, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
150 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
151 { 0x113, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
152 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
153 { 0x116, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
154 { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
155 { 0x119, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
156 { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
157 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
158 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
159 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
160 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
161 { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
162 { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
163 { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
164 { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
165 { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
166 { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
167 { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
168 { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
169 { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
170 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
171 { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
172 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
173 { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
174 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
175 { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
176 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
177 { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
178 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
179 { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
180 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
181 { 0x16d, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
182 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
183 { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
184 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
185 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
186 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
187 { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
188 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
189 { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
190 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
191 { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
192 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
193 { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
194 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
195 { 0xFFFFFFFF }
196
197 };
198
199 static const struct si_cac_config_reg cac_override_tahiti[] =
200 {
201 { 0xFFFFFFFF }
202 };
203
204 static const struct si_powertune_data powertune_data_tahiti =
205 {
206 ((1 << 16) | 27027),
207 6,
208 0,
209 4,
210 95,
211 {
212 0UL,
213 0UL,
214 4521550UL,
215 309631529UL,
216 -1270850L,
217 4513710L,
218 40
219 },
220 595000000UL,
221 12,
222 {
223 0,
224 0,
225 0,
226 0,
227 0,
228 0,
229 0,
230 0
231 },
232 true
233 };
234
235 static const struct si_dte_data dte_data_tahiti =
236 {
237 { 1159409, 0, 0, 0, 0 },
238 { 777, 0, 0, 0, 0 },
239 2,
240 54000,
241 127000,
242 25,
243 2,
244 10,
245 13,
246 { 27, 31, 35, 39, 43, 47, 54, 61, 67, 74, 81, 88, 95, 0, 0, 0 },
247 { 240888759, 221057860, 235370597, 162287531, 158510299, 131423027, 116673180, 103067515, 87941937, 76209048, 68209175, 64090048, 58301890, 0, 0, 0 },
248 { 12024, 11189, 11451, 8411, 7939, 6666, 5681, 4905, 4241, 3720, 3354, 3122, 2890, 0, 0, 0 },
249 85,
250 false
251 };
252
253 static const struct si_dte_data dte_data_tahiti_le =
254 {
255 { 0x1E8480, 0x7A1200, 0x2160EC0, 0x3938700, 0 },
256 { 0x7D, 0x7D, 0x4E4, 0xB00, 0 },
257 0x5,
258 0xAFC8,
259 0x64,
260 0x32,
261 1,
262 0,
263 0x10,
264 { 0x78, 0x7C, 0x82, 0x88, 0x8E, 0x94, 0x9A, 0xA0, 0xA6, 0xAC, 0xB0, 0xB4, 0xB8, 0xBC, 0xC0, 0xC4 },
265 { 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700 },
266 { 0x2AF8, 0x2AF8, 0x29BB, 0x27F9, 0x2637, 0x2475, 0x22B3, 0x20F1, 0x1F2F, 0x1D6D, 0x1734, 0x1414, 0x10F4, 0xDD4, 0xAB4, 0x794 },
267 85,
268 true
269 };
270
271 static const struct si_dte_data dte_data_tahiti_pro =
272 {
273 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
274 { 0x0, 0x0, 0x0, 0x0, 0x0 },
275 5,
276 45000,
277 100,
278 0xA,
279 1,
280 0,
281 0x10,
282 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
283 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
284 { 0x7D0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
285 90,
286 true
287 };
288
289 static const struct si_dte_data dte_data_new_zealand =
290 {
291 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0 },
292 { 0x29B, 0x3E9, 0x537, 0x7D2, 0 },
293 0x5,
294 0xAFC8,
295 0x69,
296 0x32,
297 1,
298 0,
299 0x10,
300 { 0x82, 0xA0, 0xB4, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE },
301 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
302 { 0xDAC, 0x1388, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685 },
303 85,
304 true
305 };
306
307 static const struct si_dte_data dte_data_aruba_pro =
308 {
309 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
310 { 0x0, 0x0, 0x0, 0x0, 0x0 },
311 5,
312 45000,
313 100,
314 0xA,
315 1,
316 0,
317 0x10,
318 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
319 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
320 { 0x1000, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
321 90,
322 true
323 };
324
325 static const struct si_dte_data dte_data_malta =
326 {
327 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
328 { 0x0, 0x0, 0x0, 0x0, 0x0 },
329 5,
330 45000,
331 100,
332 0xA,
333 1,
334 0,
335 0x10,
336 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
337 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
338 { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
339 90,
340 true
341 };
342
343 struct si_cac_config_reg cac_weights_pitcairn[] =
344 {
345 { 0x0, 0x0000ffff, 0, 0x8a, SISLANDS_CACCONFIG_CGIND },
346 { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
347 { 0x1, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
348 { 0x1, 0xffff0000, 16, 0x24d, SISLANDS_CACCONFIG_CGIND },
349 { 0x2, 0x0000ffff, 0, 0x19, SISLANDS_CACCONFIG_CGIND },
350 { 0x3, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
351 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
352 { 0x4, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
353 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
354 { 0x5, 0x0000ffff, 0, 0xc11, SISLANDS_CACCONFIG_CGIND },
355 { 0x5, 0xffff0000, 16, 0x7f3, SISLANDS_CACCONFIG_CGIND },
356 { 0x6, 0x0000ffff, 0, 0x403, SISLANDS_CACCONFIG_CGIND },
357 { 0x6, 0xffff0000, 16, 0x367, SISLANDS_CACCONFIG_CGIND },
358 { 0x18f, 0x0000ffff, 0, 0x4c9, SISLANDS_CACCONFIG_CGIND },
359 { 0x7, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
360 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
361 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
362 { 0x8, 0xffff0000, 16, 0x45d, SISLANDS_CACCONFIG_CGIND },
363 { 0x9, 0x0000ffff, 0, 0x36d, SISLANDS_CACCONFIG_CGIND },
364 { 0xa, 0x0000ffff, 0, 0x534, SISLANDS_CACCONFIG_CGIND },
365 { 0xb, 0x0000ffff, 0, 0x5da, SISLANDS_CACCONFIG_CGIND },
366 { 0xb, 0xffff0000, 16, 0x880, SISLANDS_CACCONFIG_CGIND },
367 { 0xc, 0x0000ffff, 0, 0x201, SISLANDS_CACCONFIG_CGIND },
368 { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
369 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
370 { 0xe, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND },
371 { 0xf, 0x0000ffff, 0, 0x1f, SISLANDS_CACCONFIG_CGIND },
372 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
373 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
374 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
375 { 0x11, 0x0000ffff, 0, 0x5de, SISLANDS_CACCONFIG_CGIND },
376 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
377 { 0x12, 0x0000ffff, 0, 0x7b, SISLANDS_CACCONFIG_CGIND },
378 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
379 { 0x13, 0xffff0000, 16, 0x13, SISLANDS_CACCONFIG_CGIND },
380 { 0x14, 0x0000ffff, 0, 0xf9, SISLANDS_CACCONFIG_CGIND },
381 { 0x15, 0x0000ffff, 0, 0x66, SISLANDS_CACCONFIG_CGIND },
382 { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
383 { 0x4e, 0x0000ffff, 0, 0x13, SISLANDS_CACCONFIG_CGIND },
384 { 0x16, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
385 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
386 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
387 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
388 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
389 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
390 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
391 { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
392 { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
393 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
394 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
395 { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
396 { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
397 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
398 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
399 { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
400 { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
401 { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
402 { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
403 { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
404 { 0x6d, 0x0000ffff, 0, 0x186, SISLANDS_CACCONFIG_CGIND },
405 { 0xFFFFFFFF }
406 };
407
408 static const struct si_cac_config_reg lcac_pitcairn[] =
409 {
410 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
411 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
412 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
413 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
414 { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
415 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
416 { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
417 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
418 { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
419 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
420 { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
421 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
422 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
423 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
424 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
425 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
426 { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
427 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
428 { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
429 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
430 { 0x8f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
431 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
432 { 0x146, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
433 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
434 { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
435 { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
436 { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
437 { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
438 { 0x116, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
439 { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
440 { 0x155, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
441 { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
442 { 0x92, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
443 { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
444 { 0x149, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
445 { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
446 { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
447 { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
448 { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
449 { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
450 { 0x119, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
451 { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
452 { 0x158, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
453 { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
454 { 0x95, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
455 { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
456 { 0x14c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
457 { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
458 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
459 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
460 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
461 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
462 { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
463 { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
464 { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
465 { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
466 { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
467 { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
468 { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
469 { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
470 { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
471 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
472 { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
473 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
474 { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
475 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
476 { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
477 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
478 { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
479 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
480 { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
481 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
482 { 0x16d, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
483 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
484 { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
485 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
486 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
487 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
488 { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
489 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
490 { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
491 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
492 { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
493 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
494 { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
495 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
496 { 0xFFFFFFFF }
497 };
498
499 static const struct si_cac_config_reg cac_override_pitcairn[] =
500 {
501 { 0xFFFFFFFF }
502 };
503
504 static const struct si_powertune_data powertune_data_pitcairn =
505 {
506 ((1 << 16) | 27027),
507 5,
508 0,
509 6,
510 100,
511 {
512 51600000UL,
513 1800000UL,
514 7194395UL,
515 309631529UL,
516 -1270850L,
517 4513710L,
518 100
519 },
520 117830498UL,
521 12,
522 {
523 0,
524 0,
525 0,
526 0,
527 0,
528 0,
529 0,
530 0
531 },
532 true
533 };
534
535 static const struct si_dte_data dte_data_pitcairn =
536 {
537 { 0, 0, 0, 0, 0 },
538 { 0, 0, 0, 0, 0 },
539 0,
540 0,
541 0,
542 0,
543 0,
544 0,
545 0,
546 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
547 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
548 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
549 0,
550 false
551 };
552
553 static const struct si_dte_data dte_data_curacao_xt =
554 {
555 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
556 { 0x0, 0x0, 0x0, 0x0, 0x0 },
557 5,
558 45000,
559 100,
560 0xA,
561 1,
562 0,
563 0x10,
564 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
565 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
566 { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
567 90,
568 true
569 };
570
571 static const struct si_dte_data dte_data_curacao_pro =
572 {
573 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
574 { 0x0, 0x0, 0x0, 0x0, 0x0 },
575 5,
576 45000,
577 100,
578 0xA,
579 1,
580 0,
581 0x10,
582 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
583 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
584 { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
585 90,
586 true
587 };
588
589 static const struct si_dte_data dte_data_neptune_xt =
590 {
591 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
592 { 0x0, 0x0, 0x0, 0x0, 0x0 },
593 5,
594 45000,
595 100,
596 0xA,
597 1,
598 0,
599 0x10,
600 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
601 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
602 { 0x3A2F, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
603 90,
604 true
605 };
606
607 static const struct si_cac_config_reg cac_weights_chelsea_pro[] =
608 {
609 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
610 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
611 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
612 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
613 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
614 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
615 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
616 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
617 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
618 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
619 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
620 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
621 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
622 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
623 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
624 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
625 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
626 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
627 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
628 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
629 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
630 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
631 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
632 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
633 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
634 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
635 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
636 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
637 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
638 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
639 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
640 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
641 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
642 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
643 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
644 { 0x14, 0x0000ffff, 0, 0x2BD, SISLANDS_CACCONFIG_CGIND },
645 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
646 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
647 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
648 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
649 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
650 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
651 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
652 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
653 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
654 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
655 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
656 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
657 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
658 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
659 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
660 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
661 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
662 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
663 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
664 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
665 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
666 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
667 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
668 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
669 { 0xFFFFFFFF }
670 };
671
672 static const struct si_cac_config_reg cac_weights_chelsea_xt[] =
673 {
674 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
675 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
676 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
677 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
678 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
679 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
680 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
681 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
682 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
683 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
684 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
685 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
686 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
687 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
688 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
689 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
690 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
691 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
692 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
693 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
694 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
695 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
696 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
697 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
698 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
699 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
700 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
701 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
702 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
703 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
704 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
705 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
706 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
707 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
708 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
709 { 0x14, 0x0000ffff, 0, 0x30A, SISLANDS_CACCONFIG_CGIND },
710 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
711 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
712 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
713 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
714 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
715 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
716 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
717 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
718 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
719 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
720 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
721 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
722 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
723 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
724 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
725 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
726 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
727 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
728 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
729 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
730 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
731 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
732 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
733 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
734 { 0xFFFFFFFF }
735 };
736
737 static const struct si_cac_config_reg cac_weights_heathrow[] =
738 {
739 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
740 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
741 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
742 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
743 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
744 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
745 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
746 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
747 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
748 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
749 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
750 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
751 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
752 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
753 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
754 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
755 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
756 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
757 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
758 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
759 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
760 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
761 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
762 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
763 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
764 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
765 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
766 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
767 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
768 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
769 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
770 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
771 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
772 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
773 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
774 { 0x14, 0x0000ffff, 0, 0x362, SISLANDS_CACCONFIG_CGIND },
775 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
776 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
777 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
778 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
779 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
780 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
781 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
782 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
783 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
784 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
785 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
786 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
787 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
788 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
789 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
790 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
791 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
792 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
793 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
794 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
795 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
796 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
797 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
798 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
799 { 0xFFFFFFFF }
800 };
801
802 static const struct si_cac_config_reg cac_weights_cape_verde_pro[] =
803 {
804 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
805 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
806 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
807 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
808 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
809 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
810 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
811 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
812 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
813 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
814 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
815 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
816 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
817 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
818 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
819 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
820 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
821 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
822 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
823 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
824 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
825 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
826 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
827 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
828 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
829 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
830 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
831 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
832 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
833 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
834 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
835 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
836 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
837 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
838 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
839 { 0x14, 0x0000ffff, 0, 0x315, SISLANDS_CACCONFIG_CGIND },
840 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
841 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
842 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
843 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
844 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
845 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
846 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
847 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
848 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
849 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
850 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
851 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
852 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
853 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
854 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
855 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
856 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
857 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
858 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
859 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
860 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
861 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
862 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
863 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
864 { 0xFFFFFFFF }
865 };
866
867 static const struct si_cac_config_reg cac_weights_cape_verde[] =
868 {
869 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
870 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
871 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
872 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
873 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
874 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
875 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
876 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
877 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
878 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
879 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
880 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
881 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
882 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
883 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
884 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
885 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
886 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
887 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
888 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
889 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
890 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
891 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
892 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
893 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
894 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
895 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
896 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
897 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
898 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
899 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
900 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
901 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
902 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
903 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
904 { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND },
905 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
906 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
907 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
908 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
909 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
910 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
911 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
912 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
913 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
914 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
915 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
916 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
917 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
918 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
919 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
920 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
921 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
922 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
923 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
924 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
925 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
926 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
927 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
928 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
929 { 0xFFFFFFFF }
930 };
931
932 static const struct si_cac_config_reg lcac_cape_verde[] =
933 {
934 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
935 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
936 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
937 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
938 { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
939 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
940 { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
941 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
942 { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
943 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
944 { 0x143, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
945 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
946 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
947 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
948 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
949 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
950 { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
951 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
952 { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
953 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
954 { 0x8f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
955 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
956 { 0x146, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
957 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
958 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
959 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
960 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
961 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
962 { 0x164, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
963 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
964 { 0x167, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
965 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
966 { 0x16a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
967 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
968 { 0x15e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
969 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
970 { 0x161, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
971 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
972 { 0x15b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
973 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
974 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
975 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
976 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
977 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
978 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
979 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
980 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
981 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
982 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
983 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
984 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
985 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
986 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
987 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
988 { 0xFFFFFFFF }
989 };
990
991 static const struct si_cac_config_reg cac_override_cape_verde[] =
992 {
993 { 0xFFFFFFFF }
994 };
995
996 static const struct si_powertune_data powertune_data_cape_verde =
997 {
998 ((1 << 16) | 0x6993),
999 5,
1000 0,
1001 7,
1002 105,
1003 {
1004 0UL,
1005 0UL,
1006 7194395UL,
1007 309631529UL,
1008 -1270850L,
1009 4513710L,
1010 100
1011 },
1012 117830498UL,
1013 12,
1014 {
1015 0,
1016 0,
1017 0,
1018 0,
1019 0,
1020 0,
1021 0,
1022 0
1023 },
1024 true
1025 };
1026
1027 static const struct si_dte_data dte_data_cape_verde =
1028 {
1029 { 0, 0, 0, 0, 0 },
1030 { 0, 0, 0, 0, 0 },
1031 0,
1032 0,
1033 0,
1034 0,
1035 0,
1036 0,
1037 0,
1038 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1039 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1040 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1041 0,
1042 false
1043 };
1044
1045 static const struct si_dte_data dte_data_venus_xtx =
1046 {
1047 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1048 { 0x71C, 0xAAB, 0xE39, 0x11C7, 0x0 },
1049 5,
1050 55000,
1051 0x69,
1052 0xA,
1053 1,
1054 0,
1055 0x3,
1056 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1057 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1058 { 0xD6D8, 0x88B8, 0x1555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1059 90,
1060 true
1061 };
1062
1063 static const struct si_dte_data dte_data_venus_xt =
1064 {
1065 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1066 { 0xBDA, 0x11C7, 0x17B4, 0x1DA1, 0x0 },
1067 5,
1068 55000,
1069 0x69,
1070 0xA,
1071 1,
1072 0,
1073 0x3,
1074 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1075 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1076 { 0xAFC8, 0x88B8, 0x238E, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1077 90,
1078 true
1079 };
1080
1081 static const struct si_dte_data dte_data_venus_pro =
1082 {
1083 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1084 { 0x11C7, 0x1AAB, 0x238E, 0x2C72, 0x0 },
1085 5,
1086 55000,
1087 0x69,
1088 0xA,
1089 1,
1090 0,
1091 0x3,
1092 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1093 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1094 { 0x88B8, 0x88B8, 0x3555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1095 90,
1096 true
1097 };
1098
1099 struct si_cac_config_reg cac_weights_oland[] =
1100 {
1101 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
1102 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
1103 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
1104 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
1105 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1106 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
1107 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
1108 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
1109 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
1110 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
1111 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
1112 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
1113 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
1114 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
1115 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
1116 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
1117 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
1118 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
1119 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
1120 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
1121 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
1122 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
1123 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
1124 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
1125 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
1126 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1127 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1128 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1129 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1130 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
1131 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1132 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
1133 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
1134 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
1135 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1136 { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND },
1137 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1138 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1139 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1140 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
1141 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
1142 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1143 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1144 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1145 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1146 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1147 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1148 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1149 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1150 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1151 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1152 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1153 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1154 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1155 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1156 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1157 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1158 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1159 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1160 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
1161 { 0xFFFFFFFF }
1162 };
1163
1164 static const struct si_cac_config_reg cac_weights_mars_pro[] =
1165 {
1166 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1167 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1168 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1169 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1170 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1171 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1172 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1173 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1174 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1175 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1176 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1177 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1178 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1179 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1180 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1181 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1182 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1183 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1184 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1185 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1186 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1187 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1188 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1189 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1190 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1191 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1192 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1193 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1194 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1195 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1196 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1197 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1198 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1199 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1200 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1201 { 0x14, 0x0000ffff, 0, 0x2, SISLANDS_CACCONFIG_CGIND },
1202 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1203 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1204 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1205 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1206 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1207 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1208 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1209 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1210 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1211 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1212 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1213 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1214 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1215 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1216 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1217 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1218 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1219 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1220 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1221 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1222 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1223 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1224 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1225 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1226 { 0xFFFFFFFF }
1227 };
1228
1229 static const struct si_cac_config_reg cac_weights_mars_xt[] =
1230 {
1231 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1232 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1233 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1234 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1235 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1236 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1237 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1238 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1239 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1240 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1241 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1242 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1243 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1244 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1245 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1246 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1247 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1248 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1249 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1250 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1251 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1252 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1253 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1254 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1255 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1256 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1257 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1258 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1259 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1260 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1261 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1262 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1263 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1264 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1265 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1266 { 0x14, 0x0000ffff, 0, 0x60, SISLANDS_CACCONFIG_CGIND },
1267 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1268 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1269 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1270 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1271 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1272 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1273 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1274 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1275 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1276 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1277 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1278 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1279 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1280 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1281 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1282 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1283 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1284 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1285 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1286 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1287 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1288 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1289 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1290 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1291 { 0xFFFFFFFF }
1292 };
1293
1294 static const struct si_cac_config_reg cac_weights_oland_pro[] =
1295 {
1296 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1297 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1298 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1299 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1300 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1301 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1302 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1303 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1304 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1305 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1306 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1307 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1308 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1309 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1310 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1311 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1312 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1313 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1314 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1315 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1316 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1317 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1318 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1319 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1320 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1321 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1322 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1323 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1324 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1325 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1326 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1327 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1328 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1329 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1330 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1331 { 0x14, 0x0000ffff, 0, 0x90, SISLANDS_CACCONFIG_CGIND },
1332 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1333 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1334 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1335 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1336 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1337 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1338 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1339 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1340 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1341 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1342 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1343 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1344 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1345 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1346 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1347 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1348 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1349 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1350 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1351 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1352 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1353 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1354 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1355 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1356 { 0xFFFFFFFF }
1357 };
1358
1359 static const struct si_cac_config_reg cac_weights_oland_xt[] =
1360 {
1361 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1362 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1363 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1364 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1365 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1366 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1367 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1368 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1369 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1370 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1371 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1372 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1373 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1374 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1375 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1376 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1377 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1378 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1379 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1380 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1381 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1382 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1383 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1384 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1385 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1386 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1387 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1388 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1389 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1390 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1391 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1392 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1393 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1394 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1395 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1396 { 0x14, 0x0000ffff, 0, 0x120, SISLANDS_CACCONFIG_CGIND },
1397 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1398 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1399 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1400 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1401 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1402 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1403 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1404 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1405 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1406 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1407 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1408 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1409 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1410 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1411 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1412 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1413 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1414 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1415 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1416 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1417 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1418 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1419 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1420 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1421 { 0xFFFFFFFF }
1422 };
1423
1424 static const struct si_cac_config_reg lcac_oland[] =
1425 {
1426 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1427 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1428 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1429 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1430 { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1431 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1432 { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1433 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1434 { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1435 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1436 { 0x143, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
1437 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1438 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1439 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1440 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1441 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1442 { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1443 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1444 { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1445 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1446 { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1447 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1448 { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1449 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1450 { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1451 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1452 { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1453 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1454 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1455 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1456 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1457 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1458 { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1459 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1460 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1461 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1462 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1463 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1464 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1465 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1466 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1467 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1468 { 0xFFFFFFFF }
1469 };
1470
1471 static const struct si_cac_config_reg lcac_mars_pro[] =
1472 {
1473 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1474 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1475 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1476 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1477 { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1478 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1479 { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1480 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1481 { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1482 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1483 { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1484 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1485 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1486 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1487 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1488 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1489 { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1490 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1491 { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1492 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1493 { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1494 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1495 { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1496 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1497 { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1498 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1499 { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1500 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1501 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1502 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1503 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1504 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1505 { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1506 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1507 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1508 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1509 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1510 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1511 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1512 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1513 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1514 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1515 { 0xFFFFFFFF }
1516 };
1517
1518 static const struct si_cac_config_reg cac_override_oland[] =
1519 {
1520 { 0xFFFFFFFF }
1521 };
1522
1523 static const struct si_powertune_data powertune_data_oland =
1524 {
1525 ((1 << 16) | 0x6993),
1526 5,
1527 0,
1528 7,
1529 105,
1530 {
1531 0UL,
1532 0UL,
1533 7194395UL,
1534 309631529UL,
1535 -1270850L,
1536 4513710L,
1537 100
1538 },
1539 117830498UL,
1540 12,
1541 {
1542 0,
1543 0,
1544 0,
1545 0,
1546 0,
1547 0,
1548 0,
1549 0
1550 },
1551 true
1552 };
1553
1554 static const struct si_powertune_data powertune_data_mars_pro =
1555 {
1556 ((1 << 16) | 0x6993),
1557 5,
1558 0,
1559 7,
1560 105,
1561 {
1562 0UL,
1563 0UL,
1564 7194395UL,
1565 309631529UL,
1566 -1270850L,
1567 4513710L,
1568 100
1569 },
1570 117830498UL,
1571 12,
1572 {
1573 0,
1574 0,
1575 0,
1576 0,
1577 0,
1578 0,
1579 0,
1580 0
1581 },
1582 true
1583 };
1584
1585 static const struct si_dte_data dte_data_oland =
1586 {
1587 { 0, 0, 0, 0, 0 },
1588 { 0, 0, 0, 0, 0 },
1589 0,
1590 0,
1591 0,
1592 0,
1593 0,
1594 0,
1595 0,
1596 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1597 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1598 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1599 0,
1600 false
1601 };
1602
1603 static const struct si_dte_data dte_data_mars_pro =
1604 {
1605 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1606 { 0x0, 0x0, 0x0, 0x0, 0x0 },
1607 5,
1608 55000,
1609 105,
1610 0xA,
1611 1,
1612 0,
1613 0x10,
1614 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
1615 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
1616 { 0xF627, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1617 90,
1618 true
1619 };
1620
1621 static const struct si_dte_data dte_data_sun_xt =
1622 {
1623 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1624 { 0x0, 0x0, 0x0, 0x0, 0x0 },
1625 5,
1626 55000,
1627 105,
1628 0xA,
1629 1,
1630 0,
1631 0x10,
1632 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
1633 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
1634 { 0xD555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1635 90,
1636 true
1637 };
1638
1639
1640 static const struct si_cac_config_reg cac_weights_hainan[] =
1641 {
1642 { 0x0, 0x0000ffff, 0, 0x2d9, SISLANDS_CACCONFIG_CGIND },
1643 { 0x0, 0xffff0000, 16, 0x22b, SISLANDS_CACCONFIG_CGIND },
1644 { 0x1, 0x0000ffff, 0, 0x21c, SISLANDS_CACCONFIG_CGIND },
1645 { 0x1, 0xffff0000, 16, 0x1dc, SISLANDS_CACCONFIG_CGIND },
1646 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1647 { 0x3, 0x0000ffff, 0, 0x24e, SISLANDS_CACCONFIG_CGIND },
1648 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1649 { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1650 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1651 { 0x5, 0x0000ffff, 0, 0x35e, SISLANDS_CACCONFIG_CGIND },
1652 { 0x5, 0xffff0000, 16, 0x1143, SISLANDS_CACCONFIG_CGIND },
1653 { 0x6, 0x0000ffff, 0, 0xe17, SISLANDS_CACCONFIG_CGIND },
1654 { 0x6, 0xffff0000, 16, 0x441, SISLANDS_CACCONFIG_CGIND },
1655 { 0x18f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1656 { 0x7, 0x0000ffff, 0, 0x28b, SISLANDS_CACCONFIG_CGIND },
1657 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1658 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1659 { 0x8, 0xffff0000, 16, 0xabe, SISLANDS_CACCONFIG_CGIND },
1660 { 0x9, 0x0000ffff, 0, 0xf11, SISLANDS_CACCONFIG_CGIND },
1661 { 0xa, 0x0000ffff, 0, 0x907, SISLANDS_CACCONFIG_CGIND },
1662 { 0xb, 0x0000ffff, 0, 0xb45, SISLANDS_CACCONFIG_CGIND },
1663 { 0xb, 0xffff0000, 16, 0xd1e, SISLANDS_CACCONFIG_CGIND },
1664 { 0xc, 0x0000ffff, 0, 0xa2c, SISLANDS_CACCONFIG_CGIND },
1665 { 0xd, 0x0000ffff, 0, 0x62, SISLANDS_CACCONFIG_CGIND },
1666 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1667 { 0xe, 0x0000ffff, 0, 0x1f3, SISLANDS_CACCONFIG_CGIND },
1668 { 0xf, 0x0000ffff, 0, 0x42, SISLANDS_CACCONFIG_CGIND },
1669 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1670 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1671 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1672 { 0x11, 0x0000ffff, 0, 0x709, SISLANDS_CACCONFIG_CGIND },
1673 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1674 { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1675 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1676 { 0x13, 0xffff0000, 16, 0x3a, SISLANDS_CACCONFIG_CGIND },
1677 { 0x14, 0x0000ffff, 0, 0x357, SISLANDS_CACCONFIG_CGIND },
1678 { 0x15, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND },
1679 { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1680 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1681 { 0x16, 0x0000ffff, 0, 0x314, SISLANDS_CACCONFIG_CGIND },
1682 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1683 { 0x17, 0x0000ffff, 0, 0x6d, SISLANDS_CACCONFIG_CGIND },
1684 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1685 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1686 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1687 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1688 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1689 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1690 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1691 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1692 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1693 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1694 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1695 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1696 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1697 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1698 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1699 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1700 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1701 { 0x6d, 0x0000ffff, 0, 0x1b9, SISLANDS_CACCONFIG_CGIND },
1702 { 0xFFFFFFFF }
1703 };
1704
1705 static const struct si_powertune_data powertune_data_hainan =
1706 {
1707 ((1 << 16) | 0x6993),
1708 5,
1709 0,
1710 9,
1711 105,
1712 {
1713 0UL,
1714 0UL,
1715 7194395UL,
1716 309631529UL,
1717 -1270850L,
1718 4513710L,
1719 100
1720 },
1721 117830498UL,
1722 12,
1723 {
1724 0,
1725 0,
1726 0,
1727 0,
1728 0,
1729 0,
1730 0,
1731 0
1732 },
1733 true
1734 };
1735
1736 struct rv7xx_power_info *rv770_get_pi(struct radeon_device *rdev);
1737 struct evergreen_power_info *evergreen_get_pi(struct radeon_device *rdev);
1738 struct ni_power_info *ni_get_pi(struct radeon_device *rdev);
1739 struct ni_ps *ni_get_ps(struct radeon_ps *rps);
1740
1741 static int si_populate_voltage_value(struct radeon_device *rdev,
1742 const struct atom_voltage_table *table,
1743 u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage);
1744 static int si_get_std_voltage_value(struct radeon_device *rdev,
1745 SISLANDS_SMC_VOLTAGE_VALUE *voltage,
1746 u16 *std_voltage);
1747 static int si_write_smc_soft_register(struct radeon_device *rdev,
1748 u16 reg_offset, u32 value);
1749 static int si_convert_power_level_to_smc(struct radeon_device *rdev,
1750 struct rv7xx_pl *pl,
1751 SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level);
1752 static int si_calculate_sclk_params(struct radeon_device *rdev,
1753 u32 engine_clock,
1754 SISLANDS_SMC_SCLK_VALUE *sclk);
1755
1756 extern void si_update_cg(struct radeon_device *rdev,
1757 u32 block, bool enable);
1758
1759 static struct si_power_info *si_get_pi(struct radeon_device *rdev)
1760 {
1761 struct si_power_info *pi = rdev->pm.dpm.priv;
1762
1763 return pi;
1764 }
1765
1766 static void si_calculate_leakage_for_v_and_t_formula(const struct ni_leakage_coeffients *coeff,
1767 u16 v, s32 t, u32 ileakage, u32 *leakage)
1768 {
1769 s64 kt, kv, leakage_w, i_leakage, vddc;
1770 s64 temperature, t_slope, t_intercept, av, bv, t_ref;
1771 s64 tmp;
1772
1773 i_leakage = div64_s64(drm_int2fixp(ileakage), 100);
1774 vddc = div64_s64(drm_int2fixp(v), 1000);
1775 temperature = div64_s64(drm_int2fixp(t), 1000);
1776
1777 t_slope = div64_s64(drm_int2fixp(coeff->t_slope), 100000000);
1778 t_intercept = div64_s64(drm_int2fixp(coeff->t_intercept), 100000000);
1779 av = div64_s64(drm_int2fixp(coeff->av), 100000000);
1780 bv = div64_s64(drm_int2fixp(coeff->bv), 100000000);
1781 t_ref = drm_int2fixp(coeff->t_ref);
1782
1783 tmp = drm_fixp_mul(t_slope, vddc) + t_intercept;
1784 kt = drm_fixp_exp(drm_fixp_mul(tmp, temperature));
1785 kt = drm_fixp_div(kt, drm_fixp_exp(drm_fixp_mul(tmp, t_ref)));
1786 kv = drm_fixp_mul(av, drm_fixp_exp(drm_fixp_mul(bv, vddc)));
1787
1788 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc);
1789
1790 *leakage = drm_fixp2int(leakage_w * 1000);
1791 }
1792
1793 static void si_calculate_leakage_for_v_and_t(struct radeon_device *rdev,
1794 const struct ni_leakage_coeffients *coeff,
1795 u16 v,
1796 s32 t,
1797 u32 i_leakage,
1798 u32 *leakage)
1799 {
1800 si_calculate_leakage_for_v_and_t_formula(coeff, v, t, i_leakage, leakage);
1801 }
1802
1803 static void si_calculate_leakage_for_v_formula(const struct ni_leakage_coeffients *coeff,
1804 const u32 fixed_kt, u16 v,
1805 u32 ileakage, u32 *leakage)
1806 {
1807 s64 kt, kv, leakage_w, i_leakage, vddc;
1808
1809 i_leakage = div64_s64(drm_int2fixp(ileakage), 100);
1810 vddc = div64_s64(drm_int2fixp(v), 1000);
1811
1812 kt = div64_s64(drm_int2fixp(fixed_kt), 100000000);
1813 kv = drm_fixp_mul(div64_s64(drm_int2fixp(coeff->av), 100000000),
1814 drm_fixp_exp(drm_fixp_mul(div64_s64(drm_int2fixp(coeff->bv), 100000000), vddc)));
1815
1816 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc);
1817
1818 *leakage = drm_fixp2int(leakage_w * 1000);
1819 }
1820
1821 static void si_calculate_leakage_for_v(struct radeon_device *rdev,
1822 const struct ni_leakage_coeffients *coeff,
1823 const u32 fixed_kt,
1824 u16 v,
1825 u32 i_leakage,
1826 u32 *leakage)
1827 {
1828 si_calculate_leakage_for_v_formula(coeff, fixed_kt, v, i_leakage, leakage);
1829 }
1830
1831
1832 static void si_update_dte_from_pl2(struct radeon_device *rdev,
1833 struct si_dte_data *dte_data)
1834 {
1835 u32 p_limit1 = rdev->pm.dpm.tdp_limit;
1836 u32 p_limit2 = rdev->pm.dpm.near_tdp_limit;
1837 u32 k = dte_data->k;
1838 u32 t_max = dte_data->max_t;
1839 u32 t_split[5] = { 10, 15, 20, 25, 30 };
1840 u32 t_0 = dte_data->t0;
1841 u32 i;
1842
1843 if (p_limit2 != 0 && p_limit2 <= p_limit1) {
1844 dte_data->tdep_count = 3;
1845
1846 for (i = 0; i < k; i++) {
1847 dte_data->r[i] =
1848 (t_split[i] * (t_max - t_0/(u32)1000) * (1 << 14)) /
1849 (p_limit2 * (u32)100);
1850 }
1851
1852 dte_data->tdep_r[1] = dte_data->r[4] * 2;
1853
1854 for (i = 2; i < SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE; i++) {
1855 dte_data->tdep_r[i] = dte_data->r[4];
1856 }
1857 } else {
1858 DRM_ERROR("Invalid PL2! DTE will not be updated.\n");
1859 }
1860 }
1861
1862 static void si_initialize_powertune_defaults(struct radeon_device *rdev)
1863 {
1864 struct ni_power_info *ni_pi = ni_get_pi(rdev);
1865 struct si_power_info *si_pi = si_get_pi(rdev);
1866 bool update_dte_from_pl2 = false;
1867
1868 if (rdev->family == CHIP_TAHITI) {
1869 si_pi->cac_weights = cac_weights_tahiti;
1870 si_pi->lcac_config = lcac_tahiti;
1871 si_pi->cac_override = cac_override_tahiti;
1872 si_pi->powertune_data = &powertune_data_tahiti;
1873 si_pi->dte_data = dte_data_tahiti;
1874
1875 switch (rdev->pdev->device) {
1876 case 0x6798:
1877 si_pi->dte_data.enable_dte_by_default = true;
1878 break;
1879 case 0x6799:
1880 si_pi->dte_data = dte_data_new_zealand;
1881 break;
1882 case 0x6790:
1883 case 0x6791:
1884 case 0x6792:
1885 case 0x679E:
1886 si_pi->dte_data = dte_data_aruba_pro;
1887 update_dte_from_pl2 = true;
1888 break;
1889 case 0x679B:
1890 si_pi->dte_data = dte_data_malta;
1891 update_dte_from_pl2 = true;
1892 break;
1893 case 0x679A:
1894 si_pi->dte_data = dte_data_tahiti_pro;
1895 update_dte_from_pl2 = true;
1896 break;
1897 default:
1898 if (si_pi->dte_data.enable_dte_by_default == true)
1899 DRM_ERROR("DTE is not enabled!\n");
1900 break;
1901 }
1902 } else if (rdev->family == CHIP_PITCAIRN) {
1903 switch (rdev->pdev->device) {
1904 case 0x6810:
1905 case 0x6818:
1906 si_pi->cac_weights = cac_weights_pitcairn;
1907 si_pi->lcac_config = lcac_pitcairn;
1908 si_pi->cac_override = cac_override_pitcairn;
1909 si_pi->powertune_data = &powertune_data_pitcairn;
1910 si_pi->dte_data = dte_data_curacao_xt;
1911 update_dte_from_pl2 = true;
1912 break;
1913 case 0x6819:
1914 case 0x6811:
1915 si_pi->cac_weights = cac_weights_pitcairn;
1916 si_pi->lcac_config = lcac_pitcairn;
1917 si_pi->cac_override = cac_override_pitcairn;
1918 si_pi->powertune_data = &powertune_data_pitcairn;
1919 si_pi->dte_data = dte_data_curacao_pro;
1920 update_dte_from_pl2 = true;
1921 break;
1922 case 0x6800:
1923 case 0x6806:
1924 si_pi->cac_weights = cac_weights_pitcairn;
1925 si_pi->lcac_config = lcac_pitcairn;
1926 si_pi->cac_override = cac_override_pitcairn;
1927 si_pi->powertune_data = &powertune_data_pitcairn;
1928 si_pi->dte_data = dte_data_neptune_xt;
1929 update_dte_from_pl2 = true;
1930 break;
1931 default:
1932 si_pi->cac_weights = cac_weights_pitcairn;
1933 si_pi->lcac_config = lcac_pitcairn;
1934 si_pi->cac_override = cac_override_pitcairn;
1935 si_pi->powertune_data = &powertune_data_pitcairn;
1936 si_pi->dte_data = dte_data_pitcairn;
1937 break;
1938 }
1939 } else if (rdev->family == CHIP_VERDE) {
1940 si_pi->lcac_config = lcac_cape_verde;
1941 si_pi->cac_override = cac_override_cape_verde;
1942 si_pi->powertune_data = &powertune_data_cape_verde;
1943
1944 switch (rdev->pdev->device) {
1945 case 0x683B:
1946 case 0x683F:
1947 case 0x6829:
1948 case 0x6835:
1949 si_pi->cac_weights = cac_weights_cape_verde_pro;
1950 si_pi->dte_data = dte_data_cape_verde;
1951 break;
1952 case 0x6825:
1953 case 0x6827:
1954 si_pi->cac_weights = cac_weights_heathrow;
1955 si_pi->dte_data = dte_data_cape_verde;
1956 break;
1957 case 0x6824:
1958 case 0x682D:
1959 si_pi->cac_weights = cac_weights_chelsea_xt;
1960 si_pi->dte_data = dte_data_cape_verde;
1961 break;
1962 case 0x682F:
1963 si_pi->cac_weights = cac_weights_chelsea_pro;
1964 si_pi->dte_data = dte_data_cape_verde;
1965 break;
1966 case 0x6820:
1967 si_pi->cac_weights = cac_weights_heathrow;
1968 si_pi->dte_data = dte_data_venus_xtx;
1969 break;
1970 case 0x6821:
1971 si_pi->cac_weights = cac_weights_heathrow;
1972 si_pi->dte_data = dte_data_venus_xt;
1973 break;
1974 case 0x6823:
1975 si_pi->cac_weights = cac_weights_chelsea_pro;
1976 si_pi->dte_data = dte_data_venus_pro;
1977 break;
1978 case 0x682B:
1979 si_pi->cac_weights = cac_weights_chelsea_pro;
1980 si_pi->dte_data = dte_data_venus_pro;
1981 break;
1982 default:
1983 si_pi->cac_weights = cac_weights_cape_verde;
1984 si_pi->dte_data = dte_data_cape_verde;
1985 break;
1986 }
1987 } else if (rdev->family == CHIP_OLAND) {
1988 switch (rdev->pdev->device) {
1989 case 0x6601:
1990 case 0x6621:
1991 case 0x6603:
1992 si_pi->cac_weights = cac_weights_mars_pro;
1993 si_pi->lcac_config = lcac_mars_pro;
1994 si_pi->cac_override = cac_override_oland;
1995 si_pi->powertune_data = &powertune_data_mars_pro;
1996 si_pi->dte_data = dte_data_mars_pro;
1997 update_dte_from_pl2 = true;
1998 break;
1999 case 0x6600:
2000 case 0x6606:
2001 case 0x6620:
2002 si_pi->cac_weights = cac_weights_mars_xt;
2003 si_pi->lcac_config = lcac_mars_pro;
2004 si_pi->cac_override = cac_override_oland;
2005 si_pi->powertune_data = &powertune_data_mars_pro;
2006 si_pi->dte_data = dte_data_mars_pro;
2007 update_dte_from_pl2 = true;
2008 break;
2009 case 0x6611:
2010 si_pi->cac_weights = cac_weights_oland_pro;
2011 si_pi->lcac_config = lcac_mars_pro;
2012 si_pi->cac_override = cac_override_oland;
2013 si_pi->powertune_data = &powertune_data_mars_pro;
2014 si_pi->dte_data = dte_data_mars_pro;
2015 update_dte_from_pl2 = true;
2016 break;
2017 case 0x6610:
2018 si_pi->cac_weights = cac_weights_oland_xt;
2019 si_pi->lcac_config = lcac_mars_pro;
2020 si_pi->cac_override = cac_override_oland;
2021 si_pi->powertune_data = &powertune_data_mars_pro;
2022 si_pi->dte_data = dte_data_mars_pro;
2023 update_dte_from_pl2 = true;
2024 break;
2025 default:
2026 si_pi->cac_weights = cac_weights_oland;
2027 si_pi->lcac_config = lcac_oland;
2028 si_pi->cac_override = cac_override_oland;
2029 si_pi->powertune_data = &powertune_data_oland;
2030 si_pi->dte_data = dte_data_oland;
2031 break;
2032 }
2033 } else if (rdev->family == CHIP_HAINAN) {
2034 si_pi->cac_weights = cac_weights_hainan;
2035 si_pi->lcac_config = lcac_oland;
2036 si_pi->cac_override = cac_override_oland;
2037 si_pi->powertune_data = &powertune_data_hainan;
2038 si_pi->dte_data = dte_data_sun_xt;
2039 update_dte_from_pl2 = true;
2040 } else {
2041 DRM_ERROR("Unknown SI asic revision, failed to initialize PowerTune!\n");
2042 return;
2043 }
2044
2045 ni_pi->enable_power_containment = false;
2046 ni_pi->enable_cac = false;
2047 ni_pi->enable_sq_ramping = false;
2048 si_pi->enable_dte = false;
2049
2050 if (si_pi->powertune_data->enable_powertune_by_default) {
2051 ni_pi->enable_power_containment= true;
2052 ni_pi->enable_cac = true;
2053 if (si_pi->dte_data.enable_dte_by_default) {
2054 si_pi->enable_dte = true;
2055 if (update_dte_from_pl2)
2056 si_update_dte_from_pl2(rdev, &si_pi->dte_data);
2057
2058 }
2059 ni_pi->enable_sq_ramping = true;
2060 }
2061
2062 ni_pi->driver_calculate_cac_leakage = true;
2063 ni_pi->cac_configuration_required = true;
2064
2065 if (ni_pi->cac_configuration_required) {
2066 ni_pi->support_cac_long_term_average = true;
2067 si_pi->dyn_powertune_data.l2_lta_window_size =
2068 si_pi->powertune_data->l2_lta_window_size_default;
2069 si_pi->dyn_powertune_data.lts_truncate =
2070 si_pi->powertune_data->lts_truncate_default;
2071 } else {
2072 ni_pi->support_cac_long_term_average = false;
2073 si_pi->dyn_powertune_data.l2_lta_window_size = 0;
2074 si_pi->dyn_powertune_data.lts_truncate = 0;
2075 }
2076
2077 si_pi->dyn_powertune_data.disable_uvd_powertune = false;
2078 }
2079
2080 static u32 si_get_smc_power_scaling_factor(struct radeon_device *rdev)
2081 {
2082 return 1;
2083 }
2084
2085 static u32 si_calculate_cac_wintime(struct radeon_device *rdev)
2086 {
2087 u32 xclk;
2088 u32 wintime;
2089 u32 cac_window;
2090 u32 cac_window_size;
2091
2092 xclk = radeon_get_xclk(rdev);
2093
2094 if (xclk == 0)
2095 return 0;
2096
2097 cac_window = RREG32(CG_CAC_CTRL) & CAC_WINDOW_MASK;
2098 cac_window_size = ((cac_window & 0xFFFF0000) >> 16) * (cac_window & 0x0000FFFF);
2099
2100 wintime = (cac_window_size * 100) / xclk;
2101
2102 return wintime;
2103 }
2104
2105 static u32 si_scale_power_for_smc(u32 power_in_watts, u32 scaling_factor)
2106 {
2107 return power_in_watts;
2108 }
2109
2110 static int si_calculate_adjusted_tdp_limits(struct radeon_device *rdev,
2111 bool adjust_polarity,
2112 u32 tdp_adjustment,
2113 u32 *tdp_limit,
2114 u32 *near_tdp_limit)
2115 {
2116 u32 adjustment_delta, max_tdp_limit;
2117
2118 if (tdp_adjustment > (u32)rdev->pm.dpm.tdp_od_limit)
2119 return -EINVAL;
2120
2121 max_tdp_limit = ((100 + 100) * rdev->pm.dpm.tdp_limit) / 100;
2122
2123 if (adjust_polarity) {
2124 *tdp_limit = ((100 + tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100;
2125 *near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted + (*tdp_limit - rdev->pm.dpm.tdp_limit);
2126 } else {
2127 *tdp_limit = ((100 - tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100;
2128 adjustment_delta = rdev->pm.dpm.tdp_limit - *tdp_limit;
2129 if (adjustment_delta < rdev->pm.dpm.near_tdp_limit_adjusted)
2130 *near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted - adjustment_delta;
2131 else
2132 *near_tdp_limit = 0;
2133 }
2134
2135 if ((*tdp_limit <= 0) || (*tdp_limit > max_tdp_limit))
2136 return -EINVAL;
2137 if ((*near_tdp_limit <= 0) || (*near_tdp_limit > *tdp_limit))
2138 return -EINVAL;
2139
2140 return 0;
2141 }
2142
2143 static int si_populate_smc_tdp_limits(struct radeon_device *rdev,
2144 struct radeon_ps *radeon_state)
2145 {
2146 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2147 struct si_power_info *si_pi = si_get_pi(rdev);
2148
2149 if (ni_pi->enable_power_containment) {
2150 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable;
2151 PP_SIslands_PAPMParameters *papm_parm;
2152 struct radeon_ppm_table *ppm = rdev->pm.dpm.dyn_state.ppm_table;
2153 u32 scaling_factor = si_get_smc_power_scaling_factor(rdev);
2154 u32 tdp_limit;
2155 u32 near_tdp_limit;
2156 int ret;
2157
2158 if (scaling_factor == 0)
2159 return -EINVAL;
2160
2161 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE));
2162
2163 ret = si_calculate_adjusted_tdp_limits(rdev,
2164 false, /* ??? */
2165 rdev->pm.dpm.tdp_adjustment,
2166 &tdp_limit,
2167 &near_tdp_limit);
2168 if (ret)
2169 return ret;
2170
2171 smc_table->dpm2Params.TDPLimit =
2172 cpu_to_be32(si_scale_power_for_smc(tdp_limit, scaling_factor) * 1000);
2173 smc_table->dpm2Params.NearTDPLimit =
2174 cpu_to_be32(si_scale_power_for_smc(near_tdp_limit, scaling_factor) * 1000);
2175 smc_table->dpm2Params.SafePowerLimit =
2176 cpu_to_be32(si_scale_power_for_smc((near_tdp_limit * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000);
2177
2178 ret = si_copy_bytes_to_smc(rdev,
2179 (si_pi->state_table_start + offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) +
2180 offsetof(PP_SIslands_DPM2Parameters, TDPLimit)),
2181 (u8 *)(&(smc_table->dpm2Params.TDPLimit)),
2182 sizeof(u32) * 3,
2183 si_pi->sram_end);
2184 if (ret)
2185 return ret;
2186
2187 if (si_pi->enable_ppm) {
2188 papm_parm = &si_pi->papm_parm;
2189 memset(papm_parm, 0, sizeof(PP_SIslands_PAPMParameters));
2190 papm_parm->NearTDPLimitTherm = cpu_to_be32(ppm->dgpu_tdp);
2191 papm_parm->dGPU_T_Limit = cpu_to_be32(ppm->tj_max);
2192 papm_parm->dGPU_T_Warning = cpu_to_be32(95);
2193 papm_parm->dGPU_T_Hysteresis = cpu_to_be32(5);
2194 papm_parm->PlatformPowerLimit = 0xffffffff;
2195 papm_parm->NearTDPLimitPAPM = 0xffffffff;
2196
2197 ret = si_copy_bytes_to_smc(rdev, si_pi->papm_cfg_table_start,
2198 (u8 *)papm_parm,
2199 sizeof(PP_SIslands_PAPMParameters),
2200 si_pi->sram_end);
2201 if (ret)
2202 return ret;
2203 }
2204 }
2205 return 0;
2206 }
2207
2208 static int si_populate_smc_tdp_limits_2(struct radeon_device *rdev,
2209 struct radeon_ps *radeon_state)
2210 {
2211 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2212 struct si_power_info *si_pi = si_get_pi(rdev);
2213
2214 if (ni_pi->enable_power_containment) {
2215 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable;
2216 u32 scaling_factor = si_get_smc_power_scaling_factor(rdev);
2217 int ret;
2218
2219 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE));
2220
2221 smc_table->dpm2Params.NearTDPLimit =
2222 cpu_to_be32(si_scale_power_for_smc(rdev->pm.dpm.near_tdp_limit_adjusted, scaling_factor) * 1000);
2223 smc_table->dpm2Params.SafePowerLimit =
2224 cpu_to_be32(si_scale_power_for_smc((rdev->pm.dpm.near_tdp_limit_adjusted * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000);
2225
2226 ret = si_copy_bytes_to_smc(rdev,
2227 (si_pi->state_table_start +
2228 offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) +
2229 offsetof(PP_SIslands_DPM2Parameters, NearTDPLimit)),
2230 (u8 *)(&(smc_table->dpm2Params.NearTDPLimit)),
2231 sizeof(u32) * 2,
2232 si_pi->sram_end);
2233 if (ret)
2234 return ret;
2235 }
2236
2237 return 0;
2238 }
2239
2240 static u16 si_calculate_power_efficiency_ratio(struct radeon_device *rdev,
2241 const u16 prev_std_vddc,
2242 const u16 curr_std_vddc)
2243 {
2244 u64 margin = (u64)SISLANDS_DPM2_PWREFFICIENCYRATIO_MARGIN;
2245 u64 prev_vddc = (u64)prev_std_vddc;
2246 u64 curr_vddc = (u64)curr_std_vddc;
2247 u64 pwr_efficiency_ratio, n, d;
2248
2249 if ((prev_vddc == 0) || (curr_vddc == 0))
2250 return 0;
2251
2252 n = div64_u64((u64)1024 * curr_vddc * curr_vddc * ((u64)1000 + margin), (u64)1000);
2253 d = prev_vddc * prev_vddc;
2254 pwr_efficiency_ratio = div64_u64(n, d);
2255
2256 if (pwr_efficiency_ratio > (u64)0xFFFF)
2257 return 0;
2258
2259 return (u16)pwr_efficiency_ratio;
2260 }
2261
2262 static bool si_should_disable_uvd_powertune(struct radeon_device *rdev,
2263 struct radeon_ps *radeon_state)
2264 {
2265 struct si_power_info *si_pi = si_get_pi(rdev);
2266
2267 if (si_pi->dyn_powertune_data.disable_uvd_powertune &&
2268 radeon_state->vclk && radeon_state->dclk)
2269 return true;
2270
2271 return false;
2272 }
2273
2274 static int si_populate_power_containment_values(struct radeon_device *rdev,
2275 struct radeon_ps *radeon_state,
2276 SISLANDS_SMC_SWSTATE *smc_state)
2277 {
2278 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
2279 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2280 struct ni_ps *state = ni_get_ps(radeon_state);
2281 SISLANDS_SMC_VOLTAGE_VALUE vddc;
2282 u32 prev_sclk;
2283 u32 max_sclk;
2284 u32 min_sclk;
2285 u16 prev_std_vddc;
2286 u16 curr_std_vddc;
2287 int i;
2288 u16 pwr_efficiency_ratio;
2289 u8 max_ps_percent;
2290 bool disable_uvd_power_tune;
2291 int ret;
2292
2293 if (ni_pi->enable_power_containment == false)
2294 return 0;
2295
2296 if (state->performance_level_count == 0)
2297 return -EINVAL;
2298
2299 if (smc_state->levelCount != state->performance_level_count)
2300 return -EINVAL;
2301
2302 disable_uvd_power_tune = si_should_disable_uvd_powertune(rdev, radeon_state);
2303
2304 smc_state->levels[0].dpm2.MaxPS = 0;
2305 smc_state->levels[0].dpm2.NearTDPDec = 0;
2306 smc_state->levels[0].dpm2.AboveSafeInc = 0;
2307 smc_state->levels[0].dpm2.BelowSafeInc = 0;
2308 smc_state->levels[0].dpm2.PwrEfficiencyRatio = 0;
2309
2310 for (i = 1; i < state->performance_level_count; i++) {
2311 prev_sclk = state->performance_levels[i-1].sclk;
2312 max_sclk = state->performance_levels[i].sclk;
2313 if (i == 1)
2314 max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_M;
2315 else
2316 max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_H;
2317
2318 if (prev_sclk > max_sclk)
2319 return -EINVAL;
2320
2321 if ((max_ps_percent == 0) ||
2322 (prev_sclk == max_sclk) ||
2323 disable_uvd_power_tune) {
2324 min_sclk = max_sclk;
2325 } else if (i == 1) {
2326 min_sclk = prev_sclk;
2327 } else {
2328 min_sclk = (prev_sclk * (u32)max_ps_percent) / 100;
2329 }
2330
2331 if (min_sclk < state->performance_levels[0].sclk)
2332 min_sclk = state->performance_levels[0].sclk;
2333
2334 if (min_sclk == 0)
2335 return -EINVAL;
2336
2337 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
2338 state->performance_levels[i-1].vddc, &vddc);
2339 if (ret)
2340 return ret;
2341
2342 ret = si_get_std_voltage_value(rdev, &vddc, &prev_std_vddc);
2343 if (ret)
2344 return ret;
2345
2346 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
2347 state->performance_levels[i].vddc, &vddc);
2348 if (ret)
2349 return ret;
2350
2351 ret = si_get_std_voltage_value(rdev, &vddc, &curr_std_vddc);
2352 if (ret)
2353 return ret;
2354
2355 pwr_efficiency_ratio = si_calculate_power_efficiency_ratio(rdev,
2356 prev_std_vddc, curr_std_vddc);
2357
2358 smc_state->levels[i].dpm2.MaxPS = (u8)((SISLANDS_DPM2_MAX_PULSE_SKIP * (max_sclk - min_sclk)) / max_sclk);
2359 smc_state->levels[i].dpm2.NearTDPDec = SISLANDS_DPM2_NEAR_TDP_DEC;
2360 smc_state->levels[i].dpm2.AboveSafeInc = SISLANDS_DPM2_ABOVE_SAFE_INC;
2361 smc_state->levels[i].dpm2.BelowSafeInc = SISLANDS_DPM2_BELOW_SAFE_INC;
2362 smc_state->levels[i].dpm2.PwrEfficiencyRatio = cpu_to_be16(pwr_efficiency_ratio);
2363 }
2364
2365 return 0;
2366 }
2367
2368 static int si_populate_sq_ramping_values(struct radeon_device *rdev,
2369 struct radeon_ps *radeon_state,
2370 SISLANDS_SMC_SWSTATE *smc_state)
2371 {
2372 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2373 struct ni_ps *state = ni_get_ps(radeon_state);
2374 u32 sq_power_throttle, sq_power_throttle2;
2375 bool enable_sq_ramping = ni_pi->enable_sq_ramping;
2376 int i;
2377
2378 if (state->performance_level_count == 0)
2379 return -EINVAL;
2380
2381 if (smc_state->levelCount != state->performance_level_count)
2382 return -EINVAL;
2383
2384 if (rdev->pm.dpm.sq_ramping_threshold == 0)
2385 return -EINVAL;
2386
2387 if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER > (MAX_POWER_MASK >> MAX_POWER_SHIFT))
2388 enable_sq_ramping = false;
2389
2390 if (SISLANDS_DPM2_SQ_RAMP_MIN_POWER > (MIN_POWER_MASK >> MIN_POWER_SHIFT))
2391 enable_sq_ramping = false;
2392
2393 if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA > (MAX_POWER_DELTA_MASK >> MAX_POWER_DELTA_SHIFT))
2394 enable_sq_ramping = false;
2395
2396 if (SISLANDS_DPM2_SQ_RAMP_STI_SIZE > (STI_SIZE_MASK >> STI_SIZE_SHIFT))
2397 enable_sq_ramping = false;
2398
2399 if (NISLANDS_DPM2_SQ_RAMP_LTI_RATIO <= (LTI_RATIO_MASK >> LTI_RATIO_SHIFT))
2400 enable_sq_ramping = false;
2401
2402 for (i = 0; i < state->performance_level_count; i++) {
2403 sq_power_throttle = 0;
2404 sq_power_throttle2 = 0;
2405
2406 if ((state->performance_levels[i].sclk >= rdev->pm.dpm.sq_ramping_threshold) &&
2407 enable_sq_ramping) {
2408 sq_power_throttle |= MAX_POWER(SISLANDS_DPM2_SQ_RAMP_MAX_POWER);
2409 sq_power_throttle |= MIN_POWER(SISLANDS_DPM2_SQ_RAMP_MIN_POWER);
2410 sq_power_throttle2 |= MAX_POWER_DELTA(SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA);
2411 sq_power_throttle2 |= STI_SIZE(SISLANDS_DPM2_SQ_RAMP_STI_SIZE);
2412 sq_power_throttle2 |= LTI_RATIO(SISLANDS_DPM2_SQ_RAMP_LTI_RATIO);
2413 } else {
2414 sq_power_throttle |= MAX_POWER_MASK | MIN_POWER_MASK;
2415 sq_power_throttle2 |= MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
2416 }
2417
2418 smc_state->levels[i].SQPowerThrottle = cpu_to_be32(sq_power_throttle);
2419 smc_state->levels[i].SQPowerThrottle_2 = cpu_to_be32(sq_power_throttle2);
2420 }
2421
2422 return 0;
2423 }
2424
2425 static int si_enable_power_containment(struct radeon_device *rdev,
2426 struct radeon_ps *radeon_new_state,
2427 bool enable)
2428 {
2429 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2430 PPSMC_Result smc_result;
2431 int ret = 0;
2432
2433 if (ni_pi->enable_power_containment) {
2434 if (enable) {
2435 if (!si_should_disable_uvd_powertune(rdev, radeon_new_state)) {
2436 smc_result = si_send_msg_to_smc(rdev, PPSMC_TDPClampingActive);
2437 if (smc_result != PPSMC_Result_OK) {
2438 ret = -EINVAL;
2439 ni_pi->pc_enabled = false;
2440 } else {
2441 ni_pi->pc_enabled = true;
2442 }
2443 }
2444 } else {
2445 smc_result = si_send_msg_to_smc(rdev, PPSMC_TDPClampingInactive);
2446 if (smc_result != PPSMC_Result_OK)
2447 ret = -EINVAL;
2448 ni_pi->pc_enabled = false;
2449 }
2450 }
2451
2452 return ret;
2453 }
2454
2455 static int si_initialize_smc_dte_tables(struct radeon_device *rdev)
2456 {
2457 struct si_power_info *si_pi = si_get_pi(rdev);
2458 int ret = 0;
2459 struct si_dte_data *dte_data = &si_pi->dte_data;
2460 Smc_SIslands_DTE_Configuration *dte_tables = NULL;
2461 u32 table_size;
2462 u8 tdep_count;
2463 u32 i;
2464
2465 if (dte_data == NULL)
2466 si_pi->enable_dte = false;
2467
2468 if (si_pi->enable_dte == false)
2469 return 0;
2470
2471 if (dte_data->k <= 0)
2472 return -EINVAL;
2473
2474 dte_tables = kzalloc(sizeof(Smc_SIslands_DTE_Configuration), GFP_KERNEL);
2475 if (dte_tables == NULL) {
2476 si_pi->enable_dte = false;
2477 return -ENOMEM;
2478 }
2479
2480 table_size = dte_data->k;
2481
2482 if (table_size > SMC_SISLANDS_DTE_MAX_FILTER_STAGES)
2483 table_size = SMC_SISLANDS_DTE_MAX_FILTER_STAGES;
2484
2485 tdep_count = dte_data->tdep_count;
2486 if (tdep_count > SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE)
2487 tdep_count = SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE;
2488
2489 dte_tables->K = cpu_to_be32(table_size);
2490 dte_tables->T0 = cpu_to_be32(dte_data->t0);
2491 dte_tables->MaxT = cpu_to_be32(dte_data->max_t);
2492 dte_tables->WindowSize = dte_data->window_size;
2493 dte_tables->temp_select = dte_data->temp_select;
2494 dte_tables->DTE_mode = dte_data->dte_mode;
2495 dte_tables->Tthreshold = cpu_to_be32(dte_data->t_threshold);
2496
2497 if (tdep_count > 0)
2498 table_size--;
2499
2500 for (i = 0; i < table_size; i++) {
2501 dte_tables->tau[i] = cpu_to_be32(dte_data->tau[i]);
2502 dte_tables->R[i] = cpu_to_be32(dte_data->r[i]);
2503 }
2504
2505 dte_tables->Tdep_count = tdep_count;
2506
2507 for (i = 0; i < (u32)tdep_count; i++) {
2508 dte_tables->T_limits[i] = dte_data->t_limits[i];
2509 dte_tables->Tdep_tau[i] = cpu_to_be32(dte_data->tdep_tau[i]);
2510 dte_tables->Tdep_R[i] = cpu_to_be32(dte_data->tdep_r[i]);
2511 }
2512
2513 ret = si_copy_bytes_to_smc(rdev, si_pi->dte_table_start, (u8 *)dte_tables,
2514 sizeof(Smc_SIslands_DTE_Configuration), si_pi->sram_end);
2515 kfree(dte_tables);
2516
2517 return ret;
2518 }
2519
2520 static int si_get_cac_std_voltage_max_min(struct radeon_device *rdev,
2521 u16 *max, u16 *min)
2522 {
2523 struct si_power_info *si_pi = si_get_pi(rdev);
2524 struct radeon_cac_leakage_table *table =
2525 &rdev->pm.dpm.dyn_state.cac_leakage_table;
2526 u32 i;
2527 u32 v0_loadline;
2528
2529
2530 if (table == NULL)
2531 return -EINVAL;
2532
2533 *max = 0;
2534 *min = 0xFFFF;
2535
2536 for (i = 0; i < table->count; i++) {
2537 if (table->entries[i].vddc > *max)
2538 *max = table->entries[i].vddc;
2539 if (table->entries[i].vddc < *min)
2540 *min = table->entries[i].vddc;
2541 }
2542
2543 if (si_pi->powertune_data->lkge_lut_v0_percent > 100)
2544 return -EINVAL;
2545
2546 v0_loadline = (*min) * (100 - si_pi->powertune_data->lkge_lut_v0_percent) / 100;
2547
2548 if (v0_loadline > 0xFFFFUL)
2549 return -EINVAL;
2550
2551 *min = (u16)v0_loadline;
2552
2553 if ((*min > *max) || (*max == 0) || (*min == 0))
2554 return -EINVAL;
2555
2556 return 0;
2557 }
2558
2559 static u16 si_get_cac_std_voltage_step(u16 max, u16 min)
2560 {
2561 return ((max - min) + (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1)) /
2562 SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES;
2563 }
2564
2565 static int si_init_dte_leakage_table(struct radeon_device *rdev,
2566 PP_SIslands_CacConfig *cac_tables,
2567 u16 vddc_max, u16 vddc_min, u16 vddc_step,
2568 u16 t0, u16 t_step)
2569 {
2570 struct si_power_info *si_pi = si_get_pi(rdev);
2571 u32 leakage;
2572 unsigned int i, j;
2573 s32 t;
2574 u32 smc_leakage;
2575 u32 scaling_factor;
2576 u16 voltage;
2577
2578 scaling_factor = si_get_smc_power_scaling_factor(rdev);
2579
2580 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++) {
2581 t = (1000 * (i * t_step + t0));
2582
2583 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) {
2584 voltage = vddc_max - (vddc_step * j);
2585
2586 si_calculate_leakage_for_v_and_t(rdev,
2587 &si_pi->powertune_data->leakage_coefficients,
2588 voltage,
2589 t,
2590 si_pi->dyn_powertune_data.cac_leakage,
2591 &leakage);
2592
2593 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4;
2594
2595 if (smc_leakage > 0xFFFF)
2596 smc_leakage = 0xFFFF;
2597
2598 cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] =
2599 cpu_to_be16((u16)smc_leakage);
2600 }
2601 }
2602 return 0;
2603 }
2604
2605 static int si_init_simplified_leakage_table(struct radeon_device *rdev,
2606 PP_SIslands_CacConfig *cac_tables,
2607 u16 vddc_max, u16 vddc_min, u16 vddc_step)
2608 {
2609 struct si_power_info *si_pi = si_get_pi(rdev);
2610 u32 leakage;
2611 unsigned int i, j;
2612 u32 smc_leakage;
2613 u32 scaling_factor;
2614 u16 voltage;
2615
2616 scaling_factor = si_get_smc_power_scaling_factor(rdev);
2617
2618 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) {
2619 voltage = vddc_max - (vddc_step * j);
2620
2621 si_calculate_leakage_for_v(rdev,
2622 &si_pi->powertune_data->leakage_coefficients,
2623 si_pi->powertune_data->fixed_kt,
2624 voltage,
2625 si_pi->dyn_powertune_data.cac_leakage,
2626 &leakage);
2627
2628 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4;
2629
2630 if (smc_leakage > 0xFFFF)
2631 smc_leakage = 0xFFFF;
2632
2633 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++)
2634 cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] =
2635 cpu_to_be16((u16)smc_leakage);
2636 }
2637 return 0;
2638 }
2639
2640 static int si_initialize_smc_cac_tables(struct radeon_device *rdev)
2641 {
2642 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2643 struct si_power_info *si_pi = si_get_pi(rdev);
2644 PP_SIslands_CacConfig *cac_tables = NULL;
2645 u16 vddc_max, vddc_min, vddc_step;
2646 u16 t0, t_step;
2647 u32 load_line_slope, reg;
2648 int ret = 0;
2649 u32 ticks_per_us = radeon_get_xclk(rdev) / 100;
2650
2651 if (ni_pi->enable_cac == false)
2652 return 0;
2653
2654 cac_tables = kzalloc(sizeof(PP_SIslands_CacConfig), GFP_KERNEL);
2655 if (!cac_tables)
2656 return -ENOMEM;
2657
2658 reg = RREG32(CG_CAC_CTRL) & ~CAC_WINDOW_MASK;
2659 reg |= CAC_WINDOW(si_pi->powertune_data->cac_window);
2660 WREG32(CG_CAC_CTRL, reg);
2661
2662 si_pi->dyn_powertune_data.cac_leakage = rdev->pm.dpm.cac_leakage;
2663 si_pi->dyn_powertune_data.dc_pwr_value =
2664 si_pi->powertune_data->dc_cac[NISLANDS_DCCAC_LEVEL_0];
2665 si_pi->dyn_powertune_data.wintime = si_calculate_cac_wintime(rdev);
2666 si_pi->dyn_powertune_data.shift_n = si_pi->powertune_data->shift_n_default;
2667
2668 si_pi->dyn_powertune_data.leakage_minimum_temperature = 80 * 1000;
2669
2670 ret = si_get_cac_std_voltage_max_min(rdev, &vddc_max, &vddc_min);
2671 if (ret)
2672 goto done_free;
2673
2674 vddc_step = si_get_cac_std_voltage_step(vddc_max, vddc_min);
2675 vddc_min = vddc_max - (vddc_step * (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1));
2676 t_step = 4;
2677 t0 = 60;
2678
2679 if (si_pi->enable_dte || ni_pi->driver_calculate_cac_leakage)
2680 ret = si_init_dte_leakage_table(rdev, cac_tables,
2681 vddc_max, vddc_min, vddc_step,
2682 t0, t_step);
2683 else
2684 ret = si_init_simplified_leakage_table(rdev, cac_tables,
2685 vddc_max, vddc_min, vddc_step);
2686 if (ret)
2687 goto done_free;
2688
2689 load_line_slope = ((u32)rdev->pm.dpm.load_line_slope << SMC_SISLANDS_SCALE_R) / 100;
2690
2691 cac_tables->l2numWin_TDP = cpu_to_be32(si_pi->dyn_powertune_data.l2_lta_window_size);
2692 cac_tables->lts_truncate_n = si_pi->dyn_powertune_data.lts_truncate;
2693 cac_tables->SHIFT_N = si_pi->dyn_powertune_data.shift_n;
2694 cac_tables->lkge_lut_V0 = cpu_to_be32((u32)vddc_min);
2695 cac_tables->lkge_lut_Vstep = cpu_to_be32((u32)vddc_step);
2696 cac_tables->R_LL = cpu_to_be32(load_line_slope);
2697 cac_tables->WinTime = cpu_to_be32(si_pi->dyn_powertune_data.wintime);
2698 cac_tables->calculation_repeats = cpu_to_be32(2);
2699 cac_tables->dc_cac = cpu_to_be32(0);
2700 cac_tables->log2_PG_LKG_SCALE = 12;
2701 cac_tables->cac_temp = si_pi->powertune_data->operating_temp;
2702 cac_tables->lkge_lut_T0 = cpu_to_be32((u32)t0);
2703 cac_tables->lkge_lut_Tstep = cpu_to_be32((u32)t_step);
2704
2705 ret = si_copy_bytes_to_smc(rdev, si_pi->cac_table_start, (u8 *)cac_tables,
2706 sizeof(PP_SIslands_CacConfig), si_pi->sram_end);
2707
2708 if (ret)
2709 goto done_free;
2710
2711 ret = si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_ticks_per_us, ticks_per_us);
2712
2713 done_free:
2714 if (ret) {
2715 ni_pi->enable_cac = false;
2716 ni_pi->enable_power_containment = false;
2717 }
2718
2719 kfree(cac_tables);
2720
2721 return 0;
2722 }
2723
2724 static int si_program_cac_config_registers(struct radeon_device *rdev,
2725 const struct si_cac_config_reg *cac_config_regs)
2726 {
2727 const struct si_cac_config_reg *config_regs = cac_config_regs;
2728 u32 data = 0, offset;
2729
2730 if (!config_regs)
2731 return -EINVAL;
2732
2733 while (config_regs->offset != 0xFFFFFFFF) {
2734 switch (config_regs->type) {
2735 case SISLANDS_CACCONFIG_CGIND:
2736 offset = SMC_CG_IND_START + config_regs->offset;
2737 if (offset < SMC_CG_IND_END)
2738 data = RREG32_SMC(offset);
2739 break;
2740 default:
2741 data = RREG32(config_regs->offset << 2);
2742 break;
2743 }
2744
2745 data &= ~config_regs->mask;
2746 data |= ((config_regs->value << config_regs->shift) & config_regs->mask);
2747
2748 switch (config_regs->type) {
2749 case SISLANDS_CACCONFIG_CGIND:
2750 offset = SMC_CG_IND_START + config_regs->offset;
2751 if (offset < SMC_CG_IND_END)
2752 WREG32_SMC(offset, data);
2753 break;
2754 default:
2755 WREG32(config_regs->offset << 2, data);
2756 break;
2757 }
2758 config_regs++;
2759 }
2760 return 0;
2761 }
2762
2763 static int si_initialize_hardware_cac_manager(struct radeon_device *rdev)
2764 {
2765 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2766 struct si_power_info *si_pi = si_get_pi(rdev);
2767 int ret;
2768
2769 if ((ni_pi->enable_cac == false) ||
2770 (ni_pi->cac_configuration_required == false))
2771 return 0;
2772
2773 ret = si_program_cac_config_registers(rdev, si_pi->lcac_config);
2774 if (ret)
2775 return ret;
2776 ret = si_program_cac_config_registers(rdev, si_pi->cac_override);
2777 if (ret)
2778 return ret;
2779 ret = si_program_cac_config_registers(rdev, si_pi->cac_weights);
2780 if (ret)
2781 return ret;
2782
2783 return 0;
2784 }
2785
2786 static int si_enable_smc_cac(struct radeon_device *rdev,
2787 struct radeon_ps *radeon_new_state,
2788 bool enable)
2789 {
2790 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2791 struct si_power_info *si_pi = si_get_pi(rdev);
2792 PPSMC_Result smc_result;
2793 int ret = 0;
2794
2795 if (ni_pi->enable_cac) {
2796 if (enable) {
2797 if (!si_should_disable_uvd_powertune(rdev, radeon_new_state)) {
2798 if (ni_pi->support_cac_long_term_average) {
2799 smc_result = si_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgEnable);
2800 if (smc_result != PPSMC_Result_OK)
2801 ni_pi->support_cac_long_term_average = false;
2802 }
2803
2804 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableCac);
2805 if (smc_result != PPSMC_Result_OK) {
2806 ret = -EINVAL;
2807 ni_pi->cac_enabled = false;
2808 } else {
2809 ni_pi->cac_enabled = true;
2810 }
2811
2812 if (si_pi->enable_dte) {
2813 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableDTE);
2814 if (smc_result != PPSMC_Result_OK)
2815 ret = -EINVAL;
2816 }
2817 }
2818 } else if (ni_pi->cac_enabled) {
2819 if (si_pi->enable_dte)
2820 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_DisableDTE);
2821
2822 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_DisableCac);
2823
2824 ni_pi->cac_enabled = false;
2825
2826 if (ni_pi->support_cac_long_term_average)
2827 smc_result = si_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgDisable);
2828 }
2829 }
2830 return ret;
2831 }
2832
2833 static int si_init_smc_spll_table(struct radeon_device *rdev)
2834 {
2835 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2836 struct si_power_info *si_pi = si_get_pi(rdev);
2837 SMC_SISLANDS_SPLL_DIV_TABLE *spll_table;
2838 SISLANDS_SMC_SCLK_VALUE sclk_params;
2839 u32 fb_div, p_div;
2840 u32 clk_s, clk_v;
2841 u32 sclk = 0;
2842 int ret = 0;
2843 u32 tmp;
2844 int i;
2845
2846 if (si_pi->spll_table_start == 0)
2847 return -EINVAL;
2848
2849 spll_table = kzalloc(sizeof(SMC_SISLANDS_SPLL_DIV_TABLE), GFP_KERNEL);
2850 if (spll_table == NULL)
2851 return -ENOMEM;
2852
2853 for (i = 0; i < 256; i++) {
2854 ret = si_calculate_sclk_params(rdev, sclk, &sclk_params);
2855 if (ret)
2856 break;
2857
2858 p_div = (sclk_params.vCG_SPLL_FUNC_CNTL & SPLL_PDIV_A_MASK) >> SPLL_PDIV_A_SHIFT;
2859 fb_div = (sclk_params.vCG_SPLL_FUNC_CNTL_3 & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT;
2860 clk_s = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM & CLK_S_MASK) >> CLK_S_SHIFT;
2861 clk_v = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM_2 & CLK_V_MASK) >> CLK_V_SHIFT;
2862
2863 fb_div &= ~0x00001FFF;
2864 fb_div >>= 1;
2865 clk_v >>= 6;
2866
2867 if (p_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT))
2868 ret = -EINVAL;
2869 if (fb_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT))
2870 ret = -EINVAL;
2871 if (clk_s & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT))
2872 ret = -EINVAL;
2873 if (clk_v & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT))
2874 ret = -EINVAL;
2875
2876 if (ret)
2877 break;
2878
2879 tmp = ((fb_div << SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK) |
2880 ((p_div << SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK);
2881 spll_table->freq[i] = cpu_to_be32(tmp);
2882
2883 tmp = ((clk_v << SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK) |
2884 ((clk_s << SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK);
2885 spll_table->ss[i] = cpu_to_be32(tmp);
2886
2887 sclk += 512;
2888 }
2889
2890
2891 if (!ret)
2892 ret = si_copy_bytes_to_smc(rdev, si_pi->spll_table_start,
2893 (u8 *)spll_table, sizeof(SMC_SISLANDS_SPLL_DIV_TABLE),
2894 si_pi->sram_end);
2895
2896 if (ret)
2897 ni_pi->enable_power_containment = false;
2898
2899 kfree(spll_table);
2900
2901 return ret;
2902 }
2903
2904 static void si_apply_state_adjust_rules(struct radeon_device *rdev,
2905 struct radeon_ps *rps)
2906 {
2907 struct ni_ps *ps = ni_get_ps(rps);
2908 struct radeon_clock_and_voltage_limits *max_limits;
2909 bool disable_mclk_switching = false;
2910 bool disable_sclk_switching = false;
2911 u32 mclk, sclk;
2912 u16 vddc, vddci;
2913 u32 max_sclk_vddc, max_mclk_vddci, max_mclk_vddc;
2914 int i;
2915
2916 if ((rdev->pm.dpm.new_active_crtc_count > 1) ||
2917 ni_dpm_vblank_too_short(rdev))
2918 disable_mclk_switching = true;
2919
2920 if (rps->vclk || rps->dclk) {
2921 disable_mclk_switching = true;
2922 disable_sclk_switching = true;
2923 }
2924
2925 if (rdev->pm.dpm.ac_power)
2926 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
2927 else
2928 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
2929
2930 for (i = ps->performance_level_count - 2; i >= 0; i--) {
2931 if (ps->performance_levels[i].vddc > ps->performance_levels[i+1].vddc)
2932 ps->performance_levels[i].vddc = ps->performance_levels[i+1].vddc;
2933 }
2934 if (rdev->pm.dpm.ac_power == false) {
2935 for (i = 0; i < ps->performance_level_count; i++) {
2936 if (ps->performance_levels[i].mclk > max_limits->mclk)
2937 ps->performance_levels[i].mclk = max_limits->mclk;
2938 if (ps->performance_levels[i].sclk > max_limits->sclk)
2939 ps->performance_levels[i].sclk = max_limits->sclk;
2940 if (ps->performance_levels[i].vddc > max_limits->vddc)
2941 ps->performance_levels[i].vddc = max_limits->vddc;
2942 if (ps->performance_levels[i].vddci > max_limits->vddci)
2943 ps->performance_levels[i].vddci = max_limits->vddci;
2944 }
2945 }
2946
2947 /* limit clocks to max supported clocks based on voltage dependency tables */
2948 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
2949 &max_sclk_vddc);
2950 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
2951 &max_mclk_vddci);
2952 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
2953 &max_mclk_vddc);
2954
2955 for (i = 0; i < ps->performance_level_count; i++) {
2956 if (max_sclk_vddc) {
2957 if (ps->performance_levels[i].sclk > max_sclk_vddc)
2958 ps->performance_levels[i].sclk = max_sclk_vddc;
2959 }
2960 if (max_mclk_vddci) {
2961 if (ps->performance_levels[i].mclk > max_mclk_vddci)
2962 ps->performance_levels[i].mclk = max_mclk_vddci;
2963 }
2964 if (max_mclk_vddc) {
2965 if (ps->performance_levels[i].mclk > max_mclk_vddc)
2966 ps->performance_levels[i].mclk = max_mclk_vddc;
2967 }
2968 }
2969
2970 /* XXX validate the min clocks required for display */
2971
2972 if (disable_mclk_switching) {
2973 mclk = ps->performance_levels[ps->performance_level_count - 1].mclk;
2974 vddci = ps->performance_levels[ps->performance_level_count - 1].vddci;
2975 } else {
2976 mclk = ps->performance_levels[0].mclk;
2977 vddci = ps->performance_levels[0].vddci;
2978 }
2979
2980 if (disable_sclk_switching) {
2981 sclk = ps->performance_levels[ps->performance_level_count - 1].sclk;
2982 vddc = ps->performance_levels[ps->performance_level_count - 1].vddc;
2983 } else {
2984 sclk = ps->performance_levels[0].sclk;
2985 vddc = ps->performance_levels[0].vddc;
2986 }
2987
2988 /* adjusted low state */
2989 ps->performance_levels[0].sclk = sclk;
2990 ps->performance_levels[0].mclk = mclk;
2991 ps->performance_levels[0].vddc = vddc;
2992 ps->performance_levels[0].vddci = vddci;
2993
2994 if (disable_sclk_switching) {
2995 sclk = ps->performance_levels[0].sclk;
2996 for (i = 1; i < ps->performance_level_count; i++) {
2997 if (sclk < ps->performance_levels[i].sclk)
2998 sclk = ps->performance_levels[i].sclk;
2999 }
3000 for (i = 0; i < ps->performance_level_count; i++) {
3001 ps->performance_levels[i].sclk = sclk;
3002 ps->performance_levels[i].vddc = vddc;
3003 }
3004 } else {
3005 for (i = 1; i < ps->performance_level_count; i++) {
3006 if (ps->performance_levels[i].sclk < ps->performance_levels[i - 1].sclk)
3007 ps->performance_levels[i].sclk = ps->performance_levels[i - 1].sclk;
3008 if (ps->performance_levels[i].vddc < ps->performance_levels[i - 1].vddc)
3009 ps->performance_levels[i].vddc = ps->performance_levels[i - 1].vddc;
3010 }
3011 }
3012
3013 if (disable_mclk_switching) {
3014 mclk = ps->performance_levels[0].mclk;
3015 for (i = 1; i < ps->performance_level_count; i++) {
3016 if (mclk < ps->performance_levels[i].mclk)
3017 mclk = ps->performance_levels[i].mclk;
3018 }
3019 for (i = 0; i < ps->performance_level_count; i++) {
3020 ps->performance_levels[i].mclk = mclk;
3021 ps->performance_levels[i].vddci = vddci;
3022 }
3023 } else {
3024 for (i = 1; i < ps->performance_level_count; i++) {
3025 if (ps->performance_levels[i].mclk < ps->performance_levels[i - 1].mclk)
3026 ps->performance_levels[i].mclk = ps->performance_levels[i - 1].mclk;
3027 if (ps->performance_levels[i].vddci < ps->performance_levels[i - 1].vddci)
3028 ps->performance_levels[i].vddci = ps->performance_levels[i - 1].vddci;
3029 }
3030 }
3031
3032 for (i = 0; i < ps->performance_level_count; i++)
3033 btc_adjust_clock_combinations(rdev, max_limits,
3034 &ps->performance_levels[i]);
3035
3036 for (i = 0; i < ps->performance_level_count; i++) {
3037 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
3038 ps->performance_levels[i].sclk,
3039 max_limits->vddc, &ps->performance_levels[i].vddc);
3040 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
3041 ps->performance_levels[i].mclk,
3042 max_limits->vddci, &ps->performance_levels[i].vddci);
3043 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
3044 ps->performance_levels[i].mclk,
3045 max_limits->vddc, &ps->performance_levels[i].vddc);
3046 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk,
3047 rdev->clock.current_dispclk,
3048 max_limits->vddc, &ps->performance_levels[i].vddc);
3049 }
3050
3051 for (i = 0; i < ps->performance_level_count; i++) {
3052 btc_apply_voltage_delta_rules(rdev,
3053 max_limits->vddc, max_limits->vddci,
3054 &ps->performance_levels[i].vddc,
3055 &ps->performance_levels[i].vddci);
3056 }
3057
3058 ps->dc_compatible = true;
3059 for (i = 0; i < ps->performance_level_count; i++) {
3060 if (ps->performance_levels[i].vddc > rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc)
3061 ps->dc_compatible = false;
3062 }
3063
3064 }
3065
3066 #if 0
3067 static int si_read_smc_soft_register(struct radeon_device *rdev,
3068 u16 reg_offset, u32 *value)
3069 {
3070 struct si_power_info *si_pi = si_get_pi(rdev);
3071
3072 return si_read_smc_sram_dword(rdev,
3073 si_pi->soft_regs_start + reg_offset, value,
3074 si_pi->sram_end);
3075 }
3076 #endif
3077
3078 static int si_write_smc_soft_register(struct radeon_device *rdev,
3079 u16 reg_offset, u32 value)
3080 {
3081 struct si_power_info *si_pi = si_get_pi(rdev);
3082
3083 return si_write_smc_sram_dword(rdev,
3084 si_pi->soft_regs_start + reg_offset,
3085 value, si_pi->sram_end);
3086 }
3087
3088 static bool si_is_special_1gb_platform(struct radeon_device *rdev)
3089 {
3090 bool ret = false;
3091 u32 tmp, width, row, column, bank, density;
3092 bool is_memory_gddr5, is_special;
3093
3094 tmp = RREG32(MC_SEQ_MISC0);
3095 is_memory_gddr5 = (MC_SEQ_MISC0_GDDR5_VALUE == ((tmp & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT));
3096 is_special = (MC_SEQ_MISC0_REV_ID_VALUE == ((tmp & MC_SEQ_MISC0_REV_ID_MASK) >> MC_SEQ_MISC0_REV_ID_SHIFT))
3097 & (MC_SEQ_MISC0_VEN_ID_VALUE == ((tmp & MC_SEQ_MISC0_VEN_ID_MASK) >> MC_SEQ_MISC0_VEN_ID_SHIFT));
3098
3099 WREG32(MC_SEQ_IO_DEBUG_INDEX, 0xb);
3100 width = ((RREG32(MC_SEQ_IO_DEBUG_DATA) >> 1) & 1) ? 16 : 32;
3101
3102 tmp = RREG32(MC_ARB_RAMCFG);
3103 row = ((tmp & NOOFROWS_MASK) >> NOOFROWS_SHIFT) + 10;
3104 column = ((tmp & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT) + 8;
3105 bank = ((tmp & NOOFBANK_MASK) >> NOOFBANK_SHIFT) + 2;
3106
3107 density = (1 << (row + column - 20 + bank)) * width;
3108
3109 if ((rdev->pdev->device == 0x6819) &&
3110 is_memory_gddr5 && is_special && (density == 0x400))
3111 ret = true;
3112
3113 return ret;
3114 }
3115
3116 static void si_get_leakage_vddc(struct radeon_device *rdev)
3117 {
3118 struct si_power_info *si_pi = si_get_pi(rdev);
3119 u16 vddc, count = 0;
3120 int i, ret;
3121
3122 for (i = 0; i < SISLANDS_MAX_LEAKAGE_COUNT; i++) {
3123 ret = radeon_atom_get_leakage_vddc_based_on_leakage_idx(rdev, &vddc, SISLANDS_LEAKAGE_INDEX0 + i);
3124
3125 if (!ret && (vddc > 0) && (vddc != (SISLANDS_LEAKAGE_INDEX0 + i))) {
3126 si_pi->leakage_voltage.entries[count].voltage = vddc;
3127 si_pi->leakage_voltage.entries[count].leakage_index =
3128 SISLANDS_LEAKAGE_INDEX0 + i;
3129 count++;
3130 }
3131 }
3132 si_pi->leakage_voltage.count = count;
3133 }
3134
3135 static int si_get_leakage_voltage_from_leakage_index(struct radeon_device *rdev,
3136 u32 index, u16 *leakage_voltage)
3137 {
3138 struct si_power_info *si_pi = si_get_pi(rdev);
3139 int i;
3140
3141 if (leakage_voltage == NULL)
3142 return -EINVAL;
3143
3144 if ((index & 0xff00) != 0xff00)
3145 return -EINVAL;
3146
3147 if ((index & 0xff) > SISLANDS_MAX_LEAKAGE_COUNT + 1)
3148 return -EINVAL;
3149
3150 if (index < SISLANDS_LEAKAGE_INDEX0)
3151 return -EINVAL;
3152
3153 for (i = 0; i < si_pi->leakage_voltage.count; i++) {
3154 if (si_pi->leakage_voltage.entries[i].leakage_index == index) {
3155 *leakage_voltage = si_pi->leakage_voltage.entries[i].voltage;
3156 return 0;
3157 }
3158 }
3159 return -EAGAIN;
3160 }
3161
3162 static void si_set_dpm_event_sources(struct radeon_device *rdev, u32 sources)
3163 {
3164 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3165 bool want_thermal_protection;
3166 enum radeon_dpm_event_src dpm_event_src;
3167
3168 switch (sources) {
3169 case 0:
3170 default:
3171 want_thermal_protection = false;
3172 break;
3173 case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL):
3174 want_thermal_protection = true;
3175 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGITAL;
3176 break;
3177 case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL):
3178 want_thermal_protection = true;
3179 dpm_event_src = RADEON_DPM_EVENT_SRC_EXTERNAL;
3180 break;
3181 case ((1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL) |
3182 (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL)):
3183 want_thermal_protection = true;
3184 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL;
3185 break;
3186 }
3187
3188 if (want_thermal_protection) {
3189 WREG32_P(CG_THERMAL_CTRL, DPM_EVENT_SRC(dpm_event_src), ~DPM_EVENT_SRC_MASK);
3190 if (pi->thermal_protection)
3191 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS);
3192 } else {
3193 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS);
3194 }
3195 }
3196
3197 static void si_enable_auto_throttle_source(struct radeon_device *rdev,
3198 enum radeon_dpm_auto_throttle_src source,
3199 bool enable)
3200 {
3201 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3202
3203 if (enable) {
3204 if (!(pi->active_auto_throttle_sources & (1 << source))) {
3205 pi->active_auto_throttle_sources |= 1 << source;
3206 si_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);
3207 }
3208 } else {
3209 if (pi->active_auto_throttle_sources & (1 << source)) {
3210 pi->active_auto_throttle_sources &= ~(1 << source);
3211 si_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);
3212 }
3213 }
3214 }
3215
3216 static void si_start_dpm(struct radeon_device *rdev)
3217 {
3218 WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN);
3219 }
3220
3221 static void si_stop_dpm(struct radeon_device *rdev)
3222 {
3223 WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN);
3224 }
3225
3226 static void si_enable_sclk_control(struct radeon_device *rdev, bool enable)
3227 {
3228 if (enable)
3229 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF);
3230 else
3231 WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF);
3232
3233 }
3234
3235 #if 0
3236 static int si_notify_hardware_of_thermal_state(struct radeon_device *rdev,
3237 u32 thermal_level)
3238 {
3239 PPSMC_Result ret;
3240
3241 if (thermal_level == 0) {
3242 ret = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt);
3243 if (ret == PPSMC_Result_OK)
3244 return 0;
3245 else
3246 return -EINVAL;
3247 }
3248 return 0;
3249 }
3250
3251 static void si_notify_hardware_vpu_recovery_event(struct radeon_device *rdev)
3252 {
3253 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_tdr_is_about_to_happen, true);
3254 }
3255 #endif
3256
3257 #if 0
3258 static int si_notify_hw_of_powersource(struct radeon_device *rdev, bool ac_power)
3259 {
3260 if (ac_power)
3261 return (si_send_msg_to_smc(rdev, PPSMC_MSG_RunningOnAC) == PPSMC_Result_OK) ?
3262 0 : -EINVAL;
3263
3264 return 0;
3265 }
3266 #endif
3267
3268 static PPSMC_Result si_send_msg_to_smc_with_parameter(struct radeon_device *rdev,
3269 PPSMC_Msg msg, u32 parameter)
3270 {
3271 WREG32(SMC_SCRATCH0, parameter);
3272 return si_send_msg_to_smc(rdev, msg);
3273 }
3274
3275 static int si_restrict_performance_levels_before_switch(struct radeon_device *rdev)
3276 {
3277 if (si_send_msg_to_smc(rdev, PPSMC_MSG_NoForcedLevel) != PPSMC_Result_OK)
3278 return -EINVAL;
3279
3280 return (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) == PPSMC_Result_OK) ?
3281 0 : -EINVAL;
3282 }
3283
3284 int si_dpm_force_performance_level(struct radeon_device *rdev,
3285 enum radeon_dpm_forced_level level)
3286 {
3287 struct radeon_ps *rps = rdev->pm.dpm.current_ps;
3288 struct ni_ps *ps = ni_get_ps(rps);
3289 u32 levels = ps->performance_level_count;
3290
3291 if (level == RADEON_DPM_FORCED_LEVEL_HIGH) {
3292 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK)
3293 return -EINVAL;
3294
3295 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 1) != PPSMC_Result_OK)
3296 return -EINVAL;
3297 } else if (level == RADEON_DPM_FORCED_LEVEL_LOW) {
3298 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK)
3299 return -EINVAL;
3300
3301 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) != PPSMC_Result_OK)
3302 return -EINVAL;
3303 } else if (level == RADEON_DPM_FORCED_LEVEL_AUTO) {
3304 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK)
3305 return -EINVAL;
3306
3307 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK)
3308 return -EINVAL;
3309 }
3310
3311 rdev->pm.dpm.forced_level = level;
3312
3313 return 0;
3314 }
3315
3316 static int si_set_boot_state(struct radeon_device *rdev)
3317 {
3318 return (si_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToInitialState) == PPSMC_Result_OK) ?
3319 0 : -EINVAL;
3320 }
3321
3322 static int si_set_sw_state(struct radeon_device *rdev)
3323 {
3324 return (si_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToSwState) == PPSMC_Result_OK) ?
3325 0 : -EINVAL;
3326 }
3327
3328 static int si_halt_smc(struct radeon_device *rdev)
3329 {
3330 if (si_send_msg_to_smc(rdev, PPSMC_MSG_Halt) != PPSMC_Result_OK)
3331 return -EINVAL;
3332
3333 return (si_wait_for_smc_inactive(rdev) == PPSMC_Result_OK) ?
3334 0 : -EINVAL;
3335 }
3336
3337 static int si_resume_smc(struct radeon_device *rdev)
3338 {
3339 if (si_send_msg_to_smc(rdev, PPSMC_FlushDataCache) != PPSMC_Result_OK)
3340 return -EINVAL;
3341
3342 return (si_send_msg_to_smc(rdev, PPSMC_MSG_Resume) == PPSMC_Result_OK) ?
3343 0 : -EINVAL;
3344 }
3345
3346 static void si_dpm_start_smc(struct radeon_device *rdev)
3347 {
3348 si_program_jump_on_start(rdev);
3349 si_start_smc(rdev);
3350 si_start_smc_clock(rdev);
3351 }
3352
3353 static void si_dpm_stop_smc(struct radeon_device *rdev)
3354 {
3355 si_reset_smc(rdev);
3356 si_stop_smc_clock(rdev);
3357 }
3358
3359 static int si_process_firmware_header(struct radeon_device *rdev)
3360 {
3361 struct si_power_info *si_pi = si_get_pi(rdev);
3362 u32 tmp;
3363 int ret;
3364
3365 ret = si_read_smc_sram_dword(rdev,
3366 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3367 SISLANDS_SMC_FIRMWARE_HEADER_stateTable,
3368 &tmp, si_pi->sram_end);
3369 if (ret)
3370 return ret;
3371
3372 si_pi->state_table_start = tmp;
3373
3374 ret = si_read_smc_sram_dword(rdev,
3375 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3376 SISLANDS_SMC_FIRMWARE_HEADER_softRegisters,
3377 &tmp, si_pi->sram_end);
3378 if (ret)
3379 return ret;
3380
3381 si_pi->soft_regs_start = tmp;
3382
3383 ret = si_read_smc_sram_dword(rdev,
3384 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3385 SISLANDS_SMC_FIRMWARE_HEADER_mcRegisterTable,
3386 &tmp, si_pi->sram_end);
3387 if (ret)
3388 return ret;
3389
3390 si_pi->mc_reg_table_start = tmp;
3391
3392 ret = si_read_smc_sram_dword(rdev,
3393 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3394 SISLANDS_SMC_FIRMWARE_HEADER_mcArbDramAutoRefreshTable,
3395 &tmp, si_pi->sram_end);
3396 if (ret)
3397 return ret;
3398
3399 si_pi->arb_table_start = tmp;
3400
3401 ret = si_read_smc_sram_dword(rdev,
3402 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3403 SISLANDS_SMC_FIRMWARE_HEADER_CacConfigTable,
3404 &tmp, si_pi->sram_end);
3405 if (ret)
3406 return ret;
3407
3408 si_pi->cac_table_start = tmp;
3409
3410 ret = si_read_smc_sram_dword(rdev,
3411 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3412 SISLANDS_SMC_FIRMWARE_HEADER_DteConfiguration,
3413 &tmp, si_pi->sram_end);
3414 if (ret)
3415 return ret;
3416
3417 si_pi->dte_table_start = tmp;
3418
3419 ret = si_read_smc_sram_dword(rdev,
3420 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3421 SISLANDS_SMC_FIRMWARE_HEADER_spllTable,
3422 &tmp, si_pi->sram_end);
3423 if (ret)
3424 return ret;
3425
3426 si_pi->spll_table_start = tmp;
3427
3428 ret = si_read_smc_sram_dword(rdev,
3429 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3430 SISLANDS_SMC_FIRMWARE_HEADER_PAPMParameters,
3431 &tmp, si_pi->sram_end);
3432 if (ret)
3433 return ret;
3434
3435 si_pi->papm_cfg_table_start = tmp;
3436
3437 return ret;
3438 }
3439
3440 static void si_read_clock_registers(struct radeon_device *rdev)
3441 {
3442 struct si_power_info *si_pi = si_get_pi(rdev);
3443
3444 si_pi->clock_registers.cg_spll_func_cntl = RREG32(CG_SPLL_FUNC_CNTL);
3445 si_pi->clock_registers.cg_spll_func_cntl_2 = RREG32(CG_SPLL_FUNC_CNTL_2);
3446 si_pi->clock_registers.cg_spll_func_cntl_3 = RREG32(CG_SPLL_FUNC_CNTL_3);
3447 si_pi->clock_registers.cg_spll_func_cntl_4 = RREG32(CG_SPLL_FUNC_CNTL_4);
3448 si_pi->clock_registers.cg_spll_spread_spectrum = RREG32(CG_SPLL_SPREAD_SPECTRUM);
3449 si_pi->clock_registers.cg_spll_spread_spectrum_2 = RREG32(CG_SPLL_SPREAD_SPECTRUM_2);
3450 si_pi->clock_registers.dll_cntl = RREG32(DLL_CNTL);
3451 si_pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL);
3452 si_pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL);
3453 si_pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL);
3454 si_pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL);
3455 si_pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1);
3456 si_pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2);
3457 si_pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1);
3458 si_pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2);
3459 }
3460
3461 static void si_enable_thermal_protection(struct radeon_device *rdev,
3462 bool enable)
3463 {
3464 if (enable)
3465 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS);
3466 else
3467 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS);
3468 }
3469
3470 static void si_enable_acpi_power_management(struct radeon_device *rdev)
3471 {
3472 WREG32_P(GENERAL_PWRMGT, STATIC_PM_EN, ~STATIC_PM_EN);
3473 }
3474
3475 #if 0
3476 static int si_enter_ulp_state(struct radeon_device *rdev)
3477 {
3478 WREG32(SMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower);
3479
3480 udelay(25000);
3481
3482 return 0;
3483 }
3484
3485 static int si_exit_ulp_state(struct radeon_device *rdev)
3486 {
3487 int i;
3488
3489 WREG32(SMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower);
3490
3491 udelay(7000);
3492
3493 for (i = 0; i < rdev->usec_timeout; i++) {
3494 if (RREG32(SMC_RESP_0) == 1)
3495 break;
3496 udelay(1000);
3497 }
3498
3499 return 0;
3500 }
3501 #endif
3502
3503 static int si_notify_smc_display_change(struct radeon_device *rdev,
3504 bool has_display)
3505 {
3506 PPSMC_Msg msg = has_display ?
3507 PPSMC_MSG_HasDisplay : PPSMC_MSG_NoDisplay;
3508
3509 return (si_send_msg_to_smc(rdev, msg) == PPSMC_Result_OK) ?
3510 0 : -EINVAL;
3511 }
3512
3513 static void si_program_response_times(struct radeon_device *rdev)
3514 {
3515 u32 voltage_response_time, backbias_response_time, acpi_delay_time, vbi_time_out;
3516 u32 vddc_dly, acpi_dly, vbi_dly;
3517 u32 reference_clock;
3518
3519 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mvdd_chg_time, 1);
3520
3521 voltage_response_time = (u32)rdev->pm.dpm.voltage_response_time;
3522 backbias_response_time = (u32)rdev->pm.dpm.backbias_response_time;
3523
3524 if (voltage_response_time == 0)
3525 voltage_response_time = 1000;
3526
3527 acpi_delay_time = 15000;
3528 vbi_time_out = 100000;
3529
3530 reference_clock = radeon_get_xclk(rdev);
3531
3532 vddc_dly = (voltage_response_time * reference_clock) / 100;
3533 acpi_dly = (acpi_delay_time * reference_clock) / 100;
3534 vbi_dly = (vbi_time_out * reference_clock) / 100;
3535
3536 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_delay_vreg, vddc_dly);
3537 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_delay_acpi, acpi_dly);
3538 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mclk_chg_timeout, vbi_dly);
3539 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mc_block_delay, 0xAA);
3540 }
3541
3542 static void si_program_ds_registers(struct radeon_device *rdev)
3543 {
3544 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
3545 u32 tmp = 1; /* XXX: 0x10 on tahiti A0 */
3546
3547 if (eg_pi->sclk_deep_sleep) {
3548 WREG32_P(MISC_CLK_CNTL, DEEP_SLEEP_CLK_SEL(tmp), ~DEEP_SLEEP_CLK_SEL_MASK);
3549 WREG32_P(CG_SPLL_AUTOSCALE_CNTL, AUTOSCALE_ON_SS_CLEAR,
3550 ~AUTOSCALE_ON_SS_CLEAR);
3551 }
3552 }
3553
3554 static void si_program_display_gap(struct radeon_device *rdev)
3555 {
3556 u32 tmp, pipe;
3557 int i;
3558
3559 tmp = RREG32(CG_DISPLAY_GAP_CNTL) & ~(DISP1_GAP_MASK | DISP2_GAP_MASK);
3560 if (rdev->pm.dpm.new_active_crtc_count > 0)
3561 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
3562 else
3563 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE);
3564
3565 if (rdev->pm.dpm.new_active_crtc_count > 1)
3566 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
3567 else
3568 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE);
3569
3570 WREG32(CG_DISPLAY_GAP_CNTL, tmp);
3571
3572 tmp = RREG32(DCCG_DISP_SLOW_SELECT_REG);
3573 pipe = (tmp & DCCG_DISP1_SLOW_SELECT_MASK) >> DCCG_DISP1_SLOW_SELECT_SHIFT;
3574
3575 if ((rdev->pm.dpm.new_active_crtc_count > 0) &&
3576 (!(rdev->pm.dpm.new_active_crtcs & (1 << pipe)))) {
3577 /* find the first active crtc */
3578 for (i = 0; i < rdev->num_crtc; i++) {
3579 if (rdev->pm.dpm.new_active_crtcs & (1 << i))
3580 break;
3581 }
3582 if (i == rdev->num_crtc)
3583 pipe = 0;
3584 else
3585 pipe = i;
3586
3587 tmp &= ~DCCG_DISP1_SLOW_SELECT_MASK;
3588 tmp |= DCCG_DISP1_SLOW_SELECT(pipe);
3589 WREG32(DCCG_DISP_SLOW_SELECT_REG, tmp);
3590 }
3591
3592 /* Setting this to false forces the performance state to low if the crtcs are disabled.
3593 * This can be a problem on PowerXpress systems or if you want to use the card
3594 * for offscreen rendering or compute if there are no crtcs enabled. Set it to
3595 * true for now so that performance scales even if the displays are off.
3596 */
3597 si_notify_smc_display_change(rdev, true /*rdev->pm.dpm.new_active_crtc_count > 0*/);
3598 }
3599
3600 static void si_enable_spread_spectrum(struct radeon_device *rdev, bool enable)
3601 {
3602 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3603
3604 if (enable) {
3605 if (pi->sclk_ss)
3606 WREG32_P(GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, ~DYN_SPREAD_SPECTRUM_EN);
3607 } else {
3608 WREG32_P(CG_SPLL_SPREAD_SPECTRUM, 0, ~SSEN);
3609 WREG32_P(GENERAL_PWRMGT, 0, ~DYN_SPREAD_SPECTRUM_EN);
3610 }
3611 }
3612
3613 static void si_setup_bsp(struct radeon_device *rdev)
3614 {
3615 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3616 u32 xclk = radeon_get_xclk(rdev);
3617
3618 r600_calculate_u_and_p(pi->asi,
3619 xclk,
3620 16,
3621 &pi->bsp,
3622 &pi->bsu);
3623
3624 r600_calculate_u_and_p(pi->pasi,
3625 xclk,
3626 16,
3627 &pi->pbsp,
3628 &pi->pbsu);
3629
3630
3631 pi->dsp = BSP(pi->bsp) | BSU(pi->bsu);
3632 pi->psp = BSP(pi->pbsp) | BSU(pi->pbsu);
3633
3634 WREG32(CG_BSP, pi->dsp);
3635 }
3636
3637 static void si_program_git(struct radeon_device *rdev)
3638 {
3639 WREG32_P(CG_GIT, CG_GICST(R600_GICST_DFLT), ~CG_GICST_MASK);
3640 }
3641
3642 static void si_program_tp(struct radeon_device *rdev)
3643 {
3644 int i;
3645 enum r600_td td = R600_TD_DFLT;
3646
3647 for (i = 0; i < R600_PM_NUMBER_OF_TC; i++)
3648 WREG32(CG_FFCT_0 + (i * 4), (UTC_0(r600_utc[i]) | DTC_0(r600_dtc[i])));
3649
3650 if (td == R600_TD_AUTO)
3651 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL);
3652 else
3653 WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL);
3654
3655 if (td == R600_TD_UP)
3656 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE);
3657
3658 if (td == R600_TD_DOWN)
3659 WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE);
3660 }
3661
3662 static void si_program_tpp(struct radeon_device *rdev)
3663 {
3664 WREG32(CG_TPC, R600_TPC_DFLT);
3665 }
3666
3667 static void si_program_sstp(struct radeon_device *rdev)
3668 {
3669 WREG32(CG_SSP, (SSTU(R600_SSTU_DFLT) | SST(R600_SST_DFLT)));
3670 }
3671
3672 static void si_enable_display_gap(struct radeon_device *rdev)
3673 {
3674 u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL);
3675
3676 tmp &= ~(DISP1_GAP_MASK | DISP2_GAP_MASK);
3677 tmp |= (DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE) |
3678 DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE));
3679
3680 tmp &= ~(DISP1_GAP_MCHG_MASK | DISP2_GAP_MCHG_MASK);
3681 tmp |= (DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK) |
3682 DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE));
3683 WREG32(CG_DISPLAY_GAP_CNTL, tmp);
3684 }
3685
3686 static void si_program_vc(struct radeon_device *rdev)
3687 {
3688 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3689
3690 WREG32(CG_FTV, pi->vrc);
3691 }
3692
3693 static void si_clear_vc(struct radeon_device *rdev)
3694 {
3695 WREG32(CG_FTV, 0);
3696 }
3697
3698 u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock)
3699 {
3700 u8 mc_para_index;
3701
3702 if (memory_clock < 10000)
3703 mc_para_index = 0;
3704 else if (memory_clock >= 80000)
3705 mc_para_index = 0x0f;
3706 else
3707 mc_para_index = (u8)((memory_clock - 10000) / 5000 + 1);
3708 return mc_para_index;
3709 }
3710
3711 u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode)
3712 {
3713 u8 mc_para_index;
3714
3715 if (strobe_mode) {
3716 if (memory_clock < 12500)
3717 mc_para_index = 0x00;
3718 else if (memory_clock > 47500)
3719 mc_para_index = 0x0f;
3720 else
3721 mc_para_index = (u8)((memory_clock - 10000) / 2500);
3722 } else {
3723 if (memory_clock < 65000)
3724 mc_para_index = 0x00;
3725 else if (memory_clock > 135000)
3726 mc_para_index = 0x0f;
3727 else
3728 mc_para_index = (u8)((memory_clock - 60000) / 5000);
3729 }
3730 return mc_para_index;
3731 }
3732
3733 static u8 si_get_strobe_mode_settings(struct radeon_device *rdev, u32 mclk)
3734 {
3735 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3736 bool strobe_mode = false;
3737 u8 result = 0;
3738
3739 if (mclk <= pi->mclk_strobe_mode_threshold)
3740 strobe_mode = true;
3741
3742 if (pi->mem_gddr5)
3743 result = si_get_mclk_frequency_ratio(mclk, strobe_mode);
3744 else
3745 result = si_get_ddr3_mclk_frequency_ratio(mclk);
3746
3747 if (strobe_mode)
3748 result |= SISLANDS_SMC_STROBE_ENABLE;
3749
3750 return result;
3751 }
3752
3753 static int si_upload_firmware(struct radeon_device *rdev)
3754 {
3755 struct si_power_info *si_pi = si_get_pi(rdev);
3756 int ret;
3757
3758 si_reset_smc(rdev);
3759 si_stop_smc_clock(rdev);
3760
3761 ret = si_load_smc_ucode(rdev, si_pi->sram_end);
3762
3763 return ret;
3764 }
3765
3766 static bool si_validate_phase_shedding_tables(struct radeon_device *rdev,
3767 const struct atom_voltage_table *table,
3768 const struct radeon_phase_shedding_limits_table *limits)
3769 {
3770 u32 data, num_bits, num_levels;
3771
3772 if ((table == NULL) || (limits == NULL))
3773 return false;
3774
3775 data = table->mask_low;
3776
3777 num_bits = hweight32(data);
3778
3779 if (num_bits == 0)
3780 return false;
3781
3782 num_levels = (1 << num_bits);
3783
3784 if (table->count != num_levels)
3785 return false;
3786
3787 if (limits->count != (num_levels - 1))
3788 return false;
3789
3790 return true;
3791 }
3792
3793 void si_trim_voltage_table_to_fit_state_table(struct radeon_device *rdev,
3794 u32 max_voltage_steps,
3795 struct atom_voltage_table *voltage_table)
3796 {
3797 unsigned int i, diff;
3798
3799 if (voltage_table->count <= max_voltage_steps)
3800 return;
3801
3802 diff = voltage_table->count - max_voltage_steps;
3803
3804 for (i= 0; i < max_voltage_steps; i++)
3805 voltage_table->entries[i] = voltage_table->entries[i + diff];
3806
3807 voltage_table->count = max_voltage_steps;
3808 }
3809
3810 static int si_construct_voltage_tables(struct radeon_device *rdev)
3811 {
3812 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3813 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
3814 struct si_power_info *si_pi = si_get_pi(rdev);
3815 int ret;
3816
3817 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC,
3818 VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddc_voltage_table);
3819 if (ret)
3820 return ret;
3821
3822 if (eg_pi->vddc_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
3823 si_trim_voltage_table_to_fit_state_table(rdev,
3824 SISLANDS_MAX_NO_VREG_STEPS,
3825 &eg_pi->vddc_voltage_table);
3826
3827 if (eg_pi->vddci_control) {
3828 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDCI,
3829 VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddci_voltage_table);
3830 if (ret)
3831 return ret;
3832
3833 if (eg_pi->vddci_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
3834 si_trim_voltage_table_to_fit_state_table(rdev,
3835 SISLANDS_MAX_NO_VREG_STEPS,
3836 &eg_pi->vddci_voltage_table);
3837 }
3838
3839 if (pi->mvdd_control) {
3840 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_MVDDC,
3841 VOLTAGE_OBJ_GPIO_LUT, &si_pi->mvdd_voltage_table);
3842
3843 if (ret) {
3844 pi->mvdd_control = false;
3845 return ret;
3846 }
3847
3848 if (si_pi->mvdd_voltage_table.count == 0) {
3849 pi->mvdd_control = false;
3850 return -EINVAL;
3851 }
3852
3853 if (si_pi->mvdd_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
3854 si_trim_voltage_table_to_fit_state_table(rdev,
3855 SISLANDS_MAX_NO_VREG_STEPS,
3856 &si_pi->mvdd_voltage_table);
3857 }
3858
3859 if (si_pi->vddc_phase_shed_control) {
3860 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC,
3861 VOLTAGE_OBJ_PHASE_LUT, &si_pi->vddc_phase_shed_table);
3862 if (ret)
3863 si_pi->vddc_phase_shed_control = false;
3864
3865 if ((si_pi->vddc_phase_shed_table.count == 0) ||
3866 (si_pi->vddc_phase_shed_table.count > SISLANDS_MAX_NO_VREG_STEPS))
3867 si_pi->vddc_phase_shed_control = false;
3868 }
3869
3870 return 0;
3871 }
3872
3873 static void si_populate_smc_voltage_table(struct radeon_device *rdev,
3874 const struct atom_voltage_table *voltage_table,
3875 SISLANDS_SMC_STATETABLE *table)
3876 {
3877 unsigned int i;
3878
3879 for (i = 0; i < voltage_table->count; i++)
3880 table->lowSMIO[i] |= cpu_to_be32(voltage_table->entries[i].smio_low);
3881 }
3882
3883 static int si_populate_smc_voltage_tables(struct radeon_device *rdev,
3884 SISLANDS_SMC_STATETABLE *table)
3885 {
3886 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3887 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
3888 struct si_power_info *si_pi = si_get_pi(rdev);
3889 u8 i;
3890
3891 if (eg_pi->vddc_voltage_table.count) {
3892 si_populate_smc_voltage_table(rdev, &eg_pi->vddc_voltage_table, table);
3893 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC] =
3894 cpu_to_be32(eg_pi->vddc_voltage_table.mask_low);
3895
3896 for (i = 0; i < eg_pi->vddc_voltage_table.count; i++) {
3897 if (pi->max_vddc_in_table <= eg_pi->vddc_voltage_table.entries[i].value) {
3898 table->maxVDDCIndexInPPTable = i;
3899 break;
3900 }
3901 }
3902 }
3903
3904 if (eg_pi->vddci_voltage_table.count) {
3905 si_populate_smc_voltage_table(rdev, &eg_pi->vddci_voltage_table, table);
3906
3907 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDCI] =
3908 cpu_to_be32(eg_pi->vddci_voltage_table.mask_low);
3909 }
3910
3911
3912 if (si_pi->mvdd_voltage_table.count) {
3913 si_populate_smc_voltage_table(rdev, &si_pi->mvdd_voltage_table, table);
3914
3915 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_MVDD] =
3916 cpu_to_be32(si_pi->mvdd_voltage_table.mask_low);
3917 }
3918
3919 if (si_pi->vddc_phase_shed_control) {
3920 if (si_validate_phase_shedding_tables(rdev, &si_pi->vddc_phase_shed_table,
3921 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table)) {
3922 si_populate_smc_voltage_table(rdev, &si_pi->vddc_phase_shed_table, table);
3923
3924 table->phaseMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC] =
3925 cpu_to_be32(si_pi->vddc_phase_shed_table.mask_low);
3926
3927 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_phase_shedding_delay,
3928 (u32)si_pi->vddc_phase_shed_table.phase_delay);
3929 } else {
3930 si_pi->vddc_phase_shed_control = false;
3931 }
3932 }
3933
3934 return 0;
3935 }
3936
3937 static int si_populate_voltage_value(struct radeon_device *rdev,
3938 const struct atom_voltage_table *table,
3939 u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage)
3940 {
3941 unsigned int i;
3942
3943 for (i = 0; i < table->count; i++) {
3944 if (value <= table->entries[i].value) {
3945 voltage->index = (u8)i;
3946 voltage->value = cpu_to_be16(table->entries[i].value);
3947 break;
3948 }
3949 }
3950
3951 if (i >= table->count)
3952 return -EINVAL;
3953
3954 return 0;
3955 }
3956
3957 static int si_populate_mvdd_value(struct radeon_device *rdev, u32 mclk,
3958 SISLANDS_SMC_VOLTAGE_VALUE *voltage)
3959 {
3960 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3961 struct si_power_info *si_pi = si_get_pi(rdev);
3962
3963 if (pi->mvdd_control) {
3964 if (mclk <= pi->mvdd_split_frequency)
3965 voltage->index = 0;
3966 else
3967 voltage->index = (u8)(si_pi->mvdd_voltage_table.count) - 1;
3968
3969 voltage->value = cpu_to_be16(si_pi->mvdd_voltage_table.entries[voltage->index].value);
3970 }
3971 return 0;
3972 }
3973
3974 static int si_get_std_voltage_value(struct radeon_device *rdev,
3975 SISLANDS_SMC_VOLTAGE_VALUE *voltage,
3976 u16 *std_voltage)
3977 {
3978 u16 v_index;
3979 bool voltage_found = false;
3980 *std_voltage = be16_to_cpu(voltage->value);
3981
3982 if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries) {
3983 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_NEW_CAC_VOLTAGE) {
3984 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL)
3985 return -EINVAL;
3986
3987 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
3988 if (be16_to_cpu(voltage->value) ==
3989 (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
3990 voltage_found = true;
3991 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)
3992 *std_voltage =
3993 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc;
3994 else
3995 *std_voltage =
3996 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc;
3997 break;
3998 }
3999 }
4000
4001 if (!voltage_found) {
4002 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
4003 if (be16_to_cpu(voltage->value) <=
4004 (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
4005 voltage_found = true;
4006 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)
4007 *std_voltage =
4008 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc;
4009 else
4010 *std_voltage =
4011 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc;
4012 break;
4013 }
4014 }
4015 }
4016 } else {
4017 if ((u32)voltage->index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)
4018 *std_voltage = rdev->pm.dpm.dyn_state.cac_leakage_table.entries[voltage->index].vddc;
4019 }
4020 }
4021
4022 return 0;
4023 }
4024
4025 static int si_populate_std_voltage_value(struct radeon_device *rdev,
4026 u16 value, u8 index,
4027 SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4028 {
4029 voltage->index = index;
4030 voltage->value = cpu_to_be16(value);
4031
4032 return 0;
4033 }
4034
4035 static int si_populate_phase_shedding_value(struct radeon_device *rdev,
4036 const struct radeon_phase_shedding_limits_table *limits,
4037 u16 voltage, u32 sclk, u32 mclk,
4038 SISLANDS_SMC_VOLTAGE_VALUE *smc_voltage)
4039 {
4040 unsigned int i;
4041
4042 for (i = 0; i < limits->count; i++) {
4043 if ((voltage <= limits->entries[i].voltage) &&
4044 (sclk <= limits->entries[i].sclk) &&
4045 (mclk <= limits->entries[i].mclk))
4046 break;
4047 }
4048
4049 smc_voltage->phase_settings = (u8)i;
4050
4051 return 0;
4052 }
4053
4054 static int si_init_arb_table_index(struct radeon_device *rdev)
4055 {
4056 struct si_power_info *si_pi = si_get_pi(rdev);
4057 u32 tmp;
4058 int ret;
4059
4060 ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start, &tmp, si_pi->sram_end);
4061 if (ret)
4062 return ret;
4063
4064 tmp &= 0x00FFFFFF;
4065 tmp |= MC_CG_ARB_FREQ_F1 << 24;
4066
4067 return si_write_smc_sram_dword(rdev, si_pi->arb_table_start, tmp, si_pi->sram_end);
4068 }
4069
4070 static int si_initial_switch_from_arb_f0_to_f1(struct radeon_device *rdev)
4071 {
4072 return ni_copy_and_switch_arb_sets(rdev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
4073 }
4074
4075 static int si_reset_to_default(struct radeon_device *rdev)
4076 {
4077 return (si_send_msg_to_smc(rdev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ?
4078 0 : -EINVAL;
4079 }
4080
4081 static int si_force_switch_to_arb_f0(struct radeon_device *rdev)
4082 {
4083 struct si_power_info *si_pi = si_get_pi(rdev);
4084 u32 tmp;
4085 int ret;
4086
4087 ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start,
4088 &tmp, si_pi->sram_end);
4089 if (ret)
4090 return ret;
4091
4092 tmp = (tmp >> 24) & 0xff;
4093
4094 if (tmp == MC_CG_ARB_FREQ_F0)
4095 return 0;
4096
4097 return ni_copy_and_switch_arb_sets(rdev, tmp, MC_CG_ARB_FREQ_F0);
4098 }
4099
4100 static u32 si_calculate_memory_refresh_rate(struct radeon_device *rdev,
4101 u32 engine_clock)
4102 {
4103 u32 dram_rows;
4104 u32 dram_refresh_rate;
4105 u32 mc_arb_rfsh_rate;
4106 u32 tmp = (RREG32(MC_ARB_RAMCFG) & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
4107
4108 if (tmp >= 4)
4109 dram_rows = 16384;
4110 else
4111 dram_rows = 1 << (tmp + 10);
4112
4113 dram_refresh_rate = 1 << ((RREG32(MC_SEQ_MISC0) & 0x3) + 3);
4114 mc_arb_rfsh_rate = ((engine_clock * 10) * dram_refresh_rate / dram_rows - 32) / 64;
4115
4116 return mc_arb_rfsh_rate;
4117 }
4118
4119 static int si_populate_memory_timing_parameters(struct radeon_device *rdev,
4120 struct rv7xx_pl *pl,
4121 SMC_SIslands_MCArbDramTimingRegisterSet *arb_regs)
4122 {
4123 u32 dram_timing;
4124 u32 dram_timing2;
4125 u32 burst_time;
4126
4127 arb_regs->mc_arb_rfsh_rate =
4128 (u8)si_calculate_memory_refresh_rate(rdev, pl->sclk);
4129
4130 radeon_atom_set_engine_dram_timings(rdev,
4131 pl->sclk,
4132 pl->mclk);
4133
4134 dram_timing = RREG32(MC_ARB_DRAM_TIMING);
4135 dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
4136 burst_time = RREG32(MC_ARB_BURST_TIME) & STATE0_MASK;
4137
4138 arb_regs->mc_arb_dram_timing = cpu_to_be32(dram_timing);
4139 arb_regs->mc_arb_dram_timing2 = cpu_to_be32(dram_timing2);
4140 arb_regs->mc_arb_burst_time = (u8)burst_time;
4141
4142 return 0;
4143 }
4144
4145 static int si_do_program_memory_timing_parameters(struct radeon_device *rdev,
4146 struct radeon_ps *radeon_state,
4147 unsigned int first_arb_set)
4148 {
4149 struct si_power_info *si_pi = si_get_pi(rdev);
4150 struct ni_ps *state = ni_get_ps(radeon_state);
4151 SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 };
4152 int i, ret = 0;
4153
4154 for (i = 0; i < state->performance_level_count; i++) {
4155 ret = si_populate_memory_timing_parameters(rdev, &state->performance_levels[i], &arb_regs);
4156 if (ret)
4157 break;
4158 ret = si_copy_bytes_to_smc(rdev,
4159 si_pi->arb_table_start +
4160 offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) +
4161 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * (first_arb_set + i),
4162 (u8 *)&arb_regs,
4163 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet),
4164 si_pi->sram_end);
4165 if (ret)
4166 break;
4167 }
4168
4169 return ret;
4170 }
4171
4172 static int si_program_memory_timing_parameters(struct radeon_device *rdev,
4173 struct radeon_ps *radeon_new_state)
4174 {
4175 return si_do_program_memory_timing_parameters(rdev, radeon_new_state,
4176 SISLANDS_DRIVER_STATE_ARB_INDEX);
4177 }
4178
4179 static int si_populate_initial_mvdd_value(struct radeon_device *rdev,
4180 struct SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4181 {
4182 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4183 struct si_power_info *si_pi = si_get_pi(rdev);
4184
4185 if (pi->mvdd_control)
4186 return si_populate_voltage_value(rdev, &si_pi->mvdd_voltage_table,
4187 si_pi->mvdd_bootup_value, voltage);
4188
4189 return 0;
4190 }
4191
4192 static int si_populate_smc_initial_state(struct radeon_device *rdev,
4193 struct radeon_ps *radeon_initial_state,
4194 SISLANDS_SMC_STATETABLE *table)
4195 {
4196 struct ni_ps *initial_state = ni_get_ps(radeon_initial_state);
4197 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4198 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4199 struct si_power_info *si_pi = si_get_pi(rdev);
4200 u32 reg;
4201 int ret;
4202
4203 table->initialState.levels[0].mclk.vDLL_CNTL =
4204 cpu_to_be32(si_pi->clock_registers.dll_cntl);
4205 table->initialState.levels[0].mclk.vMCLK_PWRMGT_CNTL =
4206 cpu_to_be32(si_pi->clock_registers.mclk_pwrmgt_cntl);
4207 table->initialState.levels[0].mclk.vMPLL_AD_FUNC_CNTL =
4208 cpu_to_be32(si_pi->clock_registers.mpll_ad_func_cntl);
4209 table->initialState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL =
4210 cpu_to_be32(si_pi->clock_registers.mpll_dq_func_cntl);
4211 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL =
4212 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl);
4213 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_1 =
4214 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_1);
4215 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_2 =
4216 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_2);
4217 table->initialState.levels[0].mclk.vMPLL_SS =
4218 cpu_to_be32(si_pi->clock_registers.mpll_ss1);
4219 table->initialState.levels[0].mclk.vMPLL_SS2 =
4220 cpu_to_be32(si_pi->clock_registers.mpll_ss2);
4221
4222 table->initialState.levels[0].mclk.mclk_value =
4223 cpu_to_be32(initial_state->performance_levels[0].mclk);
4224
4225 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
4226 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl);
4227 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
4228 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_2);
4229 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
4230 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_3);
4231 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 =
4232 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_4);
4233 table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM =
4234 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum);
4235 table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM_2 =
4236 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum_2);
4237
4238 table->initialState.levels[0].sclk.sclk_value =
4239 cpu_to_be32(initial_state->performance_levels[0].sclk);
4240
4241 table->initialState.levels[0].arbRefreshState =
4242 SISLANDS_INITIAL_STATE_ARB_INDEX;
4243
4244 table->initialState.levels[0].ACIndex = 0;
4245
4246 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
4247 initial_state->performance_levels[0].vddc,
4248 &table->initialState.levels[0].vddc);
4249
4250 if (!ret) {
4251 u16 std_vddc;
4252
4253 ret = si_get_std_voltage_value(rdev,
4254 &table->initialState.levels[0].vddc,
4255 &std_vddc);
4256 if (!ret)
4257 si_populate_std_voltage_value(rdev, std_vddc,
4258 table->initialState.levels[0].vddc.index,
4259 &table->initialState.levels[0].std_vddc);
4260 }
4261
4262 if (eg_pi->vddci_control)
4263 si_populate_voltage_value(rdev,
4264 &eg_pi->vddci_voltage_table,
4265 initial_state->performance_levels[0].vddci,
4266 &table->initialState.levels[0].vddci);
4267
4268 if (si_pi->vddc_phase_shed_control)
4269 si_populate_phase_shedding_value(rdev,
4270 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
4271 initial_state->performance_levels[0].vddc,
4272 initial_state->performance_levels[0].sclk,
4273 initial_state->performance_levels[0].mclk,
4274 &table->initialState.levels[0].vddc);
4275
4276 si_populate_initial_mvdd_value(rdev, &table->initialState.levels[0].mvdd);
4277
4278 reg = CG_R(0xffff) | CG_L(0);
4279 table->initialState.levels[0].aT = cpu_to_be32(reg);
4280
4281 table->initialState.levels[0].bSP = cpu_to_be32(pi->dsp);
4282
4283 table->initialState.levels[0].gen2PCIE = (u8)si_pi->boot_pcie_gen;
4284
4285 if (pi->mem_gddr5) {
4286 table->initialState.levels[0].strobeMode =
4287 si_get_strobe_mode_settings(rdev,
4288 initial_state->performance_levels[0].mclk);
4289
4290 if (initial_state->performance_levels[0].mclk > pi->mclk_edc_enable_threshold)
4291 table->initialState.levels[0].mcFlags = SISLANDS_SMC_MC_EDC_RD_FLAG | SISLANDS_SMC_MC_EDC_WR_FLAG;
4292 else
4293 table->initialState.levels[0].mcFlags = 0;
4294 }
4295
4296 table->initialState.levelCount = 1;
4297
4298 table->initialState.flags |= PPSMC_SWSTATE_FLAG_DC;
4299
4300 table->initialState.levels[0].dpm2.MaxPS = 0;
4301 table->initialState.levels[0].dpm2.NearTDPDec = 0;
4302 table->initialState.levels[0].dpm2.AboveSafeInc = 0;
4303 table->initialState.levels[0].dpm2.BelowSafeInc = 0;
4304 table->initialState.levels[0].dpm2.PwrEfficiencyRatio = 0;
4305
4306 reg = MIN_POWER_MASK | MAX_POWER_MASK;
4307 table->initialState.levels[0].SQPowerThrottle = cpu_to_be32(reg);
4308
4309 reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
4310 table->initialState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg);
4311
4312 return 0;
4313 }
4314
4315 static int si_populate_smc_acpi_state(struct radeon_device *rdev,
4316 SISLANDS_SMC_STATETABLE *table)
4317 {
4318 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4319 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4320 struct si_power_info *si_pi = si_get_pi(rdev);
4321 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl;
4322 u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2;
4323 u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3;
4324 u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4;
4325 u32 dll_cntl = si_pi->clock_registers.dll_cntl;
4326 u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl;
4327 u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl;
4328 u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl;
4329 u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl;
4330 u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1;
4331 u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2;
4332 u32 reg;
4333 int ret;
4334
4335 table->ACPIState = table->initialState;
4336
4337 table->ACPIState.flags &= ~PPSMC_SWSTATE_FLAG_DC;
4338
4339 if (pi->acpi_vddc) {
4340 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
4341 pi->acpi_vddc, &table->ACPIState.levels[0].vddc);
4342 if (!ret) {
4343 u16 std_vddc;
4344
4345 ret = si_get_std_voltage_value(rdev,
4346 &table->ACPIState.levels[0].vddc, &std_vddc);
4347 if (!ret)
4348 si_populate_std_voltage_value(rdev, std_vddc,
4349 table->ACPIState.levels[0].vddc.index,
4350 &table->ACPIState.levels[0].std_vddc);
4351 }
4352 table->ACPIState.levels[0].gen2PCIE = si_pi->acpi_pcie_gen;
4353
4354 if (si_pi->vddc_phase_shed_control) {
4355 si_populate_phase_shedding_value(rdev,
4356 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
4357 pi->acpi_vddc,
4358 0,
4359 0,
4360 &table->ACPIState.levels[0].vddc);
4361 }
4362 } else {
4363 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
4364 pi->min_vddc_in_table, &table->ACPIState.levels[0].vddc);
4365 if (!ret) {
4366 u16 std_vddc;
4367
4368 ret = si_get_std_voltage_value(rdev,
4369 &table->ACPIState.levels[0].vddc, &std_vddc);
4370
4371 if (!ret)
4372 si_populate_std_voltage_value(rdev, std_vddc,
4373 table->ACPIState.levels[0].vddc.index,
4374 &table->ACPIState.levels[0].std_vddc);
4375 }
4376 table->ACPIState.levels[0].gen2PCIE = (u8)r600_get_pcie_gen_support(rdev,
4377 si_pi->sys_pcie_mask,
4378 si_pi->boot_pcie_gen,
4379 RADEON_PCIE_GEN1);
4380
4381 if (si_pi->vddc_phase_shed_control)
4382 si_populate_phase_shedding_value(rdev,
4383 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
4384 pi->min_vddc_in_table,
4385 0,
4386 0,
4387 &table->ACPIState.levels[0].vddc);
4388 }
4389
4390 if (pi->acpi_vddc) {
4391 if (eg_pi->acpi_vddci)
4392 si_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table,
4393 eg_pi->acpi_vddci,
4394 &table->ACPIState.levels[0].vddci);
4395 }
4396
4397 mclk_pwrmgt_cntl |= MRDCK0_RESET | MRDCK1_RESET;
4398 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
4399
4400 dll_cntl &= ~(MRDCK0_BYPASS | MRDCK1_BYPASS);
4401
4402 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
4403 spll_func_cntl_2 |= SCLK_MUX_SEL(4);
4404
4405 table->ACPIState.levels[0].mclk.vDLL_CNTL =
4406 cpu_to_be32(dll_cntl);
4407 table->ACPIState.levels[0].mclk.vMCLK_PWRMGT_CNTL =
4408 cpu_to_be32(mclk_pwrmgt_cntl);
4409 table->ACPIState.levels[0].mclk.vMPLL_AD_FUNC_CNTL =
4410 cpu_to_be32(mpll_ad_func_cntl);
4411 table->ACPIState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL =
4412 cpu_to_be32(mpll_dq_func_cntl);
4413 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL =
4414 cpu_to_be32(mpll_func_cntl);
4415 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_1 =
4416 cpu_to_be32(mpll_func_cntl_1);
4417 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_2 =
4418 cpu_to_be32(mpll_func_cntl_2);
4419 table->ACPIState.levels[0].mclk.vMPLL_SS =
4420 cpu_to_be32(si_pi->clock_registers.mpll_ss1);
4421 table->ACPIState.levels[0].mclk.vMPLL_SS2 =
4422 cpu_to_be32(si_pi->clock_registers.mpll_ss2);
4423
4424 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
4425 cpu_to_be32(spll_func_cntl);
4426 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
4427 cpu_to_be32(spll_func_cntl_2);
4428 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
4429 cpu_to_be32(spll_func_cntl_3);
4430 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 =
4431 cpu_to_be32(spll_func_cntl_4);
4432
4433 table->ACPIState.levels[0].mclk.mclk_value = 0;
4434 table->ACPIState.levels[0].sclk.sclk_value = 0;
4435
4436 si_populate_mvdd_value(rdev, 0, &table->ACPIState.levels[0].mvdd);
4437
4438 if (eg_pi->dynamic_ac_timing)
4439 table->ACPIState.levels[0].ACIndex = 0;
4440
4441 table->ACPIState.levels[0].dpm2.MaxPS = 0;
4442 table->ACPIState.levels[0].dpm2.NearTDPDec = 0;
4443 table->ACPIState.levels[0].dpm2.AboveSafeInc = 0;
4444 table->ACPIState.levels[0].dpm2.BelowSafeInc = 0;
4445 table->ACPIState.levels[0].dpm2.PwrEfficiencyRatio = 0;
4446
4447 reg = MIN_POWER_MASK | MAX_POWER_MASK;
4448 table->ACPIState.levels[0].SQPowerThrottle = cpu_to_be32(reg);
4449
4450 reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
4451 table->ACPIState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg);
4452
4453 return 0;
4454 }
4455
4456 static int si_populate_ulv_state(struct radeon_device *rdev,
4457 SISLANDS_SMC_SWSTATE *state)
4458 {
4459 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4460 struct si_power_info *si_pi = si_get_pi(rdev);
4461 struct si_ulv_param *ulv = &si_pi->ulv;
4462 u32 sclk_in_sr = 1350; /* ??? */
4463 int ret;
4464
4465 ret = si_convert_power_level_to_smc(rdev, &ulv->pl,
4466 &state->levels[0]);
4467 if (!ret) {
4468 if (eg_pi->sclk_deep_sleep) {
4469 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ)
4470 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS;
4471 else
4472 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE;
4473 }
4474 if (ulv->one_pcie_lane_in_ulv)
4475 state->flags |= PPSMC_SWSTATE_FLAG_PCIE_X1;
4476 state->levels[0].arbRefreshState = (u8)(SISLANDS_ULV_STATE_ARB_INDEX);
4477 state->levels[0].ACIndex = 1;
4478 state->levels[0].std_vddc = state->levels[0].vddc;
4479 state->levelCount = 1;
4480
4481 state->flags |= PPSMC_SWSTATE_FLAG_DC;
4482 }
4483
4484 return ret;
4485 }
4486
4487 static int si_program_ulv_memory_timing_parameters(struct radeon_device *rdev)
4488 {
4489 struct si_power_info *si_pi = si_get_pi(rdev);
4490 struct si_ulv_param *ulv = &si_pi->ulv;
4491 SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 };
4492 int ret;
4493
4494 ret = si_populate_memory_timing_parameters(rdev, &ulv->pl,
4495 &arb_regs);
4496 if (ret)
4497 return ret;
4498
4499 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_ulv_volt_change_delay,
4500 ulv->volt_change_delay);
4501
4502 ret = si_copy_bytes_to_smc(rdev,
4503 si_pi->arb_table_start +
4504 offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) +
4505 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * SISLANDS_ULV_STATE_ARB_INDEX,
4506 (u8 *)&arb_regs,
4507 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet),
4508 si_pi->sram_end);
4509
4510 return ret;
4511 }
4512
4513 static void si_get_mvdd_configuration(struct radeon_device *rdev)
4514 {
4515 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4516
4517 pi->mvdd_split_frequency = 30000;
4518 }
4519
4520 static int si_init_smc_table(struct radeon_device *rdev)
4521 {
4522 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4523 struct si_power_info *si_pi = si_get_pi(rdev);
4524 struct radeon_ps *radeon_boot_state = rdev->pm.dpm.boot_ps;
4525 const struct si_ulv_param *ulv = &si_pi->ulv;
4526 SISLANDS_SMC_STATETABLE *table = &si_pi->smc_statetable;
4527 int ret;
4528 u32 lane_width;
4529 u32 vr_hot_gpio;
4530
4531 si_populate_smc_voltage_tables(rdev, table);
4532
4533 switch (rdev->pm.int_thermal_type) {
4534 case THERMAL_TYPE_SI:
4535 case THERMAL_TYPE_EMC2103_WITH_INTERNAL:
4536 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_INTERNAL;
4537 break;
4538 case THERMAL_TYPE_NONE:
4539 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_NONE;
4540 break;
4541 default:
4542 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL;
4543 break;
4544 }
4545
4546 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC)
4547 table->systemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
4548
4549 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT) {
4550 if ((rdev->pdev->device != 0x6818) && (rdev->pdev->device != 0x6819))
4551 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT;
4552 }
4553
4554 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC)
4555 table->systemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
4556
4557 if (pi->mem_gddr5)
4558 table->systemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
4559
4560 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REVERT_GPIO5_POLARITY)
4561 table->extraFlags |= PPSMC_EXTRAFLAGS_AC2DC_GPIO5_POLARITY_HIGH;
4562
4563 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VRHOT_GPIO_CONFIGURABLE) {
4564 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT_PROG_GPIO;
4565 vr_hot_gpio = rdev->pm.dpm.backbias_response_time;
4566 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_vr_hot_gpio,
4567 vr_hot_gpio);
4568 }
4569
4570 ret = si_populate_smc_initial_state(rdev, radeon_boot_state, table);
4571 if (ret)
4572 return ret;
4573
4574 ret = si_populate_smc_acpi_state(rdev, table);
4575 if (ret)
4576 return ret;
4577
4578 table->driverState = table->initialState;
4579
4580 ret = si_do_program_memory_timing_parameters(rdev, radeon_boot_state,
4581 SISLANDS_INITIAL_STATE_ARB_INDEX);
4582 if (ret)
4583 return ret;
4584
4585 if (ulv->supported && ulv->pl.vddc) {
4586 ret = si_populate_ulv_state(rdev, &table->ULVState);
4587 if (ret)
4588 return ret;
4589
4590 ret = si_program_ulv_memory_timing_parameters(rdev);
4591 if (ret)
4592 return ret;
4593
4594 WREG32(CG_ULV_CONTROL, ulv->cg_ulv_control);
4595 WREG32(CG_ULV_PARAMETER, ulv->cg_ulv_parameter);
4596
4597 lane_width = radeon_get_pcie_lanes(rdev);
4598 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width);
4599 } else {
4600 table->ULVState = table->initialState;
4601 }
4602
4603 return si_copy_bytes_to_smc(rdev, si_pi->state_table_start,
4604 (u8 *)table, sizeof(SISLANDS_SMC_STATETABLE),
4605 si_pi->sram_end);
4606 }
4607
4608 static int si_calculate_sclk_params(struct radeon_device *rdev,
4609 u32 engine_clock,
4610 SISLANDS_SMC_SCLK_VALUE *sclk)
4611 {
4612 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4613 struct si_power_info *si_pi = si_get_pi(rdev);
4614 struct atom_clock_dividers dividers;
4615 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl;
4616 u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2;
4617 u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3;
4618 u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4;
4619 u32 cg_spll_spread_spectrum = si_pi->clock_registers.cg_spll_spread_spectrum;
4620 u32 cg_spll_spread_spectrum_2 = si_pi->clock_registers.cg_spll_spread_spectrum_2;
4621 u64 tmp;
4622 u32 reference_clock = rdev->clock.spll.reference_freq;
4623 u32 reference_divider;
4624 u32 fbdiv;
4625 int ret;
4626
4627 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
4628 engine_clock, false, &dividers);
4629 if (ret)
4630 return ret;
4631
4632 reference_divider = 1 + dividers.ref_div;
4633
4634 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384;
4635 do_div(tmp, reference_clock);
4636 fbdiv = (u32) tmp;
4637
4638 spll_func_cntl &= ~(SPLL_PDIV_A_MASK | SPLL_REF_DIV_MASK);
4639 spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div);
4640 spll_func_cntl |= SPLL_PDIV_A(dividers.post_div);
4641
4642 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
4643 spll_func_cntl_2 |= SCLK_MUX_SEL(2);
4644
4645 spll_func_cntl_3 &= ~SPLL_FB_DIV_MASK;
4646 spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv);
4647 spll_func_cntl_3 |= SPLL_DITHEN;
4648
4649 if (pi->sclk_ss) {
4650 struct radeon_atom_ss ss;
4651 u32 vco_freq = engine_clock * dividers.post_div;
4652
4653 if (radeon_atombios_get_asic_ss_info(rdev, &ss,
4654 ASIC_INTERNAL_ENGINE_SS, vco_freq)) {
4655 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate);
4656 u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000);
4657
4658 cg_spll_spread_spectrum &= ~CLK_S_MASK;
4659 cg_spll_spread_spectrum |= CLK_S(clk_s);
4660 cg_spll_spread_spectrum |= SSEN;
4661
4662 cg_spll_spread_spectrum_2 &= ~CLK_V_MASK;
4663 cg_spll_spread_spectrum_2 |= CLK_V(clk_v);
4664 }
4665 }
4666
4667 sclk->sclk_value = engine_clock;
4668 sclk->vCG_SPLL_FUNC_CNTL = spll_func_cntl;
4669 sclk->vCG_SPLL_FUNC_CNTL_2 = spll_func_cntl_2;
4670 sclk->vCG_SPLL_FUNC_CNTL_3 = spll_func_cntl_3;
4671 sclk->vCG_SPLL_FUNC_CNTL_4 = spll_func_cntl_4;
4672 sclk->vCG_SPLL_SPREAD_SPECTRUM = cg_spll_spread_spectrum;
4673 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cg_spll_spread_spectrum_2;
4674
4675 return 0;
4676 }
4677
4678 static int si_populate_sclk_value(struct radeon_device *rdev,
4679 u32 engine_clock,
4680 SISLANDS_SMC_SCLK_VALUE *sclk)
4681 {
4682 SISLANDS_SMC_SCLK_VALUE sclk_tmp;
4683 int ret;
4684
4685 ret = si_calculate_sclk_params(rdev, engine_clock, &sclk_tmp);
4686 if (!ret) {
4687 sclk->sclk_value = cpu_to_be32(sclk_tmp.sclk_value);
4688 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL);
4689 sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_2);
4690 sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_3);
4691 sclk->vCG_SPLL_FUNC_CNTL_4 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_4);
4692 sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM);
4693 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM_2);
4694 }
4695
4696 return ret;
4697 }
4698
4699 static int si_populate_mclk_value(struct radeon_device *rdev,
4700 u32 engine_clock,
4701 u32 memory_clock,
4702 SISLANDS_SMC_MCLK_VALUE *mclk,
4703 bool strobe_mode,
4704 bool dll_state_on)
4705 {
4706 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4707 struct si_power_info *si_pi = si_get_pi(rdev);
4708 u32 dll_cntl = si_pi->clock_registers.dll_cntl;
4709 u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl;
4710 u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl;
4711 u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl;
4712 u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl;
4713 u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1;
4714 u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2;
4715 u32 mpll_ss1 = si_pi->clock_registers.mpll_ss1;
4716 u32 mpll_ss2 = si_pi->clock_registers.mpll_ss2;
4717 struct atom_mpll_param mpll_param;
4718 int ret;
4719
4720 ret = radeon_atom_get_memory_pll_dividers(rdev, memory_clock, strobe_mode, &mpll_param);
4721 if (ret)
4722 return ret;
4723
4724 mpll_func_cntl &= ~BWCTRL_MASK;
4725 mpll_func_cntl |= BWCTRL(mpll_param.bwcntl);
4726
4727 mpll_func_cntl_1 &= ~(CLKF_MASK | CLKFRAC_MASK | VCO_MODE_MASK);
4728 mpll_func_cntl_1 |= CLKF(mpll_param.clkf) |
4729 CLKFRAC(mpll_param.clkfrac) | VCO_MODE(mpll_param.vco_mode);
4730
4731 mpll_ad_func_cntl &= ~YCLK_POST_DIV_MASK;
4732 mpll_ad_func_cntl |= YCLK_POST_DIV(mpll_param.post_div);
4733
4734 if (pi->mem_gddr5) {
4735 mpll_dq_func_cntl &= ~(YCLK_SEL_MASK | YCLK_POST_DIV_MASK);
4736 mpll_dq_func_cntl |= YCLK_SEL(mpll_param.yclk_sel) |
4737 YCLK_POST_DIV(mpll_param.post_div);
4738 }
4739
4740 if (pi->mclk_ss) {
4741 struct radeon_atom_ss ss;
4742 u32 freq_nom;
4743 u32 tmp;
4744 u32 reference_clock = rdev->clock.mpll.reference_freq;
4745
4746 if (pi->mem_gddr5)
4747 freq_nom = memory_clock * 4;
4748 else
4749 freq_nom = memory_clock * 2;
4750
4751 tmp = freq_nom / reference_clock;
4752 tmp = tmp * tmp;
4753 if (radeon_atombios_get_asic_ss_info(rdev, &ss,
4754 ASIC_INTERNAL_MEMORY_SS, freq_nom)) {
4755 u32 clks = reference_clock * 5 / ss.rate;
4756 u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom);
4757
4758 mpll_ss1 &= ~CLKV_MASK;
4759 mpll_ss1 |= CLKV(clkv);
4760
4761 mpll_ss2 &= ~CLKS_MASK;
4762 mpll_ss2 |= CLKS(clks);
4763 }
4764 }
4765
4766 mclk_pwrmgt_cntl &= ~DLL_SPEED_MASK;
4767 mclk_pwrmgt_cntl |= DLL_SPEED(mpll_param.dll_speed);
4768
4769 if (dll_state_on)
4770 mclk_pwrmgt_cntl |= MRDCK0_PDNB | MRDCK1_PDNB;
4771 else
4772 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
4773
4774 mclk->mclk_value = cpu_to_be32(memory_clock);
4775 mclk->vMPLL_FUNC_CNTL = cpu_to_be32(mpll_func_cntl);
4776 mclk->vMPLL_FUNC_CNTL_1 = cpu_to_be32(mpll_func_cntl_1);
4777 mclk->vMPLL_FUNC_CNTL_2 = cpu_to_be32(mpll_func_cntl_2);
4778 mclk->vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl);
4779 mclk->vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl);
4780 mclk->vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl);
4781 mclk->vDLL_CNTL = cpu_to_be32(dll_cntl);
4782 mclk->vMPLL_SS = cpu_to_be32(mpll_ss1);
4783 mclk->vMPLL_SS2 = cpu_to_be32(mpll_ss2);
4784
4785 return 0;
4786 }
4787
4788 static void si_populate_smc_sp(struct radeon_device *rdev,
4789 struct radeon_ps *radeon_state,
4790 SISLANDS_SMC_SWSTATE *smc_state)
4791 {
4792 struct ni_ps *ps = ni_get_ps(radeon_state);
4793 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4794 int i;
4795
4796 for (i = 0; i < ps->performance_level_count - 1; i++)
4797 smc_state->levels[i].bSP = cpu_to_be32(pi->dsp);
4798
4799 smc_state->levels[ps->performance_level_count - 1].bSP =
4800 cpu_to_be32(pi->psp);
4801 }
4802
4803 static int si_convert_power_level_to_smc(struct radeon_device *rdev,
4804 struct rv7xx_pl *pl,
4805 SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level)
4806 {
4807 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4808 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4809 struct si_power_info *si_pi = si_get_pi(rdev);
4810 int ret;
4811 bool dll_state_on;
4812 u16 std_vddc;
4813 bool gmc_pg = false;
4814
4815 if (eg_pi->pcie_performance_request &&
4816 (si_pi->force_pcie_gen != RADEON_PCIE_GEN_INVALID))
4817 level->gen2PCIE = (u8)si_pi->force_pcie_gen;
4818 else
4819 level->gen2PCIE = (u8)pl->pcie_gen;
4820
4821 ret = si_populate_sclk_value(rdev, pl->sclk, &level->sclk);
4822 if (ret)
4823 return ret;
4824
4825 level->mcFlags = 0;
4826
4827 if (pi->mclk_stutter_mode_threshold &&
4828 (pl->mclk <= pi->mclk_stutter_mode_threshold) &&
4829 !eg_pi->uvd_enabled &&
4830 (RREG32(DPG_PIPE_STUTTER_CONTROL) & STUTTER_ENABLE) &&
4831 (rdev->pm.dpm.new_active_crtc_count <= 2)) {
4832 level->mcFlags |= SISLANDS_SMC_MC_STUTTER_EN;
4833
4834 if (gmc_pg)
4835 level->mcFlags |= SISLANDS_SMC_MC_PG_EN;
4836 }
4837
4838 if (pi->mem_gddr5) {
4839 if (pl->mclk > pi->mclk_edc_enable_threshold)
4840 level->mcFlags |= SISLANDS_SMC_MC_EDC_RD_FLAG;
4841
4842 if (pl->mclk > eg_pi->mclk_edc_wr_enable_threshold)
4843 level->mcFlags |= SISLANDS_SMC_MC_EDC_WR_FLAG;
4844
4845 level->strobeMode = si_get_strobe_mode_settings(rdev, pl->mclk);
4846
4847 if (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) {
4848 if (si_get_mclk_frequency_ratio(pl->mclk, true) >=
4849 ((RREG32(MC_SEQ_MISC7) >> 16) & 0xf))
4850 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
4851 else
4852 dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false;
4853 } else {
4854 dll_state_on = false;
4855 }
4856 } else {
4857 level->strobeMode = si_get_strobe_mode_settings(rdev,
4858 pl->mclk);
4859
4860 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
4861 }
4862
4863 ret = si_populate_mclk_value(rdev,
4864 pl->sclk,
4865 pl->mclk,
4866 &level->mclk,
4867 (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) != 0, dll_state_on);
4868 if (ret)
4869 return ret;
4870
4871 ret = si_populate_voltage_value(rdev,
4872 &eg_pi->vddc_voltage_table,
4873 pl->vddc, &level->vddc);
4874 if (ret)
4875 return ret;
4876
4877
4878 ret = si_get_std_voltage_value(rdev, &level->vddc, &std_vddc);
4879 if (ret)
4880 return ret;
4881
4882 ret = si_populate_std_voltage_value(rdev, std_vddc,
4883 level->vddc.index, &level->std_vddc);
4884 if (ret)
4885 return ret;
4886
4887 if (eg_pi->vddci_control) {
4888 ret = si_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table,
4889 pl->vddci, &level->vddci);
4890 if (ret)
4891 return ret;
4892 }
4893
4894 if (si_pi->vddc_phase_shed_control) {
4895 ret = si_populate_phase_shedding_value(rdev,
4896 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
4897 pl->vddc,
4898 pl->sclk,
4899 pl->mclk,
4900 &level->vddc);
4901 if (ret)
4902 return ret;
4903 }
4904
4905 level->MaxPoweredUpCU = si_pi->max_cu;
4906
4907 ret = si_populate_mvdd_value(rdev, pl->mclk, &level->mvdd);
4908
4909 return ret;
4910 }
4911
4912 static int si_populate_smc_t(struct radeon_device *rdev,
4913 struct radeon_ps *radeon_state,
4914 SISLANDS_SMC_SWSTATE *smc_state)
4915 {
4916 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4917 struct ni_ps *state = ni_get_ps(radeon_state);
4918 u32 a_t;
4919 u32 t_l, t_h;
4920 u32 high_bsp;
4921 int i, ret;
4922
4923 if (state->performance_level_count >= 9)
4924 return -EINVAL;
4925
4926 if (state->performance_level_count < 2) {
4927 a_t = CG_R(0xffff) | CG_L(0);
4928 smc_state->levels[0].aT = cpu_to_be32(a_t);
4929 return 0;
4930 }
4931
4932 smc_state->levels[0].aT = cpu_to_be32(0);
4933
4934 for (i = 0; i <= state->performance_level_count - 2; i++) {
4935 ret = r600_calculate_at(
4936 (50 / SISLANDS_MAX_HARDWARE_POWERLEVELS) * 100 * (i + 1),
4937 100 * R600_AH_DFLT,
4938 state->performance_levels[i + 1].sclk,
4939 state->performance_levels[i].sclk,
4940 &t_l,
4941 &t_h);
4942
4943 if (ret) {
4944 t_h = (i + 1) * 1000 - 50 * R600_AH_DFLT;
4945 t_l = (i + 1) * 1000 + 50 * R600_AH_DFLT;
4946 }
4947
4948 a_t = be32_to_cpu(smc_state->levels[i].aT) & ~CG_R_MASK;
4949 a_t |= CG_R(t_l * pi->bsp / 20000);
4950 smc_state->levels[i].aT = cpu_to_be32(a_t);
4951
4952 high_bsp = (i == state->performance_level_count - 2) ?
4953 pi->pbsp : pi->bsp;
4954 a_t = CG_R(0xffff) | CG_L(t_h * high_bsp / 20000);
4955 smc_state->levels[i + 1].aT = cpu_to_be32(a_t);
4956 }
4957
4958 return 0;
4959 }
4960
4961 static int si_disable_ulv(struct radeon_device *rdev)
4962 {
4963 struct si_power_info *si_pi = si_get_pi(rdev);
4964 struct si_ulv_param *ulv = &si_pi->ulv;
4965
4966 if (ulv->supported)
4967 return (si_send_msg_to_smc(rdev, PPSMC_MSG_DisableULV) == PPSMC_Result_OK) ?
4968 0 : -EINVAL;
4969
4970 return 0;
4971 }
4972
4973 static bool si_is_state_ulv_compatible(struct radeon_device *rdev,
4974 struct radeon_ps *radeon_state)
4975 {
4976 const struct si_power_info *si_pi = si_get_pi(rdev);
4977 const struct si_ulv_param *ulv = &si_pi->ulv;
4978 const struct ni_ps *state = ni_get_ps(radeon_state);
4979 int i;
4980
4981 if (state->performance_levels[0].mclk != ulv->pl.mclk)
4982 return false;
4983
4984 /* XXX validate against display requirements! */
4985
4986 for (i = 0; i < rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count; i++) {
4987 if (rdev->clock.current_dispclk <=
4988 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].clk) {
4989 if (ulv->pl.vddc <
4990 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].v)
4991 return false;
4992 }
4993 }
4994
4995 if ((radeon_state->vclk != 0) || (radeon_state->dclk != 0))
4996 return false;
4997
4998 return true;
4999 }
5000
5001 static int si_set_power_state_conditionally_enable_ulv(struct radeon_device *rdev,
5002 struct radeon_ps *radeon_new_state)
5003 {
5004 const struct si_power_info *si_pi = si_get_pi(rdev);
5005 const struct si_ulv_param *ulv = &si_pi->ulv;
5006
5007 if (ulv->supported) {
5008 if (si_is_state_ulv_compatible(rdev, radeon_new_state))
5009 return (si_send_msg_to_smc(rdev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ?
5010 0 : -EINVAL;
5011 }
5012 return 0;
5013 }
5014
5015 static int si_convert_power_state_to_smc(struct radeon_device *rdev,
5016 struct radeon_ps *radeon_state,
5017 SISLANDS_SMC_SWSTATE *smc_state)
5018 {
5019 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
5020 struct ni_power_info *ni_pi = ni_get_pi(rdev);
5021 struct si_power_info *si_pi = si_get_pi(rdev);
5022 struct ni_ps *state = ni_get_ps(radeon_state);
5023 int i, ret;
5024 u32 threshold;
5025 u32 sclk_in_sr = 1350; /* ??? */
5026
5027 if (state->performance_level_count > SISLANDS_MAX_HARDWARE_POWERLEVELS)
5028 return -EINVAL;
5029
5030 threshold = state->performance_levels[state->performance_level_count-1].sclk * 100 / 100;
5031
5032 if (radeon_state->vclk && radeon_state->dclk) {
5033 eg_pi->uvd_enabled = true;
5034 if (eg_pi->smu_uvd_hs)
5035 smc_state->flags |= PPSMC_SWSTATE_FLAG_UVD;
5036 } else {
5037 eg_pi->uvd_enabled = false;
5038 }
5039
5040 if (state->dc_compatible)
5041 smc_state->flags |= PPSMC_SWSTATE_FLAG_DC;
5042
5043 smc_state->levelCount = 0;
5044 for (i = 0; i < state->performance_level_count; i++) {
5045 if (eg_pi->sclk_deep_sleep) {
5046 if ((i == 0) || si_pi->sclk_deep_sleep_above_low) {
5047 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ)
5048 smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS;
5049 else
5050 smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE;
5051 }
5052 }
5053
5054 ret = si_convert_power_level_to_smc(rdev, &state->performance_levels[i],
5055 &smc_state->levels[i]);
5056 smc_state->levels[i].arbRefreshState =
5057 (u8)(SISLANDS_DRIVER_STATE_ARB_INDEX + i);
5058
5059 if (ret)
5060 return ret;
5061
5062 if (ni_pi->enable_power_containment)
5063 smc_state->levels[i].displayWatermark =
5064 (state->performance_levels[i].sclk < threshold) ?
5065 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH;
5066 else
5067 smc_state->levels[i].displayWatermark = (i < 2) ?
5068 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH;
5069
5070 if (eg_pi->dynamic_ac_timing)
5071 smc_state->levels[i].ACIndex = SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i;
5072 else
5073 smc_state->levels[i].ACIndex = 0;
5074
5075 smc_state->levelCount++;
5076 }
5077
5078 si_write_smc_soft_register(rdev,
5079 SI_SMC_SOFT_REGISTER_watermark_threshold,
5080 threshold / 512);
5081
5082 si_populate_smc_sp(rdev, radeon_state, smc_state);
5083
5084 ret = si_populate_power_containment_values(rdev, radeon_state, smc_state);
5085 if (ret)
5086 ni_pi->enable_power_containment = false;
5087
5088 ret = si_populate_sq_ramping_values(rdev, radeon_state, smc_state);
5089 if (ret)
5090 ni_pi->enable_sq_ramping = false;
5091
5092 return si_populate_smc_t(rdev, radeon_state, smc_state);
5093 }
5094
5095 static int si_upload_sw_state(struct radeon_device *rdev,
5096 struct radeon_ps *radeon_new_state)
5097 {
5098 struct si_power_info *si_pi = si_get_pi(rdev);
5099 struct ni_ps *new_state = ni_get_ps(radeon_new_state);
5100 int ret;
5101 u32 address = si_pi->state_table_start +
5102 offsetof(SISLANDS_SMC_STATETABLE, driverState);
5103 u32 state_size = sizeof(SISLANDS_SMC_SWSTATE) +
5104 ((new_state->performance_level_count - 1) *
5105 sizeof(SISLANDS_SMC_HW_PERFORMANCE_LEVEL));
5106 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.driverState;
5107
5108 memset(smc_state, 0, state_size);
5109
5110 ret = si_convert_power_state_to_smc(rdev, radeon_new_state, smc_state);
5111 if (ret)
5112 return ret;
5113
5114 ret = si_copy_bytes_to_smc(rdev, address, (u8 *)smc_state,
5115 state_size, si_pi->sram_end);
5116
5117 return ret;
5118 }
5119
5120 static int si_upload_ulv_state(struct radeon_device *rdev)
5121 {
5122 struct si_power_info *si_pi = si_get_pi(rdev);
5123 struct si_ulv_param *ulv = &si_pi->ulv;
5124 int ret = 0;
5125
5126 if (ulv->supported && ulv->pl.vddc) {
5127 u32 address = si_pi->state_table_start +
5128 offsetof(SISLANDS_SMC_STATETABLE, ULVState);
5129 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.ULVState;
5130 u32 state_size = sizeof(SISLANDS_SMC_SWSTATE);
5131
5132 memset(smc_state, 0, state_size);
5133
5134 ret = si_populate_ulv_state(rdev, smc_state);
5135 if (!ret)
5136 ret = si_copy_bytes_to_smc(rdev, address, (u8 *)smc_state,
5137 state_size, si_pi->sram_end);
5138 }
5139
5140 return ret;
5141 }
5142
5143 static int si_upload_smc_data(struct radeon_device *rdev)
5144 {
5145 struct radeon_crtc *radeon_crtc = NULL;
5146 int i;
5147
5148 if (rdev->pm.dpm.new_active_crtc_count == 0)
5149 return 0;
5150
5151 for (i = 0; i < rdev->num_crtc; i++) {
5152 if (rdev->pm.dpm.new_active_crtcs & (1 << i)) {
5153 radeon_crtc = rdev->mode_info.crtcs[i];
5154 break;
5155 }
5156 }
5157
5158 if (radeon_crtc == NULL)
5159 return 0;
5160
5161 if (radeon_crtc->line_time <= 0)
5162 return 0;
5163
5164 if (si_write_smc_soft_register(rdev,
5165 SI_SMC_SOFT_REGISTER_crtc_index,
5166 radeon_crtc->crtc_id) != PPSMC_Result_OK)
5167 return 0;
5168
5169 if (si_write_smc_soft_register(rdev,
5170 SI_SMC_SOFT_REGISTER_mclk_change_block_cp_min,
5171 radeon_crtc->wm_high / radeon_crtc->line_time) != PPSMC_Result_OK)
5172 return 0;
5173
5174 if (si_write_smc_soft_register(rdev,
5175 SI_SMC_SOFT_REGISTER_mclk_change_block_cp_max,
5176 radeon_crtc->wm_low / radeon_crtc->line_time) != PPSMC_Result_OK)
5177 return 0;
5178
5179 return 0;
5180 }
5181
5182 static int si_set_mc_special_registers(struct radeon_device *rdev,
5183 struct si_mc_reg_table *table)
5184 {
5185 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
5186 u8 i, j, k;
5187 u32 temp_reg;
5188
5189 for (i = 0, j = table->last; i < table->last; i++) {
5190 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5191 return -EINVAL;
5192 switch (table->mc_reg_address[i].s1 << 2) {
5193 case MC_SEQ_MISC1:
5194 temp_reg = RREG32(MC_PMG_CMD_EMRS);
5195 table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS >> 2;
5196 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2;
5197 for (k = 0; k < table->num_entries; k++)
5198 table->mc_reg_table_entry[k].mc_data[j] =
5199 ((temp_reg & 0xffff0000)) |
5200 ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
5201 j++;
5202 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5203 return -EINVAL;
5204
5205 temp_reg = RREG32(MC_PMG_CMD_MRS);
5206 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS >> 2;
5207 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2;
5208 for (k = 0; k < table->num_entries; k++) {
5209 table->mc_reg_table_entry[k].mc_data[j] =
5210 (temp_reg & 0xffff0000) |
5211 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
5212 if (!pi->mem_gddr5)
5213 table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
5214 }
5215 j++;
5216 if (j > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5217 return -EINVAL;
5218
5219 if (!pi->mem_gddr5) {
5220 table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD >> 2;
5221 table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD >> 2;
5222 for (k = 0; k < table->num_entries; k++)
5223 table->mc_reg_table_entry[k].mc_data[j] =
5224 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;
5225 j++;
5226 if (j > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5227 return -EINVAL;
5228 }
5229 break;
5230 case MC_SEQ_RESERVE_M:
5231 temp_reg = RREG32(MC_PMG_CMD_MRS1);
5232 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1 >> 2;
5233 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2;
5234 for(k = 0; k < table->num_entries; k++)
5235 table->mc_reg_table_entry[k].mc_data[j] =
5236 (temp_reg & 0xffff0000) |
5237 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
5238 j++;
5239 if (j > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5240 return -EINVAL;
5241 break;
5242 default:
5243 break;
5244 }
5245 }
5246
5247 table->last = j;
5248
5249 return 0;
5250 }
5251
5252 static bool si_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg)
5253 {
5254 bool result = true;
5255
5256 switch (in_reg) {
5257 case MC_SEQ_RAS_TIMING >> 2:
5258 *out_reg = MC_SEQ_RAS_TIMING_LP >> 2;
5259 break;
5260 case MC_SEQ_CAS_TIMING >> 2:
5261 *out_reg = MC_SEQ_CAS_TIMING_LP >> 2;
5262 break;
5263 case MC_SEQ_MISC_TIMING >> 2:
5264 *out_reg = MC_SEQ_MISC_TIMING_LP >> 2;
5265 break;
5266 case MC_SEQ_MISC_TIMING2 >> 2:
5267 *out_reg = MC_SEQ_MISC_TIMING2_LP >> 2;
5268 break;
5269 case MC_SEQ_RD_CTL_D0 >> 2:
5270 *out_reg = MC_SEQ_RD_CTL_D0_LP >> 2;
5271 break;
5272 case MC_SEQ_RD_CTL_D1 >> 2:
5273 *out_reg = MC_SEQ_RD_CTL_D1_LP >> 2;
5274 break;
5275 case MC_SEQ_WR_CTL_D0 >> 2:
5276 *out_reg = MC_SEQ_WR_CTL_D0_LP >> 2;
5277 break;
5278 case MC_SEQ_WR_CTL_D1 >> 2:
5279 *out_reg = MC_SEQ_WR_CTL_D1_LP >> 2;
5280 break;
5281 case MC_PMG_CMD_EMRS >> 2:
5282 *out_reg = MC_SEQ_PMG_CMD_EMRS_LP >> 2;
5283 break;
5284 case MC_PMG_CMD_MRS >> 2:
5285 *out_reg = MC_SEQ_PMG_CMD_MRS_LP >> 2;
5286 break;
5287 case MC_PMG_CMD_MRS1 >> 2:
5288 *out_reg = MC_SEQ_PMG_CMD_MRS1_LP >> 2;
5289 break;
5290 case MC_SEQ_PMG_TIMING >> 2:
5291 *out_reg = MC_SEQ_PMG_TIMING_LP >> 2;
5292 break;
5293 case MC_PMG_CMD_MRS2 >> 2:
5294 *out_reg = MC_SEQ_PMG_CMD_MRS2_LP >> 2;
5295 break;
5296 case MC_SEQ_WR_CTL_2 >> 2:
5297 *out_reg = MC_SEQ_WR_CTL_2_LP >> 2;
5298 break;
5299 default:
5300 result = false;
5301 break;
5302 }
5303
5304 return result;
5305 }
5306
5307 static void si_set_valid_flag(struct si_mc_reg_table *table)
5308 {
5309 u8 i, j;
5310
5311 for (i = 0; i < table->last; i++) {
5312 for (j = 1; j < table->num_entries; j++) {
5313 if (table->mc_reg_table_entry[j-1].mc_data[i] != table->mc_reg_table_entry[j].mc_data[i]) {
5314 table->valid_flag |= 1 << i;
5315 break;
5316 }
5317 }
5318 }
5319 }
5320
5321 static void si_set_s0_mc_reg_index(struct si_mc_reg_table *table)
5322 {
5323 u32 i;
5324 u16 address;
5325
5326 for (i = 0; i < table->last; i++)
5327 table->mc_reg_address[i].s0 = si_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ?
5328 address : table->mc_reg_address[i].s1;
5329
5330 }
5331
5332 static int si_copy_vbios_mc_reg_table(struct atom_mc_reg_table *table,
5333 struct si_mc_reg_table *si_table)
5334 {
5335 u8 i, j;
5336
5337 if (table->last > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5338 return -EINVAL;
5339 if (table->num_entries > MAX_AC_TIMING_ENTRIES)
5340 return -EINVAL;
5341
5342 for (i = 0; i < table->last; i++)
5343 si_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1;
5344 si_table->last = table->last;
5345
5346 for (i = 0; i < table->num_entries; i++) {
5347 si_table->mc_reg_table_entry[i].mclk_max =
5348 table->mc_reg_table_entry[i].mclk_max;
5349 for (j = 0; j < table->last; j++) {
5350 si_table->mc_reg_table_entry[i].mc_data[j] =
5351 table->mc_reg_table_entry[i].mc_data[j];
5352 }
5353 }
5354 si_table->num_entries = table->num_entries;
5355
5356 return 0;
5357 }
5358
5359 static int si_initialize_mc_reg_table(struct radeon_device *rdev)
5360 {
5361 struct si_power_info *si_pi = si_get_pi(rdev);
5362 struct atom_mc_reg_table *table;
5363 struct si_mc_reg_table *si_table = &si_pi->mc_reg_table;
5364 u8 module_index = rv770_get_memory_module_index(rdev);
5365 int ret;
5366
5367 table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL);
5368 if (!table)
5369 return -ENOMEM;
5370
5371 WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING));
5372 WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING));
5373 WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING));
5374 WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2));
5375 WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS));
5376 WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS));
5377 WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1));
5378 WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0));
5379 WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));
5380 WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0));
5381 WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1));
5382 WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING));
5383 WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2));
5384 WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2));
5385
5386 ret = radeon_atom_init_mc_reg_table(rdev, module_index, table);
5387 if (ret)
5388 goto init_mc_done;
5389
5390 ret = si_copy_vbios_mc_reg_table(table, si_table);
5391 if (ret)
5392 goto init_mc_done;
5393
5394 si_set_s0_mc_reg_index(si_table);
5395
5396 ret = si_set_mc_special_registers(rdev, si_table);
5397 if (ret)
5398 goto init_mc_done;
5399
5400 si_set_valid_flag(si_table);
5401
5402 init_mc_done:
5403 kfree(table);
5404
5405 return ret;
5406
5407 }
5408
5409 static void si_populate_mc_reg_addresses(struct radeon_device *rdev,
5410 SMC_SIslands_MCRegisters *mc_reg_table)
5411 {
5412 struct si_power_info *si_pi = si_get_pi(rdev);
5413 u32 i, j;
5414
5415 for (i = 0, j = 0; j < si_pi->mc_reg_table.last; j++) {
5416 if (si_pi->mc_reg_table.valid_flag & (1 << j)) {
5417 if (i >= SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE)
5418 break;
5419 mc_reg_table->address[i].s0 =
5420 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s0);
5421 mc_reg_table->address[i].s1 =
5422 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s1);
5423 i++;
5424 }
5425 }
5426 mc_reg_table->last = (u8)i;
5427 }
5428
5429 static void si_convert_mc_registers(const struct si_mc_reg_entry *entry,
5430 SMC_SIslands_MCRegisterSet *data,
5431 u32 num_entries, u32 valid_flag)
5432 {
5433 u32 i, j;
5434
5435 for(i = 0, j = 0; j < num_entries; j++) {
5436 if (valid_flag & (1 << j)) {
5437 data->value[i] = cpu_to_be32(entry->mc_data[j]);
5438 i++;
5439 }
5440 }
5441 }
5442
5443 static void si_convert_mc_reg_table_entry_to_smc(struct radeon_device *rdev,
5444 struct rv7xx_pl *pl,
5445 SMC_SIslands_MCRegisterSet *mc_reg_table_data)
5446 {
5447 struct si_power_info *si_pi = si_get_pi(rdev);
5448 u32 i = 0;
5449
5450 for (i = 0; i < si_pi->mc_reg_table.num_entries; i++) {
5451 if (pl->mclk <= si_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max)
5452 break;
5453 }
5454
5455 if ((i == si_pi->mc_reg_table.num_entries) && (i > 0))
5456 --i;
5457
5458 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[i],
5459 mc_reg_table_data, si_pi->mc_reg_table.last,
5460 si_pi->mc_reg_table.valid_flag);
5461 }
5462
5463 static void si_convert_mc_reg_table_to_smc(struct radeon_device *rdev,
5464 struct radeon_ps *radeon_state,
5465 SMC_SIslands_MCRegisters *mc_reg_table)
5466 {
5467 struct ni_ps *state = ni_get_ps(radeon_state);
5468 int i;
5469
5470 for (i = 0; i < state->performance_level_count; i++) {
5471 si_convert_mc_reg_table_entry_to_smc(rdev,
5472 &state->performance_levels[i],
5473 &mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i]);
5474 }
5475 }
5476
5477 static int si_populate_mc_reg_table(struct radeon_device *rdev,
5478 struct radeon_ps *radeon_boot_state)
5479 {
5480 struct ni_ps *boot_state = ni_get_ps(radeon_boot_state);
5481 struct si_power_info *si_pi = si_get_pi(rdev);
5482 struct si_ulv_param *ulv = &si_pi->ulv;
5483 SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table;
5484
5485 memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters));
5486
5487 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_seq_index, 1);
5488
5489 si_populate_mc_reg_addresses(rdev, smc_mc_reg_table);
5490
5491 si_convert_mc_reg_table_entry_to_smc(rdev, &boot_state->performance_levels[0],
5492 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_INITIAL_SLOT]);
5493
5494 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0],
5495 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ACPI_SLOT],
5496 si_pi->mc_reg_table.last,
5497 si_pi->mc_reg_table.valid_flag);
5498
5499 if (ulv->supported && ulv->pl.vddc != 0)
5500 si_convert_mc_reg_table_entry_to_smc(rdev, &ulv->pl,
5501 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT]);
5502 else
5503 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0],
5504 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT],
5505 si_pi->mc_reg_table.last,
5506 si_pi->mc_reg_table.valid_flag);
5507
5508 si_convert_mc_reg_table_to_smc(rdev, radeon_boot_state, smc_mc_reg_table);
5509
5510 return si_copy_bytes_to_smc(rdev, si_pi->mc_reg_table_start,
5511 (u8 *)smc_mc_reg_table,
5512 sizeof(SMC_SIslands_MCRegisters), si_pi->sram_end);
5513 }
5514
5515 static int si_upload_mc_reg_table(struct radeon_device *rdev,
5516 struct radeon_ps *radeon_new_state)
5517 {
5518 struct ni_ps *new_state = ni_get_ps(radeon_new_state);
5519 struct si_power_info *si_pi = si_get_pi(rdev);
5520 u32 address = si_pi->mc_reg_table_start +
5521 offsetof(SMC_SIslands_MCRegisters,
5522 data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT]);
5523 SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table;
5524
5525 memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters));
5526
5527 si_convert_mc_reg_table_to_smc(rdev, radeon_new_state, smc_mc_reg_table);
5528
5529
5530 return si_copy_bytes_to_smc(rdev, address,
5531 (u8 *)&smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT],
5532 sizeof(SMC_SIslands_MCRegisterSet) * new_state->performance_level_count,
5533 si_pi->sram_end);
5534
5535 }
5536
5537 static void si_enable_voltage_control(struct radeon_device *rdev, bool enable)
5538 {
5539 if (enable)
5540 WREG32_P(GENERAL_PWRMGT, VOLT_PWRMGT_EN, ~VOLT_PWRMGT_EN);
5541 else
5542 WREG32_P(GENERAL_PWRMGT, 0, ~VOLT_PWRMGT_EN);
5543 }
5544
5545 static enum radeon_pcie_gen si_get_maximum_link_speed(struct radeon_device *rdev,
5546 struct radeon_ps *radeon_state)
5547 {
5548 struct ni_ps *state = ni_get_ps(radeon_state);
5549 int i;
5550 u16 pcie_speed, max_speed = 0;
5551
5552 for (i = 0; i < state->performance_level_count; i++) {
5553 pcie_speed = state->performance_levels[i].pcie_gen;
5554 if (max_speed < pcie_speed)
5555 max_speed = pcie_speed;
5556 }
5557 return max_speed;
5558 }
5559
5560 static u16 si_get_current_pcie_speed(struct radeon_device *rdev)
5561 {
5562 u32 speed_cntl;
5563
5564 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL) & LC_CURRENT_DATA_RATE_MASK;
5565 speed_cntl >>= LC_CURRENT_DATA_RATE_SHIFT;
5566
5567 return (u16)speed_cntl;
5568 }
5569
5570 static void si_request_link_speed_change_before_state_change(struct radeon_device *rdev,
5571 struct radeon_ps *radeon_new_state,
5572 struct radeon_ps *radeon_current_state)
5573 {
5574 struct si_power_info *si_pi = si_get_pi(rdev);
5575 enum radeon_pcie_gen target_link_speed = si_get_maximum_link_speed(rdev, radeon_new_state);
5576 enum radeon_pcie_gen current_link_speed;
5577
5578 if (si_pi->force_pcie_gen == RADEON_PCIE_GEN_INVALID)
5579 current_link_speed = si_get_maximum_link_speed(rdev, radeon_current_state);
5580 else
5581 current_link_speed = si_pi->force_pcie_gen;
5582
5583 si_pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID;
5584 si_pi->pspp_notify_required = false;
5585 if (target_link_speed > current_link_speed) {
5586 switch (target_link_speed) {
5587 #if defined(CONFIG_ACPI)
5588 case RADEON_PCIE_GEN3:
5589 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN3, false) == 0)
5590 break;
5591 si_pi->force_pcie_gen = RADEON_PCIE_GEN2;
5592 if (current_link_speed == RADEON_PCIE_GEN2)
5593 break;
5594 case RADEON_PCIE_GEN2:
5595 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN2, false) == 0)
5596 break;
5597 #endif
5598 default:
5599 si_pi->force_pcie_gen = si_get_current_pcie_speed(rdev);
5600 break;
5601 }
5602 } else {
5603 if (target_link_speed < current_link_speed)
5604 si_pi->pspp_notify_required = true;
5605 }
5606 }
5607
5608 static void si_notify_link_speed_change_after_state_change(struct radeon_device *rdev,
5609 struct radeon_ps *radeon_new_state,
5610 struct radeon_ps *radeon_current_state)
5611 {
5612 struct si_power_info *si_pi = si_get_pi(rdev);
5613 enum radeon_pcie_gen target_link_speed = si_get_maximum_link_speed(rdev, radeon_new_state);
5614 u8 request;
5615
5616 if (si_pi->pspp_notify_required) {
5617 if (target_link_speed == RADEON_PCIE_GEN3)
5618 request = PCIE_PERF_REQ_PECI_GEN3;
5619 else if (target_link_speed == RADEON_PCIE_GEN2)
5620 request = PCIE_PERF_REQ_PECI_GEN2;
5621 else
5622 request = PCIE_PERF_REQ_PECI_GEN1;
5623
5624 if ((request == PCIE_PERF_REQ_PECI_GEN1) &&
5625 (si_get_current_pcie_speed(rdev) > 0))
5626 return;
5627
5628 #if defined(CONFIG_ACPI)
5629 radeon_acpi_pcie_performance_request(rdev, request, false);
5630 #endif
5631 }
5632 }
5633
5634 #if 0
5635 static int si_ds_request(struct radeon_device *rdev,
5636 bool ds_status_on, u32 count_write)
5637 {
5638 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
5639
5640 if (eg_pi->sclk_deep_sleep) {
5641 if (ds_status_on)
5642 return (si_send_msg_to_smc(rdev, PPSMC_MSG_CancelThrottleOVRDSCLKDS) ==
5643 PPSMC_Result_OK) ?
5644 0 : -EINVAL;
5645 else
5646 return (si_send_msg_to_smc(rdev, PPSMC_MSG_ThrottleOVRDSCLKDS) ==
5647 PPSMC_Result_OK) ? 0 : -EINVAL;
5648 }
5649 return 0;
5650 }
5651 #endif
5652
5653 static void si_set_max_cu_value(struct radeon_device *rdev)
5654 {
5655 struct si_power_info *si_pi = si_get_pi(rdev);
5656
5657 if (rdev->family == CHIP_VERDE) {
5658 switch (rdev->pdev->device) {
5659 case 0x6820:
5660 case 0x6825:
5661 case 0x6821:
5662 case 0x6823:
5663 case 0x6827:
5664 si_pi->max_cu = 10;
5665 break;
5666 case 0x682D:
5667 case 0x6824:
5668 case 0x682F:
5669 case 0x6826:
5670 si_pi->max_cu = 8;
5671 break;
5672 case 0x6828:
5673 case 0x6830:
5674 case 0x6831:
5675 case 0x6838:
5676 case 0x6839:
5677 case 0x683D:
5678 si_pi->max_cu = 10;
5679 break;
5680 case 0x683B:
5681 case 0x683F:
5682 case 0x6829:
5683 si_pi->max_cu = 8;
5684 break;
5685 default:
5686 si_pi->max_cu = 0;
5687 break;
5688 }
5689 } else {
5690 si_pi->max_cu = 0;
5691 }
5692 }
5693
5694 static int si_patch_single_dependency_table_based_on_leakage(struct radeon_device *rdev,
5695 struct radeon_clock_voltage_dependency_table *table)
5696 {
5697 u32 i;
5698 int j;
5699 u16 leakage_voltage;
5700
5701 if (table) {
5702 for (i = 0; i < table->count; i++) {
5703 switch (si_get_leakage_voltage_from_leakage_index(rdev,
5704 table->entries[i].v,
5705 &leakage_voltage)) {
5706 case 0:
5707 table->entries[i].v = leakage_voltage;
5708 break;
5709 case -EAGAIN:
5710 return -EINVAL;
5711 case -EINVAL:
5712 default:
5713 break;
5714 }
5715 }
5716
5717 for (j = (table->count - 2); j >= 0; j--) {
5718 table->entries[j].v = (table->entries[j].v <= table->entries[j + 1].v) ?
5719 table->entries[j].v : table->entries[j + 1].v;
5720 }
5721 }
5722 return 0;
5723 }
5724
5725 static int si_patch_dependency_tables_based_on_leakage(struct radeon_device *rdev)
5726 {
5727 int ret = 0;
5728
5729 ret = si_patch_single_dependency_table_based_on_leakage(rdev,
5730 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk);
5731 ret = si_patch_single_dependency_table_based_on_leakage(rdev,
5732 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk);
5733 ret = si_patch_single_dependency_table_based_on_leakage(rdev,
5734 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk);
5735 return ret;
5736 }
5737
5738 static void si_set_pcie_lane_width_in_smc(struct radeon_device *rdev,
5739 struct radeon_ps *radeon_new_state,
5740 struct radeon_ps *radeon_current_state)
5741 {
5742 u32 lane_width;
5743 u32 new_lane_width =
5744 (radeon_new_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT;
5745 u32 current_lane_width =
5746 (radeon_current_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT;
5747
5748 if (new_lane_width != current_lane_width) {
5749 radeon_set_pcie_lanes(rdev, new_lane_width);
5750 lane_width = radeon_get_pcie_lanes(rdev);
5751 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width);
5752 }
5753 }
5754
5755 void si_dpm_setup_asic(struct radeon_device *rdev)
5756 {
5757 rv770_get_memory_type(rdev);
5758 si_read_clock_registers(rdev);
5759 si_enable_acpi_power_management(rdev);
5760 }
5761
5762 static int si_set_thermal_temperature_range(struct radeon_device *rdev,
5763 int min_temp, int max_temp)
5764 {
5765 int low_temp = 0 * 1000;
5766 int high_temp = 255 * 1000;
5767
5768 if (low_temp < min_temp)
5769 low_temp = min_temp;
5770 if (high_temp > max_temp)
5771 high_temp = max_temp;
5772 if (high_temp < low_temp) {
5773 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp);
5774 return -EINVAL;
5775 }
5776
5777 WREG32_P(CG_THERMAL_INT, DIG_THERM_INTH(high_temp / 1000), ~DIG_THERM_INTH_MASK);
5778 WREG32_P(CG_THERMAL_INT, DIG_THERM_INTL(low_temp / 1000), ~DIG_THERM_INTL_MASK);
5779 WREG32_P(CG_THERMAL_CTRL, DIG_THERM_DPM(high_temp / 1000), ~DIG_THERM_DPM_MASK);
5780
5781 rdev->pm.dpm.thermal.min_temp = low_temp;
5782 rdev->pm.dpm.thermal.max_temp = high_temp;
5783
5784 return 0;
5785 }
5786
5787 int si_dpm_enable(struct radeon_device *rdev)
5788 {
5789 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
5790 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
5791 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
5792 int ret;
5793
5794 si_update_cg(rdev, (RADEON_CG_BLOCK_GFX |
5795 RADEON_CG_BLOCK_MC |
5796 RADEON_CG_BLOCK_SDMA |
5797 RADEON_CG_BLOCK_BIF |
5798 RADEON_CG_BLOCK_UVD |
5799 RADEON_CG_BLOCK_HDP), false);
5800
5801 if (si_is_smc_running(rdev))
5802 return -EINVAL;
5803 if (pi->voltage_control)
5804 si_enable_voltage_control(rdev, true);
5805 if (pi->mvdd_control)
5806 si_get_mvdd_configuration(rdev);
5807 if (pi->voltage_control) {
5808 ret = si_construct_voltage_tables(rdev);
5809 if (ret) {
5810 DRM_ERROR("si_construct_voltage_tables failed\n");
5811 return ret;
5812 }
5813 }
5814 if (eg_pi->dynamic_ac_timing) {
5815 ret = si_initialize_mc_reg_table(rdev);
5816 if (ret)
5817 eg_pi->dynamic_ac_timing = false;
5818 }
5819 if (pi->dynamic_ss)
5820 si_enable_spread_spectrum(rdev, true);
5821 if (pi->thermal_protection)
5822 si_enable_thermal_protection(rdev, true);
5823 si_setup_bsp(rdev);
5824 si_program_git(rdev);
5825 si_program_tp(rdev);
5826 si_program_tpp(rdev);
5827 si_program_sstp(rdev);
5828 si_enable_display_gap(rdev);
5829 si_program_vc(rdev);
5830 ret = si_upload_firmware(rdev);
5831 if (ret) {
5832 DRM_ERROR("si_upload_firmware failed\n");
5833 return ret;
5834 }
5835 ret = si_process_firmware_header(rdev);
5836 if (ret) {
5837 DRM_ERROR("si_process_firmware_header failed\n");
5838 return ret;
5839 }
5840 ret = si_initial_switch_from_arb_f0_to_f1(rdev);
5841 if (ret) {
5842 DRM_ERROR("si_initial_switch_from_arb_f0_to_f1 failed\n");
5843 return ret;
5844 }
5845 ret = si_init_smc_table(rdev);
5846 if (ret) {
5847 DRM_ERROR("si_init_smc_table failed\n");
5848 return ret;
5849 }
5850 ret = si_init_smc_spll_table(rdev);
5851 if (ret) {
5852 DRM_ERROR("si_init_smc_spll_table failed\n");
5853 return ret;
5854 }
5855 ret = si_init_arb_table_index(rdev);
5856 if (ret) {
5857 DRM_ERROR("si_init_arb_table_index failed\n");
5858 return ret;
5859 }
5860 if (eg_pi->dynamic_ac_timing) {
5861 ret = si_populate_mc_reg_table(rdev, boot_ps);
5862 if (ret) {
5863 DRM_ERROR("si_populate_mc_reg_table failed\n");
5864 return ret;
5865 }
5866 }
5867 ret = si_initialize_smc_cac_tables(rdev);
5868 if (ret) {
5869 DRM_ERROR("si_initialize_smc_cac_tables failed\n");
5870 return ret;
5871 }
5872 ret = si_initialize_hardware_cac_manager(rdev);
5873 if (ret) {
5874 DRM_ERROR("si_initialize_hardware_cac_manager failed\n");
5875 return ret;
5876 }
5877 ret = si_initialize_smc_dte_tables(rdev);
5878 if (ret) {
5879 DRM_ERROR("si_initialize_smc_dte_tables failed\n");
5880 return ret;
5881 }
5882 ret = si_populate_smc_tdp_limits(rdev, boot_ps);
5883 if (ret) {
5884 DRM_ERROR("si_populate_smc_tdp_limits failed\n");
5885 return ret;
5886 }
5887 ret = si_populate_smc_tdp_limits_2(rdev, boot_ps);
5888 if (ret) {
5889 DRM_ERROR("si_populate_smc_tdp_limits_2 failed\n");
5890 return ret;
5891 }
5892 si_program_response_times(rdev);
5893 si_program_ds_registers(rdev);
5894 si_dpm_start_smc(rdev);
5895 ret = si_notify_smc_display_change(rdev, false);
5896 if (ret) {
5897 DRM_ERROR("si_notify_smc_display_change failed\n");
5898 return ret;
5899 }
5900 si_enable_sclk_control(rdev, true);
5901 si_start_dpm(rdev);
5902
5903 if (rdev->irq.installed &&
5904 r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) {
5905 PPSMC_Result result;
5906
5907 ret = si_set_thermal_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
5908 if (ret)
5909 return ret;
5910 rdev->irq.dpm_thermal = true;
5911 radeon_irq_set(rdev);
5912 result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt);
5913
5914 if (result != PPSMC_Result_OK)
5915 DRM_DEBUG_KMS("Could not enable thermal interrupts.\n");
5916 }
5917
5918 si_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true);
5919
5920 si_update_cg(rdev, (RADEON_CG_BLOCK_GFX |
5921 RADEON_CG_BLOCK_MC |
5922 RADEON_CG_BLOCK_SDMA |
5923 RADEON_CG_BLOCK_BIF |
5924 RADEON_CG_BLOCK_UVD |
5925 RADEON_CG_BLOCK_HDP), true);
5926
5927 ni_update_current_ps(rdev, boot_ps);
5928
5929 return 0;
5930 }
5931
5932 void si_dpm_disable(struct radeon_device *rdev)
5933 {
5934 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
5935 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
5936
5937 si_update_cg(rdev, (RADEON_CG_BLOCK_GFX |
5938 RADEON_CG_BLOCK_MC |
5939 RADEON_CG_BLOCK_SDMA |
5940 RADEON_CG_BLOCK_BIF |
5941 RADEON_CG_BLOCK_UVD |
5942 RADEON_CG_BLOCK_HDP), false);
5943
5944 if (!si_is_smc_running(rdev))
5945 return;
5946 si_disable_ulv(rdev);
5947 si_clear_vc(rdev);
5948 if (pi->thermal_protection)
5949 si_enable_thermal_protection(rdev, false);
5950 si_enable_power_containment(rdev, boot_ps, false);
5951 si_enable_smc_cac(rdev, boot_ps, false);
5952 si_enable_spread_spectrum(rdev, false);
5953 si_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, false);
5954 si_stop_dpm(rdev);
5955 si_reset_to_default(rdev);
5956 si_dpm_stop_smc(rdev);
5957 si_force_switch_to_arb_f0(rdev);
5958
5959 ni_update_current_ps(rdev, boot_ps);
5960 }
5961
5962 int si_dpm_pre_set_power_state(struct radeon_device *rdev)
5963 {
5964 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
5965 struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps;
5966 struct radeon_ps *new_ps = &requested_ps;
5967
5968 ni_update_requested_ps(rdev, new_ps);
5969
5970 si_apply_state_adjust_rules(rdev, &eg_pi->requested_rps);
5971
5972 return 0;
5973 }
5974
5975 static int si_power_control_set_level(struct radeon_device *rdev)
5976 {
5977 struct radeon_ps *new_ps = rdev->pm.dpm.requested_ps;
5978 int ret;
5979
5980 ret = si_restrict_performance_levels_before_switch(rdev);
5981 if (ret)
5982 return ret;
5983 ret = si_halt_smc(rdev);
5984 if (ret)
5985 return ret;
5986 ret = si_populate_smc_tdp_limits(rdev, new_ps);
5987 if (ret)
5988 return ret;
5989 ret = si_populate_smc_tdp_limits_2(rdev, new_ps);
5990 if (ret)
5991 return ret;
5992 ret = si_resume_smc(rdev);
5993 if (ret)
5994 return ret;
5995 ret = si_set_sw_state(rdev);
5996 if (ret)
5997 return ret;
5998 return 0;
5999 }
6000
6001 int si_dpm_set_power_state(struct radeon_device *rdev)
6002 {
6003 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6004 struct radeon_ps *new_ps = &eg_pi->requested_rps;
6005 struct radeon_ps *old_ps = &eg_pi->current_rps;
6006 int ret;
6007
6008 si_update_cg(rdev, (RADEON_CG_BLOCK_GFX |
6009 RADEON_CG_BLOCK_MC |
6010 RADEON_CG_BLOCK_SDMA |
6011 RADEON_CG_BLOCK_BIF |
6012 RADEON_CG_BLOCK_UVD |
6013 RADEON_CG_BLOCK_HDP), false);
6014
6015 ret = si_disable_ulv(rdev);
6016 if (ret) {
6017 DRM_ERROR("si_disable_ulv failed\n");
6018 return ret;
6019 }
6020 ret = si_restrict_performance_levels_before_switch(rdev);
6021 if (ret) {
6022 DRM_ERROR("si_restrict_performance_levels_before_switch failed\n");
6023 return ret;
6024 }
6025 if (eg_pi->pcie_performance_request)
6026 si_request_link_speed_change_before_state_change(rdev, new_ps, old_ps);
6027 ni_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps);
6028 ret = si_enable_power_containment(rdev, new_ps, false);
6029 if (ret) {
6030 DRM_ERROR("si_enable_power_containment failed\n");
6031 return ret;
6032 }
6033 ret = si_enable_smc_cac(rdev, new_ps, false);
6034 if (ret) {
6035 DRM_ERROR("si_enable_smc_cac failed\n");
6036 return ret;
6037 }
6038 ret = si_halt_smc(rdev);
6039 if (ret) {
6040 DRM_ERROR("si_halt_smc failed\n");
6041 return ret;
6042 }
6043 ret = si_upload_sw_state(rdev, new_ps);
6044 if (ret) {
6045 DRM_ERROR("si_upload_sw_state failed\n");
6046 return ret;
6047 }
6048 ret = si_upload_smc_data(rdev);
6049 if (ret) {
6050 DRM_ERROR("si_upload_smc_data failed\n");
6051 return ret;
6052 }
6053 ret = si_upload_ulv_state(rdev);
6054 if (ret) {
6055 DRM_ERROR("si_upload_ulv_state failed\n");
6056 return ret;
6057 }
6058 if (eg_pi->dynamic_ac_timing) {
6059 ret = si_upload_mc_reg_table(rdev, new_ps);
6060 if (ret) {
6061 DRM_ERROR("si_upload_mc_reg_table failed\n");
6062 return ret;
6063 }
6064 }
6065 ret = si_program_memory_timing_parameters(rdev, new_ps);
6066 if (ret) {
6067 DRM_ERROR("si_program_memory_timing_parameters failed\n");
6068 return ret;
6069 }
6070 si_set_pcie_lane_width_in_smc(rdev, new_ps, old_ps);
6071
6072 ret = si_resume_smc(rdev);
6073 if (ret) {
6074 DRM_ERROR("si_resume_smc failed\n");
6075 return ret;
6076 }
6077 ret = si_set_sw_state(rdev);
6078 if (ret) {
6079 DRM_ERROR("si_set_sw_state failed\n");
6080 return ret;
6081 }
6082 ni_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps);
6083 if (eg_pi->pcie_performance_request)
6084 si_notify_link_speed_change_after_state_change(rdev, new_ps, old_ps);
6085 ret = si_set_power_state_conditionally_enable_ulv(rdev, new_ps);
6086 if (ret) {
6087 DRM_ERROR("si_set_power_state_conditionally_enable_ulv failed\n");
6088 return ret;
6089 }
6090 ret = si_enable_smc_cac(rdev, new_ps, true);
6091 if (ret) {
6092 DRM_ERROR("si_enable_smc_cac failed\n");
6093 return ret;
6094 }
6095 ret = si_enable_power_containment(rdev, new_ps, true);
6096 if (ret) {
6097 DRM_ERROR("si_enable_power_containment failed\n");
6098 return ret;
6099 }
6100
6101 ret = si_power_control_set_level(rdev);
6102 if (ret) {
6103 DRM_ERROR("si_power_control_set_level failed\n");
6104 return ret;
6105 }
6106
6107 si_update_cg(rdev, (RADEON_CG_BLOCK_GFX |
6108 RADEON_CG_BLOCK_MC |
6109 RADEON_CG_BLOCK_SDMA |
6110 RADEON_CG_BLOCK_BIF |
6111 RADEON_CG_BLOCK_UVD |
6112 RADEON_CG_BLOCK_HDP), true);
6113
6114 return 0;
6115 }
6116
6117 void si_dpm_post_set_power_state(struct radeon_device *rdev)
6118 {
6119 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6120 struct radeon_ps *new_ps = &eg_pi->requested_rps;
6121
6122 ni_update_current_ps(rdev, new_ps);
6123 }
6124
6125
6126 void si_dpm_reset_asic(struct radeon_device *rdev)
6127 {
6128 si_restrict_performance_levels_before_switch(rdev);
6129 si_disable_ulv(rdev);
6130 si_set_boot_state(rdev);
6131 }
6132
6133 void si_dpm_display_configuration_changed(struct radeon_device *rdev)
6134 {
6135 si_program_display_gap(rdev);
6136 }
6137
6138 union power_info {
6139 struct _ATOM_POWERPLAY_INFO info;
6140 struct _ATOM_POWERPLAY_INFO_V2 info_2;
6141 struct _ATOM_POWERPLAY_INFO_V3 info_3;
6142 struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
6143 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
6144 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
6145 };
6146
6147 union pplib_clock_info {
6148 struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
6149 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
6150 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
6151 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
6152 struct _ATOM_PPLIB_SI_CLOCK_INFO si;
6153 };
6154
6155 union pplib_power_state {
6156 struct _ATOM_PPLIB_STATE v1;
6157 struct _ATOM_PPLIB_STATE_V2 v2;
6158 };
6159
6160 static void si_parse_pplib_non_clock_info(struct radeon_device *rdev,
6161 struct radeon_ps *rps,
6162 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info,
6163 u8 table_rev)
6164 {
6165 rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);
6166 rps->class = le16_to_cpu(non_clock_info->usClassification);
6167 rps->class2 = le16_to_cpu(non_clock_info->usClassification2);
6168
6169 if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {
6170 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
6171 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
6172 } else if (r600_is_uvd_state(rps->class, rps->class2)) {
6173 rps->vclk = RV770_DEFAULT_VCLK_FREQ;
6174 rps->dclk = RV770_DEFAULT_DCLK_FREQ;
6175 } else {
6176 rps->vclk = 0;
6177 rps->dclk = 0;
6178 }
6179
6180 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT)
6181 rdev->pm.dpm.boot_ps = rps;
6182 if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
6183 rdev->pm.dpm.uvd_ps = rps;
6184 }
6185
6186 static void si_parse_pplib_clock_info(struct radeon_device *rdev,
6187 struct radeon_ps *rps, int index,
6188 union pplib_clock_info *clock_info)
6189 {
6190 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
6191 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6192 struct si_power_info *si_pi = si_get_pi(rdev);
6193 struct ni_ps *ps = ni_get_ps(rps);
6194 u16 leakage_voltage;
6195 struct rv7xx_pl *pl = &ps->performance_levels[index];
6196 int ret;
6197
6198 ps->performance_level_count = index + 1;
6199
6200 pl->sclk = le16_to_cpu(clock_info->si.usEngineClockLow);
6201 pl->sclk |= clock_info->si.ucEngineClockHigh << 16;
6202 pl->mclk = le16_to_cpu(clock_info->si.usMemoryClockLow);
6203 pl->mclk |= clock_info->si.ucMemoryClockHigh << 16;
6204
6205 pl->vddc = le16_to_cpu(clock_info->si.usVDDC);
6206 pl->vddci = le16_to_cpu(clock_info->si.usVDDCI);
6207 pl->flags = le32_to_cpu(clock_info->si.ulFlags);
6208 pl->pcie_gen = r600_get_pcie_gen_support(rdev,
6209 si_pi->sys_pcie_mask,
6210 si_pi->boot_pcie_gen,
6211 clock_info->si.ucPCIEGen);
6212
6213 /* patch up vddc if necessary */
6214 ret = si_get_leakage_voltage_from_leakage_index(rdev, pl->vddc,
6215 &leakage_voltage);
6216 if (ret == 0)
6217 pl->vddc = leakage_voltage;
6218
6219 if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) {
6220 pi->acpi_vddc = pl->vddc;
6221 eg_pi->acpi_vddci = pl->vddci;
6222 si_pi->acpi_pcie_gen = pl->pcie_gen;
6223 }
6224
6225 if ((rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) &&
6226 index == 0) {
6227 /* XXX disable for A0 tahiti */
6228 si_pi->ulv.supported = true;
6229 si_pi->ulv.pl = *pl;
6230 si_pi->ulv.one_pcie_lane_in_ulv = false;
6231 si_pi->ulv.volt_change_delay = SISLANDS_ULVVOLTAGECHANGEDELAY_DFLT;
6232 si_pi->ulv.cg_ulv_parameter = SISLANDS_CGULVPARAMETER_DFLT;
6233 si_pi->ulv.cg_ulv_control = SISLANDS_CGULVCONTROL_DFLT;
6234 }
6235
6236 if (pi->min_vddc_in_table > pl->vddc)
6237 pi->min_vddc_in_table = pl->vddc;
6238
6239 if (pi->max_vddc_in_table < pl->vddc)
6240 pi->max_vddc_in_table = pl->vddc;
6241
6242 /* patch up boot state */
6243 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {
6244 u16 vddc, vddci, mvdd;
6245 radeon_atombios_get_default_voltages(rdev, &vddc, &vddci, &mvdd);
6246 pl->mclk = rdev->clock.default_mclk;
6247 pl->sclk = rdev->clock.default_sclk;
6248 pl->vddc = vddc;
6249 pl->vddci = vddci;
6250 si_pi->mvdd_bootup_value = mvdd;
6251 }
6252
6253 if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) ==
6254 ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
6255 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk;
6256 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk;
6257 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc;
6258 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci;
6259 }
6260 }
6261
6262 static int si_parse_power_table(struct radeon_device *rdev)
6263 {
6264 struct radeon_mode_info *mode_info = &rdev->mode_info;
6265 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
6266 union pplib_power_state *power_state;
6267 int i, j, k, non_clock_array_index, clock_array_index;
6268 union pplib_clock_info *clock_info;
6269 struct _StateArray *state_array;
6270 struct _ClockInfoArray *clock_info_array;
6271 struct _NonClockInfoArray *non_clock_info_array;
6272 union power_info *power_info;
6273 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
6274 u16 data_offset;
6275 u8 frev, crev;
6276 u8 *power_state_offset;
6277 struct ni_ps *ps;
6278
6279 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
6280 &frev, &crev, &data_offset))
6281 return -EINVAL;
6282 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
6283
6284 state_array = (struct _StateArray *)
6285 (mode_info->atom_context->bios + data_offset +
6286 le16_to_cpu(power_info->pplib.usStateArrayOffset));
6287 clock_info_array = (struct _ClockInfoArray *)
6288 (mode_info->atom_context->bios + data_offset +
6289 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
6290 non_clock_info_array = (struct _NonClockInfoArray *)
6291 (mode_info->atom_context->bios + data_offset +
6292 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
6293
6294 rdev->pm.dpm.ps = kzalloc(sizeof(struct radeon_ps) *
6295 state_array->ucNumEntries, GFP_KERNEL);
6296 if (!rdev->pm.dpm.ps)
6297 return -ENOMEM;
6298 power_state_offset = (u8 *)state_array->states;
6299 rdev->pm.dpm.platform_caps = le32_to_cpu(power_info->pplib.ulPlatformCaps);
6300 rdev->pm.dpm.backbias_response_time = le16_to_cpu(power_info->pplib.usBackbiasTime);
6301 rdev->pm.dpm.voltage_response_time = le16_to_cpu(power_info->pplib.usVoltageTime);
6302 for (i = 0; i < state_array->ucNumEntries; i++) {
6303 u8 *idx;
6304 power_state = (union pplib_power_state *)power_state_offset;
6305 non_clock_array_index = power_state->v2.nonClockInfoIndex;
6306 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
6307 &non_clock_info_array->nonClockInfo[non_clock_array_index];
6308 if (!rdev->pm.power_state[i].clock_info)
6309 return -EINVAL;
6310 ps = kzalloc(sizeof(struct ni_ps), GFP_KERNEL);
6311 if (ps == NULL) {
6312 kfree(rdev->pm.dpm.ps);
6313 return -ENOMEM;
6314 }
6315 rdev->pm.dpm.ps[i].ps_priv = ps;
6316 si_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i],
6317 non_clock_info,
6318 non_clock_info_array->ucEntrySize);
6319 k = 0;
6320 idx = (u8 *)&power_state->v2.clockInfoIndex[0];
6321 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
6322 clock_array_index = idx[j];
6323 if (clock_array_index >= clock_info_array->ucNumEntries)
6324 continue;
6325 if (k >= SISLANDS_MAX_HARDWARE_POWERLEVELS)
6326 break;
6327 clock_info = (union pplib_clock_info *)
6328 ((u8 *)&clock_info_array->clockInfo[0] +
6329 (clock_array_index * clock_info_array->ucEntrySize));
6330 si_parse_pplib_clock_info(rdev,
6331 &rdev->pm.dpm.ps[i], k,
6332 clock_info);
6333 k++;
6334 }
6335 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
6336 }
6337 rdev->pm.dpm.num_ps = state_array->ucNumEntries;
6338 return 0;
6339 }
6340
6341 int si_dpm_init(struct radeon_device *rdev)
6342 {
6343 struct rv7xx_power_info *pi;
6344 struct evergreen_power_info *eg_pi;
6345 struct ni_power_info *ni_pi;
6346 struct si_power_info *si_pi;
6347 struct atom_clock_dividers dividers;
6348 int ret;
6349 u32 mask;
6350
6351 si_pi = kzalloc(sizeof(struct si_power_info), GFP_KERNEL);
6352 if (si_pi == NULL)
6353 return -ENOMEM;
6354 rdev->pm.dpm.priv = si_pi;
6355 ni_pi = &si_pi->ni;
6356 eg_pi = &ni_pi->eg;
6357 pi = &eg_pi->rv7xx;
6358
6359 ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask);
6360 if (ret)
6361 si_pi->sys_pcie_mask = 0;
6362 else
6363 si_pi->sys_pcie_mask = mask;
6364 si_pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID;
6365 si_pi->boot_pcie_gen = si_get_current_pcie_speed(rdev);
6366
6367 si_set_max_cu_value(rdev);
6368
6369 rv770_get_max_vddc(rdev);
6370 si_get_leakage_vddc(rdev);
6371 si_patch_dependency_tables_based_on_leakage(rdev);
6372
6373 pi->acpi_vddc = 0;
6374 eg_pi->acpi_vddci = 0;
6375 pi->min_vddc_in_table = 0;
6376 pi->max_vddc_in_table = 0;
6377
6378 ret = si_parse_power_table(rdev);
6379 if (ret)
6380 return ret;
6381 ret = r600_parse_extended_power_table(rdev);
6382 if (ret)
6383 return ret;
6384
6385 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries =
6386 kzalloc(4 * sizeof(struct radeon_clock_voltage_dependency_entry), GFP_KERNEL);
6387 if (!rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) {
6388 r600_free_extended_power_table(rdev);
6389 return -ENOMEM;
6390 }
6391 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4;
6392 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0;
6393 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0;
6394 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000;
6395 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720;
6396 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000;
6397 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810;
6398 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000;
6399 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900;
6400
6401 if (rdev->pm.dpm.voltage_response_time == 0)
6402 rdev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT;
6403 if (rdev->pm.dpm.backbias_response_time == 0)
6404 rdev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT;
6405
6406 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
6407 0, false, &dividers);
6408 if (ret)
6409 pi->ref_div = dividers.ref_div + 1;
6410 else
6411 pi->ref_div = R600_REFERENCEDIVIDER_DFLT;
6412
6413 eg_pi->smu_uvd_hs = false;
6414
6415 pi->mclk_strobe_mode_threshold = 40000;
6416 if (si_is_special_1gb_platform(rdev))
6417 pi->mclk_stutter_mode_threshold = 0;
6418 else
6419 pi->mclk_stutter_mode_threshold = pi->mclk_strobe_mode_threshold;
6420 pi->mclk_edc_enable_threshold = 40000;
6421 eg_pi->mclk_edc_wr_enable_threshold = 40000;
6422
6423 ni_pi->mclk_rtt_mode_threshold = eg_pi->mclk_edc_wr_enable_threshold;
6424
6425 pi->voltage_control =
6426 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, VOLTAGE_OBJ_GPIO_LUT);
6427
6428 pi->mvdd_control =
6429 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_MVDDC, VOLTAGE_OBJ_GPIO_LUT);
6430
6431 eg_pi->vddci_control =
6432 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI, VOLTAGE_OBJ_GPIO_LUT);
6433
6434 si_pi->vddc_phase_shed_control =
6435 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, VOLTAGE_OBJ_PHASE_LUT);
6436
6437 rv770_get_engine_memory_ss(rdev);
6438
6439 pi->asi = RV770_ASI_DFLT;
6440 pi->pasi = CYPRESS_HASI_DFLT;
6441 pi->vrc = SISLANDS_VRC_DFLT;
6442
6443 pi->gfx_clock_gating = true;
6444
6445 eg_pi->sclk_deep_sleep = true;
6446 si_pi->sclk_deep_sleep_above_low = false;
6447
6448 if (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE)
6449 pi->thermal_protection = true;
6450 else
6451 pi->thermal_protection = false;
6452
6453 eg_pi->dynamic_ac_timing = true;
6454
6455 eg_pi->light_sleep = true;
6456 #if defined(CONFIG_ACPI)
6457 eg_pi->pcie_performance_request =
6458 radeon_acpi_is_pcie_performance_request_supported(rdev);
6459 #else
6460 eg_pi->pcie_performance_request = false;
6461 #endif
6462
6463 si_pi->sram_end = SMC_RAM_END;
6464
6465 rdev->pm.dpm.dyn_state.mclk_sclk_ratio = 4;
6466 rdev->pm.dpm.dyn_state.sclk_mclk_delta = 15000;
6467 rdev->pm.dpm.dyn_state.vddc_vddci_delta = 200;
6468 rdev->pm.dpm.dyn_state.valid_sclk_values.count = 0;
6469 rdev->pm.dpm.dyn_state.valid_sclk_values.values = NULL;
6470 rdev->pm.dpm.dyn_state.valid_mclk_values.count = 0;
6471 rdev->pm.dpm.dyn_state.valid_mclk_values.values = NULL;
6472
6473 si_initialize_powertune_defaults(rdev);
6474
6475 /* make sure dc limits are valid */
6476 if ((rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) ||
6477 (rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0))
6478 rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc =
6479 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
6480
6481 return 0;
6482 }
6483
6484 void si_dpm_fini(struct radeon_device *rdev)
6485 {
6486 int i;
6487
6488 for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
6489 kfree(rdev->pm.dpm.ps[i].ps_priv);
6490 }
6491 kfree(rdev->pm.dpm.ps);
6492 kfree(rdev->pm.dpm.priv);
6493 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries);
6494 r600_free_extended_power_table(rdev);
6495 }
6496
6497 void si_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
6498 struct seq_file *m)
6499 {
6500 struct radeon_ps *rps = rdev->pm.dpm.current_ps;
6501 struct ni_ps *ps = ni_get_ps(rps);
6502 struct rv7xx_pl *pl;
6503 u32 current_index =
6504 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >>
6505 CURRENT_STATE_INDEX_SHIFT;
6506
6507 if (current_index >= ps->performance_level_count) {
6508 seq_printf(m, "invalid dpm profile %d\n", current_index);
6509 } else {
6510 pl = &ps->performance_levels[current_index];
6511 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
6512 seq_printf(m, "power level %d sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n",
6513 current_index, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1);
6514 }
6515 }
Linux kernel - Deliverables
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