307ffdfd644c2f3f2161e6d4e6528dabf89d23fa
2 * Copyright 2011 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 * Authors: Alex Deucher
27 #define TAHITI_RB_BITMAP_WIDTH_PER_SH 2
29 #define TAHITI_GB_ADDR_CONFIG_GOLDEN 0x12011003
30 #define VERDE_GB_ADDR_CONFIG_GOLDEN 0x12010002
31 #define HAINAN_GB_ADDR_CONFIG_GOLDEN 0x02010001
33 #define SI_MAX_SH_GPRS 256
34 #define SI_MAX_TEMP_GPRS 16
35 #define SI_MAX_SH_THREADS 256
36 #define SI_MAX_SH_STACK_ENTRIES 4096
37 #define SI_MAX_FRC_EOV_CNT 16384
38 #define SI_MAX_BACKENDS 8
39 #define SI_MAX_BACKENDS_MASK 0xFF
40 #define SI_MAX_BACKENDS_PER_SE_MASK 0x0F
41 #define SI_MAX_SIMDS 12
42 #define SI_MAX_SIMDS_MASK 0x0FFF
43 #define SI_MAX_SIMDS_PER_SE_MASK 0x00FF
44 #define SI_MAX_PIPES 8
45 #define SI_MAX_PIPES_MASK 0xFF
46 #define SI_MAX_PIPES_PER_SIMD_MASK 0x3F
47 #define SI_MAX_LDS_NUM 0xFFFF
49 #define SI_MAX_TCC_MASK 0xFFFF
51 /* SMC IND accessor regs */
52 #define SMC_IND_INDEX_0 0x200
53 #define SMC_IND_DATA_0 0x204
55 #define SMC_IND_ACCESS_CNTL 0x228
56 # define AUTO_INCREMENT_IND_0 (1 << 0)
57 #define SMC_MESSAGE_0 0x22c
58 #define SMC_RESP_0 0x230
60 /* CG IND registers are accessed via SMC indirect space + SMC_CG_IND_START */
61 #define SMC_CG_IND_START 0xc0030000
62 #define SMC_CG_IND_END 0xc0040000
64 #define CG_CGTT_LOCAL_0 0x400
65 #define CG_CGTT_LOCAL_1 0x401
67 /* SMC IND registers */
68 #define SMC_SYSCON_RESET_CNTL 0x80000000
69 # define RST_REG (1 << 0)
70 #define SMC_SYSCON_CLOCK_CNTL_0 0x80000004
71 # define CK_DISABLE (1 << 0)
72 # define CKEN (1 << 24)
74 #define VGA_HDP_CONTROL 0x328
75 #define VGA_MEMORY_DISABLE (1 << 4)
77 #define DCCG_DISP_SLOW_SELECT_REG 0x4fc
78 #define DCCG_DISP1_SLOW_SELECT(x) ((x) << 0)
79 #define DCCG_DISP1_SLOW_SELECT_MASK (7 << 0)
80 #define DCCG_DISP1_SLOW_SELECT_SHIFT 0
81 #define DCCG_DISP2_SLOW_SELECT(x) ((x) << 4)
82 #define DCCG_DISP2_SLOW_SELECT_MASK (7 << 4)
83 #define DCCG_DISP2_SLOW_SELECT_SHIFT 4
85 #define CG_SPLL_FUNC_CNTL 0x600
86 #define SPLL_RESET (1 << 0)
87 #define SPLL_SLEEP (1 << 1)
88 #define SPLL_BYPASS_EN (1 << 3)
89 #define SPLL_REF_DIV(x) ((x) << 4)
90 #define SPLL_REF_DIV_MASK (0x3f << 4)
91 #define SPLL_PDIV_A(x) ((x) << 20)
92 #define SPLL_PDIV_A_MASK (0x7f << 20)
93 #define SPLL_PDIV_A_SHIFT 20
94 #define CG_SPLL_FUNC_CNTL_2 0x604
95 #define SCLK_MUX_SEL(x) ((x) << 0)
96 #define SCLK_MUX_SEL_MASK (0x1ff << 0)
97 #define CG_SPLL_FUNC_CNTL_3 0x608
98 #define SPLL_FB_DIV(x) ((x) << 0)
99 #define SPLL_FB_DIV_MASK (0x3ffffff << 0)
100 #define SPLL_FB_DIV_SHIFT 0
101 #define SPLL_DITHEN (1 << 28)
102 #define CG_SPLL_FUNC_CNTL_4 0x60c
104 #define SPLL_CNTL_MODE 0x618
105 # define SPLL_REFCLK_SEL(x) ((x) << 8)
106 # define SPLL_REFCLK_SEL_MASK 0xFF00
108 #define CG_SPLL_SPREAD_SPECTRUM 0x620
109 #define SSEN (1 << 0)
110 #define CLK_S(x) ((x) << 4)
111 #define CLK_S_MASK (0xfff << 4)
112 #define CLK_S_SHIFT 4
113 #define CG_SPLL_SPREAD_SPECTRUM_2 0x624
114 #define CLK_V(x) ((x) << 0)
115 #define CLK_V_MASK (0x3ffffff << 0)
116 #define CLK_V_SHIFT 0
118 #define CG_SPLL_AUTOSCALE_CNTL 0x62c
119 # define AUTOSCALE_ON_SS_CLEAR (1 << 9)
121 /* discrete uvd clocks */
122 #define CG_UPLL_FUNC_CNTL 0x634
123 # define UPLL_RESET_MASK 0x00000001
124 # define UPLL_SLEEP_MASK 0x00000002
125 # define UPLL_BYPASS_EN_MASK 0x00000004
126 # define UPLL_CTLREQ_MASK 0x00000008
127 # define UPLL_VCO_MODE_MASK 0x00000600
128 # define UPLL_REF_DIV_MASK 0x003F0000
129 # define UPLL_CTLACK_MASK 0x40000000
130 # define UPLL_CTLACK2_MASK 0x80000000
131 #define CG_UPLL_FUNC_CNTL_2 0x638
132 # define UPLL_PDIV_A(x) ((x) << 0)
133 # define UPLL_PDIV_A_MASK 0x0000007F
134 # define UPLL_PDIV_B(x) ((x) << 8)
135 # define UPLL_PDIV_B_MASK 0x00007F00
136 # define VCLK_SRC_SEL(x) ((x) << 20)
137 # define VCLK_SRC_SEL_MASK 0x01F00000
138 # define DCLK_SRC_SEL(x) ((x) << 25)
139 # define DCLK_SRC_SEL_MASK 0x3E000000
140 #define CG_UPLL_FUNC_CNTL_3 0x63C
141 # define UPLL_FB_DIV(x) ((x) << 0)
142 # define UPLL_FB_DIV_MASK 0x01FFFFFF
143 #define CG_UPLL_FUNC_CNTL_4 0x644
144 # define UPLL_SPARE_ISPARE9 0x00020000
145 #define CG_UPLL_FUNC_CNTL_5 0x648
146 # define RESET_ANTI_MUX_MASK 0x00000200
147 #define CG_UPLL_SPREAD_SPECTRUM 0x650
148 # define SSEN_MASK 0x00000001
150 #define MPLL_BYPASSCLK_SEL 0x65c
151 # define MPLL_CLKOUT_SEL(x) ((x) << 8)
152 # define MPLL_CLKOUT_SEL_MASK 0xFF00
154 #define CG_CLKPIN_CNTL 0x660
155 # define XTALIN_DIVIDE (1 << 1)
156 # define BCLK_AS_XCLK (1 << 2)
157 #define CG_CLKPIN_CNTL_2 0x664
158 # define FORCE_BIF_REFCLK_EN (1 << 3)
159 # define MUX_TCLK_TO_XCLK (1 << 8)
161 #define THM_CLK_CNTL 0x66c
162 # define CMON_CLK_SEL(x) ((x) << 0)
163 # define CMON_CLK_SEL_MASK 0xFF
164 # define TMON_CLK_SEL(x) ((x) << 8)
165 # define TMON_CLK_SEL_MASK 0xFF00
166 #define MISC_CLK_CNTL 0x670
167 # define DEEP_SLEEP_CLK_SEL(x) ((x) << 0)
168 # define DEEP_SLEEP_CLK_SEL_MASK 0xFF
169 # define ZCLK_SEL(x) ((x) << 8)
170 # define ZCLK_SEL_MASK 0xFF00
172 #define CG_THERMAL_CTRL 0x700
173 #define DPM_EVENT_SRC(x) ((x) << 0)
174 #define DPM_EVENT_SRC_MASK (7 << 0)
175 #define DIG_THERM_DPM(x) ((x) << 14)
176 #define DIG_THERM_DPM_MASK 0x003FC000
177 #define DIG_THERM_DPM_SHIFT 14
179 #define CG_THERMAL_INT 0x708
180 #define DIG_THERM_INTH(x) ((x) << 8)
181 #define DIG_THERM_INTH_MASK 0x0000FF00
182 #define DIG_THERM_INTH_SHIFT 8
183 #define DIG_THERM_INTL(x) ((x) << 16)
184 #define DIG_THERM_INTL_MASK 0x00FF0000
185 #define DIG_THERM_INTL_SHIFT 16
186 #define THERM_INT_MASK_HIGH (1 << 24)
187 #define THERM_INT_MASK_LOW (1 << 25)
189 #define CG_MULT_THERMAL_STATUS 0x714
190 #define ASIC_MAX_TEMP(x) ((x) << 0)
191 #define ASIC_MAX_TEMP_MASK 0x000001ff
192 #define ASIC_MAX_TEMP_SHIFT 0
193 #define CTF_TEMP(x) ((x) << 9)
194 #define CTF_TEMP_MASK 0x0003fe00
195 #define CTF_TEMP_SHIFT 9
197 #define GENERAL_PWRMGT 0x780
198 # define GLOBAL_PWRMGT_EN (1 << 0)
199 # define STATIC_PM_EN (1 << 1)
200 # define THERMAL_PROTECTION_DIS (1 << 2)
201 # define THERMAL_PROTECTION_TYPE (1 << 3)
202 # define SW_SMIO_INDEX(x) ((x) << 6)
203 # define SW_SMIO_INDEX_MASK (1 << 6)
204 # define SW_SMIO_INDEX_SHIFT 6
205 # define VOLT_PWRMGT_EN (1 << 10)
206 # define DYN_SPREAD_SPECTRUM_EN (1 << 23)
208 #define SCLK_PWRMGT_CNTL 0x788
209 # define SCLK_PWRMGT_OFF (1 << 0)
210 # define SCLK_LOW_D1 (1 << 1)
211 # define FIR_RESET (1 << 4)
212 # define FIR_FORCE_TREND_SEL (1 << 5)
213 # define FIR_TREND_MODE (1 << 6)
214 # define DYN_GFX_CLK_OFF_EN (1 << 7)
215 # define GFX_CLK_FORCE_ON (1 << 8)
216 # define GFX_CLK_REQUEST_OFF (1 << 9)
217 # define GFX_CLK_FORCE_OFF (1 << 10)
218 # define GFX_CLK_OFF_ACPI_D1 (1 << 11)
219 # define GFX_CLK_OFF_ACPI_D2 (1 << 12)
220 # define GFX_CLK_OFF_ACPI_D3 (1 << 13)
221 # define DYN_LIGHT_SLEEP_EN (1 << 14)
223 #define TARGET_AND_CURRENT_PROFILE_INDEX 0x798
224 # define CURRENT_STATE_INDEX_MASK (0xf << 4)
225 # define CURRENT_STATE_INDEX_SHIFT 4
229 #define CG_FFCT_0 0x7c0
230 # define UTC_0(x) ((x) << 0)
231 # define UTC_0_MASK (0x3ff << 0)
232 # define DTC_0(x) ((x) << 10)
233 # define DTC_0_MASK (0x3ff << 10)
236 # define BSP(x) ((x) << 0)
237 # define BSP_MASK (0xffff << 0)
238 # define BSU(x) ((x) << 16)
239 # define BSU_MASK (0xf << 16)
241 # define CG_R(x) ((x) << 0)
242 # define CG_R_MASK (0xffff << 0)
243 # define CG_L(x) ((x) << 16)
244 # define CG_L_MASK (0xffff << 16)
247 # define CG_GICST(x) ((x) << 0)
248 # define CG_GICST_MASK (0xffff << 0)
249 # define CG_GIPOT(x) ((x) << 16)
250 # define CG_GIPOT_MASK (0xffff << 16)
253 # define SST(x) ((x) << 0)
254 # define SST_MASK (0xffff << 0)
255 # define SSTU(x) ((x) << 16)
256 # define SSTU_MASK (0xf << 16)
258 #define CG_DISPLAY_GAP_CNTL 0x828
259 # define DISP1_GAP(x) ((x) << 0)
260 # define DISP1_GAP_MASK (3 << 0)
261 # define DISP2_GAP(x) ((x) << 2)
262 # define DISP2_GAP_MASK (3 << 2)
263 # define VBI_TIMER_COUNT(x) ((x) << 4)
264 # define VBI_TIMER_COUNT_MASK (0x3fff << 4)
265 # define VBI_TIMER_UNIT(x) ((x) << 20)
266 # define VBI_TIMER_UNIT_MASK (7 << 20)
267 # define DISP1_GAP_MCHG(x) ((x) << 24)
268 # define DISP1_GAP_MCHG_MASK (3 << 24)
269 # define DISP2_GAP_MCHG(x) ((x) << 26)
270 # define DISP2_GAP_MCHG_MASK (3 << 26)
272 #define CG_ULV_CONTROL 0x878
273 #define CG_ULV_PARAMETER 0x87c
275 #define SMC_SCRATCH0 0x884
277 #define CG_CAC_CTRL 0x8b8
278 # define CAC_WINDOW(x) ((x) << 0)
279 # define CAC_WINDOW_MASK 0x00ffffff
281 #define DMIF_ADDR_CONFIG 0xBD4
283 #define DMIF_ADDR_CALC 0xC00
285 #define PIPE0_DMIF_BUFFER_CONTROL 0x0ca0
286 # define DMIF_BUFFERS_ALLOCATED(x) ((x) << 0)
287 # define DMIF_BUFFERS_ALLOCATED_COMPLETED (1 << 4)
289 #define SRBM_STATUS 0xE50
290 #define GRBM_RQ_PENDING (1 << 5)
291 #define VMC_BUSY (1 << 8)
292 #define MCB_BUSY (1 << 9)
293 #define MCB_NON_DISPLAY_BUSY (1 << 10)
294 #define MCC_BUSY (1 << 11)
295 #define MCD_BUSY (1 << 12)
296 #define SEM_BUSY (1 << 14)
297 #define IH_BUSY (1 << 17)
299 #define SRBM_SOFT_RESET 0x0E60
300 #define SOFT_RESET_BIF (1 << 1)
301 #define SOFT_RESET_DC (1 << 5)
302 #define SOFT_RESET_DMA1 (1 << 6)
303 #define SOFT_RESET_GRBM (1 << 8)
304 #define SOFT_RESET_HDP (1 << 9)
305 #define SOFT_RESET_IH (1 << 10)
306 #define SOFT_RESET_MC (1 << 11)
307 #define SOFT_RESET_ROM (1 << 14)
308 #define SOFT_RESET_SEM (1 << 15)
309 #define SOFT_RESET_VMC (1 << 17)
310 #define SOFT_RESET_DMA (1 << 20)
311 #define SOFT_RESET_TST (1 << 21)
312 #define SOFT_RESET_REGBB (1 << 22)
313 #define SOFT_RESET_ORB (1 << 23)
315 #define CC_SYS_RB_BACKEND_DISABLE 0xe80
316 #define GC_USER_SYS_RB_BACKEND_DISABLE 0xe84
318 #define SRBM_STATUS2 0x0EC4
319 #define DMA_BUSY (1 << 5)
320 #define DMA1_BUSY (1 << 6)
322 #define VM_L2_CNTL 0x1400
323 #define ENABLE_L2_CACHE (1 << 0)
324 #define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1)
325 #define L2_CACHE_PTE_ENDIAN_SWAP_MODE(x) ((x) << 2)
326 #define L2_CACHE_PDE_ENDIAN_SWAP_MODE(x) ((x) << 4)
327 #define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9)
328 #define ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE (1 << 10)
329 #define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 15)
330 #define CONTEXT1_IDENTITY_ACCESS_MODE(x) (((x) & 3) << 19)
331 #define VM_L2_CNTL2 0x1404
332 #define INVALIDATE_ALL_L1_TLBS (1 << 0)
333 #define INVALIDATE_L2_CACHE (1 << 1)
334 #define INVALIDATE_CACHE_MODE(x) ((x) << 26)
335 #define INVALIDATE_PTE_AND_PDE_CACHES 0
336 #define INVALIDATE_ONLY_PTE_CACHES 1
337 #define INVALIDATE_ONLY_PDE_CACHES 2
338 #define VM_L2_CNTL3 0x1408
339 #define BANK_SELECT(x) ((x) << 0)
340 #define L2_CACHE_UPDATE_MODE(x) ((x) << 6)
341 #define L2_CACHE_BIGK_FRAGMENT_SIZE(x) ((x) << 15)
342 #define L2_CACHE_BIGK_ASSOCIATIVITY (1 << 20)
343 #define VM_L2_STATUS 0x140C
344 #define L2_BUSY (1 << 0)
345 #define VM_CONTEXT0_CNTL 0x1410
346 #define ENABLE_CONTEXT (1 << 0)
347 #define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1)
348 #define RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 3)
349 #define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4)
350 #define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 6)
351 #define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 7)
352 #define PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 9)
353 #define PDE0_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 10)
354 #define VALID_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 12)
355 #define VALID_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 13)
356 #define READ_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 15)
357 #define READ_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 16)
358 #define WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 18)
359 #define WRITE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 19)
360 #define VM_CONTEXT1_CNTL 0x1414
361 #define VM_CONTEXT0_CNTL2 0x1430
362 #define VM_CONTEXT1_CNTL2 0x1434
363 #define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR 0x1438
364 #define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR 0x143c
365 #define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR 0x1440
366 #define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR 0x1444
367 #define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR 0x1448
368 #define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR 0x144c
369 #define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR 0x1450
370 #define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR 0x1454
372 #define VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x14FC
373 #define VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x14DC
374 #define PROTECTIONS_MASK (0xf << 0)
375 #define PROTECTIONS_SHIFT 0
382 #define MEMORY_CLIENT_ID_MASK (0xff << 12)
383 #define MEMORY_CLIENT_ID_SHIFT 12
384 #define MEMORY_CLIENT_RW_MASK (1 << 24)
385 #define MEMORY_CLIENT_RW_SHIFT 24
386 #define FAULT_VMID_MASK (0xf << 25)
387 #define FAULT_VMID_SHIFT 25
389 #define VM_INVALIDATE_REQUEST 0x1478
390 #define VM_INVALIDATE_RESPONSE 0x147c
392 #define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1518
393 #define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR 0x151c
395 #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153c
396 #define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR 0x1540
397 #define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR 0x1544
398 #define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR 0x1548
399 #define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR 0x154c
400 #define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR 0x1550
401 #define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR 0x1554
402 #define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR 0x1558
403 #define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155c
404 #define VM_CONTEXT1_PAGE_TABLE_START_ADDR 0x1560
406 #define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157C
407 #define VM_CONTEXT1_PAGE_TABLE_END_ADDR 0x1580
409 #define VM_L2_CG 0x15c0
410 #define MC_CG_ENABLE (1 << 18)
411 #define MC_LS_ENABLE (1 << 19)
413 #define MC_SHARED_CHMAP 0x2004
414 #define NOOFCHAN_SHIFT 12
415 #define NOOFCHAN_MASK 0x0000f000
416 #define MC_SHARED_CHREMAP 0x2008
418 #define MC_VM_FB_LOCATION 0x2024
419 #define MC_VM_AGP_TOP 0x2028
420 #define MC_VM_AGP_BOT 0x202C
421 #define MC_VM_AGP_BASE 0x2030
422 #define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034
423 #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038
424 #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203C
426 #define MC_VM_MX_L1_TLB_CNTL 0x2064
427 #define ENABLE_L1_TLB (1 << 0)
428 #define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1)
429 #define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 3)
430 #define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 3)
431 #define SYSTEM_ACCESS_MODE_IN_SYS (2 << 3)
432 #define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 3)
433 #define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5)
434 #define ENABLE_ADVANCED_DRIVER_MODEL (1 << 6)
436 #define MC_SHARED_BLACKOUT_CNTL 0x20ac
438 #define MC_HUB_MISC_HUB_CG 0x20b8
439 #define MC_HUB_MISC_VM_CG 0x20bc
441 #define MC_HUB_MISC_SIP_CG 0x20c0
443 #define MC_XPB_CLK_GAT 0x2478
445 #define MC_CITF_MISC_RD_CG 0x2648
446 #define MC_CITF_MISC_WR_CG 0x264c
447 #define MC_CITF_MISC_VM_CG 0x2650
449 #define MC_ARB_RAMCFG 0x2760
450 #define NOOFBANK_SHIFT 0
451 #define NOOFBANK_MASK 0x00000003
452 #define NOOFRANK_SHIFT 2
453 #define NOOFRANK_MASK 0x00000004
454 #define NOOFROWS_SHIFT 3
455 #define NOOFROWS_MASK 0x00000038
456 #define NOOFCOLS_SHIFT 6
457 #define NOOFCOLS_MASK 0x000000C0
458 #define CHANSIZE_SHIFT 8
459 #define CHANSIZE_MASK 0x00000100
460 #define CHANSIZE_OVERRIDE (1 << 11)
461 #define NOOFGROUPS_SHIFT 12
462 #define NOOFGROUPS_MASK 0x00001000
464 #define MC_ARB_DRAM_TIMING 0x2774
465 #define MC_ARB_DRAM_TIMING2 0x2778
467 #define MC_ARB_BURST_TIME 0x2808
468 #define STATE0(x) ((x) << 0)
469 #define STATE0_MASK (0x1f << 0)
470 #define STATE0_SHIFT 0
471 #define STATE1(x) ((x) << 5)
472 #define STATE1_MASK (0x1f << 5)
473 #define STATE1_SHIFT 5
474 #define STATE2(x) ((x) << 10)
475 #define STATE2_MASK (0x1f << 10)
476 #define STATE2_SHIFT 10
477 #define STATE3(x) ((x) << 15)
478 #define STATE3_MASK (0x1f << 15)
479 #define STATE3_SHIFT 15
481 #define MC_SEQ_TRAIN_WAKEUP_CNTL 0x2808
482 #define TRAIN_DONE_D0 (1 << 30)
483 #define TRAIN_DONE_D1 (1 << 31)
485 #define MC_SEQ_SUP_CNTL 0x28c8
486 #define RUN_MASK (1 << 0)
487 #define MC_SEQ_SUP_PGM 0x28cc
488 #define MC_PMG_AUTO_CMD 0x28d0
490 #define MC_IO_PAD_CNTL_D0 0x29d0
491 #define MEM_FALL_OUT_CMD (1 << 8)
493 #define MC_SEQ_RAS_TIMING 0x28a0
494 #define MC_SEQ_CAS_TIMING 0x28a4
495 #define MC_SEQ_MISC_TIMING 0x28a8
496 #define MC_SEQ_MISC_TIMING2 0x28ac
497 #define MC_SEQ_PMG_TIMING 0x28b0
498 #define MC_SEQ_RD_CTL_D0 0x28b4
499 #define MC_SEQ_RD_CTL_D1 0x28b8
500 #define MC_SEQ_WR_CTL_D0 0x28bc
501 #define MC_SEQ_WR_CTL_D1 0x28c0
503 #define MC_SEQ_MISC0 0x2a00
504 #define MC_SEQ_MISC0_VEN_ID_SHIFT 8
505 #define MC_SEQ_MISC0_VEN_ID_MASK 0x00000f00
506 #define MC_SEQ_MISC0_VEN_ID_VALUE 3
507 #define MC_SEQ_MISC0_REV_ID_SHIFT 12
508 #define MC_SEQ_MISC0_REV_ID_MASK 0x0000f000
509 #define MC_SEQ_MISC0_REV_ID_VALUE 1
510 #define MC_SEQ_MISC0_GDDR5_SHIFT 28
511 #define MC_SEQ_MISC0_GDDR5_MASK 0xf0000000
512 #define MC_SEQ_MISC0_GDDR5_VALUE 5
513 #define MC_SEQ_MISC1 0x2a04
514 #define MC_SEQ_RESERVE_M 0x2a08
515 #define MC_PMG_CMD_EMRS 0x2a0c
517 #define MC_SEQ_IO_DEBUG_INDEX 0x2a44
518 #define MC_SEQ_IO_DEBUG_DATA 0x2a48
520 #define MC_SEQ_MISC5 0x2a54
521 #define MC_SEQ_MISC6 0x2a58
523 #define MC_SEQ_MISC7 0x2a64
525 #define MC_SEQ_RAS_TIMING_LP 0x2a6c
526 #define MC_SEQ_CAS_TIMING_LP 0x2a70
527 #define MC_SEQ_MISC_TIMING_LP 0x2a74
528 #define MC_SEQ_MISC_TIMING2_LP 0x2a78
529 #define MC_SEQ_WR_CTL_D0_LP 0x2a7c
530 #define MC_SEQ_WR_CTL_D1_LP 0x2a80
531 #define MC_SEQ_PMG_CMD_EMRS_LP 0x2a84
532 #define MC_SEQ_PMG_CMD_MRS_LP 0x2a88
534 #define MC_PMG_CMD_MRS 0x2aac
536 #define MC_SEQ_RD_CTL_D0_LP 0x2b1c
537 #define MC_SEQ_RD_CTL_D1_LP 0x2b20
539 #define MC_PMG_CMD_MRS1 0x2b44
540 #define MC_SEQ_PMG_CMD_MRS1_LP 0x2b48
541 #define MC_SEQ_PMG_TIMING_LP 0x2b4c
543 #define MC_SEQ_WR_CTL_2 0x2b54
544 #define MC_SEQ_WR_CTL_2_LP 0x2b58
545 #define MC_PMG_CMD_MRS2 0x2b5c
546 #define MC_SEQ_PMG_CMD_MRS2_LP 0x2b60
548 #define MCLK_PWRMGT_CNTL 0x2ba0
549 # define DLL_SPEED(x) ((x) << 0)
550 # define DLL_SPEED_MASK (0x1f << 0)
551 # define DLL_READY (1 << 6)
552 # define MC_INT_CNTL (1 << 7)
553 # define MRDCK0_PDNB (1 << 8)
554 # define MRDCK1_PDNB (1 << 9)
555 # define MRDCK0_RESET (1 << 16)
556 # define MRDCK1_RESET (1 << 17)
557 # define DLL_READY_READ (1 << 24)
558 #define DLL_CNTL 0x2ba4
559 # define MRDCK0_BYPASS (1 << 24)
560 # define MRDCK1_BYPASS (1 << 25)
562 #define MPLL_FUNC_CNTL 0x2bb4
563 #define BWCTRL(x) ((x) << 20)
564 #define BWCTRL_MASK (0xff << 20)
565 #define MPLL_FUNC_CNTL_1 0x2bb8
566 #define VCO_MODE(x) ((x) << 0)
567 #define VCO_MODE_MASK (3 << 0)
568 #define CLKFRAC(x) ((x) << 4)
569 #define CLKFRAC_MASK (0xfff << 4)
570 #define CLKF(x) ((x) << 16)
571 #define CLKF_MASK (0xfff << 16)
572 #define MPLL_FUNC_CNTL_2 0x2bbc
573 #define MPLL_AD_FUNC_CNTL 0x2bc0
574 #define YCLK_POST_DIV(x) ((x) << 0)
575 #define YCLK_POST_DIV_MASK (7 << 0)
576 #define MPLL_DQ_FUNC_CNTL 0x2bc4
577 #define YCLK_SEL(x) ((x) << 4)
578 #define YCLK_SEL_MASK (1 << 4)
580 #define MPLL_SS1 0x2bcc
581 #define CLKV(x) ((x) << 0)
582 #define CLKV_MASK (0x3ffffff << 0)
583 #define MPLL_SS2 0x2bd0
584 #define CLKS(x) ((x) << 0)
585 #define CLKS_MASK (0xfff << 0)
587 #define HDP_HOST_PATH_CNTL 0x2C00
588 #define CLOCK_GATING_DIS (1 << 23)
589 #define HDP_NONSURFACE_BASE 0x2C04
590 #define HDP_NONSURFACE_INFO 0x2C08
591 #define HDP_NONSURFACE_SIZE 0x2C0C
593 #define HDP_ADDR_CONFIG 0x2F48
594 #define HDP_MISC_CNTL 0x2F4C
595 #define HDP_FLUSH_INVALIDATE_CACHE (1 << 0)
596 #define HDP_MEM_POWER_LS 0x2F50
597 #define HDP_LS_ENABLE (1 << 0)
599 #define ATC_MISC_CG 0x3350
601 #define IH_RB_CNTL 0x3e00
602 # define IH_RB_ENABLE (1 << 0)
603 # define IH_IB_SIZE(x) ((x) << 1) /* log2 */
604 # define IH_RB_FULL_DRAIN_ENABLE (1 << 6)
605 # define IH_WPTR_WRITEBACK_ENABLE (1 << 8)
606 # define IH_WPTR_WRITEBACK_TIMER(x) ((x) << 9) /* log2 */
607 # define IH_WPTR_OVERFLOW_ENABLE (1 << 16)
608 # define IH_WPTR_OVERFLOW_CLEAR (1 << 31)
609 #define IH_RB_BASE 0x3e04
610 #define IH_RB_RPTR 0x3e08
611 #define IH_RB_WPTR 0x3e0c
612 # define RB_OVERFLOW (1 << 0)
613 # define WPTR_OFFSET_MASK 0x3fffc
614 #define IH_RB_WPTR_ADDR_HI 0x3e10
615 #define IH_RB_WPTR_ADDR_LO 0x3e14
616 #define IH_CNTL 0x3e18
617 # define ENABLE_INTR (1 << 0)
618 # define IH_MC_SWAP(x) ((x) << 1)
619 # define IH_MC_SWAP_NONE 0
620 # define IH_MC_SWAP_16BIT 1
621 # define IH_MC_SWAP_32BIT 2
622 # define IH_MC_SWAP_64BIT 3
623 # define RPTR_REARM (1 << 4)
624 # define MC_WRREQ_CREDIT(x) ((x) << 15)
625 # define MC_WR_CLEAN_CNT(x) ((x) << 20)
626 # define MC_VMID(x) ((x) << 25)
628 #define CONFIG_MEMSIZE 0x5428
630 #define INTERRUPT_CNTL 0x5468
631 # define IH_DUMMY_RD_OVERRIDE (1 << 0)
632 # define IH_DUMMY_RD_EN (1 << 1)
633 # define IH_REQ_NONSNOOP_EN (1 << 3)
634 # define GEN_IH_INT_EN (1 << 8)
635 #define INTERRUPT_CNTL2 0x546c
637 #define HDP_MEM_COHERENCY_FLUSH_CNTL 0x5480
639 #define BIF_FB_EN 0x5490
640 #define FB_READ_EN (1 << 0)
641 #define FB_WRITE_EN (1 << 1)
643 #define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0
645 /* DCE6 ELD audio interface */
646 #define AZ_F0_CODEC_ENDPOINT_INDEX 0x5E00
647 # define AZ_ENDPOINT_REG_INDEX(x) (((x) & 0xff) << 0)
648 # define AZ_ENDPOINT_REG_WRITE_EN (1 << 8)
649 #define AZ_F0_CODEC_ENDPOINT_DATA 0x5E04
651 #define AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x25
652 #define SPEAKER_ALLOCATION(x) (((x) & 0x7f) << 0)
653 #define SPEAKER_ALLOCATION_MASK (0x7f << 0)
654 #define SPEAKER_ALLOCATION_SHIFT 0
655 #define HDMI_CONNECTION (1 << 16)
656 #define DP_CONNECTION (1 << 17)
658 #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x28 /* LPCM */
659 #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x29 /* AC3 */
660 #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x2A /* MPEG1 */
661 #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x2B /* MP3 */
662 #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x2C /* MPEG2 */
663 #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x2D /* AAC */
664 #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x2E /* DTS */
665 #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x2F /* ATRAC */
666 #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x30 /* one bit audio - leave at 0 (default) */
667 #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x31 /* Dolby Digital */
668 #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x32 /* DTS-HD */
669 #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x33 /* MAT-MLP */
670 #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x34 /* DTS */
671 #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x35 /* WMA Pro */
672 # define MAX_CHANNELS(x) (((x) & 0x7) << 0)
673 /* max channels minus one. 7 = 8 channels */
674 # define SUPPORTED_FREQUENCIES(x) (((x) & 0xff) << 8)
675 # define DESCRIPTOR_BYTE_2(x) (((x) & 0xff) << 16)
676 # define SUPPORTED_FREQUENCIES_STEREO(x) (((x) & 0xff) << 24) /* LPCM only */
677 /* SUPPORTED_FREQUENCIES, SUPPORTED_FREQUENCIES_STEREO
687 #define AZ_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x37
688 # define VIDEO_LIPSYNC(x) (((x) & 0xff) << 0)
689 # define AUDIO_LIPSYNC(x) (((x) & 0xff) << 8)
690 /* VIDEO_LIPSYNC, AUDIO_LIPSYNC
692 * x = legal delay value
693 * 255 = sync not supported
695 #define AZ_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x38
696 # define HBR_CAPABLE (1 << 0) /* enabled by default */
698 #define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x3a
699 # define MANUFACTURER_ID(x) (((x) & 0xffff) << 0)
700 # define PRODUCT_ID(x) (((x) & 0xffff) << 16)
701 #define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x3b
702 # define SINK_DESCRIPTION_LEN(x) (((x) & 0xff) << 0)
703 #define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x3c
704 # define PORT_ID0(x) (((x) & 0xffffffff) << 0)
705 #define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x3d
706 # define PORT_ID1(x) (((x) & 0xffffffff) << 0)
707 #define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x3e
708 # define DESCRIPTION0(x) (((x) & 0xff) << 0)
709 # define DESCRIPTION1(x) (((x) & 0xff) << 8)
710 # define DESCRIPTION2(x) (((x) & 0xff) << 16)
711 # define DESCRIPTION3(x) (((x) & 0xff) << 24)
712 #define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x3f
713 # define DESCRIPTION4(x) (((x) & 0xff) << 0)
714 # define DESCRIPTION5(x) (((x) & 0xff) << 8)
715 # define DESCRIPTION6(x) (((x) & 0xff) << 16)
716 # define DESCRIPTION7(x) (((x) & 0xff) << 24)
717 #define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x40
718 # define DESCRIPTION8(x) (((x) & 0xff) << 0)
719 # define DESCRIPTION9(x) (((x) & 0xff) << 8)
720 # define DESCRIPTION10(x) (((x) & 0xff) << 16)
721 # define DESCRIPTION11(x) (((x) & 0xff) << 24)
722 #define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x41
723 # define DESCRIPTION12(x) (((x) & 0xff) << 0)
724 # define DESCRIPTION13(x) (((x) & 0xff) << 8)
725 # define DESCRIPTION14(x) (((x) & 0xff) << 16)
726 # define DESCRIPTION15(x) (((x) & 0xff) << 24)
727 #define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x42
728 # define DESCRIPTION16(x) (((x) & 0xff) << 0)
729 # define DESCRIPTION17(x) (((x) & 0xff) << 8)
731 #define AZ_F0_CODEC_PIN_CONTROL_HOTPLUG_CONTROL 0x54
732 # define AUDIO_ENABLED (1 << 31)
734 #define AZ_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x56
735 #define PORT_CONNECTIVITY_MASK (3 << 30)
736 #define PORT_CONNECTIVITY_SHIFT 30
738 #define DC_LB_MEMORY_SPLIT 0x6b0c
739 #define DC_LB_MEMORY_CONFIG(x) ((x) << 20)
741 #define PRIORITY_A_CNT 0x6b18
742 #define PRIORITY_MARK_MASK 0x7fff
743 #define PRIORITY_OFF (1 << 16)
744 #define PRIORITY_ALWAYS_ON (1 << 20)
745 #define PRIORITY_B_CNT 0x6b1c
747 #define DPG_PIPE_ARBITRATION_CONTROL3 0x6cc8
748 # define LATENCY_WATERMARK_MASK(x) ((x) << 16)
749 #define DPG_PIPE_LATENCY_CONTROL 0x6ccc
750 # define LATENCY_LOW_WATERMARK(x) ((x) << 0)
751 # define LATENCY_HIGH_WATERMARK(x) ((x) << 16)
753 /* 0x6bb8, 0x77b8, 0x103b8, 0x10fb8, 0x11bb8, 0x127b8 */
754 #define VLINE_STATUS 0x6bb8
755 # define VLINE_OCCURRED (1 << 0)
756 # define VLINE_ACK (1 << 4)
757 # define VLINE_STAT (1 << 12)
758 # define VLINE_INTERRUPT (1 << 16)
759 # define VLINE_INTERRUPT_TYPE (1 << 17)
760 /* 0x6bbc, 0x77bc, 0x103bc, 0x10fbc, 0x11bbc, 0x127bc */
761 #define VBLANK_STATUS 0x6bbc
762 # define VBLANK_OCCURRED (1 << 0)
763 # define VBLANK_ACK (1 << 4)
764 # define VBLANK_STAT (1 << 12)
765 # define VBLANK_INTERRUPT (1 << 16)
766 # define VBLANK_INTERRUPT_TYPE (1 << 17)
768 /* 0x6b40, 0x7740, 0x10340, 0x10f40, 0x11b40, 0x12740 */
769 #define INT_MASK 0x6b40
770 # define VBLANK_INT_MASK (1 << 0)
771 # define VLINE_INT_MASK (1 << 4)
773 #define DISP_INTERRUPT_STATUS 0x60f4
774 # define LB_D1_VLINE_INTERRUPT (1 << 2)
775 # define LB_D1_VBLANK_INTERRUPT (1 << 3)
776 # define DC_HPD1_INTERRUPT (1 << 17)
777 # define DC_HPD1_RX_INTERRUPT (1 << 18)
778 # define DACA_AUTODETECT_INTERRUPT (1 << 22)
779 # define DACB_AUTODETECT_INTERRUPT (1 << 23)
780 # define DC_I2C_SW_DONE_INTERRUPT (1 << 24)
781 # define DC_I2C_HW_DONE_INTERRUPT (1 << 25)
782 #define DISP_INTERRUPT_STATUS_CONTINUE 0x60f8
783 # define LB_D2_VLINE_INTERRUPT (1 << 2)
784 # define LB_D2_VBLANK_INTERRUPT (1 << 3)
785 # define DC_HPD2_INTERRUPT (1 << 17)
786 # define DC_HPD2_RX_INTERRUPT (1 << 18)
787 # define DISP_TIMER_INTERRUPT (1 << 24)
788 #define DISP_INTERRUPT_STATUS_CONTINUE2 0x60fc
789 # define LB_D3_VLINE_INTERRUPT (1 << 2)
790 # define LB_D3_VBLANK_INTERRUPT (1 << 3)
791 # define DC_HPD3_INTERRUPT (1 << 17)
792 # define DC_HPD3_RX_INTERRUPT (1 << 18)
793 #define DISP_INTERRUPT_STATUS_CONTINUE3 0x6100
794 # define LB_D4_VLINE_INTERRUPT (1 << 2)
795 # define LB_D4_VBLANK_INTERRUPT (1 << 3)
796 # define DC_HPD4_INTERRUPT (1 << 17)
797 # define DC_HPD4_RX_INTERRUPT (1 << 18)
798 #define DISP_INTERRUPT_STATUS_CONTINUE4 0x614c
799 # define LB_D5_VLINE_INTERRUPT (1 << 2)
800 # define LB_D5_VBLANK_INTERRUPT (1 << 3)
801 # define DC_HPD5_INTERRUPT (1 << 17)
802 # define DC_HPD5_RX_INTERRUPT (1 << 18)
803 #define DISP_INTERRUPT_STATUS_CONTINUE5 0x6150
804 # define LB_D6_VLINE_INTERRUPT (1 << 2)
805 # define LB_D6_VBLANK_INTERRUPT (1 << 3)
806 # define DC_HPD6_INTERRUPT (1 << 17)
807 # define DC_HPD6_RX_INTERRUPT (1 << 18)
809 /* 0x6858, 0x7458, 0x10058, 0x10c58, 0x11858, 0x12458 */
810 #define GRPH_INT_STATUS 0x6858
811 # define GRPH_PFLIP_INT_OCCURRED (1 << 0)
812 # define GRPH_PFLIP_INT_CLEAR (1 << 8)
813 /* 0x685c, 0x745c, 0x1005c, 0x10c5c, 0x1185c, 0x1245c */
814 #define GRPH_INT_CONTROL 0x685c
815 # define GRPH_PFLIP_INT_MASK (1 << 0)
816 # define GRPH_PFLIP_INT_TYPE (1 << 8)
818 #define DACA_AUTODETECT_INT_CONTROL 0x66c8
820 #define DC_HPD1_INT_STATUS 0x601c
821 #define DC_HPD2_INT_STATUS 0x6028
822 #define DC_HPD3_INT_STATUS 0x6034
823 #define DC_HPD4_INT_STATUS 0x6040
824 #define DC_HPD5_INT_STATUS 0x604c
825 #define DC_HPD6_INT_STATUS 0x6058
826 # define DC_HPDx_INT_STATUS (1 << 0)
827 # define DC_HPDx_SENSE (1 << 1)
828 # define DC_HPDx_RX_INT_STATUS (1 << 8)
830 #define DC_HPD1_INT_CONTROL 0x6020
831 #define DC_HPD2_INT_CONTROL 0x602c
832 #define DC_HPD3_INT_CONTROL 0x6038
833 #define DC_HPD4_INT_CONTROL 0x6044
834 #define DC_HPD5_INT_CONTROL 0x6050
835 #define DC_HPD6_INT_CONTROL 0x605c
836 # define DC_HPDx_INT_ACK (1 << 0)
837 # define DC_HPDx_INT_POLARITY (1 << 8)
838 # define DC_HPDx_INT_EN (1 << 16)
839 # define DC_HPDx_RX_INT_ACK (1 << 20)
840 # define DC_HPDx_RX_INT_EN (1 << 24)
842 #define DC_HPD1_CONTROL 0x6024
843 #define DC_HPD2_CONTROL 0x6030
844 #define DC_HPD3_CONTROL 0x603c
845 #define DC_HPD4_CONTROL 0x6048
846 #define DC_HPD5_CONTROL 0x6054
847 #define DC_HPD6_CONTROL 0x6060
848 # define DC_HPDx_CONNECTION_TIMER(x) ((x) << 0)
849 # define DC_HPDx_RX_INT_TIMER(x) ((x) << 16)
850 # define DC_HPDx_EN (1 << 28)
852 #define DPG_PIPE_STUTTER_CONTROL 0x6cd4
853 # define STUTTER_ENABLE (1 << 0)
855 /* 0x6e98, 0x7a98, 0x10698, 0x11298, 0x11e98, 0x12a98 */
856 #define CRTC_STATUS_FRAME_COUNT 0x6e98
858 #define AFMT_AUDIO_SRC_CONTROL 0x713c
859 #define AFMT_AUDIO_SRC_SELECT(x) (((x) & 7) << 0)
860 /* AFMT_AUDIO_SRC_SELECT
869 #define GRBM_CNTL 0x8000
870 #define GRBM_READ_TIMEOUT(x) ((x) << 0)
872 #define GRBM_STATUS2 0x8008
873 #define RLC_RQ_PENDING (1 << 0)
874 #define RLC_BUSY (1 << 8)
875 #define TC_BUSY (1 << 9)
877 #define GRBM_STATUS 0x8010
878 #define CMDFIFO_AVAIL_MASK 0x0000000F
879 #define RING2_RQ_PENDING (1 << 4)
880 #define SRBM_RQ_PENDING (1 << 5)
881 #define RING1_RQ_PENDING (1 << 6)
882 #define CF_RQ_PENDING (1 << 7)
883 #define PF_RQ_PENDING (1 << 8)
884 #define GDS_DMA_RQ_PENDING (1 << 9)
885 #define GRBM_EE_BUSY (1 << 10)
886 #define DB_CLEAN (1 << 12)
887 #define CB_CLEAN (1 << 13)
888 #define TA_BUSY (1 << 14)
889 #define GDS_BUSY (1 << 15)
890 #define VGT_BUSY (1 << 17)
891 #define IA_BUSY_NO_DMA (1 << 18)
892 #define IA_BUSY (1 << 19)
893 #define SX_BUSY (1 << 20)
894 #define SPI_BUSY (1 << 22)
895 #define BCI_BUSY (1 << 23)
896 #define SC_BUSY (1 << 24)
897 #define PA_BUSY (1 << 25)
898 #define DB_BUSY (1 << 26)
899 #define CP_COHERENCY_BUSY (1 << 28)
900 #define CP_BUSY (1 << 29)
901 #define CB_BUSY (1 << 30)
902 #define GUI_ACTIVE (1 << 31)
903 #define GRBM_STATUS_SE0 0x8014
904 #define GRBM_STATUS_SE1 0x8018
905 #define SE_DB_CLEAN (1 << 1)
906 #define SE_CB_CLEAN (1 << 2)
907 #define SE_BCI_BUSY (1 << 22)
908 #define SE_VGT_BUSY (1 << 23)
909 #define SE_PA_BUSY (1 << 24)
910 #define SE_TA_BUSY (1 << 25)
911 #define SE_SX_BUSY (1 << 26)
912 #define SE_SPI_BUSY (1 << 27)
913 #define SE_SC_BUSY (1 << 29)
914 #define SE_DB_BUSY (1 << 30)
915 #define SE_CB_BUSY (1 << 31)
917 #define GRBM_SOFT_RESET 0x8020
918 #define SOFT_RESET_CP (1 << 0)
919 #define SOFT_RESET_CB (1 << 1)
920 #define SOFT_RESET_RLC (1 << 2)
921 #define SOFT_RESET_DB (1 << 3)
922 #define SOFT_RESET_GDS (1 << 4)
923 #define SOFT_RESET_PA (1 << 5)
924 #define SOFT_RESET_SC (1 << 6)
925 #define SOFT_RESET_BCI (1 << 7)
926 #define SOFT_RESET_SPI (1 << 8)
927 #define SOFT_RESET_SX (1 << 10)
928 #define SOFT_RESET_TC (1 << 11)
929 #define SOFT_RESET_TA (1 << 12)
930 #define SOFT_RESET_VGT (1 << 14)
931 #define SOFT_RESET_IA (1 << 15)
933 #define GRBM_GFX_INDEX 0x802C
934 #define INSTANCE_INDEX(x) ((x) << 0)
935 #define SH_INDEX(x) ((x) << 8)
936 #define SE_INDEX(x) ((x) << 16)
937 #define SH_BROADCAST_WRITES (1 << 29)
938 #define INSTANCE_BROADCAST_WRITES (1 << 30)
939 #define SE_BROADCAST_WRITES (1 << 31)
941 #define GRBM_INT_CNTL 0x8060
942 # define RDERR_INT_ENABLE (1 << 0)
943 # define GUI_IDLE_INT_ENABLE (1 << 19)
945 #define CP_STRMOUT_CNTL 0x84FC
946 #define SCRATCH_REG0 0x8500
947 #define SCRATCH_REG1 0x8504
948 #define SCRATCH_REG2 0x8508
949 #define SCRATCH_REG3 0x850C
950 #define SCRATCH_REG4 0x8510
951 #define SCRATCH_REG5 0x8514
952 #define SCRATCH_REG6 0x8518
953 #define SCRATCH_REG7 0x851C
955 #define SCRATCH_UMSK 0x8540
956 #define SCRATCH_ADDR 0x8544
958 #define CP_SEM_WAIT_TIMER 0x85BC
960 #define CP_SEM_INCOMPLETE_TIMER_CNTL 0x85C8
962 #define CP_ME_CNTL 0x86D8
963 #define CP_CE_HALT (1 << 24)
964 #define CP_PFP_HALT (1 << 26)
965 #define CP_ME_HALT (1 << 28)
967 #define CP_COHER_CNTL2 0x85E8
969 #define CP_RB2_RPTR 0x86f8
970 #define CP_RB1_RPTR 0x86fc
971 #define CP_RB0_RPTR 0x8700
972 #define CP_RB_WPTR_DELAY 0x8704
974 #define CP_QUEUE_THRESHOLDS 0x8760
975 #define ROQ_IB1_START(x) ((x) << 0)
976 #define ROQ_IB2_START(x) ((x) << 8)
977 #define CP_MEQ_THRESHOLDS 0x8764
978 #define MEQ1_START(x) ((x) << 0)
979 #define MEQ2_START(x) ((x) << 8)
981 #define CP_PERFMON_CNTL 0x87FC
983 #define VGT_VTX_VECT_EJECT_REG 0x88B0
985 #define VGT_CACHE_INVALIDATION 0x88C4
986 #define CACHE_INVALIDATION(x) ((x) << 0)
990 #define AUTO_INVLD_EN(x) ((x) << 6)
994 #define ES_AND_GS_AUTO 3
995 #define VGT_ESGS_RING_SIZE 0x88C8
996 #define VGT_GSVS_RING_SIZE 0x88CC
998 #define VGT_GS_VERTEX_REUSE 0x88D4
1000 #define VGT_PRIMITIVE_TYPE 0x8958
1001 #define VGT_INDEX_TYPE 0x895C
1003 #define VGT_NUM_INDICES 0x8970
1004 #define VGT_NUM_INSTANCES 0x8974
1006 #define VGT_TF_RING_SIZE 0x8988
1008 #define VGT_HS_OFFCHIP_PARAM 0x89B0
1010 #define VGT_TF_MEMORY_BASE 0x89B8
1012 #define CC_GC_SHADER_ARRAY_CONFIG 0x89bc
1013 #define INACTIVE_CUS_MASK 0xFFFF0000
1014 #define INACTIVE_CUS_SHIFT 16
1015 #define GC_USER_SHADER_ARRAY_CONFIG 0x89c0
1017 #define PA_CL_ENHANCE 0x8A14
1018 #define CLIP_VTX_REORDER_ENA (1 << 0)
1019 #define NUM_CLIP_SEQ(x) ((x) << 1)
1021 #define PA_SU_LINE_STIPPLE_VALUE 0x8A60
1023 #define PA_SC_LINE_STIPPLE_STATE 0x8B10
1025 #define PA_SC_FORCE_EOV_MAX_CNTS 0x8B24
1026 #define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0)
1027 #define FORCE_EOV_MAX_REZ_CNT(x) ((x) << 16)
1029 #define PA_SC_FIFO_SIZE 0x8BCC
1030 #define SC_FRONTEND_PRIM_FIFO_SIZE(x) ((x) << 0)
1031 #define SC_BACKEND_PRIM_FIFO_SIZE(x) ((x) << 6)
1032 #define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 15)
1033 #define SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 23)
1035 #define PA_SC_ENHANCE 0x8BF0
1037 #define SQ_CONFIG 0x8C00
1039 #define SQC_CACHES 0x8C08
1041 #define SQ_POWER_THROTTLE 0x8e58
1042 #define MIN_POWER(x) ((x) << 0)
1043 #define MIN_POWER_MASK (0x3fff << 0)
1044 #define MIN_POWER_SHIFT 0
1045 #define MAX_POWER(x) ((x) << 16)
1046 #define MAX_POWER_MASK (0x3fff << 16)
1047 #define MAX_POWER_SHIFT 0
1048 #define SQ_POWER_THROTTLE2 0x8e5c
1049 #define MAX_POWER_DELTA(x) ((x) << 0)
1050 #define MAX_POWER_DELTA_MASK (0x3fff << 0)
1051 #define MAX_POWER_DELTA_SHIFT 0
1052 #define STI_SIZE(x) ((x) << 16)
1053 #define STI_SIZE_MASK (0x3ff << 16)
1054 #define STI_SIZE_SHIFT 16
1055 #define LTI_RATIO(x) ((x) << 27)
1056 #define LTI_RATIO_MASK (0xf << 27)
1057 #define LTI_RATIO_SHIFT 27
1059 #define SX_DEBUG_1 0x9060
1061 #define SPI_STATIC_THREAD_MGMT_1 0x90E0
1062 #define SPI_STATIC_THREAD_MGMT_2 0x90E4
1063 #define SPI_STATIC_THREAD_MGMT_3 0x90E8
1064 #define SPI_PS_MAX_WAVE_ID 0x90EC
1066 #define SPI_CONFIG_CNTL 0x9100
1068 #define SPI_CONFIG_CNTL_1 0x913C
1069 #define VTX_DONE_DELAY(x) ((x) << 0)
1070 #define INTERP_ONE_PRIM_PER_ROW (1 << 4)
1072 #define CGTS_TCC_DISABLE 0x9148
1073 #define CGTS_USER_TCC_DISABLE 0x914C
1074 #define TCC_DISABLE_MASK 0xFFFF0000
1075 #define TCC_DISABLE_SHIFT 16
1076 #define CGTS_SM_CTRL_REG 0x9150
1077 #define OVERRIDE (1 << 21)
1078 #define LS_OVERRIDE (1 << 22)
1080 #define SPI_LB_CU_MASK 0x9354
1082 #define TA_CNTL_AUX 0x9508
1084 #define CC_RB_BACKEND_DISABLE 0x98F4
1085 #define BACKEND_DISABLE(x) ((x) << 16)
1086 #define GB_ADDR_CONFIG 0x98F8
1087 #define NUM_PIPES(x) ((x) << 0)
1088 #define NUM_PIPES_MASK 0x00000007
1089 #define NUM_PIPES_SHIFT 0
1090 #define PIPE_INTERLEAVE_SIZE(x) ((x) << 4)
1091 #define PIPE_INTERLEAVE_SIZE_MASK 0x00000070
1092 #define PIPE_INTERLEAVE_SIZE_SHIFT 4
1093 #define NUM_SHADER_ENGINES(x) ((x) << 12)
1094 #define NUM_SHADER_ENGINES_MASK 0x00003000
1095 #define NUM_SHADER_ENGINES_SHIFT 12
1096 #define SHADER_ENGINE_TILE_SIZE(x) ((x) << 16)
1097 #define SHADER_ENGINE_TILE_SIZE_MASK 0x00070000
1098 #define SHADER_ENGINE_TILE_SIZE_SHIFT 16
1099 #define NUM_GPUS(x) ((x) << 20)
1100 #define NUM_GPUS_MASK 0x00700000
1101 #define NUM_GPUS_SHIFT 20
1102 #define MULTI_GPU_TILE_SIZE(x) ((x) << 24)
1103 #define MULTI_GPU_TILE_SIZE_MASK 0x03000000
1104 #define MULTI_GPU_TILE_SIZE_SHIFT 24
1105 #define ROW_SIZE(x) ((x) << 28)
1106 #define ROW_SIZE_MASK 0x30000000
1107 #define ROW_SIZE_SHIFT 28
1109 #define GB_TILE_MODE0 0x9910
1110 # define MICRO_TILE_MODE(x) ((x) << 0)
1111 # define ADDR_SURF_DISPLAY_MICRO_TILING 0
1112 # define ADDR_SURF_THIN_MICRO_TILING 1
1113 # define ADDR_SURF_DEPTH_MICRO_TILING 2
1114 # define ARRAY_MODE(x) ((x) << 2)
1115 # define ARRAY_LINEAR_GENERAL 0
1116 # define ARRAY_LINEAR_ALIGNED 1
1117 # define ARRAY_1D_TILED_THIN1 2
1118 # define ARRAY_2D_TILED_THIN1 4
1119 # define PIPE_CONFIG(x) ((x) << 6)
1120 # define ADDR_SURF_P2 0
1121 # define ADDR_SURF_P4_8x16 4
1122 # define ADDR_SURF_P4_16x16 5
1123 # define ADDR_SURF_P4_16x32 6
1124 # define ADDR_SURF_P4_32x32 7
1125 # define ADDR_SURF_P8_16x16_8x16 8
1126 # define ADDR_SURF_P8_16x32_8x16 9
1127 # define ADDR_SURF_P8_32x32_8x16 10
1128 # define ADDR_SURF_P8_16x32_16x16 11
1129 # define ADDR_SURF_P8_32x32_16x16 12
1130 # define ADDR_SURF_P8_32x32_16x32 13
1131 # define ADDR_SURF_P8_32x64_32x32 14
1132 # define TILE_SPLIT(x) ((x) << 11)
1133 # define ADDR_SURF_TILE_SPLIT_64B 0
1134 # define ADDR_SURF_TILE_SPLIT_128B 1
1135 # define ADDR_SURF_TILE_SPLIT_256B 2
1136 # define ADDR_SURF_TILE_SPLIT_512B 3
1137 # define ADDR_SURF_TILE_SPLIT_1KB 4
1138 # define ADDR_SURF_TILE_SPLIT_2KB 5
1139 # define ADDR_SURF_TILE_SPLIT_4KB 6
1140 # define BANK_WIDTH(x) ((x) << 14)
1141 # define ADDR_SURF_BANK_WIDTH_1 0
1142 # define ADDR_SURF_BANK_WIDTH_2 1
1143 # define ADDR_SURF_BANK_WIDTH_4 2
1144 # define ADDR_SURF_BANK_WIDTH_8 3
1145 # define BANK_HEIGHT(x) ((x) << 16)
1146 # define ADDR_SURF_BANK_HEIGHT_1 0
1147 # define ADDR_SURF_BANK_HEIGHT_2 1
1148 # define ADDR_SURF_BANK_HEIGHT_4 2
1149 # define ADDR_SURF_BANK_HEIGHT_8 3
1150 # define MACRO_TILE_ASPECT(x) ((x) << 18)
1151 # define ADDR_SURF_MACRO_ASPECT_1 0
1152 # define ADDR_SURF_MACRO_ASPECT_2 1
1153 # define ADDR_SURF_MACRO_ASPECT_4 2
1154 # define ADDR_SURF_MACRO_ASPECT_8 3
1155 # define NUM_BANKS(x) ((x) << 20)
1156 # define ADDR_SURF_2_BANK 0
1157 # define ADDR_SURF_4_BANK 1
1158 # define ADDR_SURF_8_BANK 2
1159 # define ADDR_SURF_16_BANK 3
1161 #define CB_PERFCOUNTER0_SELECT0 0x9a20
1162 #define CB_PERFCOUNTER0_SELECT1 0x9a24
1163 #define CB_PERFCOUNTER1_SELECT0 0x9a28
1164 #define CB_PERFCOUNTER1_SELECT1 0x9a2c
1165 #define CB_PERFCOUNTER2_SELECT0 0x9a30
1166 #define CB_PERFCOUNTER2_SELECT1 0x9a34
1167 #define CB_PERFCOUNTER3_SELECT0 0x9a38
1168 #define CB_PERFCOUNTER3_SELECT1 0x9a3c
1170 #define CB_CGTT_SCLK_CTRL 0x9a60
1172 #define GC_USER_RB_BACKEND_DISABLE 0x9B7C
1173 #define BACKEND_DISABLE_MASK 0x00FF0000
1174 #define BACKEND_DISABLE_SHIFT 16
1176 #define TCP_CHAN_STEER_LO 0xac0c
1177 #define TCP_CHAN_STEER_HI 0xac10
1179 #define CP_RB0_BASE 0xC100
1180 #define CP_RB0_CNTL 0xC104
1181 #define RB_BUFSZ(x) ((x) << 0)
1182 #define RB_BLKSZ(x) ((x) << 8)
1183 #define BUF_SWAP_32BIT (2 << 16)
1184 #define RB_NO_UPDATE (1 << 27)
1185 #define RB_RPTR_WR_ENA (1 << 31)
1187 #define CP_RB0_RPTR_ADDR 0xC10C
1188 #define CP_RB0_RPTR_ADDR_HI 0xC110
1189 #define CP_RB0_WPTR 0xC114
1191 #define CP_PFP_UCODE_ADDR 0xC150
1192 #define CP_PFP_UCODE_DATA 0xC154
1193 #define CP_ME_RAM_RADDR 0xC158
1194 #define CP_ME_RAM_WADDR 0xC15C
1195 #define CP_ME_RAM_DATA 0xC160
1197 #define CP_CE_UCODE_ADDR 0xC168
1198 #define CP_CE_UCODE_DATA 0xC16C
1200 #define CP_RB1_BASE 0xC180
1201 #define CP_RB1_CNTL 0xC184
1202 #define CP_RB1_RPTR_ADDR 0xC188
1203 #define CP_RB1_RPTR_ADDR_HI 0xC18C
1204 #define CP_RB1_WPTR 0xC190
1205 #define CP_RB2_BASE 0xC194
1206 #define CP_RB2_CNTL 0xC198
1207 #define CP_RB2_RPTR_ADDR 0xC19C
1208 #define CP_RB2_RPTR_ADDR_HI 0xC1A0
1209 #define CP_RB2_WPTR 0xC1A4
1210 #define CP_INT_CNTL_RING0 0xC1A8
1211 #define CP_INT_CNTL_RING1 0xC1AC
1212 #define CP_INT_CNTL_RING2 0xC1B0
1213 # define CNTX_BUSY_INT_ENABLE (1 << 19)
1214 # define CNTX_EMPTY_INT_ENABLE (1 << 20)
1215 # define WAIT_MEM_SEM_INT_ENABLE (1 << 21)
1216 # define TIME_STAMP_INT_ENABLE (1 << 26)
1217 # define CP_RINGID2_INT_ENABLE (1 << 29)
1218 # define CP_RINGID1_INT_ENABLE (1 << 30)
1219 # define CP_RINGID0_INT_ENABLE (1 << 31)
1220 #define CP_INT_STATUS_RING0 0xC1B4
1221 #define CP_INT_STATUS_RING1 0xC1B8
1222 #define CP_INT_STATUS_RING2 0xC1BC
1223 # define WAIT_MEM_SEM_INT_STAT (1 << 21)
1224 # define TIME_STAMP_INT_STAT (1 << 26)
1225 # define CP_RINGID2_INT_STAT (1 << 29)
1226 # define CP_RINGID1_INT_STAT (1 << 30)
1227 # define CP_RINGID0_INT_STAT (1 << 31)
1229 #define CP_MEM_SLP_CNTL 0xC1E4
1230 # define CP_MEM_LS_EN (1 << 0)
1232 #define CP_DEBUG 0xC1FC
1234 #define RLC_CNTL 0xC300
1235 # define RLC_ENABLE (1 << 0)
1236 #define RLC_RL_BASE 0xC304
1237 #define RLC_RL_SIZE 0xC308
1238 #define RLC_LB_CNTL 0xC30C
1239 # define LOAD_BALANCE_ENABLE (1 << 0)
1240 #define RLC_SAVE_AND_RESTORE_BASE 0xC310
1241 #define RLC_LB_CNTR_MAX 0xC314
1242 #define RLC_LB_CNTR_INIT 0xC318
1244 #define RLC_CLEAR_STATE_RESTORE_BASE 0xC320
1246 #define RLC_UCODE_ADDR 0xC32C
1247 #define RLC_UCODE_DATA 0xC330
1249 #define RLC_GPU_CLOCK_COUNT_LSB 0xC338
1250 #define RLC_GPU_CLOCK_COUNT_MSB 0xC33C
1251 #define RLC_CAPTURE_GPU_CLOCK_COUNT 0xC340
1252 #define RLC_MC_CNTL 0xC344
1253 #define RLC_UCODE_CNTL 0xC348
1254 #define RLC_STAT 0xC34C
1255 # define RLC_BUSY_STATUS (1 << 0)
1256 # define GFX_POWER_STATUS (1 << 1)
1257 # define GFX_CLOCK_STATUS (1 << 2)
1258 # define GFX_LS_STATUS (1 << 3)
1260 #define RLC_PG_CNTL 0xC35C
1261 # define GFX_PG_ENABLE (1 << 0)
1262 # define GFX_PG_SRC (1 << 1)
1264 #define RLC_CGTT_MGCG_OVERRIDE 0xC400
1265 #define RLC_CGCG_CGLS_CTRL 0xC404
1266 # define CGCG_EN (1 << 0)
1267 # define CGLS_EN (1 << 1)
1269 #define RLC_TTOP_D 0xC414
1270 # define RLC_PUD(x) ((x) << 0)
1271 # define RLC_PUD_MASK (0xff << 0)
1272 # define RLC_PDD(x) ((x) << 8)
1273 # define RLC_PDD_MASK (0xff << 8)
1274 # define RLC_TTPD(x) ((x) << 16)
1275 # define RLC_TTPD_MASK (0xff << 16)
1276 # define RLC_MSD(x) ((x) << 24)
1277 # define RLC_MSD_MASK (0xff << 24)
1279 #define RLC_LB_INIT_CU_MASK 0xC41C
1281 #define RLC_PG_AO_CU_MASK 0xC42C
1282 #define RLC_MAX_PG_CU 0xC430
1283 # define MAX_PU_CU(x) ((x) << 0)
1284 # define MAX_PU_CU_MASK (0xff << 0)
1285 #define RLC_AUTO_PG_CTRL 0xC434
1286 # define AUTO_PG_EN (1 << 0)
1287 # define GRBM_REG_SGIT(x) ((x) << 3)
1288 # define GRBM_REG_SGIT_MASK (0xffff << 3)
1289 # define PG_AFTER_GRBM_REG_ST(x) ((x) << 19)
1290 # define PG_AFTER_GRBM_REG_ST_MASK (0x1fff << 19)
1292 #define RLC_SERDES_WR_MASTER_MASK_0 0xC454
1293 #define RLC_SERDES_WR_MASTER_MASK_1 0xC458
1294 #define RLC_SERDES_WR_CTRL 0xC45C
1296 #define RLC_SERDES_MASTER_BUSY_0 0xC464
1297 #define RLC_SERDES_MASTER_BUSY_1 0xC468
1299 #define RLC_GCPM_GENERAL_3 0xC478
1301 #define DB_RENDER_CONTROL 0x28000
1303 #define DB_DEPTH_INFO 0x2803c
1305 #define PA_SC_RASTER_CONFIG 0x28350
1306 # define RASTER_CONFIG_RB_MAP_0 0
1307 # define RASTER_CONFIG_RB_MAP_1 1
1308 # define RASTER_CONFIG_RB_MAP_2 2
1309 # define RASTER_CONFIG_RB_MAP_3 3
1311 #define VGT_EVENT_INITIATOR 0x28a90
1312 # define SAMPLE_STREAMOUTSTATS1 (1 << 0)
1313 # define SAMPLE_STREAMOUTSTATS2 (2 << 0)
1314 # define SAMPLE_STREAMOUTSTATS3 (3 << 0)
1315 # define CACHE_FLUSH_TS (4 << 0)
1316 # define CACHE_FLUSH (6 << 0)
1317 # define CS_PARTIAL_FLUSH (7 << 0)
1318 # define VGT_STREAMOUT_RESET (10 << 0)
1319 # define END_OF_PIPE_INCR_DE (11 << 0)
1320 # define END_OF_PIPE_IB_END (12 << 0)
1321 # define RST_PIX_CNT (13 << 0)
1322 # define VS_PARTIAL_FLUSH (15 << 0)
1323 # define PS_PARTIAL_FLUSH (16 << 0)
1324 # define CACHE_FLUSH_AND_INV_TS_EVENT (20 << 0)
1325 # define ZPASS_DONE (21 << 0)
1326 # define CACHE_FLUSH_AND_INV_EVENT (22 << 0)
1327 # define PERFCOUNTER_START (23 << 0)
1328 # define PERFCOUNTER_STOP (24 << 0)
1329 # define PIPELINESTAT_START (25 << 0)
1330 # define PIPELINESTAT_STOP (26 << 0)
1331 # define PERFCOUNTER_SAMPLE (27 << 0)
1332 # define SAMPLE_PIPELINESTAT (30 << 0)
1333 # define SAMPLE_STREAMOUTSTATS (32 << 0)
1334 # define RESET_VTX_CNT (33 << 0)
1335 # define VGT_FLUSH (36 << 0)
1336 # define BOTTOM_OF_PIPE_TS (40 << 0)
1337 # define DB_CACHE_FLUSH_AND_INV (42 << 0)
1338 # define FLUSH_AND_INV_DB_DATA_TS (43 << 0)
1339 # define FLUSH_AND_INV_DB_META (44 << 0)
1340 # define FLUSH_AND_INV_CB_DATA_TS (45 << 0)
1341 # define FLUSH_AND_INV_CB_META (46 << 0)
1342 # define CS_DONE (47 << 0)
1343 # define PS_DONE (48 << 0)
1344 # define FLUSH_AND_INV_CB_PIXEL_DATA (49 << 0)
1345 # define THREAD_TRACE_START (51 << 0)
1346 # define THREAD_TRACE_STOP (52 << 0)
1347 # define THREAD_TRACE_FLUSH (54 << 0)
1348 # define THREAD_TRACE_FINISH (55 << 0)
1350 /* PIF PHY0 registers idx/data 0x8/0xc */
1351 #define PB0_PIF_CNTL 0x10
1352 # define LS2_EXIT_TIME(x) ((x) << 17)
1353 # define LS2_EXIT_TIME_MASK (0x7 << 17)
1354 # define LS2_EXIT_TIME_SHIFT 17
1355 #define PB0_PIF_PAIRING 0x11
1356 # define MULTI_PIF (1 << 25)
1357 #define PB0_PIF_PWRDOWN_0 0x12
1358 # define PLL_POWER_STATE_IN_TXS2_0(x) ((x) << 7)
1359 # define PLL_POWER_STATE_IN_TXS2_0_MASK (0x7 << 7)
1360 # define PLL_POWER_STATE_IN_TXS2_0_SHIFT 7
1361 # define PLL_POWER_STATE_IN_OFF_0(x) ((x) << 10)
1362 # define PLL_POWER_STATE_IN_OFF_0_MASK (0x7 << 10)
1363 # define PLL_POWER_STATE_IN_OFF_0_SHIFT 10
1364 # define PLL_RAMP_UP_TIME_0(x) ((x) << 24)
1365 # define PLL_RAMP_UP_TIME_0_MASK (0x7 << 24)
1366 # define PLL_RAMP_UP_TIME_0_SHIFT 24
1367 #define PB0_PIF_PWRDOWN_1 0x13
1368 # define PLL_POWER_STATE_IN_TXS2_1(x) ((x) << 7)
1369 # define PLL_POWER_STATE_IN_TXS2_1_MASK (0x7 << 7)
1370 # define PLL_POWER_STATE_IN_TXS2_1_SHIFT 7
1371 # define PLL_POWER_STATE_IN_OFF_1(x) ((x) << 10)
1372 # define PLL_POWER_STATE_IN_OFF_1_MASK (0x7 << 10)
1373 # define PLL_POWER_STATE_IN_OFF_1_SHIFT 10
1374 # define PLL_RAMP_UP_TIME_1(x) ((x) << 24)
1375 # define PLL_RAMP_UP_TIME_1_MASK (0x7 << 24)
1376 # define PLL_RAMP_UP_TIME_1_SHIFT 24
1378 #define PB0_PIF_PWRDOWN_2 0x17
1379 # define PLL_POWER_STATE_IN_TXS2_2(x) ((x) << 7)
1380 # define PLL_POWER_STATE_IN_TXS2_2_MASK (0x7 << 7)
1381 # define PLL_POWER_STATE_IN_TXS2_2_SHIFT 7
1382 # define PLL_POWER_STATE_IN_OFF_2(x) ((x) << 10)
1383 # define PLL_POWER_STATE_IN_OFF_2_MASK (0x7 << 10)
1384 # define PLL_POWER_STATE_IN_OFF_2_SHIFT 10
1385 # define PLL_RAMP_UP_TIME_2(x) ((x) << 24)
1386 # define PLL_RAMP_UP_TIME_2_MASK (0x7 << 24)
1387 # define PLL_RAMP_UP_TIME_2_SHIFT 24
1388 #define PB0_PIF_PWRDOWN_3 0x18
1389 # define PLL_POWER_STATE_IN_TXS2_3(x) ((x) << 7)
1390 # define PLL_POWER_STATE_IN_TXS2_3_MASK (0x7 << 7)
1391 # define PLL_POWER_STATE_IN_TXS2_3_SHIFT 7
1392 # define PLL_POWER_STATE_IN_OFF_3(x) ((x) << 10)
1393 # define PLL_POWER_STATE_IN_OFF_3_MASK (0x7 << 10)
1394 # define PLL_POWER_STATE_IN_OFF_3_SHIFT 10
1395 # define PLL_RAMP_UP_TIME_3(x) ((x) << 24)
1396 # define PLL_RAMP_UP_TIME_3_MASK (0x7 << 24)
1397 # define PLL_RAMP_UP_TIME_3_SHIFT 24
1398 /* PIF PHY1 registers idx/data 0x10/0x14 */
1399 #define PB1_PIF_CNTL 0x10
1400 #define PB1_PIF_PAIRING 0x11
1401 #define PB1_PIF_PWRDOWN_0 0x12
1402 #define PB1_PIF_PWRDOWN_1 0x13
1404 #define PB1_PIF_PWRDOWN_2 0x17
1405 #define PB1_PIF_PWRDOWN_3 0x18
1406 /* PCIE registers idx/data 0x30/0x34 */
1407 #define PCIE_CNTL2 0x1c /* PCIE */
1408 # define SLV_MEM_LS_EN (1 << 16)
1409 # define SLV_MEM_AGGRESSIVE_LS_EN (1 << 17)
1410 # define MST_MEM_LS_EN (1 << 18)
1411 # define REPLAY_MEM_LS_EN (1 << 19)
1412 #define PCIE_LC_STATUS1 0x28 /* PCIE */
1413 # define LC_REVERSE_RCVR (1 << 0)
1414 # define LC_REVERSE_XMIT (1 << 1)
1415 # define LC_OPERATING_LINK_WIDTH_MASK (0x7 << 2)
1416 # define LC_OPERATING_LINK_WIDTH_SHIFT 2
1417 # define LC_DETECTED_LINK_WIDTH_MASK (0x7 << 5)
1418 # define LC_DETECTED_LINK_WIDTH_SHIFT 5
1420 #define PCIE_P_CNTL 0x40 /* PCIE */
1421 # define P_IGNORE_EDB_ERR (1 << 6)
1423 /* PCIE PORT registers idx/data 0x38/0x3c */
1424 #define PCIE_LC_CNTL 0xa0
1425 # define LC_L0S_INACTIVITY(x) ((x) << 8)
1426 # define LC_L0S_INACTIVITY_MASK (0xf << 8)
1427 # define LC_L0S_INACTIVITY_SHIFT 8
1428 # define LC_L1_INACTIVITY(x) ((x) << 12)
1429 # define LC_L1_INACTIVITY_MASK (0xf << 12)
1430 # define LC_L1_INACTIVITY_SHIFT 12
1431 # define LC_PMI_TO_L1_DIS (1 << 16)
1432 # define LC_ASPM_TO_L1_DIS (1 << 24)
1433 #define PCIE_LC_LINK_WIDTH_CNTL 0xa2 /* PCIE_P */
1434 # define LC_LINK_WIDTH_SHIFT 0
1435 # define LC_LINK_WIDTH_MASK 0x7
1436 # define LC_LINK_WIDTH_X0 0
1437 # define LC_LINK_WIDTH_X1 1
1438 # define LC_LINK_WIDTH_X2 2
1439 # define LC_LINK_WIDTH_X4 3
1440 # define LC_LINK_WIDTH_X8 4
1441 # define LC_LINK_WIDTH_X16 6
1442 # define LC_LINK_WIDTH_RD_SHIFT 4
1443 # define LC_LINK_WIDTH_RD_MASK 0x70
1444 # define LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7)
1445 # define LC_RECONFIG_NOW (1 << 8)
1446 # define LC_RENEGOTIATION_SUPPORT (1 << 9)
1447 # define LC_RENEGOTIATE_EN (1 << 10)
1448 # define LC_SHORT_RECONFIG_EN (1 << 11)
1449 # define LC_UPCONFIGURE_SUPPORT (1 << 12)
1450 # define LC_UPCONFIGURE_DIS (1 << 13)
1451 # define LC_DYN_LANES_PWR_STATE(x) ((x) << 21)
1452 # define LC_DYN_LANES_PWR_STATE_MASK (0x3 << 21)
1453 # define LC_DYN_LANES_PWR_STATE_SHIFT 21
1454 #define PCIE_LC_N_FTS_CNTL 0xa3 /* PCIE_P */
1455 # define LC_XMIT_N_FTS(x) ((x) << 0)
1456 # define LC_XMIT_N_FTS_MASK (0xff << 0)
1457 # define LC_XMIT_N_FTS_SHIFT 0
1458 # define LC_XMIT_N_FTS_OVERRIDE_EN (1 << 8)
1459 # define LC_N_FTS_MASK (0xff << 24)
1460 #define PCIE_LC_SPEED_CNTL 0xa4 /* PCIE_P */
1461 # define LC_GEN2_EN_STRAP (1 << 0)
1462 # define LC_GEN3_EN_STRAP (1 << 1)
1463 # define LC_TARGET_LINK_SPEED_OVERRIDE_EN (1 << 2)
1464 # define LC_TARGET_LINK_SPEED_OVERRIDE_MASK (0x3 << 3)
1465 # define LC_TARGET_LINK_SPEED_OVERRIDE_SHIFT 3
1466 # define LC_FORCE_EN_SW_SPEED_CHANGE (1 << 5)
1467 # define LC_FORCE_DIS_SW_SPEED_CHANGE (1 << 6)
1468 # define LC_FORCE_EN_HW_SPEED_CHANGE (1 << 7)
1469 # define LC_FORCE_DIS_HW_SPEED_CHANGE (1 << 8)
1470 # define LC_INITIATE_LINK_SPEED_CHANGE (1 << 9)
1471 # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK (0x3 << 10)
1472 # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT 10
1473 # define LC_CURRENT_DATA_RATE_MASK (0x3 << 13) /* 0/1/2 = gen1/2/3 */
1474 # define LC_CURRENT_DATA_RATE_SHIFT 13
1475 # define LC_CLR_FAILED_SPD_CHANGE_CNT (1 << 16)
1476 # define LC_OTHER_SIDE_EVER_SENT_GEN2 (1 << 18)
1477 # define LC_OTHER_SIDE_SUPPORTS_GEN2 (1 << 19)
1478 # define LC_OTHER_SIDE_EVER_SENT_GEN3 (1 << 20)
1479 # define LC_OTHER_SIDE_SUPPORTS_GEN3 (1 << 21)
1481 #define PCIE_LC_CNTL2 0xb1
1482 # define LC_ALLOW_PDWN_IN_L1 (1 << 17)
1483 # define LC_ALLOW_PDWN_IN_L23 (1 << 18)
1485 #define PCIE_LC_CNTL3 0xb5 /* PCIE_P */
1486 # define LC_GO_TO_RECOVERY (1 << 30)
1487 #define PCIE_LC_CNTL4 0xb6 /* PCIE_P */
1488 # define LC_REDO_EQ (1 << 5)
1489 # define LC_SET_QUIESCE (1 << 13)
1494 #define UVD_UDEC_ADDR_CONFIG 0xEF4C
1495 #define UVD_UDEC_DB_ADDR_CONFIG 0xEF50
1496 #define UVD_UDEC_DBW_ADDR_CONFIG 0xEF54
1497 #define UVD_RBC_RB_RPTR 0xF690
1498 #define UVD_RBC_RB_WPTR 0xF694
1500 #define UVD_CGC_CTRL 0xF4B0
1501 # define DCM (1 << 0)
1502 # define CG_DT(x) ((x) << 2)
1503 # define CG_DT_MASK (0xf << 2)
1504 # define CLK_OD(x) ((x) << 6)
1505 # define CLK_OD_MASK (0x1f << 6)
1507 /* UVD CTX indirect */
1508 #define UVD_CGC_MEM_CTRL 0xC0
1509 #define UVD_CGC_CTRL2 0xC1
1510 # define DYN_OR_EN (1 << 0)
1511 # define DYN_RR_EN (1 << 1)
1512 # define G_DIV_ID(x) ((x) << 2)
1513 # define G_DIV_ID_MASK (0x7 << 2)
1518 #define PACKET0(reg, n) ((RADEON_PACKET_TYPE0 << 30) | \
1519 (((reg) >> 2) & 0xFFFF) | \
1520 ((n) & 0x3FFF) << 16)
1521 #define CP_PACKET2 0x80000000
1522 #define PACKET2_PAD_SHIFT 0
1523 #define PACKET2_PAD_MASK (0x3fffffff << 0)
1525 #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
1527 #define PACKET3(op, n) ((RADEON_PACKET_TYPE3 << 30) | \
1528 (((op) & 0xFF) << 8) | \
1529 ((n) & 0x3FFF) << 16)
1531 #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)
1533 /* Packet 3 types */
1534 #define PACKET3_NOP 0x10
1535 #define PACKET3_SET_BASE 0x11
1536 #define PACKET3_BASE_INDEX(x) ((x) << 0)
1537 #define GDS_PARTITION_BASE 2
1538 #define CE_PARTITION_BASE 3
1539 #define PACKET3_CLEAR_STATE 0x12
1540 #define PACKET3_INDEX_BUFFER_SIZE 0x13
1541 #define PACKET3_DISPATCH_DIRECT 0x15
1542 #define PACKET3_DISPATCH_INDIRECT 0x16
1543 #define PACKET3_ALLOC_GDS 0x1B
1544 #define PACKET3_WRITE_GDS_RAM 0x1C
1545 #define PACKET3_ATOMIC_GDS 0x1D
1546 #define PACKET3_ATOMIC 0x1E
1547 #define PACKET3_OCCLUSION_QUERY 0x1F
1548 #define PACKET3_SET_PREDICATION 0x20
1549 #define PACKET3_REG_RMW 0x21
1550 #define PACKET3_COND_EXEC 0x22
1551 #define PACKET3_PRED_EXEC 0x23
1552 #define PACKET3_DRAW_INDIRECT 0x24
1553 #define PACKET3_DRAW_INDEX_INDIRECT 0x25
1554 #define PACKET3_INDEX_BASE 0x26
1555 #define PACKET3_DRAW_INDEX_2 0x27
1556 #define PACKET3_CONTEXT_CONTROL 0x28
1557 #define PACKET3_INDEX_TYPE 0x2A
1558 #define PACKET3_DRAW_INDIRECT_MULTI 0x2C
1559 #define PACKET3_DRAW_INDEX_AUTO 0x2D
1560 #define PACKET3_DRAW_INDEX_IMMD 0x2E
1561 #define PACKET3_NUM_INSTANCES 0x2F
1562 #define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30
1563 #define PACKET3_INDIRECT_BUFFER_CONST 0x31
1564 #define PACKET3_INDIRECT_BUFFER 0x32
1565 #define PACKET3_STRMOUT_BUFFER_UPDATE 0x34
1566 #define PACKET3_DRAW_INDEX_OFFSET_2 0x35
1567 #define PACKET3_DRAW_INDEX_MULTI_ELEMENT 0x36
1568 #define PACKET3_WRITE_DATA 0x37
1569 #define WRITE_DATA_DST_SEL(x) ((x) << 8)
1571 * 1 - memory (sync - via GRBM)
1575 * 5 - memory (async - direct)
1577 #define WR_ONE_ADDR (1 << 16)
1578 #define WR_CONFIRM (1 << 20)
1579 #define WRITE_DATA_ENGINE_SEL(x) ((x) << 30)
1584 #define PACKET3_DRAW_INDEX_INDIRECT_MULTI 0x38
1585 #define PACKET3_MEM_SEMAPHORE 0x39
1586 #define PACKET3_MPEG_INDEX 0x3A
1587 #define PACKET3_COPY_DW 0x3B
1588 #define PACKET3_WAIT_REG_MEM 0x3C
1589 #define PACKET3_MEM_WRITE 0x3D
1590 #define PACKET3_COPY_DATA 0x40
1591 #define PACKET3_CP_DMA 0x41
1593 * 2. SRC_ADDR_LO or DATA [31:0]
1594 * 3. CP_SYNC [31] | SRC_SEL [30:29] | ENGINE [27] | DST_SEL [21:20] |
1596 * 4. DST_ADDR_LO [31:0]
1597 * 5. DST_ADDR_HI [7:0]
1598 * 6. COMMAND [30:21] | BYTE_COUNT [20:0]
1600 # define PACKET3_CP_DMA_DST_SEL(x) ((x) << 20)
1604 # define PACKET3_CP_DMA_ENGINE(x) ((x) << 27)
1608 # define PACKET3_CP_DMA_SRC_SEL(x) ((x) << 29)
1613 # define PACKET3_CP_DMA_CP_SYNC (1 << 31)
1615 # define PACKET3_CP_DMA_DIS_WC (1 << 21)
1616 # define PACKET3_CP_DMA_CMD_SRC_SWAP(x) ((x) << 23)
1622 # define PACKET3_CP_DMA_CMD_DST_SWAP(x) ((x) << 24)
1628 # define PACKET3_CP_DMA_CMD_SAS (1 << 26)
1632 # define PACKET3_CP_DMA_CMD_DAS (1 << 27)
1636 # define PACKET3_CP_DMA_CMD_SAIC (1 << 28)
1637 # define PACKET3_CP_DMA_CMD_DAIC (1 << 29)
1638 # define PACKET3_CP_DMA_CMD_RAW_WAIT (1 << 30)
1639 #define PACKET3_PFP_SYNC_ME 0x42
1640 #define PACKET3_SURFACE_SYNC 0x43
1641 # define PACKET3_DEST_BASE_0_ENA (1 << 0)
1642 # define PACKET3_DEST_BASE_1_ENA (1 << 1)
1643 # define PACKET3_CB0_DEST_BASE_ENA (1 << 6)
1644 # define PACKET3_CB1_DEST_BASE_ENA (1 << 7)
1645 # define PACKET3_CB2_DEST_BASE_ENA (1 << 8)
1646 # define PACKET3_CB3_DEST_BASE_ENA (1 << 9)
1647 # define PACKET3_CB4_DEST_BASE_ENA (1 << 10)
1648 # define PACKET3_CB5_DEST_BASE_ENA (1 << 11)
1649 # define PACKET3_CB6_DEST_BASE_ENA (1 << 12)
1650 # define PACKET3_CB7_DEST_BASE_ENA (1 << 13)
1651 # define PACKET3_DB_DEST_BASE_ENA (1 << 14)
1652 # define PACKET3_DEST_BASE_2_ENA (1 << 19)
1653 # define PACKET3_DEST_BASE_3_ENA (1 << 21)
1654 # define PACKET3_TCL1_ACTION_ENA (1 << 22)
1655 # define PACKET3_TC_ACTION_ENA (1 << 23)
1656 # define PACKET3_CB_ACTION_ENA (1 << 25)
1657 # define PACKET3_DB_ACTION_ENA (1 << 26)
1658 # define PACKET3_SH_KCACHE_ACTION_ENA (1 << 27)
1659 # define PACKET3_SH_ICACHE_ACTION_ENA (1 << 29)
1660 #define PACKET3_ME_INITIALIZE 0x44
1661 #define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16)
1662 #define PACKET3_COND_WRITE 0x45
1663 #define PACKET3_EVENT_WRITE 0x46
1664 #define EVENT_TYPE(x) ((x) << 0)
1665 #define EVENT_INDEX(x) ((x) << 8)
1666 /* 0 - any non-TS event
1668 * 2 - SAMPLE_PIPELINESTAT
1669 * 3 - SAMPLE_STREAMOUTSTAT*
1670 * 4 - *S_PARTIAL_FLUSH
1673 * 7 - CACHE_FLUSH, CACHE_FLUSH_AND_INV_EVENT
1675 #define INV_L2 (1 << 20)
1676 /* INV TC L2 cache when EVENT_INDEX = 7 */
1677 #define PACKET3_EVENT_WRITE_EOP 0x47
1678 #define DATA_SEL(x) ((x) << 29)
1680 * 1 - send low 32bit data
1681 * 2 - send 64bit data
1682 * 3 - send 64bit counter value
1684 #define INT_SEL(x) ((x) << 24)
1686 * 1 - interrupt only (DATA_SEL = 0)
1687 * 2 - interrupt when data write is confirmed
1689 #define PACKET3_EVENT_WRITE_EOS 0x48
1690 #define PACKET3_PREAMBLE_CNTL 0x4A
1691 # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28)
1692 # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28)
1693 #define PACKET3_ONE_REG_WRITE 0x57
1694 #define PACKET3_LOAD_CONFIG_REG 0x5F
1695 #define PACKET3_LOAD_CONTEXT_REG 0x60
1696 #define PACKET3_LOAD_SH_REG 0x61
1697 #define PACKET3_SET_CONFIG_REG 0x68
1698 #define PACKET3_SET_CONFIG_REG_START 0x00008000
1699 #define PACKET3_SET_CONFIG_REG_END 0x0000b000
1700 #define PACKET3_SET_CONTEXT_REG 0x69
1701 #define PACKET3_SET_CONTEXT_REG_START 0x00028000
1702 #define PACKET3_SET_CONTEXT_REG_END 0x00029000
1703 #define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73
1704 #define PACKET3_SET_RESOURCE_INDIRECT 0x74
1705 #define PACKET3_SET_SH_REG 0x76
1706 #define PACKET3_SET_SH_REG_START 0x0000b000
1707 #define PACKET3_SET_SH_REG_END 0x0000c000
1708 #define PACKET3_SET_SH_REG_OFFSET 0x77
1709 #define PACKET3_ME_WRITE 0x7A
1710 #define PACKET3_SCRATCH_RAM_WRITE 0x7D
1711 #define PACKET3_SCRATCH_RAM_READ 0x7E
1712 #define PACKET3_CE_WRITE 0x7F
1713 #define PACKET3_LOAD_CONST_RAM 0x80
1714 #define PACKET3_WRITE_CONST_RAM 0x81
1715 #define PACKET3_WRITE_CONST_RAM_OFFSET 0x82
1716 #define PACKET3_DUMP_CONST_RAM 0x83
1717 #define PACKET3_INCREMENT_CE_COUNTER 0x84
1718 #define PACKET3_INCREMENT_DE_COUNTER 0x85
1719 #define PACKET3_WAIT_ON_CE_COUNTER 0x86
1720 #define PACKET3_WAIT_ON_DE_COUNTER 0x87
1721 #define PACKET3_WAIT_ON_DE_COUNTER_DIFF 0x88
1722 #define PACKET3_SET_CE_DE_COUNTERS 0x89
1723 #define PACKET3_WAIT_ON_AVAIL_BUFFER 0x8A
1724 #define PACKET3_SWITCH_BUFFER 0x8B
1726 /* ASYNC DMA - first instance at 0xd000, second at 0xd800 */
1727 #define DMA0_REGISTER_OFFSET 0x0 /* not a register */
1728 #define DMA1_REGISTER_OFFSET 0x800 /* not a register */
1730 #define DMA_RB_CNTL 0xd000
1731 # define DMA_RB_ENABLE (1 << 0)
1732 # define DMA_RB_SIZE(x) ((x) << 1) /* log2 */
1733 # define DMA_RB_SWAP_ENABLE (1 << 9) /* 8IN32 */
1734 # define DMA_RPTR_WRITEBACK_ENABLE (1 << 12)
1735 # define DMA_RPTR_WRITEBACK_SWAP_ENABLE (1 << 13) /* 8IN32 */
1736 # define DMA_RPTR_WRITEBACK_TIMER(x) ((x) << 16) /* log2 */
1737 #define DMA_RB_BASE 0xd004
1738 #define DMA_RB_RPTR 0xd008
1739 #define DMA_RB_WPTR 0xd00c
1741 #define DMA_RB_RPTR_ADDR_HI 0xd01c
1742 #define DMA_RB_RPTR_ADDR_LO 0xd020
1744 #define DMA_IB_CNTL 0xd024
1745 # define DMA_IB_ENABLE (1 << 0)
1746 # define DMA_IB_SWAP_ENABLE (1 << 4)
1747 #define DMA_IB_RPTR 0xd028
1748 #define DMA_CNTL 0xd02c
1749 # define TRAP_ENABLE (1 << 0)
1750 # define SEM_INCOMPLETE_INT_ENABLE (1 << 1)
1751 # define SEM_WAIT_INT_ENABLE (1 << 2)
1752 # define DATA_SWAP_ENABLE (1 << 3)
1753 # define FENCE_SWAP_ENABLE (1 << 4)
1754 # define CTXEMPTY_INT_ENABLE (1 << 28)
1755 #define DMA_STATUS_REG 0xd034
1756 # define DMA_IDLE (1 << 0)
1757 #define DMA_TILING_CONFIG 0xd0b8
1759 #define DMA_POWER_CNTL 0xd0bc
1760 # define MEM_POWER_OVERRIDE (1 << 8)
1761 #define DMA_CLK_CTRL 0xd0c0
1763 #define DMA_PG 0xd0d4
1764 # define PG_CNTL_ENABLE (1 << 0)
1765 #define DMA_PGFSM_CONFIG 0xd0d8
1766 #define DMA_PGFSM_WRITE 0xd0dc
1768 #define DMA_PACKET(cmd, b, t, s, n) ((((cmd) & 0xF) << 28) | \
1769 (((b) & 0x1) << 26) | \
1770 (((t) & 0x1) << 23) | \
1771 (((s) & 0x1) << 22) | \
1772 (((n) & 0xFFFFF) << 0))
1774 #define DMA_IB_PACKET(cmd, vmid, n) ((((cmd) & 0xF) << 28) | \
1775 (((vmid) & 0xF) << 20) | \
1776 (((n) & 0xFFFFF) << 0))
1778 #define DMA_PTE_PDE_PACKET(n) ((2 << 28) | \
1781 (((n) & 0xFFFFF) << 0))
1783 /* async DMA Packet types */
1784 #define DMA_PACKET_WRITE 0x2
1785 #define DMA_PACKET_COPY 0x3
1786 #define DMA_PACKET_INDIRECT_BUFFER 0x4
1787 #define DMA_PACKET_SEMAPHORE 0x5
1788 #define DMA_PACKET_FENCE 0x6
1789 #define DMA_PACKET_TRAP 0x7
1790 #define DMA_PACKET_SRBM_WRITE 0x9
1791 #define DMA_PACKET_CONSTANT_FILL 0xd
1792 #define DMA_PACKET_NOP 0xf
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