2 * Copyright 2011 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 * Authors: Alex Deucher
27 #define TAHITI_RB_BITMAP_WIDTH_PER_SH 2
29 #define TAHITI_GB_ADDR_CONFIG_GOLDEN 0x12011003
30 #define VERDE_GB_ADDR_CONFIG_GOLDEN 0x12010002
32 #define CG_MULT_THERMAL_STATUS 0x714
33 #define ASIC_MAX_TEMP(x) ((x) << 0)
34 #define ASIC_MAX_TEMP_MASK 0x000001ff
35 #define ASIC_MAX_TEMP_SHIFT 0
36 #define CTF_TEMP(x) ((x) << 9)
37 #define CTF_TEMP_MASK 0x0003fe00
38 #define CTF_TEMP_SHIFT 9
40 #define SI_MAX_SH_GPRS 256
41 #define SI_MAX_TEMP_GPRS 16
42 #define SI_MAX_SH_THREADS 256
43 #define SI_MAX_SH_STACK_ENTRIES 4096
44 #define SI_MAX_FRC_EOV_CNT 16384
45 #define SI_MAX_BACKENDS 8
46 #define SI_MAX_BACKENDS_MASK 0xFF
47 #define SI_MAX_BACKENDS_PER_SE_MASK 0x0F
48 #define SI_MAX_SIMDS 12
49 #define SI_MAX_SIMDS_MASK 0x0FFF
50 #define SI_MAX_SIMDS_PER_SE_MASK 0x00FF
51 #define SI_MAX_PIPES 8
52 #define SI_MAX_PIPES_MASK 0xFF
53 #define SI_MAX_PIPES_PER_SIMD_MASK 0x3F
54 #define SI_MAX_LDS_NUM 0xFFFF
56 #define SI_MAX_TCC_MASK 0xFFFF
58 #define VGA_HDP_CONTROL 0x328
59 #define VGA_MEMORY_DISABLE (1 << 4)
61 #define DMIF_ADDR_CONFIG 0xBD4
63 #define SRBM_STATUS 0xE50
65 #define CC_SYS_RB_BACKEND_DISABLE 0xe80
66 #define GC_USER_SYS_RB_BACKEND_DISABLE 0xe84
68 #define VM_L2_CNTL 0x1400
69 #define ENABLE_L2_CACHE (1 << 0)
70 #define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1)
71 #define L2_CACHE_PTE_ENDIAN_SWAP_MODE(x) ((x) << 2)
72 #define L2_CACHE_PDE_ENDIAN_SWAP_MODE(x) ((x) << 4)
73 #define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9)
74 #define ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE (1 << 10)
75 #define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 15)
76 #define CONTEXT1_IDENTITY_ACCESS_MODE(x) (((x) & 3) << 19)
77 #define VM_L2_CNTL2 0x1404
78 #define INVALIDATE_ALL_L1_TLBS (1 << 0)
79 #define INVALIDATE_L2_CACHE (1 << 1)
80 #define INVALIDATE_CACHE_MODE(x) ((x) << 26)
81 #define INVALIDATE_PTE_AND_PDE_CACHES 0
82 #define INVALIDATE_ONLY_PTE_CACHES 1
83 #define INVALIDATE_ONLY_PDE_CACHES 2
84 #define VM_L2_CNTL3 0x1408
85 #define BANK_SELECT(x) ((x) << 0)
86 #define L2_CACHE_UPDATE_MODE(x) ((x) << 6)
87 #define L2_CACHE_BIGK_FRAGMENT_SIZE(x) ((x) << 15)
88 #define L2_CACHE_BIGK_ASSOCIATIVITY (1 << 20)
89 #define VM_L2_STATUS 0x140C
90 #define L2_BUSY (1 << 0)
91 #define VM_CONTEXT0_CNTL 0x1410
92 #define ENABLE_CONTEXT (1 << 0)
93 #define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1)
94 #define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4)
95 #define VM_CONTEXT1_CNTL 0x1414
96 #define VM_CONTEXT0_CNTL2 0x1430
97 #define VM_CONTEXT1_CNTL2 0x1434
98 #define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR 0x1438
99 #define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR 0x143c
100 #define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR 0x1440
101 #define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR 0x1444
102 #define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR 0x1448
103 #define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR 0x144c
104 #define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR 0x1450
105 #define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR 0x1454
107 #define VM_INVALIDATE_REQUEST 0x1478
108 #define VM_INVALIDATE_RESPONSE 0x147c
110 #define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1518
111 #define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR 0x151c
113 #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153c
114 #define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR 0x1540
115 #define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR 0x1544
116 #define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR 0x1548
117 #define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR 0x154c
118 #define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR 0x1550
119 #define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR 0x1554
120 #define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR 0x1558
121 #define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155c
122 #define VM_CONTEXT1_PAGE_TABLE_START_ADDR 0x1560
124 #define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157C
125 #define VM_CONTEXT1_PAGE_TABLE_END_ADDR 0x1580
127 #define MC_SHARED_CHMAP 0x2004
128 #define NOOFCHAN_SHIFT 12
129 #define NOOFCHAN_MASK 0x0000f000
130 #define MC_SHARED_CHREMAP 0x2008
132 #define MC_VM_FB_LOCATION 0x2024
133 #define MC_VM_AGP_TOP 0x2028
134 #define MC_VM_AGP_BOT 0x202C
135 #define MC_VM_AGP_BASE 0x2030
136 #define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034
137 #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038
138 #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203C
140 #define MC_VM_MX_L1_TLB_CNTL 0x2064
141 #define ENABLE_L1_TLB (1 << 0)
142 #define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1)
143 #define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 3)
144 #define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 3)
145 #define SYSTEM_ACCESS_MODE_IN_SYS (2 << 3)
146 #define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 3)
147 #define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5)
148 #define ENABLE_ADVANCED_DRIVER_MODEL (1 << 6)
150 #define MC_SHARED_BLACKOUT_CNTL 0x20ac
152 #define MC_ARB_RAMCFG 0x2760
153 #define NOOFBANK_SHIFT 0
154 #define NOOFBANK_MASK 0x00000003
155 #define NOOFRANK_SHIFT 2
156 #define NOOFRANK_MASK 0x00000004
157 #define NOOFROWS_SHIFT 3
158 #define NOOFROWS_MASK 0x00000038
159 #define NOOFCOLS_SHIFT 6
160 #define NOOFCOLS_MASK 0x000000C0
161 #define CHANSIZE_SHIFT 8
162 #define CHANSIZE_MASK 0x00000100
163 #define CHANSIZE_OVERRIDE (1 << 11)
164 #define NOOFGROUPS_SHIFT 12
165 #define NOOFGROUPS_MASK 0x00001000
167 #define MC_SEQ_TRAIN_WAKEUP_CNTL 0x2808
168 #define TRAIN_DONE_D0 (1 << 30)
169 #define TRAIN_DONE_D1 (1 << 31)
171 #define MC_SEQ_SUP_CNTL 0x28c8
172 #define RUN_MASK (1 << 0)
173 #define MC_SEQ_SUP_PGM 0x28cc
175 #define MC_IO_PAD_CNTL_D0 0x29d0
176 #define MEM_FALL_OUT_CMD (1 << 8)
178 #define MC_SEQ_IO_DEBUG_INDEX 0x2a44
179 #define MC_SEQ_IO_DEBUG_DATA 0x2a48
181 #define HDP_HOST_PATH_CNTL 0x2C00
182 #define HDP_NONSURFACE_BASE 0x2C04
183 #define HDP_NONSURFACE_INFO 0x2C08
184 #define HDP_NONSURFACE_SIZE 0x2C0C
186 #define HDP_ADDR_CONFIG 0x2F48
187 #define HDP_MISC_CNTL 0x2F4C
188 #define HDP_FLUSH_INVALIDATE_CACHE (1 << 0)
190 #define IH_RB_CNTL 0x3e00
191 # define IH_RB_ENABLE (1 << 0)
192 # define IH_IB_SIZE(x) ((x) << 1) /* log2 */
193 # define IH_RB_FULL_DRAIN_ENABLE (1 << 6)
194 # define IH_WPTR_WRITEBACK_ENABLE (1 << 8)
195 # define IH_WPTR_WRITEBACK_TIMER(x) ((x) << 9) /* log2 */
196 # define IH_WPTR_OVERFLOW_ENABLE (1 << 16)
197 # define IH_WPTR_OVERFLOW_CLEAR (1 << 31)
198 #define IH_RB_BASE 0x3e04
199 #define IH_RB_RPTR 0x3e08
200 #define IH_RB_WPTR 0x3e0c
201 # define RB_OVERFLOW (1 << 0)
202 # define WPTR_OFFSET_MASK 0x3fffc
203 #define IH_RB_WPTR_ADDR_HI 0x3e10
204 #define IH_RB_WPTR_ADDR_LO 0x3e14
205 #define IH_CNTL 0x3e18
206 # define ENABLE_INTR (1 << 0)
207 # define IH_MC_SWAP(x) ((x) << 1)
208 # define IH_MC_SWAP_NONE 0
209 # define IH_MC_SWAP_16BIT 1
210 # define IH_MC_SWAP_32BIT 2
211 # define IH_MC_SWAP_64BIT 3
212 # define RPTR_REARM (1 << 4)
213 # define MC_WRREQ_CREDIT(x) ((x) << 15)
214 # define MC_WR_CLEAN_CNT(x) ((x) << 20)
215 # define MC_VMID(x) ((x) << 25)
217 #define CONFIG_MEMSIZE 0x5428
219 #define INTERRUPT_CNTL 0x5468
220 # define IH_DUMMY_RD_OVERRIDE (1 << 0)
221 # define IH_DUMMY_RD_EN (1 << 1)
222 # define IH_REQ_NONSNOOP_EN (1 << 3)
223 # define GEN_IH_INT_EN (1 << 8)
224 #define INTERRUPT_CNTL2 0x546c
226 #define HDP_MEM_COHERENCY_FLUSH_CNTL 0x5480
228 #define BIF_FB_EN 0x5490
229 #define FB_READ_EN (1 << 0)
230 #define FB_WRITE_EN (1 << 1)
232 #define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0
234 #define DC_LB_MEMORY_SPLIT 0x6b0c
235 #define DC_LB_MEMORY_CONFIG(x) ((x) << 20)
237 #define PRIORITY_A_CNT 0x6b18
238 #define PRIORITY_MARK_MASK 0x7fff
239 #define PRIORITY_OFF (1 << 16)
240 #define PRIORITY_ALWAYS_ON (1 << 20)
241 #define PRIORITY_B_CNT 0x6b1c
243 #define DPG_PIPE_ARBITRATION_CONTROL3 0x6cc8
244 # define LATENCY_WATERMARK_MASK(x) ((x) << 16)
245 #define DPG_PIPE_LATENCY_CONTROL 0x6ccc
246 # define LATENCY_LOW_WATERMARK(x) ((x) << 0)
247 # define LATENCY_HIGH_WATERMARK(x) ((x) << 16)
249 /* 0x6bb8, 0x77b8, 0x103b8, 0x10fb8, 0x11bb8, 0x127b8 */
250 #define VLINE_STATUS 0x6bb8
251 # define VLINE_OCCURRED (1 << 0)
252 # define VLINE_ACK (1 << 4)
253 # define VLINE_STAT (1 << 12)
254 # define VLINE_INTERRUPT (1 << 16)
255 # define VLINE_INTERRUPT_TYPE (1 << 17)
256 /* 0x6bbc, 0x77bc, 0x103bc, 0x10fbc, 0x11bbc, 0x127bc */
257 #define VBLANK_STATUS 0x6bbc
258 # define VBLANK_OCCURRED (1 << 0)
259 # define VBLANK_ACK (1 << 4)
260 # define VBLANK_STAT (1 << 12)
261 # define VBLANK_INTERRUPT (1 << 16)
262 # define VBLANK_INTERRUPT_TYPE (1 << 17)
264 /* 0x6b40, 0x7740, 0x10340, 0x10f40, 0x11b40, 0x12740 */
265 #define INT_MASK 0x6b40
266 # define VBLANK_INT_MASK (1 << 0)
267 # define VLINE_INT_MASK (1 << 4)
269 #define DISP_INTERRUPT_STATUS 0x60f4
270 # define LB_D1_VLINE_INTERRUPT (1 << 2)
271 # define LB_D1_VBLANK_INTERRUPT (1 << 3)
272 # define DC_HPD1_INTERRUPT (1 << 17)
273 # define DC_HPD1_RX_INTERRUPT (1 << 18)
274 # define DACA_AUTODETECT_INTERRUPT (1 << 22)
275 # define DACB_AUTODETECT_INTERRUPT (1 << 23)
276 # define DC_I2C_SW_DONE_INTERRUPT (1 << 24)
277 # define DC_I2C_HW_DONE_INTERRUPT (1 << 25)
278 #define DISP_INTERRUPT_STATUS_CONTINUE 0x60f8
279 # define LB_D2_VLINE_INTERRUPT (1 << 2)
280 # define LB_D2_VBLANK_INTERRUPT (1 << 3)
281 # define DC_HPD2_INTERRUPT (1 << 17)
282 # define DC_HPD2_RX_INTERRUPT (1 << 18)
283 # define DISP_TIMER_INTERRUPT (1 << 24)
284 #define DISP_INTERRUPT_STATUS_CONTINUE2 0x60fc
285 # define LB_D3_VLINE_INTERRUPT (1 << 2)
286 # define LB_D3_VBLANK_INTERRUPT (1 << 3)
287 # define DC_HPD3_INTERRUPT (1 << 17)
288 # define DC_HPD3_RX_INTERRUPT (1 << 18)
289 #define DISP_INTERRUPT_STATUS_CONTINUE3 0x6100
290 # define LB_D4_VLINE_INTERRUPT (1 << 2)
291 # define LB_D4_VBLANK_INTERRUPT (1 << 3)
292 # define DC_HPD4_INTERRUPT (1 << 17)
293 # define DC_HPD4_RX_INTERRUPT (1 << 18)
294 #define DISP_INTERRUPT_STATUS_CONTINUE4 0x614c
295 # define LB_D5_VLINE_INTERRUPT (1 << 2)
296 # define LB_D5_VBLANK_INTERRUPT (1 << 3)
297 # define DC_HPD5_INTERRUPT (1 << 17)
298 # define DC_HPD5_RX_INTERRUPT (1 << 18)
299 #define DISP_INTERRUPT_STATUS_CONTINUE5 0x6150
300 # define LB_D6_VLINE_INTERRUPT (1 << 2)
301 # define LB_D6_VBLANK_INTERRUPT (1 << 3)
302 # define DC_HPD6_INTERRUPT (1 << 17)
303 # define DC_HPD6_RX_INTERRUPT (1 << 18)
305 /* 0x6858, 0x7458, 0x10058, 0x10c58, 0x11858, 0x12458 */
306 #define GRPH_INT_STATUS 0x6858
307 # define GRPH_PFLIP_INT_OCCURRED (1 << 0)
308 # define GRPH_PFLIP_INT_CLEAR (1 << 8)
309 /* 0x685c, 0x745c, 0x1005c, 0x10c5c, 0x1185c, 0x1245c */
310 #define GRPH_INT_CONTROL 0x685c
311 # define GRPH_PFLIP_INT_MASK (1 << 0)
312 # define GRPH_PFLIP_INT_TYPE (1 << 8)
314 #define DACA_AUTODETECT_INT_CONTROL 0x66c8
316 #define DC_HPD1_INT_STATUS 0x601c
317 #define DC_HPD2_INT_STATUS 0x6028
318 #define DC_HPD3_INT_STATUS 0x6034
319 #define DC_HPD4_INT_STATUS 0x6040
320 #define DC_HPD5_INT_STATUS 0x604c
321 #define DC_HPD6_INT_STATUS 0x6058
322 # define DC_HPDx_INT_STATUS (1 << 0)
323 # define DC_HPDx_SENSE (1 << 1)
324 # define DC_HPDx_RX_INT_STATUS (1 << 8)
326 #define DC_HPD1_INT_CONTROL 0x6020
327 #define DC_HPD2_INT_CONTROL 0x602c
328 #define DC_HPD3_INT_CONTROL 0x6038
329 #define DC_HPD4_INT_CONTROL 0x6044
330 #define DC_HPD5_INT_CONTROL 0x6050
331 #define DC_HPD6_INT_CONTROL 0x605c
332 # define DC_HPDx_INT_ACK (1 << 0)
333 # define DC_HPDx_INT_POLARITY (1 << 8)
334 # define DC_HPDx_INT_EN (1 << 16)
335 # define DC_HPDx_RX_INT_ACK (1 << 20)
336 # define DC_HPDx_RX_INT_EN (1 << 24)
338 #define DC_HPD1_CONTROL 0x6024
339 #define DC_HPD2_CONTROL 0x6030
340 #define DC_HPD3_CONTROL 0x603c
341 #define DC_HPD4_CONTROL 0x6048
342 #define DC_HPD5_CONTROL 0x6054
343 #define DC_HPD6_CONTROL 0x6060
344 # define DC_HPDx_CONNECTION_TIMER(x) ((x) << 0)
345 # define DC_HPDx_RX_INT_TIMER(x) ((x) << 16)
346 # define DC_HPDx_EN (1 << 28)
348 /* 0x6e98, 0x7a98, 0x10698, 0x11298, 0x11e98, 0x12a98 */
349 #define CRTC_STATUS_FRAME_COUNT 0x6e98
351 #define GRBM_CNTL 0x8000
352 #define GRBM_READ_TIMEOUT(x) ((x) << 0)
354 #define GRBM_STATUS2 0x8008
355 #define RLC_RQ_PENDING (1 << 0)
356 #define RLC_BUSY (1 << 8)
357 #define TC_BUSY (1 << 9)
359 #define GRBM_STATUS 0x8010
360 #define CMDFIFO_AVAIL_MASK 0x0000000F
361 #define RING2_RQ_PENDING (1 << 4)
362 #define SRBM_RQ_PENDING (1 << 5)
363 #define RING1_RQ_PENDING (1 << 6)
364 #define CF_RQ_PENDING (1 << 7)
365 #define PF_RQ_PENDING (1 << 8)
366 #define GDS_DMA_RQ_PENDING (1 << 9)
367 #define GRBM_EE_BUSY (1 << 10)
368 #define DB_CLEAN (1 << 12)
369 #define CB_CLEAN (1 << 13)
370 #define TA_BUSY (1 << 14)
371 #define GDS_BUSY (1 << 15)
372 #define VGT_BUSY (1 << 17)
373 #define IA_BUSY_NO_DMA (1 << 18)
374 #define IA_BUSY (1 << 19)
375 #define SX_BUSY (1 << 20)
376 #define SPI_BUSY (1 << 22)
377 #define BCI_BUSY (1 << 23)
378 #define SC_BUSY (1 << 24)
379 #define PA_BUSY (1 << 25)
380 #define DB_BUSY (1 << 26)
381 #define CP_COHERENCY_BUSY (1 << 28)
382 #define CP_BUSY (1 << 29)
383 #define CB_BUSY (1 << 30)
384 #define GUI_ACTIVE (1 << 31)
385 #define GRBM_STATUS_SE0 0x8014
386 #define GRBM_STATUS_SE1 0x8018
387 #define SE_DB_CLEAN (1 << 1)
388 #define SE_CB_CLEAN (1 << 2)
389 #define SE_BCI_BUSY (1 << 22)
390 #define SE_VGT_BUSY (1 << 23)
391 #define SE_PA_BUSY (1 << 24)
392 #define SE_TA_BUSY (1 << 25)
393 #define SE_SX_BUSY (1 << 26)
394 #define SE_SPI_BUSY (1 << 27)
395 #define SE_SC_BUSY (1 << 29)
396 #define SE_DB_BUSY (1 << 30)
397 #define SE_CB_BUSY (1 << 31)
399 #define GRBM_SOFT_RESET 0x8020
400 #define SOFT_RESET_CP (1 << 0)
401 #define SOFT_RESET_CB (1 << 1)
402 #define SOFT_RESET_RLC (1 << 2)
403 #define SOFT_RESET_DB (1 << 3)
404 #define SOFT_RESET_GDS (1 << 4)
405 #define SOFT_RESET_PA (1 << 5)
406 #define SOFT_RESET_SC (1 << 6)
407 #define SOFT_RESET_BCI (1 << 7)
408 #define SOFT_RESET_SPI (1 << 8)
409 #define SOFT_RESET_SX (1 << 10)
410 #define SOFT_RESET_TC (1 << 11)
411 #define SOFT_RESET_TA (1 << 12)
412 #define SOFT_RESET_VGT (1 << 14)
413 #define SOFT_RESET_IA (1 << 15)
415 #define GRBM_GFX_INDEX 0x802C
416 #define INSTANCE_INDEX(x) ((x) << 0)
417 #define SH_INDEX(x) ((x) << 8)
418 #define SE_INDEX(x) ((x) << 16)
419 #define SH_BROADCAST_WRITES (1 << 29)
420 #define INSTANCE_BROADCAST_WRITES (1 << 30)
421 #define SE_BROADCAST_WRITES (1 << 31)
423 #define GRBM_INT_CNTL 0x8060
424 # define RDERR_INT_ENABLE (1 << 0)
425 # define GUI_IDLE_INT_ENABLE (1 << 19)
427 #define SCRATCH_REG0 0x8500
428 #define SCRATCH_REG1 0x8504
429 #define SCRATCH_REG2 0x8508
430 #define SCRATCH_REG3 0x850C
431 #define SCRATCH_REG4 0x8510
432 #define SCRATCH_REG5 0x8514
433 #define SCRATCH_REG6 0x8518
434 #define SCRATCH_REG7 0x851C
436 #define SCRATCH_UMSK 0x8540
437 #define SCRATCH_ADDR 0x8544
439 #define CP_SEM_WAIT_TIMER 0x85BC
441 #define CP_SEM_INCOMPLETE_TIMER_CNTL 0x85C8
443 #define CP_ME_CNTL 0x86D8
444 #define CP_CE_HALT (1 << 24)
445 #define CP_PFP_HALT (1 << 26)
446 #define CP_ME_HALT (1 << 28)
448 #define CP_COHER_CNTL2 0x85E8
450 #define CP_RB2_RPTR 0x86f8
451 #define CP_RB1_RPTR 0x86fc
452 #define CP_RB0_RPTR 0x8700
453 #define CP_RB_WPTR_DELAY 0x8704
455 #define CP_QUEUE_THRESHOLDS 0x8760
456 #define ROQ_IB1_START(x) ((x) << 0)
457 #define ROQ_IB2_START(x) ((x) << 8)
458 #define CP_MEQ_THRESHOLDS 0x8764
459 #define MEQ1_START(x) ((x) << 0)
460 #define MEQ2_START(x) ((x) << 8)
462 #define CP_PERFMON_CNTL 0x87FC
464 #define VGT_VTX_VECT_EJECT_REG 0x88B0
466 #define VGT_CACHE_INVALIDATION 0x88C4
467 #define CACHE_INVALIDATION(x) ((x) << 0)
471 #define AUTO_INVLD_EN(x) ((x) << 6)
475 #define ES_AND_GS_AUTO 3
476 #define VGT_ESGS_RING_SIZE 0x88C8
477 #define VGT_GSVS_RING_SIZE 0x88CC
479 #define VGT_GS_VERTEX_REUSE 0x88D4
481 #define VGT_PRIMITIVE_TYPE 0x8958
482 #define VGT_INDEX_TYPE 0x895C
484 #define VGT_NUM_INDICES 0x8970
485 #define VGT_NUM_INSTANCES 0x8974
487 #define VGT_TF_RING_SIZE 0x8988
489 #define VGT_HS_OFFCHIP_PARAM 0x89B0
491 #define VGT_TF_MEMORY_BASE 0x89B8
493 #define CC_GC_SHADER_ARRAY_CONFIG 0x89bc
494 #define INACTIVE_CUS_MASK 0xFFFF0000
495 #define INACTIVE_CUS_SHIFT 16
496 #define GC_USER_SHADER_ARRAY_CONFIG 0x89c0
498 #define PA_CL_ENHANCE 0x8A14
499 #define CLIP_VTX_REORDER_ENA (1 << 0)
500 #define NUM_CLIP_SEQ(x) ((x) << 1)
502 #define PA_SU_LINE_STIPPLE_VALUE 0x8A60
504 #define PA_SC_LINE_STIPPLE_STATE 0x8B10
506 #define PA_SC_FORCE_EOV_MAX_CNTS 0x8B24
507 #define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0)
508 #define FORCE_EOV_MAX_REZ_CNT(x) ((x) << 16)
510 #define PA_SC_FIFO_SIZE 0x8BCC
511 #define SC_FRONTEND_PRIM_FIFO_SIZE(x) ((x) << 0)
512 #define SC_BACKEND_PRIM_FIFO_SIZE(x) ((x) << 6)
513 #define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 15)
514 #define SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 23)
516 #define PA_SC_ENHANCE 0x8BF0
518 #define SQ_CONFIG 0x8C00
520 #define SQC_CACHES 0x8C08
522 #define SX_DEBUG_1 0x9060
524 #define SPI_STATIC_THREAD_MGMT_1 0x90E0
525 #define SPI_STATIC_THREAD_MGMT_2 0x90E4
526 #define SPI_STATIC_THREAD_MGMT_3 0x90E8
527 #define SPI_PS_MAX_WAVE_ID 0x90EC
529 #define SPI_CONFIG_CNTL 0x9100
531 #define SPI_CONFIG_CNTL_1 0x913C
532 #define VTX_DONE_DELAY(x) ((x) << 0)
533 #define INTERP_ONE_PRIM_PER_ROW (1 << 4)
535 #define CGTS_TCC_DISABLE 0x9148
536 #define CGTS_USER_TCC_DISABLE 0x914C
537 #define TCC_DISABLE_MASK 0xFFFF0000
538 #define TCC_DISABLE_SHIFT 16
540 #define TA_CNTL_AUX 0x9508
542 #define CC_RB_BACKEND_DISABLE 0x98F4
543 #define BACKEND_DISABLE(x) ((x) << 16)
544 #define GB_ADDR_CONFIG 0x98F8
545 #define NUM_PIPES(x) ((x) << 0)
546 #define NUM_PIPES_MASK 0x00000007
547 #define NUM_PIPES_SHIFT 0
548 #define PIPE_INTERLEAVE_SIZE(x) ((x) << 4)
549 #define PIPE_INTERLEAVE_SIZE_MASK 0x00000070
550 #define PIPE_INTERLEAVE_SIZE_SHIFT 4
551 #define NUM_SHADER_ENGINES(x) ((x) << 12)
552 #define NUM_SHADER_ENGINES_MASK 0x00003000
553 #define NUM_SHADER_ENGINES_SHIFT 12
554 #define SHADER_ENGINE_TILE_SIZE(x) ((x) << 16)
555 #define SHADER_ENGINE_TILE_SIZE_MASK 0x00070000
556 #define SHADER_ENGINE_TILE_SIZE_SHIFT 16
557 #define NUM_GPUS(x) ((x) << 20)
558 #define NUM_GPUS_MASK 0x00700000
559 #define NUM_GPUS_SHIFT 20
560 #define MULTI_GPU_TILE_SIZE(x) ((x) << 24)
561 #define MULTI_GPU_TILE_SIZE_MASK 0x03000000
562 #define MULTI_GPU_TILE_SIZE_SHIFT 24
563 #define ROW_SIZE(x) ((x) << 28)
564 #define ROW_SIZE_MASK 0x30000000
565 #define ROW_SIZE_SHIFT 28
567 #define GB_TILE_MODE0 0x9910
568 # define MICRO_TILE_MODE(x) ((x) << 0)
569 # define ADDR_SURF_DISPLAY_MICRO_TILING 0
570 # define ADDR_SURF_THIN_MICRO_TILING 1
571 # define ADDR_SURF_DEPTH_MICRO_TILING 2
572 # define ARRAY_MODE(x) ((x) << 2)
573 # define ARRAY_LINEAR_GENERAL 0
574 # define ARRAY_LINEAR_ALIGNED 1
575 # define ARRAY_1D_TILED_THIN1 2
576 # define ARRAY_2D_TILED_THIN1 4
577 # define PIPE_CONFIG(x) ((x) << 6)
578 # define ADDR_SURF_P2 0
579 # define ADDR_SURF_P4_8x16 4
580 # define ADDR_SURF_P4_16x16 5
581 # define ADDR_SURF_P4_16x32 6
582 # define ADDR_SURF_P4_32x32 7
583 # define ADDR_SURF_P8_16x16_8x16 8
584 # define ADDR_SURF_P8_16x32_8x16 9
585 # define ADDR_SURF_P8_32x32_8x16 10
586 # define ADDR_SURF_P8_16x32_16x16 11
587 # define ADDR_SURF_P8_32x32_16x16 12
588 # define ADDR_SURF_P8_32x32_16x32 13
589 # define ADDR_SURF_P8_32x64_32x32 14
590 # define TILE_SPLIT(x) ((x) << 11)
591 # define ADDR_SURF_TILE_SPLIT_64B 0
592 # define ADDR_SURF_TILE_SPLIT_128B 1
593 # define ADDR_SURF_TILE_SPLIT_256B 2
594 # define ADDR_SURF_TILE_SPLIT_512B 3
595 # define ADDR_SURF_TILE_SPLIT_1KB 4
596 # define ADDR_SURF_TILE_SPLIT_2KB 5
597 # define ADDR_SURF_TILE_SPLIT_4KB 6
598 # define BANK_WIDTH(x) ((x) << 14)
599 # define ADDR_SURF_BANK_WIDTH_1 0
600 # define ADDR_SURF_BANK_WIDTH_2 1
601 # define ADDR_SURF_BANK_WIDTH_4 2
602 # define ADDR_SURF_BANK_WIDTH_8 3
603 # define BANK_HEIGHT(x) ((x) << 16)
604 # define ADDR_SURF_BANK_HEIGHT_1 0
605 # define ADDR_SURF_BANK_HEIGHT_2 1
606 # define ADDR_SURF_BANK_HEIGHT_4 2
607 # define ADDR_SURF_BANK_HEIGHT_8 3
608 # define MACRO_TILE_ASPECT(x) ((x) << 18)
609 # define ADDR_SURF_MACRO_ASPECT_1 0
610 # define ADDR_SURF_MACRO_ASPECT_2 1
611 # define ADDR_SURF_MACRO_ASPECT_4 2
612 # define ADDR_SURF_MACRO_ASPECT_8 3
613 # define NUM_BANKS(x) ((x) << 20)
614 # define ADDR_SURF_2_BANK 0
615 # define ADDR_SURF_4_BANK 1
616 # define ADDR_SURF_8_BANK 2
617 # define ADDR_SURF_16_BANK 3
619 #define CB_PERFCOUNTER0_SELECT0 0x9a20
620 #define CB_PERFCOUNTER0_SELECT1 0x9a24
621 #define CB_PERFCOUNTER1_SELECT0 0x9a28
622 #define CB_PERFCOUNTER1_SELECT1 0x9a2c
623 #define CB_PERFCOUNTER2_SELECT0 0x9a30
624 #define CB_PERFCOUNTER2_SELECT1 0x9a34
625 #define CB_PERFCOUNTER3_SELECT0 0x9a38
626 #define CB_PERFCOUNTER3_SELECT1 0x9a3c
628 #define GC_USER_RB_BACKEND_DISABLE 0x9B7C
629 #define BACKEND_DISABLE_MASK 0x00FF0000
630 #define BACKEND_DISABLE_SHIFT 16
632 #define TCP_CHAN_STEER_LO 0xac0c
633 #define TCP_CHAN_STEER_HI 0xac10
635 #define CP_RB0_BASE 0xC100
636 #define CP_RB0_CNTL 0xC104
637 #define RB_BUFSZ(x) ((x) << 0)
638 #define RB_BLKSZ(x) ((x) << 8)
639 #define BUF_SWAP_32BIT (2 << 16)
640 #define RB_NO_UPDATE (1 << 27)
641 #define RB_RPTR_WR_ENA (1 << 31)
643 #define CP_RB0_RPTR_ADDR 0xC10C
644 #define CP_RB0_RPTR_ADDR_HI 0xC110
645 #define CP_RB0_WPTR 0xC114
647 #define CP_PFP_UCODE_ADDR 0xC150
648 #define CP_PFP_UCODE_DATA 0xC154
649 #define CP_ME_RAM_RADDR 0xC158
650 #define CP_ME_RAM_WADDR 0xC15C
651 #define CP_ME_RAM_DATA 0xC160
653 #define CP_CE_UCODE_ADDR 0xC168
654 #define CP_CE_UCODE_DATA 0xC16C
656 #define CP_RB1_BASE 0xC180
657 #define CP_RB1_CNTL 0xC184
658 #define CP_RB1_RPTR_ADDR 0xC188
659 #define CP_RB1_RPTR_ADDR_HI 0xC18C
660 #define CP_RB1_WPTR 0xC190
661 #define CP_RB2_BASE 0xC194
662 #define CP_RB2_CNTL 0xC198
663 #define CP_RB2_RPTR_ADDR 0xC19C
664 #define CP_RB2_RPTR_ADDR_HI 0xC1A0
665 #define CP_RB2_WPTR 0xC1A4
666 #define CP_INT_CNTL_RING0 0xC1A8
667 #define CP_INT_CNTL_RING1 0xC1AC
668 #define CP_INT_CNTL_RING2 0xC1B0
669 # define CNTX_BUSY_INT_ENABLE (1 << 19)
670 # define CNTX_EMPTY_INT_ENABLE (1 << 20)
671 # define WAIT_MEM_SEM_INT_ENABLE (1 << 21)
672 # define TIME_STAMP_INT_ENABLE (1 << 26)
673 # define CP_RINGID2_INT_ENABLE (1 << 29)
674 # define CP_RINGID1_INT_ENABLE (1 << 30)
675 # define CP_RINGID0_INT_ENABLE (1 << 31)
676 #define CP_INT_STATUS_RING0 0xC1B4
677 #define CP_INT_STATUS_RING1 0xC1B8
678 #define CP_INT_STATUS_RING2 0xC1BC
679 # define WAIT_MEM_SEM_INT_STAT (1 << 21)
680 # define TIME_STAMP_INT_STAT (1 << 26)
681 # define CP_RINGID2_INT_STAT (1 << 29)
682 # define CP_RINGID1_INT_STAT (1 << 30)
683 # define CP_RINGID0_INT_STAT (1 << 31)
685 #define CP_DEBUG 0xC1FC
687 #define RLC_CNTL 0xC300
688 # define RLC_ENABLE (1 << 0)
689 #define RLC_RL_BASE 0xC304
690 #define RLC_RL_SIZE 0xC308
691 #define RLC_LB_CNTL 0xC30C
692 #define RLC_SAVE_AND_RESTORE_BASE 0xC310
693 #define RLC_LB_CNTR_MAX 0xC314
694 #define RLC_LB_CNTR_INIT 0xC318
696 #define RLC_CLEAR_STATE_RESTORE_BASE 0xC320
698 #define RLC_UCODE_ADDR 0xC32C
699 #define RLC_UCODE_DATA 0xC330
701 #define RLC_GPU_CLOCK_COUNT_LSB 0xC338
702 #define RLC_GPU_CLOCK_COUNT_MSB 0xC33C
703 #define RLC_CAPTURE_GPU_CLOCK_COUNT 0xC340
704 #define RLC_MC_CNTL 0xC344
705 #define RLC_UCODE_CNTL 0xC348
707 #define PA_SC_RASTER_CONFIG 0x28350
708 # define RASTER_CONFIG_RB_MAP_0 0
709 # define RASTER_CONFIG_RB_MAP_1 1
710 # define RASTER_CONFIG_RB_MAP_2 2
711 # define RASTER_CONFIG_RB_MAP_3 3
713 #define VGT_EVENT_INITIATOR 0x28a90
714 # define SAMPLE_STREAMOUTSTATS1 (1 << 0)
715 # define SAMPLE_STREAMOUTSTATS2 (2 << 0)
716 # define SAMPLE_STREAMOUTSTATS3 (3 << 0)
717 # define CACHE_FLUSH_TS (4 << 0)
718 # define CACHE_FLUSH (6 << 0)
719 # define CS_PARTIAL_FLUSH (7 << 0)
720 # define VGT_STREAMOUT_RESET (10 << 0)
721 # define END_OF_PIPE_INCR_DE (11 << 0)
722 # define END_OF_PIPE_IB_END (12 << 0)
723 # define RST_PIX_CNT (13 << 0)
724 # define VS_PARTIAL_FLUSH (15 << 0)
725 # define PS_PARTIAL_FLUSH (16 << 0)
726 # define CACHE_FLUSH_AND_INV_TS_EVENT (20 << 0)
727 # define ZPASS_DONE (21 << 0)
728 # define CACHE_FLUSH_AND_INV_EVENT (22 << 0)
729 # define PERFCOUNTER_START (23 << 0)
730 # define PERFCOUNTER_STOP (24 << 0)
731 # define PIPELINESTAT_START (25 << 0)
732 # define PIPELINESTAT_STOP (26 << 0)
733 # define PERFCOUNTER_SAMPLE (27 << 0)
734 # define SAMPLE_PIPELINESTAT (30 << 0)
735 # define SAMPLE_STREAMOUTSTATS (32 << 0)
736 # define RESET_VTX_CNT (33 << 0)
737 # define VGT_FLUSH (36 << 0)
738 # define BOTTOM_OF_PIPE_TS (40 << 0)
739 # define DB_CACHE_FLUSH_AND_INV (42 << 0)
740 # define FLUSH_AND_INV_DB_DATA_TS (43 << 0)
741 # define FLUSH_AND_INV_DB_META (44 << 0)
742 # define FLUSH_AND_INV_CB_DATA_TS (45 << 0)
743 # define FLUSH_AND_INV_CB_META (46 << 0)
744 # define CS_DONE (47 << 0)
745 # define PS_DONE (48 << 0)
746 # define FLUSH_AND_INV_CB_PIXEL_DATA (49 << 0)
747 # define THREAD_TRACE_START (51 << 0)
748 # define THREAD_TRACE_STOP (52 << 0)
749 # define THREAD_TRACE_FLUSH (54 << 0)
750 # define THREAD_TRACE_FINISH (55 << 0)
755 #define PACKET_TYPE0 0
756 #define PACKET_TYPE1 1
757 #define PACKET_TYPE2 2
758 #define PACKET_TYPE3 3
760 #define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3)
761 #define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF)
762 #define CP_PACKET0_GET_REG(h) (((h) & 0xFFFF) << 2)
763 #define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF)
764 #define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \
765 (((reg) >> 2) & 0xFFFF) | \
766 ((n) & 0x3FFF) << 16)
767 #define CP_PACKET2 0x80000000
768 #define PACKET2_PAD_SHIFT 0
769 #define PACKET2_PAD_MASK (0x3fffffff << 0)
771 #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
773 #define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \
774 (((op) & 0xFF) << 8) | \
775 ((n) & 0x3FFF) << 16)
777 #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)
780 #define PACKET3_NOP 0x10
781 #define PACKET3_SET_BASE 0x11
782 #define PACKET3_BASE_INDEX(x) ((x) << 0)
783 #define GDS_PARTITION_BASE 2
784 #define CE_PARTITION_BASE 3
785 #define PACKET3_CLEAR_STATE 0x12
786 #define PACKET3_INDEX_BUFFER_SIZE 0x13
787 #define PACKET3_DISPATCH_DIRECT 0x15
788 #define PACKET3_DISPATCH_INDIRECT 0x16
789 #define PACKET3_ALLOC_GDS 0x1B
790 #define PACKET3_WRITE_GDS_RAM 0x1C
791 #define PACKET3_ATOMIC_GDS 0x1D
792 #define PACKET3_ATOMIC 0x1E
793 #define PACKET3_OCCLUSION_QUERY 0x1F
794 #define PACKET3_SET_PREDICATION 0x20
795 #define PACKET3_REG_RMW 0x21
796 #define PACKET3_COND_EXEC 0x22
797 #define PACKET3_PRED_EXEC 0x23
798 #define PACKET3_DRAW_INDIRECT 0x24
799 #define PACKET3_DRAW_INDEX_INDIRECT 0x25
800 #define PACKET3_INDEX_BASE 0x26
801 #define PACKET3_DRAW_INDEX_2 0x27
802 #define PACKET3_CONTEXT_CONTROL 0x28
803 #define PACKET3_INDEX_TYPE 0x2A
804 #define PACKET3_DRAW_INDIRECT_MULTI 0x2C
805 #define PACKET3_DRAW_INDEX_AUTO 0x2D
806 #define PACKET3_DRAW_INDEX_IMMD 0x2E
807 #define PACKET3_NUM_INSTANCES 0x2F
808 #define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30
809 #define PACKET3_INDIRECT_BUFFER_CONST 0x31
810 #define PACKET3_INDIRECT_BUFFER 0x32
811 #define PACKET3_STRMOUT_BUFFER_UPDATE 0x34
812 #define PACKET3_DRAW_INDEX_OFFSET_2 0x35
813 #define PACKET3_DRAW_INDEX_MULTI_ELEMENT 0x36
814 #define PACKET3_WRITE_DATA 0x37
815 #define PACKET3_DRAW_INDEX_INDIRECT_MULTI 0x38
816 #define PACKET3_MEM_SEMAPHORE 0x39
817 #define PACKET3_MPEG_INDEX 0x3A
818 #define PACKET3_COPY_DW 0x3B
819 #define PACKET3_WAIT_REG_MEM 0x3C
820 #define PACKET3_MEM_WRITE 0x3D
821 #define PACKET3_COPY_DATA 0x40
822 #define PACKET3_PFP_SYNC_ME 0x42
823 #define PACKET3_SURFACE_SYNC 0x43
824 # define PACKET3_DEST_BASE_0_ENA (1 << 0)
825 # define PACKET3_DEST_BASE_1_ENA (1 << 1)
826 # define PACKET3_CB0_DEST_BASE_ENA (1 << 6)
827 # define PACKET3_CB1_DEST_BASE_ENA (1 << 7)
828 # define PACKET3_CB2_DEST_BASE_ENA (1 << 8)
829 # define PACKET3_CB3_DEST_BASE_ENA (1 << 9)
830 # define PACKET3_CB4_DEST_BASE_ENA (1 << 10)
831 # define PACKET3_CB5_DEST_BASE_ENA (1 << 11)
832 # define PACKET3_CB6_DEST_BASE_ENA (1 << 12)
833 # define PACKET3_CB7_DEST_BASE_ENA (1 << 13)
834 # define PACKET3_DB_DEST_BASE_ENA (1 << 14)
835 # define PACKET3_DEST_BASE_2_ENA (1 << 19)
836 # define PACKET3_DEST_BASE_3_ENA (1 << 21)
837 # define PACKET3_TCL1_ACTION_ENA (1 << 22)
838 # define PACKET3_TC_ACTION_ENA (1 << 23)
839 # define PACKET3_CB_ACTION_ENA (1 << 25)
840 # define PACKET3_DB_ACTION_ENA (1 << 26)
841 # define PACKET3_SH_KCACHE_ACTION_ENA (1 << 27)
842 # define PACKET3_SH_ICACHE_ACTION_ENA (1 << 29)
843 #define PACKET3_ME_INITIALIZE 0x44
844 #define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16)
845 #define PACKET3_COND_WRITE 0x45
846 #define PACKET3_EVENT_WRITE 0x46
847 #define EVENT_TYPE(x) ((x) << 0)
848 #define EVENT_INDEX(x) ((x) << 8)
849 /* 0 - any non-TS event
851 * 2 - SAMPLE_PIPELINESTAT
852 * 3 - SAMPLE_STREAMOUTSTAT*
853 * 4 - *S_PARTIAL_FLUSH
856 * 7 - CACHE_FLUSH, CACHE_FLUSH_AND_INV_EVENT
858 #define INV_L2 (1 << 20)
859 /* INV TC L2 cache when EVENT_INDEX = 7 */
860 #define PACKET3_EVENT_WRITE_EOP 0x47
861 #define DATA_SEL(x) ((x) << 29)
863 * 1 - send low 32bit data
864 * 2 - send 64bit data
865 * 3 - send 64bit counter value
867 #define INT_SEL(x) ((x) << 24)
869 * 1 - interrupt only (DATA_SEL = 0)
870 * 2 - interrupt when data write is confirmed
872 #define PACKET3_EVENT_WRITE_EOS 0x48
873 #define PACKET3_PREAMBLE_CNTL 0x4A
874 # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28)
875 # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28)
876 #define PACKET3_ONE_REG_WRITE 0x57
877 #define PACKET3_LOAD_CONFIG_REG 0x5F
878 #define PACKET3_LOAD_CONTEXT_REG 0x60
879 #define PACKET3_LOAD_SH_REG 0x61
880 #define PACKET3_SET_CONFIG_REG 0x68
881 #define PACKET3_SET_CONFIG_REG_START 0x00008000
882 #define PACKET3_SET_CONFIG_REG_END 0x0000b000
883 #define PACKET3_SET_CONTEXT_REG 0x69
884 #define PACKET3_SET_CONTEXT_REG_START 0x00028000
885 #define PACKET3_SET_CONTEXT_REG_END 0x00029000
886 #define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73
887 #define PACKET3_SET_RESOURCE_INDIRECT 0x74
888 #define PACKET3_SET_SH_REG 0x76
889 #define PACKET3_SET_SH_REG_START 0x0000b000
890 #define PACKET3_SET_SH_REG_END 0x0000c000
891 #define PACKET3_SET_SH_REG_OFFSET 0x77
892 #define PACKET3_ME_WRITE 0x7A
893 #define PACKET3_SCRATCH_RAM_WRITE 0x7D
894 #define PACKET3_SCRATCH_RAM_READ 0x7E
895 #define PACKET3_CE_WRITE 0x7F
896 #define PACKET3_LOAD_CONST_RAM 0x80
897 #define PACKET3_WRITE_CONST_RAM 0x81
898 #define PACKET3_WRITE_CONST_RAM_OFFSET 0x82
899 #define PACKET3_DUMP_CONST_RAM 0x83
900 #define PACKET3_INCREMENT_CE_COUNTER 0x84
901 #define PACKET3_INCREMENT_DE_COUNTER 0x85
902 #define PACKET3_WAIT_ON_CE_COUNTER 0x86
903 #define PACKET3_WAIT_ON_DE_COUNTER 0x87
904 #define PACKET3_WAIT_ON_DE_COUNTER_DIFF 0x88
905 #define PACKET3_SET_CE_DE_COUNTERS 0x89
906 #define PACKET3_WAIT_ON_AVAIL_BUFFER 0x8A
907 #define PACKET3_SWITCH_BUFFER 0x8B
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