2 * Copyright 2012 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
28 #include "cypress_dpm.h"
31 #define SUMO_MAX_DEEPSLEEP_DIVIDER_ID 5
32 #define SUMO_MINIMUM_ENGINE_CLOCK 800
33 #define BOOST_DPM_LEVEL 7
35 static const u32 sumo_utc
[SUMO_PM_NUMBER_OF_TC
] =
54 static const u32 sumo_dtc
[SUMO_PM_NUMBER_OF_TC
] =
73 struct sumo_ps
*sumo_get_ps(struct radeon_ps
*rps
)
75 struct sumo_ps
*ps
= rps
->ps_priv
;
80 struct sumo_power_info
*sumo_get_pi(struct radeon_device
*rdev
)
82 struct sumo_power_info
*pi
= rdev
->pm
.dpm
.priv
;
87 u32
sumo_get_xclk(struct radeon_device
*rdev
)
89 return rdev
->clock
.spll
.reference_freq
;
92 static void sumo_gfx_clockgating_enable(struct radeon_device
*rdev
, bool enable
)
95 WREG32_P(SCLK_PWRMGT_CNTL
, DYN_GFX_CLK_OFF_EN
, ~DYN_GFX_CLK_OFF_EN
);
97 WREG32_P(SCLK_PWRMGT_CNTL
, 0, ~DYN_GFX_CLK_OFF_EN
);
98 WREG32_P(SCLK_PWRMGT_CNTL
, GFX_CLK_FORCE_ON
, ~GFX_CLK_FORCE_ON
);
99 WREG32_P(SCLK_PWRMGT_CNTL
, 0, ~GFX_CLK_FORCE_ON
);
100 RREG32(GB_ADDR_CONFIG
);
104 #define CGCG_CGTT_LOCAL0_MASK 0xE5BFFFFF
105 #define CGCG_CGTT_LOCAL1_MASK 0xEFFF07FF
107 static void sumo_mg_clockgating_enable(struct radeon_device
*rdev
, bool enable
)
112 local0
= RREG32(CG_CGTT_LOCAL_0
);
113 local1
= RREG32(CG_CGTT_LOCAL_1
);
116 WREG32(CG_CGTT_LOCAL_0
, (0 & CGCG_CGTT_LOCAL0_MASK
) | (local0
& ~CGCG_CGTT_LOCAL0_MASK
) );
117 WREG32(CG_CGTT_LOCAL_1
, (0 & CGCG_CGTT_LOCAL1_MASK
) | (local1
& ~CGCG_CGTT_LOCAL1_MASK
) );
119 WREG32(CG_CGTT_LOCAL_0
, (0xFFFFFFFF & CGCG_CGTT_LOCAL0_MASK
) | (local0
& ~CGCG_CGTT_LOCAL0_MASK
) );
120 WREG32(CG_CGTT_LOCAL_1
, (0xFFFFCFFF & CGCG_CGTT_LOCAL1_MASK
) | (local1
& ~CGCG_CGTT_LOCAL1_MASK
) );
124 static void sumo_program_git(struct radeon_device
*rdev
)
127 u32 xclk
= sumo_get_xclk(rdev
);
129 r600_calculate_u_and_p(SUMO_GICST_DFLT
,
132 WREG32_P(CG_GIT
, CG_GICST(p
), ~CG_GICST_MASK
);
135 static void sumo_program_grsd(struct radeon_device
*rdev
)
138 u32 xclk
= sumo_get_xclk(rdev
);
139 u32 grs
= 256 * 25 / 100;
141 r600_calculate_u_and_p(1, xclk
, 14, &p
, &u
);
143 WREG32(CG_GCOOR
, PHC(grs
) | SDC(p
) | SU(u
));
146 void sumo_gfx_clockgating_initialize(struct radeon_device
*rdev
)
148 sumo_program_git(rdev
);
149 sumo_program_grsd(rdev
);
152 static void sumo_gfx_powergating_initialize(struct radeon_device
*rdev
)
154 u32 rcu_pwr_gating_cntl
;
158 u32 xclk
= sumo_get_xclk(rdev
);
160 if (rdev
->family
== CHIP_PALM
) {
165 p_p
= 50 + 1000/200 + 6 * 32;
174 WREG32(CG_SCRATCH2
, 0x01B60A17);
176 r600_calculate_u_and_p(SUMO_GFXPOWERGATINGT_DFLT
,
179 WREG32_P(CG_PWR_GATING_CNTL
, PGP(p
) | PGU(u
),
180 ~(PGP_MASK
| PGU_MASK
));
182 r600_calculate_u_and_p(SUMO_VOLTAGEDROPT_DFLT
,
185 WREG32_P(CG_CG_VOLTAGE_CNTL
, PGP(p
) | PGU(u
),
186 ~(PGP_MASK
| PGU_MASK
));
188 if (rdev
->family
== CHIP_PALM
) {
189 WREG32_RCU(RCU_PWR_GATING_SEQ0
, 0x10103210);
190 WREG32_RCU(RCU_PWR_GATING_SEQ1
, 0x10101010);
192 WREG32_RCU(RCU_PWR_GATING_SEQ0
, 0x76543210);
193 WREG32_RCU(RCU_PWR_GATING_SEQ1
, 0xFEDCBA98);
196 rcu_pwr_gating_cntl
= RREG32_RCU(RCU_PWR_GATING_CNTL
);
197 rcu_pwr_gating_cntl
&=
198 ~(RSVD_MASK
| PCV_MASK
| PGS_MASK
);
199 rcu_pwr_gating_cntl
|= PCV(p_c
) | PGS(1) | PWR_GATING_EN
;
200 if (rdev
->family
== CHIP_PALM
) {
201 rcu_pwr_gating_cntl
&= ~PCP_MASK
;
202 rcu_pwr_gating_cntl
|= PCP(0x77);
204 WREG32_RCU(RCU_PWR_GATING_CNTL
, rcu_pwr_gating_cntl
);
206 rcu_pwr_gating_cntl
= RREG32_RCU(RCU_PWR_GATING_CNTL_2
);
207 rcu_pwr_gating_cntl
&= ~(MPPU_MASK
| MPPD_MASK
);
208 rcu_pwr_gating_cntl
|= MPPU(p_p
) | MPPD(50);
209 WREG32_RCU(RCU_PWR_GATING_CNTL_2
, rcu_pwr_gating_cntl
);
211 rcu_pwr_gating_cntl
= RREG32_RCU(RCU_PWR_GATING_CNTL_3
);
212 rcu_pwr_gating_cntl
&= ~(DPPU_MASK
| DPPD_MASK
);
213 rcu_pwr_gating_cntl
|= DPPU(d_p
) | DPPD(50);
214 WREG32_RCU(RCU_PWR_GATING_CNTL_3
, rcu_pwr_gating_cntl
);
216 rcu_pwr_gating_cntl
= RREG32_RCU(RCU_PWR_GATING_CNTL_4
);
217 rcu_pwr_gating_cntl
&= ~(RT_MASK
| IT_MASK
);
218 rcu_pwr_gating_cntl
|= RT(r_t
) | IT(i_t
);
219 WREG32_RCU(RCU_PWR_GATING_CNTL_4
, rcu_pwr_gating_cntl
);
221 if (rdev
->family
== CHIP_PALM
)
222 WREG32_RCU(RCU_PWR_GATING_CNTL_5
, 0xA02);
224 sumo_smu_pg_init(rdev
);
226 rcu_pwr_gating_cntl
= RREG32_RCU(RCU_PWR_GATING_CNTL
);
227 rcu_pwr_gating_cntl
&=
228 ~(RSVD_MASK
| PCV_MASK
| PGS_MASK
);
229 rcu_pwr_gating_cntl
|= PCV(p_c
) | PGS(4) | PWR_GATING_EN
;
230 if (rdev
->family
== CHIP_PALM
) {
231 rcu_pwr_gating_cntl
&= ~PCP_MASK
;
232 rcu_pwr_gating_cntl
|= PCP(0x77);
234 WREG32_RCU(RCU_PWR_GATING_CNTL
, rcu_pwr_gating_cntl
);
236 if (rdev
->family
== CHIP_PALM
) {
237 rcu_pwr_gating_cntl
= RREG32_RCU(RCU_PWR_GATING_CNTL_2
);
238 rcu_pwr_gating_cntl
&= ~(MPPU_MASK
| MPPD_MASK
);
239 rcu_pwr_gating_cntl
|= MPPU(113) | MPPD(50);
240 WREG32_RCU(RCU_PWR_GATING_CNTL_2
, rcu_pwr_gating_cntl
);
242 rcu_pwr_gating_cntl
= RREG32_RCU(RCU_PWR_GATING_CNTL_3
);
243 rcu_pwr_gating_cntl
&= ~(DPPU_MASK
| DPPD_MASK
);
244 rcu_pwr_gating_cntl
|= DPPU(16) | DPPD(50);
245 WREG32_RCU(RCU_PWR_GATING_CNTL_3
, rcu_pwr_gating_cntl
);
248 sumo_smu_pg_init(rdev
);
250 rcu_pwr_gating_cntl
= RREG32_RCU(RCU_PWR_GATING_CNTL
);
251 rcu_pwr_gating_cntl
&=
252 ~(RSVD_MASK
| PCV_MASK
| PGS_MASK
);
253 rcu_pwr_gating_cntl
|= PGS(5) | PWR_GATING_EN
;
255 if (rdev
->family
== CHIP_PALM
) {
256 rcu_pwr_gating_cntl
|= PCV(4);
257 rcu_pwr_gating_cntl
&= ~PCP_MASK
;
258 rcu_pwr_gating_cntl
|= PCP(0x77);
260 rcu_pwr_gating_cntl
|= PCV(11);
261 WREG32_RCU(RCU_PWR_GATING_CNTL
, rcu_pwr_gating_cntl
);
263 if (rdev
->family
== CHIP_PALM
) {
264 rcu_pwr_gating_cntl
= RREG32_RCU(RCU_PWR_GATING_CNTL_2
);
265 rcu_pwr_gating_cntl
&= ~(MPPU_MASK
| MPPD_MASK
);
266 rcu_pwr_gating_cntl
|= MPPU(113) | MPPD(50);
267 WREG32_RCU(RCU_PWR_GATING_CNTL_2
, rcu_pwr_gating_cntl
);
269 rcu_pwr_gating_cntl
= RREG32_RCU(RCU_PWR_GATING_CNTL_3
);
270 rcu_pwr_gating_cntl
&= ~(DPPU_MASK
| DPPD_MASK
);
271 rcu_pwr_gating_cntl
|= DPPU(22) | DPPD(50);
272 WREG32_RCU(RCU_PWR_GATING_CNTL_3
, rcu_pwr_gating_cntl
);
275 sumo_smu_pg_init(rdev
);
278 static void sumo_gfx_powergating_enable(struct radeon_device
*rdev
, bool enable
)
281 WREG32_P(CG_PWR_GATING_CNTL
, DYN_PWR_DOWN_EN
, ~DYN_PWR_DOWN_EN
);
283 WREG32_P(CG_PWR_GATING_CNTL
, 0, ~DYN_PWR_DOWN_EN
);
284 RREG32(GB_ADDR_CONFIG
);
288 static int sumo_enable_clock_power_gating(struct radeon_device
*rdev
)
290 struct sumo_power_info
*pi
= sumo_get_pi(rdev
);
292 if (pi
->enable_gfx_clock_gating
)
293 sumo_gfx_clockgating_initialize(rdev
);
294 if (pi
->enable_gfx_power_gating
)
295 sumo_gfx_powergating_initialize(rdev
);
296 if (pi
->enable_mg_clock_gating
)
297 sumo_mg_clockgating_enable(rdev
, true);
298 if (pi
->enable_gfx_clock_gating
)
299 sumo_gfx_clockgating_enable(rdev
, true);
300 if (pi
->enable_gfx_power_gating
)
301 sumo_gfx_powergating_enable(rdev
, true);
306 static void sumo_disable_clock_power_gating(struct radeon_device
*rdev
)
308 struct sumo_power_info
*pi
= sumo_get_pi(rdev
);
310 if (pi
->enable_gfx_clock_gating
)
311 sumo_gfx_clockgating_enable(rdev
, false);
312 if (pi
->enable_gfx_power_gating
)
313 sumo_gfx_powergating_enable(rdev
, false);
314 if (pi
->enable_mg_clock_gating
)
315 sumo_mg_clockgating_enable(rdev
, false);
318 static void sumo_calculate_bsp(struct radeon_device
*rdev
,
321 struct sumo_power_info
*pi
= sumo_get_pi(rdev
);
322 u32 xclk
= sumo_get_xclk(rdev
);
324 pi
->pasi
= 65535 * 100 / high_clk
;
325 pi
->asi
= 65535 * 100 / high_clk
;
327 r600_calculate_u_and_p(pi
->asi
,
328 xclk
, 16, &pi
->bsp
, &pi
->bsu
);
330 r600_calculate_u_and_p(pi
->pasi
,
331 xclk
, 16, &pi
->pbsp
, &pi
->pbsu
);
333 pi
->dsp
= BSP(pi
->bsp
) | BSU(pi
->bsu
);
334 pi
->psp
= BSP(pi
->pbsp
) | BSU(pi
->pbsu
);
337 static void sumo_init_bsp(struct radeon_device
*rdev
)
339 struct sumo_power_info
*pi
= sumo_get_pi(rdev
);
341 WREG32(CG_BSP_0
, pi
->psp
);
345 static void sumo_program_bsp(struct radeon_device
*rdev
,
346 struct radeon_ps
*rps
)
348 struct sumo_power_info
*pi
= sumo_get_pi(rdev
);
349 struct sumo_ps
*ps
= sumo_get_ps(rps
);
351 u32 highest_engine_clock
= ps
->levels
[ps
->num_levels
- 1].sclk
;
353 if (ps
->flags
& SUMO_POWERSTATE_FLAGS_BOOST_STATE
)
354 highest_engine_clock
= pi
->boost_pl
.sclk
;
356 sumo_calculate_bsp(rdev
, highest_engine_clock
);
358 for (i
= 0; i
< ps
->num_levels
- 1; i
++)
359 WREG32(CG_BSP_0
+ (i
* 4), pi
->dsp
);
361 WREG32(CG_BSP_0
+ (i
* 4), pi
->psp
);
363 if (ps
->flags
& SUMO_POWERSTATE_FLAGS_BOOST_STATE
)
364 WREG32(CG_BSP_0
+ (BOOST_DPM_LEVEL
* 4), pi
->psp
);
367 static void sumo_write_at(struct radeon_device
*rdev
,
368 u32 index
, u32 value
)
371 WREG32(CG_AT_0
, value
);
373 WREG32(CG_AT_1
, value
);
375 WREG32(CG_AT_2
, value
);
377 WREG32(CG_AT_3
, value
);
379 WREG32(CG_AT_4
, value
);
381 WREG32(CG_AT_5
, value
);
383 WREG32(CG_AT_6
, value
);
385 WREG32(CG_AT_7
, value
);
388 static void sumo_program_at(struct radeon_device
*rdev
,
389 struct radeon_ps
*rps
)
391 struct sumo_power_info
*pi
= sumo_get_pi(rdev
);
392 struct sumo_ps
*ps
= sumo_get_ps(rps
);
397 u32 r
[SUMO_MAX_HARDWARE_POWERLEVELS
];
398 u32 l
[SUMO_MAX_HARDWARE_POWERLEVELS
];
412 for (i
= 0; i
< ps
->num_levels
; i
++) {
413 asi
= (i
== ps
->num_levels
- 1) ? pi
->pasi
: pi
->asi
;
415 m_a
= asi
* ps
->levels
[i
].sclk
/ 100;
417 a_t
= CG_R(m_a
* r
[i
] / 100) | CG_L(m_a
* l
[i
] / 100);
419 sumo_write_at(rdev
, i
, a_t
);
422 if (ps
->flags
& SUMO_POWERSTATE_FLAGS_BOOST_STATE
) {
425 m_a
= asi
* pi
->boost_pl
.sclk
/ 100;
427 a_t
= CG_R(m_a
* r
[ps
->num_levels
- 1] / 100) |
428 CG_L(m_a
* l
[ps
->num_levels
- 1] / 100);
430 sumo_write_at(rdev
, BOOST_DPM_LEVEL
, a_t
);
434 static void sumo_program_tp(struct radeon_device
*rdev
)
437 enum r600_td td
= R600_TD_DFLT
;
439 for (i
= 0; i
< SUMO_PM_NUMBER_OF_TC
; i
++) {
440 WREG32_P(CG_FFCT_0
+ (i
* 4), UTC_0(sumo_utc
[i
]), ~UTC_0_MASK
);
441 WREG32_P(CG_FFCT_0
+ (i
* 4), DTC_0(sumo_dtc
[i
]), ~DTC_0_MASK
);
444 if (td
== R600_TD_AUTO
)
445 WREG32_P(SCLK_PWRMGT_CNTL
, 0, ~FIR_FORCE_TREND_SEL
);
447 WREG32_P(SCLK_PWRMGT_CNTL
, FIR_FORCE_TREND_SEL
, ~FIR_FORCE_TREND_SEL
);
449 if (td
== R600_TD_UP
)
450 WREG32_P(SCLK_PWRMGT_CNTL
, 0, ~FIR_TREND_MODE
);
452 if (td
== R600_TD_DOWN
)
453 WREG32_P(SCLK_PWRMGT_CNTL
, FIR_TREND_MODE
, ~FIR_TREND_MODE
);
456 void sumo_program_vc(struct radeon_device
*rdev
, u32 vrc
)
461 void sumo_clear_vc(struct radeon_device
*rdev
)
466 void sumo_program_sstp(struct radeon_device
*rdev
)
469 u32 xclk
= sumo_get_xclk(rdev
);
471 r600_calculate_u_and_p(SUMO_SST_DFLT
,
474 WREG32(CG_SSP
, SSTU(u
) | SST(p
));
477 static void sumo_set_divider_value(struct radeon_device
*rdev
,
478 u32 index
, u32 divider
)
480 u32 reg_index
= index
/ 4;
481 u32 field_index
= index
% 4;
483 if (field_index
== 0)
484 WREG32_P(CG_SCLK_DPM_CTRL
+ (reg_index
* 4),
485 SCLK_FSTATE_0_DIV(divider
), ~SCLK_FSTATE_0_DIV_MASK
);
486 else if (field_index
== 1)
487 WREG32_P(CG_SCLK_DPM_CTRL
+ (reg_index
* 4),
488 SCLK_FSTATE_1_DIV(divider
), ~SCLK_FSTATE_1_DIV_MASK
);
489 else if (field_index
== 2)
490 WREG32_P(CG_SCLK_DPM_CTRL
+ (reg_index
* 4),
491 SCLK_FSTATE_2_DIV(divider
), ~SCLK_FSTATE_2_DIV_MASK
);
492 else if (field_index
== 3)
493 WREG32_P(CG_SCLK_DPM_CTRL
+ (reg_index
* 4),
494 SCLK_FSTATE_3_DIV(divider
), ~SCLK_FSTATE_3_DIV_MASK
);
497 static void sumo_set_ds_dividers(struct radeon_device
*rdev
,
498 u32 index
, u32 divider
)
500 struct sumo_power_info
*pi
= sumo_get_pi(rdev
);
502 if (pi
->enable_sclk_ds
) {
503 u32 dpm_ctrl
= RREG32(CG_SCLK_DPM_CTRL_6
);
505 dpm_ctrl
&= ~(0x7 << (index
* 3));
506 dpm_ctrl
|= (divider
<< (index
* 3));
507 WREG32(CG_SCLK_DPM_CTRL_6
, dpm_ctrl
);
511 static void sumo_set_ss_dividers(struct radeon_device
*rdev
,
512 u32 index
, u32 divider
)
514 struct sumo_power_info
*pi
= sumo_get_pi(rdev
);
516 if (pi
->enable_sclk_ds
) {
517 u32 dpm_ctrl
= RREG32(CG_SCLK_DPM_CTRL_11
);
519 dpm_ctrl
&= ~(0x7 << (index
* 3));
520 dpm_ctrl
|= (divider
<< (index
* 3));
521 WREG32(CG_SCLK_DPM_CTRL_11
, dpm_ctrl
);
525 static void sumo_set_vid(struct radeon_device
*rdev
, u32 index
, u32 vid
)
527 u32 voltage_cntl
= RREG32(CG_DPM_VOLTAGE_CNTL
);
529 voltage_cntl
&= ~(DPM_STATE0_LEVEL_MASK
<< (index
* 2));
530 voltage_cntl
|= (vid
<< (DPM_STATE0_LEVEL_SHIFT
+ index
* 2));
531 WREG32(CG_DPM_VOLTAGE_CNTL
, voltage_cntl
);
534 static void sumo_set_allos_gnb_slow(struct radeon_device
*rdev
, u32 index
, u32 gnb_slow
)
536 struct sumo_power_info
*pi
= sumo_get_pi(rdev
);
538 u32 cg_sclk_dpm_ctrl_3
;
540 if (pi
->driver_nbps_policy_disable
)
543 cg_sclk_dpm_ctrl_3
= RREG32(CG_SCLK_DPM_CTRL_3
);
544 cg_sclk_dpm_ctrl_3
&= ~(GNB_SLOW_FSTATE_0_MASK
<< index
);
545 cg_sclk_dpm_ctrl_3
|= (temp
<< (GNB_SLOW_FSTATE_0_SHIFT
+ index
));
547 WREG32(CG_SCLK_DPM_CTRL_3
, cg_sclk_dpm_ctrl_3
);
550 static void sumo_program_power_level(struct radeon_device
*rdev
,
551 struct sumo_pl
*pl
, u32 index
)
553 struct sumo_power_info
*pi
= sumo_get_pi(rdev
);
555 struct atom_clock_dividers dividers
;
556 u32 ds_en
= RREG32(DEEP_SLEEP_CNTL
) & ENABLE_DS
;
558 ret
= radeon_atom_get_clock_dividers(rdev
, COMPUTE_ENGINE_PLL_PARAM
,
559 pl
->sclk
, false, ÷rs
);
563 sumo_set_divider_value(rdev
, index
, dividers
.post_div
);
565 sumo_set_vid(rdev
, index
, pl
->vddc_index
);
567 if (pl
->ss_divider_index
== 0 || pl
->ds_divider_index
== 0) {
569 WREG32_P(DEEP_SLEEP_CNTL
, 0, ~ENABLE_DS
);
571 sumo_set_ss_dividers(rdev
, index
, pl
->ss_divider_index
);
572 sumo_set_ds_dividers(rdev
, index
, pl
->ds_divider_index
);
575 WREG32_P(DEEP_SLEEP_CNTL
, ENABLE_DS
, ~ENABLE_DS
);
578 sumo_set_allos_gnb_slow(rdev
, index
, pl
->allow_gnb_slow
);
580 if (pi
->enable_boost
)
581 sumo_set_tdp_limit(rdev
, index
, pl
->sclk_dpm_tdp_limit
);
584 static void sumo_power_level_enable(struct radeon_device
*rdev
, u32 index
, bool enable
)
586 u32 reg_index
= index
/ 4;
587 u32 field_index
= index
% 4;
589 if (field_index
== 0)
590 WREG32_P(CG_SCLK_DPM_CTRL
+ (reg_index
* 4),
591 enable
? SCLK_FSTATE_0_VLD
: 0, ~SCLK_FSTATE_0_VLD
);
592 else if (field_index
== 1)
593 WREG32_P(CG_SCLK_DPM_CTRL
+ (reg_index
* 4),
594 enable
? SCLK_FSTATE_1_VLD
: 0, ~SCLK_FSTATE_1_VLD
);
595 else if (field_index
== 2)
596 WREG32_P(CG_SCLK_DPM_CTRL
+ (reg_index
* 4),
597 enable
? SCLK_FSTATE_2_VLD
: 0, ~SCLK_FSTATE_2_VLD
);
598 else if (field_index
== 3)
599 WREG32_P(CG_SCLK_DPM_CTRL
+ (reg_index
* 4),
600 enable
? SCLK_FSTATE_3_VLD
: 0, ~SCLK_FSTATE_3_VLD
);
603 static bool sumo_dpm_enabled(struct radeon_device
*rdev
)
605 if (RREG32(CG_SCLK_DPM_CTRL_3
) & DPM_SCLK_ENABLE
)
611 static void sumo_start_dpm(struct radeon_device
*rdev
)
613 WREG32_P(CG_SCLK_DPM_CTRL_3
, DPM_SCLK_ENABLE
, ~DPM_SCLK_ENABLE
);
616 static void sumo_stop_dpm(struct radeon_device
*rdev
)
618 WREG32_P(CG_SCLK_DPM_CTRL_3
, 0, ~DPM_SCLK_ENABLE
);
621 static void sumo_set_forced_mode(struct radeon_device
*rdev
, bool enable
)
624 WREG32_P(CG_SCLK_DPM_CTRL_3
, FORCE_SCLK_STATE_EN
, ~FORCE_SCLK_STATE_EN
);
626 WREG32_P(CG_SCLK_DPM_CTRL_3
, 0, ~FORCE_SCLK_STATE_EN
);
629 static void sumo_set_forced_mode_enabled(struct radeon_device
*rdev
)
633 sumo_set_forced_mode(rdev
, true);
634 for (i
= 0; i
< rdev
->usec_timeout
; i
++) {
635 if (RREG32(CG_SCLK_STATUS
) & SCLK_OVERCLK_DETECT
)
641 static void sumo_wait_for_level_0(struct radeon_device
*rdev
)
645 for (i
= 0; i
< rdev
->usec_timeout
; i
++) {
646 if ((RREG32(TARGET_AND_CURRENT_PROFILE_INDEX
) & CURR_SCLK_INDEX_MASK
) == 0)
650 for (i
= 0; i
< rdev
->usec_timeout
; i
++) {
651 if ((RREG32(TARGET_AND_CURRENT_PROFILE_INDEX
) & CURR_INDEX_MASK
) == 0)
657 static void sumo_set_forced_mode_disabled(struct radeon_device
*rdev
)
659 sumo_set_forced_mode(rdev
, false);
662 static void sumo_enable_power_level_0(struct radeon_device
*rdev
)
664 sumo_power_level_enable(rdev
, 0, true);
667 static void sumo_patch_boost_state(struct radeon_device
*rdev
,
668 struct radeon_ps
*rps
)
670 struct sumo_power_info
*pi
= sumo_get_pi(rdev
);
671 struct sumo_ps
*new_ps
= sumo_get_ps(rps
);
673 if (new_ps
->flags
& SUMO_POWERSTATE_FLAGS_BOOST_STATE
) {
674 pi
->boost_pl
= new_ps
->levels
[new_ps
->num_levels
- 1];
675 pi
->boost_pl
.sclk
= pi
->sys_info
.boost_sclk
;
676 pi
->boost_pl
.vddc_index
= pi
->sys_info
.boost_vid_2bit
;
677 pi
->boost_pl
.sclk_dpm_tdp_limit
= pi
->sys_info
.sclk_dpm_tdp_limit_boost
;
681 static void sumo_pre_notify_alt_vddnb_change(struct radeon_device
*rdev
,
682 struct radeon_ps
*new_rps
,
683 struct radeon_ps
*old_rps
)
685 struct sumo_ps
*new_ps
= sumo_get_ps(new_rps
);
686 struct sumo_ps
*old_ps
= sumo_get_ps(old_rps
);
691 nbps1_old
= (old_ps
->flags
& SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE
) ? 1 : 0;
693 nbps1_new
= (new_ps
->flags
& SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE
) ? 1 : 0;
695 if (nbps1_old
== 1 && nbps1_new
== 0)
696 sumo_smu_notify_alt_vddnb_change(rdev
, 0, 0);
699 static void sumo_post_notify_alt_vddnb_change(struct radeon_device
*rdev
,
700 struct radeon_ps
*new_rps
,
701 struct radeon_ps
*old_rps
)
703 struct sumo_ps
*new_ps
= sumo_get_ps(new_rps
);
704 struct sumo_ps
*old_ps
= sumo_get_ps(old_rps
);
709 nbps1_old
= (old_ps
->flags
& SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE
)? 1 : 0;
711 nbps1_new
= (new_ps
->flags
& SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE
)? 1 : 0;
713 if (nbps1_old
== 0 && nbps1_new
== 1)
714 sumo_smu_notify_alt_vddnb_change(rdev
, 1, 1);
717 static void sumo_enable_boost(struct radeon_device
*rdev
,
718 struct radeon_ps
*rps
,
721 struct sumo_ps
*new_ps
= sumo_get_ps(rps
);
724 if (new_ps
->flags
& SUMO_POWERSTATE_FLAGS_BOOST_STATE
)
725 sumo_boost_state_enable(rdev
, true);
727 sumo_boost_state_enable(rdev
, false);
730 static void sumo_update_current_power_levels(struct radeon_device
*rdev
,
731 struct radeon_ps
*rps
)
733 struct sumo_ps
*new_ps
= sumo_get_ps(rps
);
734 struct sumo_power_info
*pi
= sumo_get_pi(rdev
);
736 pi
->current_ps
= *new_ps
;
739 static void sumo_set_forced_level(struct radeon_device
*rdev
, u32 index
)
741 WREG32_P(CG_SCLK_DPM_CTRL_3
, FORCE_SCLK_STATE(index
), ~FORCE_SCLK_STATE_MASK
);
744 static void sumo_set_forced_level_0(struct radeon_device
*rdev
)
746 sumo_set_forced_level(rdev
, 0);
749 static void sumo_program_wl(struct radeon_device
*rdev
,
750 struct radeon_ps
*rps
)
752 struct sumo_ps
*new_ps
= sumo_get_ps(rps
);
753 u32 dpm_ctrl4
= RREG32(CG_SCLK_DPM_CTRL_4
);
755 dpm_ctrl4
&= 0xFFFFFF00;
756 dpm_ctrl4
|= (1 << (new_ps
->num_levels
- 1));
758 if (new_ps
->flags
& SUMO_POWERSTATE_FLAGS_BOOST_STATE
)
759 dpm_ctrl4
|= (1 << BOOST_DPM_LEVEL
);
761 WREG32(CG_SCLK_DPM_CTRL_4
, dpm_ctrl4
);
764 static void sumo_program_power_levels_0_to_n(struct radeon_device
*rdev
,
765 struct radeon_ps
*new_rps
,
766 struct radeon_ps
*old_rps
)
768 struct sumo_power_info
*pi
= sumo_get_pi(rdev
);
769 struct sumo_ps
*new_ps
= sumo_get_ps(new_rps
);
770 struct sumo_ps
*old_ps
= sumo_get_ps(old_rps
);
772 u32 n_current_state_levels
= (old_ps
== NULL
) ? 1 : old_ps
->num_levels
;
774 for (i
= 0; i
< new_ps
->num_levels
; i
++) {
775 sumo_program_power_level(rdev
, &new_ps
->levels
[i
], i
);
776 sumo_power_level_enable(rdev
, i
, true);
779 for (i
= new_ps
->num_levels
; i
< n_current_state_levels
; i
++)
780 sumo_power_level_enable(rdev
, i
, false);
782 if (new_ps
->flags
& SUMO_POWERSTATE_FLAGS_BOOST_STATE
)
783 sumo_program_power_level(rdev
, &pi
->boost_pl
, BOOST_DPM_LEVEL
);
786 static void sumo_enable_acpi_pm(struct radeon_device
*rdev
)
788 WREG32_P(GENERAL_PWRMGT
, STATIC_PM_EN
, ~STATIC_PM_EN
);
791 static void sumo_program_power_level_enter_state(struct radeon_device
*rdev
)
793 WREG32_P(CG_SCLK_DPM_CTRL_5
, SCLK_FSTATE_BOOTUP(0), ~SCLK_FSTATE_BOOTUP_MASK
);
796 static void sumo_program_acpi_power_level(struct radeon_device
*rdev
)
798 struct sumo_power_info
*pi
= sumo_get_pi(rdev
);
799 struct atom_clock_dividers dividers
;
802 ret
= radeon_atom_get_clock_dividers(rdev
, COMPUTE_ENGINE_PLL_PARAM
,
808 WREG32_P(CG_ACPI_CNTL
, SCLK_ACPI_DIV(dividers
.post_div
), ~SCLK_ACPI_DIV_MASK
);
809 WREG32_P(CG_ACPI_VOLTAGE_CNTL
, 0, ~ACPI_VOLTAGE_EN
);
812 static void sumo_program_bootup_state(struct radeon_device
*rdev
)
814 struct sumo_power_info
*pi
= sumo_get_pi(rdev
);
815 u32 dpm_ctrl4
= RREG32(CG_SCLK_DPM_CTRL_4
);
818 sumo_program_power_level(rdev
, &pi
->boot_pl
, 0);
820 dpm_ctrl4
&= 0xFFFFFF00;
821 WREG32(CG_SCLK_DPM_CTRL_4
, dpm_ctrl4
);
823 for (i
= 1; i
< 8; i
++)
824 sumo_power_level_enable(rdev
, i
, false);
827 static void sumo_set_uvd_clock_before_set_eng_clock(struct radeon_device
*rdev
,
828 struct radeon_ps
*new_rps
,
829 struct radeon_ps
*old_rps
)
831 struct sumo_ps
*new_ps
= sumo_get_ps(new_rps
);
832 struct sumo_ps
*current_ps
= sumo_get_ps(old_rps
);
834 if ((new_rps
->vclk
== old_rps
->vclk
) &&
835 (new_rps
->dclk
== old_rps
->dclk
))
838 if (new_ps
->levels
[new_ps
->num_levels
- 1].sclk
>=
839 current_ps
->levels
[current_ps
->num_levels
- 1].sclk
)
842 radeon_set_uvd_clocks(rdev
, new_rps
->vclk
, new_rps
->dclk
);
845 static void sumo_set_uvd_clock_after_set_eng_clock(struct radeon_device
*rdev
,
846 struct radeon_ps
*new_rps
,
847 struct radeon_ps
*old_rps
)
849 struct sumo_ps
*new_ps
= sumo_get_ps(new_rps
);
850 struct sumo_ps
*current_ps
= sumo_get_ps(old_rps
);
852 if ((new_rps
->vclk
== old_rps
->vclk
) &&
853 (new_rps
->dclk
== old_rps
->dclk
))
856 if (new_ps
->levels
[new_ps
->num_levels
- 1].sclk
<
857 current_ps
->levels
[current_ps
->num_levels
- 1].sclk
)
860 radeon_set_uvd_clocks(rdev
, new_rps
->vclk
, new_rps
->dclk
);
863 void sumo_take_smu_control(struct radeon_device
*rdev
, bool enable
)
865 /* This bit selects who handles display phy powergating.
866 * Clear the bit to let atom handle it.
867 * Set it to let the driver handle it.
868 * For now we just let atom handle it.
871 u32 v
= RREG32(DOUT_SCRATCH3
);
878 WREG32(DOUT_SCRATCH3
, v
);
882 static void sumo_enable_sclk_ds(struct radeon_device
*rdev
, bool enable
)
885 u32 deep_sleep_cntl
= RREG32(DEEP_SLEEP_CNTL
);
886 u32 deep_sleep_cntl2
= RREG32(DEEP_SLEEP_CNTL2
);
889 deep_sleep_cntl
&= ~R_DIS
;
890 deep_sleep_cntl
&= ~HS_MASK
;
891 deep_sleep_cntl
|= HS(t
> 4095 ? 4095 : t
);
893 deep_sleep_cntl2
|= LB_UFP_EN
;
894 deep_sleep_cntl2
&= INOUT_C_MASK
;
895 deep_sleep_cntl2
|= INOUT_C(0xf);
897 WREG32(DEEP_SLEEP_CNTL2
, deep_sleep_cntl2
);
898 WREG32(DEEP_SLEEP_CNTL
, deep_sleep_cntl
);
900 WREG32_P(DEEP_SLEEP_CNTL
, 0, ~ENABLE_DS
);
903 static void sumo_program_bootup_at(struct radeon_device
*rdev
)
905 WREG32_P(CG_AT_0
, CG_R(0xffff), ~CG_R_MASK
);
906 WREG32_P(CG_AT_0
, CG_L(0), ~CG_L_MASK
);
909 static void sumo_reset_am(struct radeon_device
*rdev
)
911 WREG32_P(SCLK_PWRMGT_CNTL
, FIR_RESET
, ~FIR_RESET
);
914 static void sumo_start_am(struct radeon_device
*rdev
)
916 WREG32_P(SCLK_PWRMGT_CNTL
, 0, ~FIR_RESET
);
919 static void sumo_program_ttp(struct radeon_device
*rdev
)
921 u32 xclk
= sumo_get_xclk(rdev
);
923 u32 cg_sclk_dpm_ctrl_5
= RREG32(CG_SCLK_DPM_CTRL_5
);
925 r600_calculate_u_and_p(1000,
928 cg_sclk_dpm_ctrl_5
&= ~(TT_TP_MASK
| TT_TU_MASK
);
929 cg_sclk_dpm_ctrl_5
|= TT_TP(p
) | TT_TU(u
);
931 WREG32(CG_SCLK_DPM_CTRL_5
, cg_sclk_dpm_ctrl_5
);
934 static void sumo_program_ttt(struct radeon_device
*rdev
)
936 u32 cg_sclk_dpm_ctrl_3
= RREG32(CG_SCLK_DPM_CTRL_3
);
937 struct sumo_power_info
*pi
= sumo_get_pi(rdev
);
939 cg_sclk_dpm_ctrl_3
&= ~(GNB_TT_MASK
| GNB_THERMTHRO_MASK
);
940 cg_sclk_dpm_ctrl_3
|= GNB_TT(pi
->thermal_auto_throttling
+ 49);
942 WREG32(CG_SCLK_DPM_CTRL_3
, cg_sclk_dpm_ctrl_3
);
946 static void sumo_enable_voltage_scaling(struct radeon_device
*rdev
, bool enable
)
949 WREG32_P(CG_DPM_VOLTAGE_CNTL
, DPM_VOLTAGE_EN
, ~DPM_VOLTAGE_EN
);
950 WREG32_P(CG_CG_VOLTAGE_CNTL
, 0, ~CG_VOLTAGE_EN
);
952 WREG32_P(CG_CG_VOLTAGE_CNTL
, CG_VOLTAGE_EN
, ~CG_VOLTAGE_EN
);
953 WREG32_P(CG_DPM_VOLTAGE_CNTL
, 0, ~DPM_VOLTAGE_EN
);
957 static void sumo_override_cnb_thermal_events(struct radeon_device
*rdev
)
959 WREG32_P(CG_SCLK_DPM_CTRL_3
, CNB_THERMTHRO_MASK_SCLK
,
960 ~CNB_THERMTHRO_MASK_SCLK
);
963 static void sumo_program_dc_hto(struct radeon_device
*rdev
)
965 u32 cg_sclk_dpm_ctrl_4
= RREG32(CG_SCLK_DPM_CTRL_4
);
967 u32 xclk
= sumo_get_xclk(rdev
);
969 r600_calculate_u_and_p(100000,
972 cg_sclk_dpm_ctrl_4
&= ~(DC_HDC_MASK
| DC_HU_MASK
);
973 cg_sclk_dpm_ctrl_4
|= DC_HDC(p
) | DC_HU(u
);
975 WREG32(CG_SCLK_DPM_CTRL_4
, cg_sclk_dpm_ctrl_4
);
978 static void sumo_force_nbp_state(struct radeon_device
*rdev
,
979 struct radeon_ps
*rps
)
981 struct sumo_power_info
*pi
= sumo_get_pi(rdev
);
982 struct sumo_ps
*new_ps
= sumo_get_ps(rps
);
984 if (!pi
->driver_nbps_policy_disable
) {
985 if (new_ps
->flags
& SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE
)
986 WREG32_P(CG_SCLK_DPM_CTRL_3
, FORCE_NB_PSTATE_1
, ~FORCE_NB_PSTATE_1
);
988 WREG32_P(CG_SCLK_DPM_CTRL_3
, 0, ~FORCE_NB_PSTATE_1
);
992 u32
sumo_get_sleep_divider_from_id(u32 id
)
997 u32
sumo_get_sleep_divider_id_from_clock(struct radeon_device
*rdev
,
1001 struct sumo_power_info
*pi
= sumo_get_pi(rdev
);
1004 u32 min
= (min_sclk_in_sr
> SUMO_MINIMUM_ENGINE_CLOCK
) ?
1005 min_sclk_in_sr
: SUMO_MINIMUM_ENGINE_CLOCK
;
1010 if (!pi
->enable_sclk_ds
)
1013 for (i
= SUMO_MAX_DEEPSLEEP_DIVIDER_ID
; ; i
--) {
1014 temp
= sclk
/ sumo_get_sleep_divider_from_id(i
);
1016 if (temp
>= min
|| i
== 0)
1022 static u32
sumo_get_valid_engine_clock(struct radeon_device
*rdev
,
1025 struct sumo_power_info
*pi
= sumo_get_pi(rdev
);
1028 for (i
= 0; i
< pi
->sys_info
.sclk_voltage_mapping_table
.num_max_dpm_entries
; i
++) {
1029 if (pi
->sys_info
.sclk_voltage_mapping_table
.entries
[i
].sclk_frequency
>= lower_limit
)
1030 return pi
->sys_info
.sclk_voltage_mapping_table
.entries
[i
].sclk_frequency
;
1033 return pi
->sys_info
.sclk_voltage_mapping_table
.entries
[pi
->sys_info
.sclk_voltage_mapping_table
.num_max_dpm_entries
- 1].sclk_frequency
;
1036 static void sumo_patch_thermal_state(struct radeon_device
*rdev
,
1038 struct sumo_ps
*current_ps
)
1040 struct sumo_power_info
*pi
= sumo_get_pi(rdev
);
1041 u32 sclk_in_sr
= pi
->sys_info
.min_sclk
; /* ??? */
1044 u32 current_index
= 0;
1047 current_vddc
= current_ps
->levels
[current_index
].vddc_index
;
1048 current_sclk
= current_ps
->levels
[current_index
].sclk
;
1050 current_vddc
= pi
->boot_pl
.vddc_index
;
1051 current_sclk
= pi
->boot_pl
.sclk
;
1054 ps
->levels
[0].vddc_index
= current_vddc
;
1056 if (ps
->levels
[0].sclk
> current_sclk
)
1057 ps
->levels
[0].sclk
= current_sclk
;
1059 ps
->levels
[0].ss_divider_index
=
1060 sumo_get_sleep_divider_id_from_clock(rdev
, ps
->levels
[0].sclk
, sclk_in_sr
);
1062 ps
->levels
[0].ds_divider_index
=
1063 sumo_get_sleep_divider_id_from_clock(rdev
, ps
->levels
[0].sclk
, SUMO_MINIMUM_ENGINE_CLOCK
);
1065 if (ps
->levels
[0].ds_divider_index
> ps
->levels
[0].ss_divider_index
+ 1)
1066 ps
->levels
[0].ds_divider_index
= ps
->levels
[0].ss_divider_index
+ 1;
1068 if (ps
->levels
[0].ss_divider_index
== ps
->levels
[0].ds_divider_index
) {
1069 if (ps
->levels
[0].ss_divider_index
> 1)
1070 ps
->levels
[0].ss_divider_index
= ps
->levels
[0].ss_divider_index
- 1;
1073 if (ps
->levels
[0].ss_divider_index
== 0)
1074 ps
->levels
[0].ds_divider_index
= 0;
1076 if (ps
->levels
[0].ds_divider_index
== 0)
1077 ps
->levels
[0].ss_divider_index
= 0;
1080 static void sumo_apply_state_adjust_rules(struct radeon_device
*rdev
,
1081 struct radeon_ps
*new_rps
,
1082 struct radeon_ps
*old_rps
)
1084 struct sumo_ps
*ps
= sumo_get_ps(new_rps
);
1085 struct sumo_ps
*current_ps
= sumo_get_ps(old_rps
);
1086 struct sumo_power_info
*pi
= sumo_get_pi(rdev
);
1087 u32 min_voltage
= 0; /* ??? */
1088 u32 min_sclk
= pi
->sys_info
.min_sclk
; /* XXX check against disp reqs */
1089 u32 sclk_in_sr
= pi
->sys_info
.min_sclk
; /* ??? */
1092 /* point to the hw copy since this function will modify the ps */
1094 rdev
->pm
.dpm
.hw_ps
.ps_priv
= &pi
->hw_ps
;
1097 if (new_rps
->class & ATOM_PPLIB_CLASSIFICATION_THERMAL
)
1098 return sumo_patch_thermal_state(rdev
, ps
, current_ps
);
1100 if (pi
->enable_boost
) {
1101 if (new_rps
->class & ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE
)
1102 ps
->flags
|= SUMO_POWERSTATE_FLAGS_BOOST_STATE
;
1105 if ((new_rps
->class & ATOM_PPLIB_CLASSIFICATION_UI_BATTERY
) ||
1106 (new_rps
->class & ATOM_PPLIB_CLASSIFICATION_SDSTATE
) ||
1107 (new_rps
->class & ATOM_PPLIB_CLASSIFICATION_HDSTATE
))
1108 ps
->flags
|= SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE
;
1110 for (i
= 0; i
< ps
->num_levels
; i
++) {
1111 if (ps
->levels
[i
].vddc_index
< min_voltage
)
1112 ps
->levels
[i
].vddc_index
= min_voltage
;
1114 if (ps
->levels
[i
].sclk
< min_sclk
)
1115 ps
->levels
[i
].sclk
=
1116 sumo_get_valid_engine_clock(rdev
, min_sclk
);
1118 ps
->levels
[i
].ss_divider_index
=
1119 sumo_get_sleep_divider_id_from_clock(rdev
, ps
->levels
[i
].sclk
, sclk_in_sr
);
1121 ps
->levels
[i
].ds_divider_index
=
1122 sumo_get_sleep_divider_id_from_clock(rdev
, ps
->levels
[i
].sclk
, SUMO_MINIMUM_ENGINE_CLOCK
);
1124 if (ps
->levels
[i
].ds_divider_index
> ps
->levels
[i
].ss_divider_index
+ 1)
1125 ps
->levels
[i
].ds_divider_index
= ps
->levels
[i
].ss_divider_index
+ 1;
1127 if (ps
->levels
[i
].ss_divider_index
== ps
->levels
[i
].ds_divider_index
) {
1128 if (ps
->levels
[i
].ss_divider_index
> 1)
1129 ps
->levels
[i
].ss_divider_index
= ps
->levels
[i
].ss_divider_index
- 1;
1132 if (ps
->levels
[i
].ss_divider_index
== 0)
1133 ps
->levels
[i
].ds_divider_index
= 0;
1135 if (ps
->levels
[i
].ds_divider_index
== 0)
1136 ps
->levels
[i
].ss_divider_index
= 0;
1138 if (ps
->flags
& SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE
)
1139 ps
->levels
[i
].allow_gnb_slow
= 1;
1140 else if ((new_rps
->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE
) ||
1141 (new_rps
->class2
& ATOM_PPLIB_CLASSIFICATION2_MVC
))
1142 ps
->levels
[i
].allow_gnb_slow
= 0;
1143 else if (i
== ps
->num_levels
- 1)
1144 ps
->levels
[i
].allow_gnb_slow
= 0;
1146 ps
->levels
[i
].allow_gnb_slow
= 1;
1150 static void sumo_cleanup_asic(struct radeon_device
*rdev
)
1152 sumo_take_smu_control(rdev
, false);
1155 static void sumo_uvd_init(struct radeon_device
*rdev
)
1159 tmp
= RREG32(CG_VCLK_CNTL
);
1160 tmp
&= ~VCLK_DIR_CNTL_EN
;
1161 WREG32(CG_VCLK_CNTL
, tmp
);
1163 tmp
= RREG32(CG_DCLK_CNTL
);
1164 tmp
&= ~DCLK_DIR_CNTL_EN
;
1165 WREG32(CG_DCLK_CNTL
, tmp
);
1168 radeon_set_uvd_clocks(rdev
, 10000, 10000);
1171 static int sumo_set_thermal_temperature_range(struct radeon_device
*rdev
,
1172 int min_temp
, int max_temp
)
1174 int low_temp
= 0 * 1000;
1175 int high_temp
= 255 * 1000;
1177 if (low_temp
< min_temp
)
1178 low_temp
= min_temp
;
1179 if (high_temp
> max_temp
)
1180 high_temp
= max_temp
;
1181 if (high_temp
< low_temp
) {
1182 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp
, high_temp
);
1186 WREG32_P(CG_THERMAL_INT
, DIG_THERM_INTH(49 + (high_temp
/ 1000)), ~DIG_THERM_INTH_MASK
);
1187 WREG32_P(CG_THERMAL_INT
, DIG_THERM_INTL(49 + (low_temp
/ 1000)), ~DIG_THERM_INTL_MASK
);
1189 rdev
->pm
.dpm
.thermal
.min_temp
= low_temp
;
1190 rdev
->pm
.dpm
.thermal
.max_temp
= high_temp
;
1195 int sumo_dpm_enable(struct radeon_device
*rdev
)
1197 struct sumo_power_info
*pi
= sumo_get_pi(rdev
);
1199 if (sumo_dpm_enabled(rdev
))
1202 sumo_enable_clock_power_gating(rdev
);
1203 sumo_program_bootup_state(rdev
);
1204 sumo_init_bsp(rdev
);
1205 sumo_reset_am(rdev
);
1206 sumo_program_tp(rdev
);
1207 sumo_program_bootup_at(rdev
);
1208 sumo_start_am(rdev
);
1209 if (pi
->enable_auto_thermal_throttling
) {
1210 sumo_program_ttp(rdev
);
1211 sumo_program_ttt(rdev
);
1213 sumo_program_dc_hto(rdev
);
1214 sumo_program_power_level_enter_state(rdev
);
1215 sumo_enable_voltage_scaling(rdev
, true);
1216 sumo_program_sstp(rdev
);
1217 sumo_program_vc(rdev
, SUMO_VRC_DFLT
);
1218 sumo_override_cnb_thermal_events(rdev
);
1219 sumo_start_dpm(rdev
);
1220 sumo_wait_for_level_0(rdev
);
1221 if (pi
->enable_sclk_ds
)
1222 sumo_enable_sclk_ds(rdev
, true);
1223 if (pi
->enable_boost
)
1224 sumo_enable_boost_timer(rdev
);
1226 if (rdev
->irq
.installed
&&
1227 r600_is_internal_thermal_sensor(rdev
->pm
.int_thermal_type
)) {
1228 sumo_set_thermal_temperature_range(rdev
, R600_TEMP_RANGE_MIN
, R600_TEMP_RANGE_MAX
);
1229 rdev
->irq
.dpm_thermal
= true;
1230 radeon_irq_set(rdev
);
1236 void sumo_dpm_disable(struct radeon_device
*rdev
)
1238 struct sumo_power_info
*pi
= sumo_get_pi(rdev
);
1240 if (!sumo_dpm_enabled(rdev
))
1242 sumo_disable_clock_power_gating(rdev
);
1243 if (pi
->enable_sclk_ds
)
1244 sumo_enable_sclk_ds(rdev
, false);
1245 sumo_clear_vc(rdev
);
1246 sumo_wait_for_level_0(rdev
);
1247 sumo_stop_dpm(rdev
);
1248 sumo_enable_voltage_scaling(rdev
, false);
1250 if (rdev
->irq
.installed
&&
1251 r600_is_internal_thermal_sensor(rdev
->pm
.int_thermal_type
)) {
1252 rdev
->irq
.dpm_thermal
= false;
1253 radeon_irq_set(rdev
);
1257 int sumo_dpm_set_power_state(struct radeon_device
*rdev
)
1259 struct sumo_power_info
*pi
= sumo_get_pi(rdev
);
1260 struct radeon_ps
*new_ps
= rdev
->pm
.dpm
.requested_ps
;
1261 struct radeon_ps
*old_ps
= rdev
->pm
.dpm
.current_ps
;
1263 if (pi
->enable_dynamic_patch_ps
)
1264 sumo_apply_state_adjust_rules(rdev
, new_ps
, old_ps
);
1266 sumo_set_uvd_clock_before_set_eng_clock(rdev
, new_ps
, old_ps
);
1267 sumo_update_current_power_levels(rdev
, new_ps
);
1268 if (pi
->enable_boost
) {
1269 sumo_enable_boost(rdev
, new_ps
, false);
1270 sumo_patch_boost_state(rdev
, new_ps
);
1272 if (pi
->enable_dpm
) {
1273 sumo_pre_notify_alt_vddnb_change(rdev
, new_ps
, old_ps
);
1274 sumo_enable_power_level_0(rdev
);
1275 sumo_set_forced_level_0(rdev
);
1276 sumo_set_forced_mode_enabled(rdev
);
1277 sumo_wait_for_level_0(rdev
);
1278 sumo_program_power_levels_0_to_n(rdev
, new_ps
, old_ps
);
1279 sumo_program_wl(rdev
, new_ps
);
1280 sumo_program_bsp(rdev
, new_ps
);
1281 sumo_program_at(rdev
, new_ps
);
1282 sumo_force_nbp_state(rdev
, new_ps
);
1283 sumo_set_forced_mode_disabled(rdev
);
1284 sumo_set_forced_mode_enabled(rdev
);
1285 sumo_set_forced_mode_disabled(rdev
);
1286 sumo_post_notify_alt_vddnb_change(rdev
, new_ps
, old_ps
);
1288 if (pi
->enable_boost
)
1289 sumo_enable_boost(rdev
, new_ps
, true);
1291 sumo_set_uvd_clock_after_set_eng_clock(rdev
, new_ps
, old_ps
);
1296 void sumo_dpm_reset_asic(struct radeon_device
*rdev
)
1298 sumo_program_bootup_state(rdev
);
1299 sumo_enable_power_level_0(rdev
);
1300 sumo_set_forced_level_0(rdev
);
1301 sumo_set_forced_mode_enabled(rdev
);
1302 sumo_wait_for_level_0(rdev
);
1303 sumo_set_forced_mode_disabled(rdev
);
1304 sumo_set_forced_mode_enabled(rdev
);
1305 sumo_set_forced_mode_disabled(rdev
);
1308 void sumo_dpm_setup_asic(struct radeon_device
*rdev
)
1310 struct sumo_power_info
*pi
= sumo_get_pi(rdev
);
1312 sumo_initialize_m3_arb(rdev
);
1313 pi
->fw_version
= sumo_get_running_fw_version(rdev
);
1314 DRM_INFO("Found smc ucode version: 0x%08x\n", pi
->fw_version
);
1315 sumo_program_acpi_power_level(rdev
);
1316 sumo_enable_acpi_pm(rdev
);
1317 sumo_take_smu_control(rdev
, true);
1318 sumo_uvd_init(rdev
);
1321 void sumo_dpm_display_configuration_changed(struct radeon_device
*rdev
)
1327 struct _ATOM_POWERPLAY_INFO info
;
1328 struct _ATOM_POWERPLAY_INFO_V2 info_2
;
1329 struct _ATOM_POWERPLAY_INFO_V3 info_3
;
1330 struct _ATOM_PPLIB_POWERPLAYTABLE pplib
;
1331 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2
;
1332 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3
;
1335 union pplib_clock_info
{
1336 struct _ATOM_PPLIB_R600_CLOCK_INFO r600
;
1337 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780
;
1338 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen
;
1339 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo
;
1342 union pplib_power_state
{
1343 struct _ATOM_PPLIB_STATE v1
;
1344 struct _ATOM_PPLIB_STATE_V2 v2
;
1347 static void sumo_patch_boot_state(struct radeon_device
*rdev
,
1350 struct sumo_power_info
*pi
= sumo_get_pi(rdev
);
1354 ps
->levels
[0] = pi
->boot_pl
;
1357 static void sumo_parse_pplib_non_clock_info(struct radeon_device
*rdev
,
1358 struct radeon_ps
*rps
,
1359 struct _ATOM_PPLIB_NONCLOCK_INFO
*non_clock_info
,
1362 struct sumo_ps
*ps
= sumo_get_ps(rps
);
1364 rps
->caps
= le32_to_cpu(non_clock_info
->ulCapsAndSettings
);
1365 rps
->class = le16_to_cpu(non_clock_info
->usClassification
);
1366 rps
->class2
= le16_to_cpu(non_clock_info
->usClassification2
);
1368 if (ATOM_PPLIB_NONCLOCKINFO_VER1
< table_rev
) {
1369 rps
->vclk
= le32_to_cpu(non_clock_info
->ulVCLK
);
1370 rps
->dclk
= le32_to_cpu(non_clock_info
->ulDCLK
);
1376 if (rps
->class & ATOM_PPLIB_CLASSIFICATION_BOOT
) {
1377 rdev
->pm
.dpm
.boot_ps
= rps
;
1378 sumo_patch_boot_state(rdev
, ps
);
1380 if (rps
->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE
)
1381 rdev
->pm
.dpm
.uvd_ps
= rps
;
1384 static void sumo_parse_pplib_clock_info(struct radeon_device
*rdev
,
1385 struct radeon_ps
*rps
, int index
,
1386 union pplib_clock_info
*clock_info
)
1388 struct sumo_power_info
*pi
= sumo_get_pi(rdev
);
1389 struct sumo_ps
*ps
= sumo_get_ps(rps
);
1390 struct sumo_pl
*pl
= &ps
->levels
[index
];
1393 sclk
= le16_to_cpu(clock_info
->sumo
.usEngineClockLow
);
1394 sclk
|= clock_info
->sumo
.ucEngineClockHigh
<< 16;
1396 pl
->vddc_index
= clock_info
->sumo
.vddcIndex
;
1397 pl
->sclk_dpm_tdp_limit
= clock_info
->sumo
.tdpLimit
;
1399 ps
->num_levels
= index
+ 1;
1401 if (pi
->enable_sclk_ds
) {
1402 pl
->ds_divider_index
= 5;
1403 pl
->ss_divider_index
= 4;
1407 static int sumo_parse_power_table(struct radeon_device
*rdev
)
1409 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
1410 struct _ATOM_PPLIB_NONCLOCK_INFO
*non_clock_info
;
1411 union pplib_power_state
*power_state
;
1412 int i
, j
, k
, non_clock_array_index
, clock_array_index
;
1413 union pplib_clock_info
*clock_info
;
1414 struct _StateArray
*state_array
;
1415 struct _ClockInfoArray
*clock_info_array
;
1416 struct _NonClockInfoArray
*non_clock_info_array
;
1417 union power_info
*power_info
;
1418 int index
= GetIndexIntoMasterTable(DATA
, PowerPlayInfo
);
1421 u8
*power_state_offset
;
1424 if (!atom_parse_data_header(mode_info
->atom_context
, index
, NULL
,
1425 &frev
, &crev
, &data_offset
))
1427 power_info
= (union power_info
*)(mode_info
->atom_context
->bios
+ data_offset
);
1429 state_array
= (struct _StateArray
*)
1430 (mode_info
->atom_context
->bios
+ data_offset
+
1431 le16_to_cpu(power_info
->pplib
.usStateArrayOffset
));
1432 clock_info_array
= (struct _ClockInfoArray
*)
1433 (mode_info
->atom_context
->bios
+ data_offset
+
1434 le16_to_cpu(power_info
->pplib
.usClockInfoArrayOffset
));
1435 non_clock_info_array
= (struct _NonClockInfoArray
*)
1436 (mode_info
->atom_context
->bios
+ data_offset
+
1437 le16_to_cpu(power_info
->pplib
.usNonClockInfoArrayOffset
));
1439 rdev
->pm
.dpm
.ps
= kzalloc(sizeof(struct radeon_ps
) *
1440 state_array
->ucNumEntries
, GFP_KERNEL
);
1441 if (!rdev
->pm
.dpm
.ps
)
1443 power_state_offset
= (u8
*)state_array
->states
;
1444 rdev
->pm
.dpm
.platform_caps
= le32_to_cpu(power_info
->pplib
.ulPlatformCaps
);
1445 rdev
->pm
.dpm
.backbias_response_time
= le16_to_cpu(power_info
->pplib
.usBackbiasTime
);
1446 rdev
->pm
.dpm
.voltage_response_time
= le16_to_cpu(power_info
->pplib
.usVoltageTime
);
1447 for (i
= 0; i
< state_array
->ucNumEntries
; i
++) {
1448 power_state
= (union pplib_power_state
*)power_state_offset
;
1449 non_clock_array_index
= power_state
->v2
.nonClockInfoIndex
;
1450 non_clock_info
= (struct _ATOM_PPLIB_NONCLOCK_INFO
*)
1451 &non_clock_info_array
->nonClockInfo
[non_clock_array_index
];
1452 if (!rdev
->pm
.power_state
[i
].clock_info
)
1454 ps
= kzalloc(sizeof(struct sumo_ps
), GFP_KERNEL
);
1456 kfree(rdev
->pm
.dpm
.ps
);
1459 rdev
->pm
.dpm
.ps
[i
].ps_priv
= ps
;
1461 for (j
= 0; j
< power_state
->v2
.ucNumDPMLevels
; j
++) {
1462 clock_array_index
= power_state
->v2
.clockInfoIndex
[j
];
1463 if (k
>= SUMO_MAX_HARDWARE_POWERLEVELS
)
1465 clock_info
= (union pplib_clock_info
*)
1466 &clock_info_array
->clockInfo
[clock_array_index
* clock_info_array
->ucEntrySize
];
1467 sumo_parse_pplib_clock_info(rdev
,
1468 &rdev
->pm
.dpm
.ps
[i
], k
,
1472 sumo_parse_pplib_non_clock_info(rdev
, &rdev
->pm
.dpm
.ps
[i
],
1474 non_clock_info_array
->ucEntrySize
);
1475 power_state_offset
+= 2 + power_state
->v2
.ucNumDPMLevels
;
1477 rdev
->pm
.dpm
.num_ps
= state_array
->ucNumEntries
;
1481 u32
sumo_convert_vid2_to_vid7(struct radeon_device
*rdev
,
1482 struct sumo_vid_mapping_table
*vid_mapping_table
,
1487 for (i
= 0; i
< vid_mapping_table
->num_entries
; i
++) {
1488 if (vid_mapping_table
->entries
[i
].vid_2bit
== vid_2bit
)
1489 return vid_mapping_table
->entries
[i
].vid_7bit
;
1492 return vid_mapping_table
->entries
[vid_mapping_table
->num_entries
- 1].vid_7bit
;
1495 static u16
sumo_convert_voltage_index_to_value(struct radeon_device
*rdev
,
1498 struct sumo_power_info
*pi
= sumo_get_pi(rdev
);
1499 u32 vid_7bit
= sumo_convert_vid2_to_vid7(rdev
, &pi
->sys_info
.vid_mapping_table
, vid_2bit
);
1501 if (vid_7bit
> 0x7C)
1504 return (15500 - vid_7bit
* 125 + 5) / 10;
1507 static void sumo_construct_display_voltage_mapping_table(struct radeon_device
*rdev
,
1508 struct sumo_disp_clock_voltage_mapping_table
*disp_clk_voltage_mapping_table
,
1509 ATOM_CLK_VOLT_CAPABILITY
*table
)
1513 for (i
= 0; i
< SUMO_MAX_NUMBER_VOLTAGES
; i
++) {
1514 if (table
[i
].ulMaximumSupportedCLK
== 0)
1517 disp_clk_voltage_mapping_table
->display_clock_frequency
[i
] =
1518 table
[i
].ulMaximumSupportedCLK
;
1521 disp_clk_voltage_mapping_table
->num_max_voltage_levels
= i
;
1523 if (disp_clk_voltage_mapping_table
->num_max_voltage_levels
== 0) {
1524 disp_clk_voltage_mapping_table
->display_clock_frequency
[0] = 80000;
1525 disp_clk_voltage_mapping_table
->num_max_voltage_levels
= 1;
1529 void sumo_construct_sclk_voltage_mapping_table(struct radeon_device
*rdev
,
1530 struct sumo_sclk_voltage_mapping_table
*sclk_voltage_mapping_table
,
1531 ATOM_AVAILABLE_SCLK_LIST
*table
)
1537 for (i
= 0; i
< SUMO_MAX_HARDWARE_POWERLEVELS
; i
++) {
1538 if (table
[i
].ulSupportedSCLK
> prev_sclk
) {
1539 sclk_voltage_mapping_table
->entries
[n
].sclk_frequency
=
1540 table
[i
].ulSupportedSCLK
;
1541 sclk_voltage_mapping_table
->entries
[n
].vid_2bit
=
1542 table
[i
].usVoltageIndex
;
1543 prev_sclk
= table
[i
].ulSupportedSCLK
;
1548 sclk_voltage_mapping_table
->num_max_dpm_entries
= n
;
1551 void sumo_construct_vid_mapping_table(struct radeon_device
*rdev
,
1552 struct sumo_vid_mapping_table
*vid_mapping_table
,
1553 ATOM_AVAILABLE_SCLK_LIST
*table
)
1557 for (i
= 0; i
< SUMO_MAX_HARDWARE_POWERLEVELS
; i
++) {
1558 if (table
[i
].ulSupportedSCLK
!= 0) {
1559 vid_mapping_table
->entries
[table
[i
].usVoltageIndex
].vid_7bit
=
1560 table
[i
].usVoltageID
;
1561 vid_mapping_table
->entries
[table
[i
].usVoltageIndex
].vid_2bit
=
1562 table
[i
].usVoltageIndex
;
1566 for (i
= 0; i
< SUMO_MAX_NUMBER_VOLTAGES
; i
++) {
1567 if (vid_mapping_table
->entries
[i
].vid_7bit
== 0) {
1568 for (j
= i
+ 1; j
< SUMO_MAX_NUMBER_VOLTAGES
; j
++) {
1569 if (vid_mapping_table
->entries
[j
].vid_7bit
!= 0) {
1570 vid_mapping_table
->entries
[i
] =
1571 vid_mapping_table
->entries
[j
];
1572 vid_mapping_table
->entries
[j
].vid_7bit
= 0;
1577 if (j
== SUMO_MAX_NUMBER_VOLTAGES
)
1582 vid_mapping_table
->num_entries
= i
;
1586 struct _ATOM_INTEGRATED_SYSTEM_INFO info
;
1587 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2
;
1588 struct _ATOM_INTEGRATED_SYSTEM_INFO_V5 info_5
;
1589 struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 info_6
;
1592 static int sumo_parse_sys_info_table(struct radeon_device
*rdev
)
1594 struct sumo_power_info
*pi
= sumo_get_pi(rdev
);
1595 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
1596 int index
= GetIndexIntoMasterTable(DATA
, IntegratedSystemInfo
);
1597 union igp_info
*igp_info
;
1602 if (atom_parse_data_header(mode_info
->atom_context
, index
, NULL
,
1603 &frev
, &crev
, &data_offset
)) {
1604 igp_info
= (union igp_info
*)(mode_info
->atom_context
->bios
+
1608 DRM_ERROR("Unsupported IGP table: %d %d\n", frev
, crev
);
1611 pi
->sys_info
.bootup_sclk
= le32_to_cpu(igp_info
->info_6
.ulBootUpEngineClock
);
1612 pi
->sys_info
.min_sclk
= le32_to_cpu(igp_info
->info_6
.ulMinEngineClock
);
1613 pi
->sys_info
.bootup_uma_clk
= le32_to_cpu(igp_info
->info_6
.ulBootUpUMAClock
);
1614 pi
->sys_info
.bootup_nb_voltage_index
=
1615 le16_to_cpu(igp_info
->info_6
.usBootUpNBVoltage
);
1616 if (igp_info
->info_6
.ucHtcTmpLmt
== 0)
1617 pi
->sys_info
.htc_tmp_lmt
= 203;
1619 pi
->sys_info
.htc_tmp_lmt
= igp_info
->info_6
.ucHtcTmpLmt
;
1620 if (igp_info
->info_6
.ucHtcHystLmt
== 0)
1621 pi
->sys_info
.htc_hyst_lmt
= 5;
1623 pi
->sys_info
.htc_hyst_lmt
= igp_info
->info_6
.ucHtcHystLmt
;
1624 if (pi
->sys_info
.htc_tmp_lmt
<= pi
->sys_info
.htc_hyst_lmt
) {
1625 DRM_ERROR("The htcTmpLmt should be larger than htcHystLmt.\n");
1627 for (i
= 0; i
< NUMBER_OF_M3ARB_PARAM_SETS
; i
++) {
1628 pi
->sys_info
.csr_m3_arb_cntl_default
[i
] =
1629 le32_to_cpu(igp_info
->info_6
.ulCSR_M3_ARB_CNTL_DEFAULT
[i
]);
1630 pi
->sys_info
.csr_m3_arb_cntl_uvd
[i
] =
1631 le32_to_cpu(igp_info
->info_6
.ulCSR_M3_ARB_CNTL_UVD
[i
]);
1632 pi
->sys_info
.csr_m3_arb_cntl_fs3d
[i
] =
1633 le32_to_cpu(igp_info
->info_6
.ulCSR_M3_ARB_CNTL_FS3D
[i
]);
1635 pi
->sys_info
.sclk_dpm_boost_margin
=
1636 le32_to_cpu(igp_info
->info_6
.SclkDpmBoostMargin
);
1637 pi
->sys_info
.sclk_dpm_throttle_margin
=
1638 le32_to_cpu(igp_info
->info_6
.SclkDpmThrottleMargin
);
1639 pi
->sys_info
.sclk_dpm_tdp_limit_pg
=
1640 le16_to_cpu(igp_info
->info_6
.SclkDpmTdpLimitPG
);
1641 pi
->sys_info
.gnb_tdp_limit
= le16_to_cpu(igp_info
->info_6
.GnbTdpLimit
);
1642 pi
->sys_info
.sclk_dpm_tdp_limit_boost
=
1643 le16_to_cpu(igp_info
->info_6
.SclkDpmTdpLimitBoost
);
1644 pi
->sys_info
.boost_sclk
= le32_to_cpu(igp_info
->info_6
.ulBoostEngineCLock
);
1645 pi
->sys_info
.boost_vid_2bit
= igp_info
->info_6
.ulBoostVid_2bit
;
1646 if (igp_info
->info_6
.EnableBoost
)
1647 pi
->sys_info
.enable_boost
= true;
1649 pi
->sys_info
.enable_boost
= false;
1650 sumo_construct_display_voltage_mapping_table(rdev
,
1651 &pi
->sys_info
.disp_clk_voltage_mapping_table
,
1652 igp_info
->info_6
.sDISPCLK_Voltage
);
1653 sumo_construct_sclk_voltage_mapping_table(rdev
,
1654 &pi
->sys_info
.sclk_voltage_mapping_table
,
1655 igp_info
->info_6
.sAvail_SCLK
);
1656 sumo_construct_vid_mapping_table(rdev
, &pi
->sys_info
.vid_mapping_table
,
1657 igp_info
->info_6
.sAvail_SCLK
);
1663 static void sumo_construct_boot_and_acpi_state(struct radeon_device
*rdev
)
1665 struct sumo_power_info
*pi
= sumo_get_pi(rdev
);
1667 pi
->boot_pl
.sclk
= pi
->sys_info
.bootup_sclk
;
1668 pi
->boot_pl
.vddc_index
= pi
->sys_info
.bootup_nb_voltage_index
;
1669 pi
->boot_pl
.ds_divider_index
= 0;
1670 pi
->boot_pl
.ss_divider_index
= 0;
1671 pi
->boot_pl
.allow_gnb_slow
= 1;
1672 pi
->acpi_pl
= pi
->boot_pl
;
1673 pi
->current_ps
.num_levels
= 1;
1674 pi
->current_ps
.levels
[0] = pi
->boot_pl
;
1677 int sumo_dpm_init(struct radeon_device
*rdev
)
1679 struct sumo_power_info
*pi
;
1680 u32 hw_rev
= (RREG32(HW_REV
) & ATI_REV_ID_MASK
) >> ATI_REV_ID_SHIFT
;
1683 pi
= kzalloc(sizeof(struct sumo_power_info
), GFP_KERNEL
);
1686 rdev
->pm
.dpm
.priv
= pi
;
1688 pi
->driver_nbps_policy_disable
= false;
1689 if ((rdev
->family
== CHIP_PALM
) && (hw_rev
< 3))
1690 pi
->disable_gfx_power_gating_in_uvd
= true;
1692 pi
->disable_gfx_power_gating_in_uvd
= false;
1693 pi
->enable_alt_vddnb
= true;
1694 pi
->enable_sclk_ds
= true;
1695 pi
->enable_dynamic_m3_arbiter
= false;
1696 pi
->enable_dynamic_patch_ps
= true;
1697 pi
->enable_gfx_power_gating
= true;
1698 pi
->enable_gfx_clock_gating
= true;
1699 pi
->enable_mg_clock_gating
= true;
1700 pi
->enable_auto_thermal_throttling
= true;
1702 ret
= sumo_parse_sys_info_table(rdev
);
1706 sumo_construct_boot_and_acpi_state(rdev
);
1708 ret
= sumo_parse_power_table(rdev
);
1712 pi
->pasi
= CYPRESS_HASI_DFLT
;
1713 pi
->asi
= RV770_ASI_DFLT
;
1714 pi
->thermal_auto_throttling
= pi
->sys_info
.htc_tmp_lmt
;
1715 pi
->enable_boost
= pi
->sys_info
.enable_boost
;
1716 pi
->enable_dpm
= true;
1721 void sumo_dpm_print_power_state(struct radeon_device
*rdev
,
1722 struct radeon_ps
*rps
)
1725 struct sumo_ps
*ps
= sumo_get_ps(rps
);
1727 r600_dpm_print_class_info(rps
->class, rps
->class2
);
1728 r600_dpm_print_cap_info(rps
->caps
);
1729 printk("\tuvd vclk: %d dclk: %d\n", rps
->vclk
, rps
->dclk
);
1730 for (i
= 0; i
< ps
->num_levels
; i
++) {
1731 struct sumo_pl
*pl
= &ps
->levels
[i
];
1732 printk("\t\tpower level %d sclk: %u vddc: %u\n",
1734 sumo_convert_voltage_index_to_value(rdev
, pl
->vddc_index
));
1736 r600_dpm_print_ps_status(rdev
, rps
);
1739 void sumo_dpm_fini(struct radeon_device
*rdev
)
1743 sumo_cleanup_asic(rdev
); /* ??? */
1745 for (i
= 0; i
< rdev
->pm
.dpm
.num_ps
; i
++) {
1746 kfree(rdev
->pm
.dpm
.ps
[i
].ps_priv
);
1748 kfree(rdev
->pm
.dpm
.ps
);
1749 kfree(rdev
->pm
.dpm
.priv
);
1752 u32
sumo_dpm_get_sclk(struct radeon_device
*rdev
, bool low
)
1754 struct sumo_ps
*requested_state
= sumo_get_ps(rdev
->pm
.dpm
.requested_ps
);
1757 return requested_state
->levels
[0].sclk
;
1759 return requested_state
->levels
[requested_state
->num_levels
- 1].sclk
;
1762 u32
sumo_dpm_get_mclk(struct radeon_device
*rdev
, bool low
)
1764 struct sumo_power_info
*pi
= sumo_get_pi(rdev
);
1766 return pi
->sys_info
.bootup_uma_clk
;