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drm/radeon/dpm: add pre/post_set_power_state callback (sumo)
[deliverable/linux.git] / drivers / gpu / drm / radeon / sumo_dpm.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #include "drmP.h"
25 #include "radeon.h"
26 #include "sumod.h"
27 #include "r600_dpm.h"
28 #include "cypress_dpm.h"
29 #include "sumo_dpm.h"
30
31 #define SUMO_MAX_DEEPSLEEP_DIVIDER_ID 5
32 #define SUMO_MINIMUM_ENGINE_CLOCK 800
33 #define BOOST_DPM_LEVEL 7
34
35 static const u32 sumo_utc[SUMO_PM_NUMBER_OF_TC] =
36 {
37 SUMO_UTC_DFLT_00,
38 SUMO_UTC_DFLT_01,
39 SUMO_UTC_DFLT_02,
40 SUMO_UTC_DFLT_03,
41 SUMO_UTC_DFLT_04,
42 SUMO_UTC_DFLT_05,
43 SUMO_UTC_DFLT_06,
44 SUMO_UTC_DFLT_07,
45 SUMO_UTC_DFLT_08,
46 SUMO_UTC_DFLT_09,
47 SUMO_UTC_DFLT_10,
48 SUMO_UTC_DFLT_11,
49 SUMO_UTC_DFLT_12,
50 SUMO_UTC_DFLT_13,
51 SUMO_UTC_DFLT_14,
52 };
53
54 static const u32 sumo_dtc[SUMO_PM_NUMBER_OF_TC] =
55 {
56 SUMO_DTC_DFLT_00,
57 SUMO_DTC_DFLT_01,
58 SUMO_DTC_DFLT_02,
59 SUMO_DTC_DFLT_03,
60 SUMO_DTC_DFLT_04,
61 SUMO_DTC_DFLT_05,
62 SUMO_DTC_DFLT_06,
63 SUMO_DTC_DFLT_07,
64 SUMO_DTC_DFLT_08,
65 SUMO_DTC_DFLT_09,
66 SUMO_DTC_DFLT_10,
67 SUMO_DTC_DFLT_11,
68 SUMO_DTC_DFLT_12,
69 SUMO_DTC_DFLT_13,
70 SUMO_DTC_DFLT_14,
71 };
72
73 struct sumo_ps *sumo_get_ps(struct radeon_ps *rps)
74 {
75 struct sumo_ps *ps = rps->ps_priv;
76
77 return ps;
78 }
79
80 struct sumo_power_info *sumo_get_pi(struct radeon_device *rdev)
81 {
82 struct sumo_power_info *pi = rdev->pm.dpm.priv;
83
84 return pi;
85 }
86
87 u32 sumo_get_xclk(struct radeon_device *rdev)
88 {
89 return rdev->clock.spll.reference_freq;
90 }
91
92 static void sumo_gfx_clockgating_enable(struct radeon_device *rdev, bool enable)
93 {
94 if (enable)
95 WREG32_P(SCLK_PWRMGT_CNTL, DYN_GFX_CLK_OFF_EN, ~DYN_GFX_CLK_OFF_EN);
96 else {
97 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN);
98 WREG32_P(SCLK_PWRMGT_CNTL, GFX_CLK_FORCE_ON, ~GFX_CLK_FORCE_ON);
99 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~GFX_CLK_FORCE_ON);
100 RREG32(GB_ADDR_CONFIG);
101 }
102 }
103
104 #define CGCG_CGTT_LOCAL0_MASK 0xE5BFFFFF
105 #define CGCG_CGTT_LOCAL1_MASK 0xEFFF07FF
106
107 static void sumo_mg_clockgating_enable(struct radeon_device *rdev, bool enable)
108 {
109 u32 local0;
110 u32 local1;
111
112 local0 = RREG32(CG_CGTT_LOCAL_0);
113 local1 = RREG32(CG_CGTT_LOCAL_1);
114
115 if (enable) {
116 WREG32(CG_CGTT_LOCAL_0, (0 & CGCG_CGTT_LOCAL0_MASK) | (local0 & ~CGCG_CGTT_LOCAL0_MASK) );
117 WREG32(CG_CGTT_LOCAL_1, (0 & CGCG_CGTT_LOCAL1_MASK) | (local1 & ~CGCG_CGTT_LOCAL1_MASK) );
118 } else {
119 WREG32(CG_CGTT_LOCAL_0, (0xFFFFFFFF & CGCG_CGTT_LOCAL0_MASK) | (local0 & ~CGCG_CGTT_LOCAL0_MASK) );
120 WREG32(CG_CGTT_LOCAL_1, (0xFFFFCFFF & CGCG_CGTT_LOCAL1_MASK) | (local1 & ~CGCG_CGTT_LOCAL1_MASK) );
121 }
122 }
123
124 static void sumo_program_git(struct radeon_device *rdev)
125 {
126 u32 p, u;
127 u32 xclk = sumo_get_xclk(rdev);
128
129 r600_calculate_u_and_p(SUMO_GICST_DFLT,
130 xclk, 16, &p, &u);
131
132 WREG32_P(CG_GIT, CG_GICST(p), ~CG_GICST_MASK);
133 }
134
135 static void sumo_program_grsd(struct radeon_device *rdev)
136 {
137 u32 p, u;
138 u32 xclk = sumo_get_xclk(rdev);
139 u32 grs = 256 * 25 / 100;
140
141 r600_calculate_u_and_p(1, xclk, 14, &p, &u);
142
143 WREG32(CG_GCOOR, PHC(grs) | SDC(p) | SU(u));
144 }
145
146 void sumo_gfx_clockgating_initialize(struct radeon_device *rdev)
147 {
148 sumo_program_git(rdev);
149 sumo_program_grsd(rdev);
150 }
151
152 static void sumo_gfx_powergating_initialize(struct radeon_device *rdev)
153 {
154 u32 rcu_pwr_gating_cntl;
155 u32 p, u;
156 u32 p_c, p_p, d_p;
157 u32 r_t, i_t;
158 u32 xclk = sumo_get_xclk(rdev);
159
160 if (rdev->family == CHIP_PALM) {
161 p_c = 4;
162 d_p = 10;
163 r_t = 10;
164 i_t = 4;
165 p_p = 50 + 1000/200 + 6 * 32;
166 } else {
167 p_c = 16;
168 d_p = 50;
169 r_t = 50;
170 i_t = 50;
171 p_p = 113;
172 }
173
174 WREG32(CG_SCRATCH2, 0x01B60A17);
175
176 r600_calculate_u_and_p(SUMO_GFXPOWERGATINGT_DFLT,
177 xclk, 16, &p, &u);
178
179 WREG32_P(CG_PWR_GATING_CNTL, PGP(p) | PGU(u),
180 ~(PGP_MASK | PGU_MASK));
181
182 r600_calculate_u_and_p(SUMO_VOLTAGEDROPT_DFLT,
183 xclk, 16, &p, &u);
184
185 WREG32_P(CG_CG_VOLTAGE_CNTL, PGP(p) | PGU(u),
186 ~(PGP_MASK | PGU_MASK));
187
188 if (rdev->family == CHIP_PALM) {
189 WREG32_RCU(RCU_PWR_GATING_SEQ0, 0x10103210);
190 WREG32_RCU(RCU_PWR_GATING_SEQ1, 0x10101010);
191 } else {
192 WREG32_RCU(RCU_PWR_GATING_SEQ0, 0x76543210);
193 WREG32_RCU(RCU_PWR_GATING_SEQ1, 0xFEDCBA98);
194 }
195
196 rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL);
197 rcu_pwr_gating_cntl &=
198 ~(RSVD_MASK | PCV_MASK | PGS_MASK);
199 rcu_pwr_gating_cntl |= PCV(p_c) | PGS(1) | PWR_GATING_EN;
200 if (rdev->family == CHIP_PALM) {
201 rcu_pwr_gating_cntl &= ~PCP_MASK;
202 rcu_pwr_gating_cntl |= PCP(0x77);
203 }
204 WREG32_RCU(RCU_PWR_GATING_CNTL, rcu_pwr_gating_cntl);
205
206 rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL_2);
207 rcu_pwr_gating_cntl &= ~(MPPU_MASK | MPPD_MASK);
208 rcu_pwr_gating_cntl |= MPPU(p_p) | MPPD(50);
209 WREG32_RCU(RCU_PWR_GATING_CNTL_2, rcu_pwr_gating_cntl);
210
211 rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL_3);
212 rcu_pwr_gating_cntl &= ~(DPPU_MASK | DPPD_MASK);
213 rcu_pwr_gating_cntl |= DPPU(d_p) | DPPD(50);
214 WREG32_RCU(RCU_PWR_GATING_CNTL_3, rcu_pwr_gating_cntl);
215
216 rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL_4);
217 rcu_pwr_gating_cntl &= ~(RT_MASK | IT_MASK);
218 rcu_pwr_gating_cntl |= RT(r_t) | IT(i_t);
219 WREG32_RCU(RCU_PWR_GATING_CNTL_4, rcu_pwr_gating_cntl);
220
221 if (rdev->family == CHIP_PALM)
222 WREG32_RCU(RCU_PWR_GATING_CNTL_5, 0xA02);
223
224 sumo_smu_pg_init(rdev);
225
226 rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL);
227 rcu_pwr_gating_cntl &=
228 ~(RSVD_MASK | PCV_MASK | PGS_MASK);
229 rcu_pwr_gating_cntl |= PCV(p_c) | PGS(4) | PWR_GATING_EN;
230 if (rdev->family == CHIP_PALM) {
231 rcu_pwr_gating_cntl &= ~PCP_MASK;
232 rcu_pwr_gating_cntl |= PCP(0x77);
233 }
234 WREG32_RCU(RCU_PWR_GATING_CNTL, rcu_pwr_gating_cntl);
235
236 if (rdev->family == CHIP_PALM) {
237 rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL_2);
238 rcu_pwr_gating_cntl &= ~(MPPU_MASK | MPPD_MASK);
239 rcu_pwr_gating_cntl |= MPPU(113) | MPPD(50);
240 WREG32_RCU(RCU_PWR_GATING_CNTL_2, rcu_pwr_gating_cntl);
241
242 rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL_3);
243 rcu_pwr_gating_cntl &= ~(DPPU_MASK | DPPD_MASK);
244 rcu_pwr_gating_cntl |= DPPU(16) | DPPD(50);
245 WREG32_RCU(RCU_PWR_GATING_CNTL_3, rcu_pwr_gating_cntl);
246 }
247
248 sumo_smu_pg_init(rdev);
249
250 rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL);
251 rcu_pwr_gating_cntl &=
252 ~(RSVD_MASK | PCV_MASK | PGS_MASK);
253 rcu_pwr_gating_cntl |= PGS(5) | PWR_GATING_EN;
254
255 if (rdev->family == CHIP_PALM) {
256 rcu_pwr_gating_cntl |= PCV(4);
257 rcu_pwr_gating_cntl &= ~PCP_MASK;
258 rcu_pwr_gating_cntl |= PCP(0x77);
259 } else
260 rcu_pwr_gating_cntl |= PCV(11);
261 WREG32_RCU(RCU_PWR_GATING_CNTL, rcu_pwr_gating_cntl);
262
263 if (rdev->family == CHIP_PALM) {
264 rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL_2);
265 rcu_pwr_gating_cntl &= ~(MPPU_MASK | MPPD_MASK);
266 rcu_pwr_gating_cntl |= MPPU(113) | MPPD(50);
267 WREG32_RCU(RCU_PWR_GATING_CNTL_2, rcu_pwr_gating_cntl);
268
269 rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL_3);
270 rcu_pwr_gating_cntl &= ~(DPPU_MASK | DPPD_MASK);
271 rcu_pwr_gating_cntl |= DPPU(22) | DPPD(50);
272 WREG32_RCU(RCU_PWR_GATING_CNTL_3, rcu_pwr_gating_cntl);
273 }
274
275 sumo_smu_pg_init(rdev);
276 }
277
278 static void sumo_gfx_powergating_enable(struct radeon_device *rdev, bool enable)
279 {
280 if (enable)
281 WREG32_P(CG_PWR_GATING_CNTL, DYN_PWR_DOWN_EN, ~DYN_PWR_DOWN_EN);
282 else {
283 WREG32_P(CG_PWR_GATING_CNTL, 0, ~DYN_PWR_DOWN_EN);
284 RREG32(GB_ADDR_CONFIG);
285 }
286 }
287
288 static int sumo_enable_clock_power_gating(struct radeon_device *rdev)
289 {
290 struct sumo_power_info *pi = sumo_get_pi(rdev);
291
292 if (pi->enable_gfx_clock_gating)
293 sumo_gfx_clockgating_initialize(rdev);
294 if (pi->enable_gfx_power_gating)
295 sumo_gfx_powergating_initialize(rdev);
296 if (pi->enable_mg_clock_gating)
297 sumo_mg_clockgating_enable(rdev, true);
298 if (pi->enable_gfx_clock_gating)
299 sumo_gfx_clockgating_enable(rdev, true);
300 if (pi->enable_gfx_power_gating)
301 sumo_gfx_powergating_enable(rdev, true);
302
303 return 0;
304 }
305
306 static void sumo_disable_clock_power_gating(struct radeon_device *rdev)
307 {
308 struct sumo_power_info *pi = sumo_get_pi(rdev);
309
310 if (pi->enable_gfx_clock_gating)
311 sumo_gfx_clockgating_enable(rdev, false);
312 if (pi->enable_gfx_power_gating)
313 sumo_gfx_powergating_enable(rdev, false);
314 if (pi->enable_mg_clock_gating)
315 sumo_mg_clockgating_enable(rdev, false);
316 }
317
318 static void sumo_calculate_bsp(struct radeon_device *rdev,
319 u32 high_clk)
320 {
321 struct sumo_power_info *pi = sumo_get_pi(rdev);
322 u32 xclk = sumo_get_xclk(rdev);
323
324 pi->pasi = 65535 * 100 / high_clk;
325 pi->asi = 65535 * 100 / high_clk;
326
327 r600_calculate_u_and_p(pi->asi,
328 xclk, 16, &pi->bsp, &pi->bsu);
329
330 r600_calculate_u_and_p(pi->pasi,
331 xclk, 16, &pi->pbsp, &pi->pbsu);
332
333 pi->dsp = BSP(pi->bsp) | BSU(pi->bsu);
334 pi->psp = BSP(pi->pbsp) | BSU(pi->pbsu);
335 }
336
337 static void sumo_init_bsp(struct radeon_device *rdev)
338 {
339 struct sumo_power_info *pi = sumo_get_pi(rdev);
340
341 WREG32(CG_BSP_0, pi->psp);
342 }
343
344
345 static void sumo_program_bsp(struct radeon_device *rdev,
346 struct radeon_ps *rps)
347 {
348 struct sumo_power_info *pi = sumo_get_pi(rdev);
349 struct sumo_ps *ps = sumo_get_ps(rps);
350 u32 i;
351 u32 highest_engine_clock = ps->levels[ps->num_levels - 1].sclk;
352
353 if (ps->flags & SUMO_POWERSTATE_FLAGS_BOOST_STATE)
354 highest_engine_clock = pi->boost_pl.sclk;
355
356 sumo_calculate_bsp(rdev, highest_engine_clock);
357
358 for (i = 0; i < ps->num_levels - 1; i++)
359 WREG32(CG_BSP_0 + (i * 4), pi->dsp);
360
361 WREG32(CG_BSP_0 + (i * 4), pi->psp);
362
363 if (ps->flags & SUMO_POWERSTATE_FLAGS_BOOST_STATE)
364 WREG32(CG_BSP_0 + (BOOST_DPM_LEVEL * 4), pi->psp);
365 }
366
367 static void sumo_write_at(struct radeon_device *rdev,
368 u32 index, u32 value)
369 {
370 if (index == 0)
371 WREG32(CG_AT_0, value);
372 else if (index == 1)
373 WREG32(CG_AT_1, value);
374 else if (index == 2)
375 WREG32(CG_AT_2, value);
376 else if (index == 3)
377 WREG32(CG_AT_3, value);
378 else if (index == 4)
379 WREG32(CG_AT_4, value);
380 else if (index == 5)
381 WREG32(CG_AT_5, value);
382 else if (index == 6)
383 WREG32(CG_AT_6, value);
384 else if (index == 7)
385 WREG32(CG_AT_7, value);
386 }
387
388 static void sumo_program_at(struct radeon_device *rdev,
389 struct radeon_ps *rps)
390 {
391 struct sumo_power_info *pi = sumo_get_pi(rdev);
392 struct sumo_ps *ps = sumo_get_ps(rps);
393 u32 asi;
394 u32 i;
395 u32 m_a;
396 u32 a_t;
397 u32 r[SUMO_MAX_HARDWARE_POWERLEVELS];
398 u32 l[SUMO_MAX_HARDWARE_POWERLEVELS];
399
400 r[0] = SUMO_R_DFLT0;
401 r[1] = SUMO_R_DFLT1;
402 r[2] = SUMO_R_DFLT2;
403 r[3] = SUMO_R_DFLT3;
404 r[4] = SUMO_R_DFLT4;
405
406 l[0] = SUMO_L_DFLT0;
407 l[1] = SUMO_L_DFLT1;
408 l[2] = SUMO_L_DFLT2;
409 l[3] = SUMO_L_DFLT3;
410 l[4] = SUMO_L_DFLT4;
411
412 for (i = 0; i < ps->num_levels; i++) {
413 asi = (i == ps->num_levels - 1) ? pi->pasi : pi->asi;
414
415 m_a = asi * ps->levels[i].sclk / 100;
416
417 a_t = CG_R(m_a * r[i] / 100) | CG_L(m_a * l[i] / 100);
418
419 sumo_write_at(rdev, i, a_t);
420 }
421
422 if (ps->flags & SUMO_POWERSTATE_FLAGS_BOOST_STATE) {
423 asi = pi->pasi;
424
425 m_a = asi * pi->boost_pl.sclk / 100;
426
427 a_t = CG_R(m_a * r[ps->num_levels - 1] / 100) |
428 CG_L(m_a * l[ps->num_levels - 1] / 100);
429
430 sumo_write_at(rdev, BOOST_DPM_LEVEL, a_t);
431 }
432 }
433
434 static void sumo_program_tp(struct radeon_device *rdev)
435 {
436 int i;
437 enum r600_td td = R600_TD_DFLT;
438
439 for (i = 0; i < SUMO_PM_NUMBER_OF_TC; i++) {
440 WREG32_P(CG_FFCT_0 + (i * 4), UTC_0(sumo_utc[i]), ~UTC_0_MASK);
441 WREG32_P(CG_FFCT_0 + (i * 4), DTC_0(sumo_dtc[i]), ~DTC_0_MASK);
442 }
443
444 if (td == R600_TD_AUTO)
445 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL);
446 else
447 WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL);
448
449 if (td == R600_TD_UP)
450 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE);
451
452 if (td == R600_TD_DOWN)
453 WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE);
454 }
455
456 void sumo_program_vc(struct radeon_device *rdev, u32 vrc)
457 {
458 WREG32(CG_FTV, vrc);
459 }
460
461 void sumo_clear_vc(struct radeon_device *rdev)
462 {
463 WREG32(CG_FTV, 0);
464 }
465
466 void sumo_program_sstp(struct radeon_device *rdev)
467 {
468 u32 p, u;
469 u32 xclk = sumo_get_xclk(rdev);
470
471 r600_calculate_u_and_p(SUMO_SST_DFLT,
472 xclk, 16, &p, &u);
473
474 WREG32(CG_SSP, SSTU(u) | SST(p));
475 }
476
477 static void sumo_set_divider_value(struct radeon_device *rdev,
478 u32 index, u32 divider)
479 {
480 u32 reg_index = index / 4;
481 u32 field_index = index % 4;
482
483 if (field_index == 0)
484 WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4),
485 SCLK_FSTATE_0_DIV(divider), ~SCLK_FSTATE_0_DIV_MASK);
486 else if (field_index == 1)
487 WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4),
488 SCLK_FSTATE_1_DIV(divider), ~SCLK_FSTATE_1_DIV_MASK);
489 else if (field_index == 2)
490 WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4),
491 SCLK_FSTATE_2_DIV(divider), ~SCLK_FSTATE_2_DIV_MASK);
492 else if (field_index == 3)
493 WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4),
494 SCLK_FSTATE_3_DIV(divider), ~SCLK_FSTATE_3_DIV_MASK);
495 }
496
497 static void sumo_set_ds_dividers(struct radeon_device *rdev,
498 u32 index, u32 divider)
499 {
500 struct sumo_power_info *pi = sumo_get_pi(rdev);
501
502 if (pi->enable_sclk_ds) {
503 u32 dpm_ctrl = RREG32(CG_SCLK_DPM_CTRL_6);
504
505 dpm_ctrl &= ~(0x7 << (index * 3));
506 dpm_ctrl |= (divider << (index * 3));
507 WREG32(CG_SCLK_DPM_CTRL_6, dpm_ctrl);
508 }
509 }
510
511 static void sumo_set_ss_dividers(struct radeon_device *rdev,
512 u32 index, u32 divider)
513 {
514 struct sumo_power_info *pi = sumo_get_pi(rdev);
515
516 if (pi->enable_sclk_ds) {
517 u32 dpm_ctrl = RREG32(CG_SCLK_DPM_CTRL_11);
518
519 dpm_ctrl &= ~(0x7 << (index * 3));
520 dpm_ctrl |= (divider << (index * 3));
521 WREG32(CG_SCLK_DPM_CTRL_11, dpm_ctrl);
522 }
523 }
524
525 static void sumo_set_vid(struct radeon_device *rdev, u32 index, u32 vid)
526 {
527 u32 voltage_cntl = RREG32(CG_DPM_VOLTAGE_CNTL);
528
529 voltage_cntl &= ~(DPM_STATE0_LEVEL_MASK << (index * 2));
530 voltage_cntl |= (vid << (DPM_STATE0_LEVEL_SHIFT + index * 2));
531 WREG32(CG_DPM_VOLTAGE_CNTL, voltage_cntl);
532 }
533
534 static void sumo_set_allos_gnb_slow(struct radeon_device *rdev, u32 index, u32 gnb_slow)
535 {
536 struct sumo_power_info *pi = sumo_get_pi(rdev);
537 u32 temp = gnb_slow;
538 u32 cg_sclk_dpm_ctrl_3;
539
540 if (pi->driver_nbps_policy_disable)
541 temp = 1;
542
543 cg_sclk_dpm_ctrl_3 = RREG32(CG_SCLK_DPM_CTRL_3);
544 cg_sclk_dpm_ctrl_3 &= ~(GNB_SLOW_FSTATE_0_MASK << index);
545 cg_sclk_dpm_ctrl_3 |= (temp << (GNB_SLOW_FSTATE_0_SHIFT + index));
546
547 WREG32(CG_SCLK_DPM_CTRL_3, cg_sclk_dpm_ctrl_3);
548 }
549
550 static void sumo_program_power_level(struct radeon_device *rdev,
551 struct sumo_pl *pl, u32 index)
552 {
553 struct sumo_power_info *pi = sumo_get_pi(rdev);
554 int ret;
555 struct atom_clock_dividers dividers;
556 u32 ds_en = RREG32(DEEP_SLEEP_CNTL) & ENABLE_DS;
557
558 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
559 pl->sclk, false, &dividers);
560 if (ret)
561 return;
562
563 sumo_set_divider_value(rdev, index, dividers.post_div);
564
565 sumo_set_vid(rdev, index, pl->vddc_index);
566
567 if (pl->ss_divider_index == 0 || pl->ds_divider_index == 0) {
568 if (ds_en)
569 WREG32_P(DEEP_SLEEP_CNTL, 0, ~ENABLE_DS);
570 } else {
571 sumo_set_ss_dividers(rdev, index, pl->ss_divider_index);
572 sumo_set_ds_dividers(rdev, index, pl->ds_divider_index);
573
574 if (!ds_en)
575 WREG32_P(DEEP_SLEEP_CNTL, ENABLE_DS, ~ENABLE_DS);
576 }
577
578 sumo_set_allos_gnb_slow(rdev, index, pl->allow_gnb_slow);
579
580 if (pi->enable_boost)
581 sumo_set_tdp_limit(rdev, index, pl->sclk_dpm_tdp_limit);
582 }
583
584 static void sumo_power_level_enable(struct radeon_device *rdev, u32 index, bool enable)
585 {
586 u32 reg_index = index / 4;
587 u32 field_index = index % 4;
588
589 if (field_index == 0)
590 WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4),
591 enable ? SCLK_FSTATE_0_VLD : 0, ~SCLK_FSTATE_0_VLD);
592 else if (field_index == 1)
593 WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4),
594 enable ? SCLK_FSTATE_1_VLD : 0, ~SCLK_FSTATE_1_VLD);
595 else if (field_index == 2)
596 WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4),
597 enable ? SCLK_FSTATE_2_VLD : 0, ~SCLK_FSTATE_2_VLD);
598 else if (field_index == 3)
599 WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4),
600 enable ? SCLK_FSTATE_3_VLD : 0, ~SCLK_FSTATE_3_VLD);
601 }
602
603 static bool sumo_dpm_enabled(struct radeon_device *rdev)
604 {
605 if (RREG32(CG_SCLK_DPM_CTRL_3) & DPM_SCLK_ENABLE)
606 return true;
607 else
608 return false;
609 }
610
611 static void sumo_start_dpm(struct radeon_device *rdev)
612 {
613 WREG32_P(CG_SCLK_DPM_CTRL_3, DPM_SCLK_ENABLE, ~DPM_SCLK_ENABLE);
614 }
615
616 static void sumo_stop_dpm(struct radeon_device *rdev)
617 {
618 WREG32_P(CG_SCLK_DPM_CTRL_3, 0, ~DPM_SCLK_ENABLE);
619 }
620
621 static void sumo_set_forced_mode(struct radeon_device *rdev, bool enable)
622 {
623 if (enable)
624 WREG32_P(CG_SCLK_DPM_CTRL_3, FORCE_SCLK_STATE_EN, ~FORCE_SCLK_STATE_EN);
625 else
626 WREG32_P(CG_SCLK_DPM_CTRL_3, 0, ~FORCE_SCLK_STATE_EN);
627 }
628
629 static void sumo_set_forced_mode_enabled(struct radeon_device *rdev)
630 {
631 int i;
632
633 sumo_set_forced_mode(rdev, true);
634 for (i = 0; i < rdev->usec_timeout; i++) {
635 if (RREG32(CG_SCLK_STATUS) & SCLK_OVERCLK_DETECT)
636 break;
637 udelay(1);
638 }
639 }
640
641 static void sumo_wait_for_level_0(struct radeon_device *rdev)
642 {
643 int i;
644
645 for (i = 0; i < rdev->usec_timeout; i++) {
646 if ((RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURR_SCLK_INDEX_MASK) == 0)
647 break;
648 udelay(1);
649 }
650 for (i = 0; i < rdev->usec_timeout; i++) {
651 if ((RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURR_INDEX_MASK) == 0)
652 break;
653 udelay(1);
654 }
655 }
656
657 static void sumo_set_forced_mode_disabled(struct radeon_device *rdev)
658 {
659 sumo_set_forced_mode(rdev, false);
660 }
661
662 static void sumo_enable_power_level_0(struct radeon_device *rdev)
663 {
664 sumo_power_level_enable(rdev, 0, true);
665 }
666
667 static void sumo_patch_boost_state(struct radeon_device *rdev,
668 struct radeon_ps *rps)
669 {
670 struct sumo_power_info *pi = sumo_get_pi(rdev);
671 struct sumo_ps *new_ps = sumo_get_ps(rps);
672
673 if (new_ps->flags & SUMO_POWERSTATE_FLAGS_BOOST_STATE) {
674 pi->boost_pl = new_ps->levels[new_ps->num_levels - 1];
675 pi->boost_pl.sclk = pi->sys_info.boost_sclk;
676 pi->boost_pl.vddc_index = pi->sys_info.boost_vid_2bit;
677 pi->boost_pl.sclk_dpm_tdp_limit = pi->sys_info.sclk_dpm_tdp_limit_boost;
678 }
679 }
680
681 static void sumo_pre_notify_alt_vddnb_change(struct radeon_device *rdev,
682 struct radeon_ps *new_rps,
683 struct radeon_ps *old_rps)
684 {
685 struct sumo_ps *new_ps = sumo_get_ps(new_rps);
686 struct sumo_ps *old_ps = sumo_get_ps(old_rps);
687 u32 nbps1_old = 0;
688 u32 nbps1_new = 0;
689
690 if (old_ps != NULL)
691 nbps1_old = (old_ps->flags & SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE) ? 1 : 0;
692
693 nbps1_new = (new_ps->flags & SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE) ? 1 : 0;
694
695 if (nbps1_old == 1 && nbps1_new == 0)
696 sumo_smu_notify_alt_vddnb_change(rdev, 0, 0);
697 }
698
699 static void sumo_post_notify_alt_vddnb_change(struct radeon_device *rdev,
700 struct radeon_ps *new_rps,
701 struct radeon_ps *old_rps)
702 {
703 struct sumo_ps *new_ps = sumo_get_ps(new_rps);
704 struct sumo_ps *old_ps = sumo_get_ps(old_rps);
705 u32 nbps1_old = 0;
706 u32 nbps1_new = 0;
707
708 if (old_ps != NULL)
709 nbps1_old = (old_ps->flags & SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE)? 1 : 0;
710
711 nbps1_new = (new_ps->flags & SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE)? 1 : 0;
712
713 if (nbps1_old == 0 && nbps1_new == 1)
714 sumo_smu_notify_alt_vddnb_change(rdev, 1, 1);
715 }
716
717 static void sumo_enable_boost(struct radeon_device *rdev,
718 struct radeon_ps *rps,
719 bool enable)
720 {
721 struct sumo_ps *new_ps = sumo_get_ps(rps);
722
723 if (enable) {
724 if (new_ps->flags & SUMO_POWERSTATE_FLAGS_BOOST_STATE)
725 sumo_boost_state_enable(rdev, true);
726 } else
727 sumo_boost_state_enable(rdev, false);
728 }
729
730 static void sumo_set_forced_level(struct radeon_device *rdev, u32 index)
731 {
732 WREG32_P(CG_SCLK_DPM_CTRL_3, FORCE_SCLK_STATE(index), ~FORCE_SCLK_STATE_MASK);
733 }
734
735 static void sumo_set_forced_level_0(struct radeon_device *rdev)
736 {
737 sumo_set_forced_level(rdev, 0);
738 }
739
740 static void sumo_program_wl(struct radeon_device *rdev,
741 struct radeon_ps *rps)
742 {
743 struct sumo_ps *new_ps = sumo_get_ps(rps);
744 u32 dpm_ctrl4 = RREG32(CG_SCLK_DPM_CTRL_4);
745
746 dpm_ctrl4 &= 0xFFFFFF00;
747 dpm_ctrl4 |= (1 << (new_ps->num_levels - 1));
748
749 if (new_ps->flags & SUMO_POWERSTATE_FLAGS_BOOST_STATE)
750 dpm_ctrl4 |= (1 << BOOST_DPM_LEVEL);
751
752 WREG32(CG_SCLK_DPM_CTRL_4, dpm_ctrl4);
753 }
754
755 static void sumo_program_power_levels_0_to_n(struct radeon_device *rdev,
756 struct radeon_ps *new_rps,
757 struct radeon_ps *old_rps)
758 {
759 struct sumo_power_info *pi = sumo_get_pi(rdev);
760 struct sumo_ps *new_ps = sumo_get_ps(new_rps);
761 struct sumo_ps *old_ps = sumo_get_ps(old_rps);
762 u32 i;
763 u32 n_current_state_levels = (old_ps == NULL) ? 1 : old_ps->num_levels;
764
765 for (i = 0; i < new_ps->num_levels; i++) {
766 sumo_program_power_level(rdev, &new_ps->levels[i], i);
767 sumo_power_level_enable(rdev, i, true);
768 }
769
770 for (i = new_ps->num_levels; i < n_current_state_levels; i++)
771 sumo_power_level_enable(rdev, i, false);
772
773 if (new_ps->flags & SUMO_POWERSTATE_FLAGS_BOOST_STATE)
774 sumo_program_power_level(rdev, &pi->boost_pl, BOOST_DPM_LEVEL);
775 }
776
777 static void sumo_enable_acpi_pm(struct radeon_device *rdev)
778 {
779 WREG32_P(GENERAL_PWRMGT, STATIC_PM_EN, ~STATIC_PM_EN);
780 }
781
782 static void sumo_program_power_level_enter_state(struct radeon_device *rdev)
783 {
784 WREG32_P(CG_SCLK_DPM_CTRL_5, SCLK_FSTATE_BOOTUP(0), ~SCLK_FSTATE_BOOTUP_MASK);
785 }
786
787 static void sumo_program_acpi_power_level(struct radeon_device *rdev)
788 {
789 struct sumo_power_info *pi = sumo_get_pi(rdev);
790 struct atom_clock_dividers dividers;
791 int ret;
792
793 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
794 pi->acpi_pl.sclk,
795 false, &dividers);
796 if (ret)
797 return;
798
799 WREG32_P(CG_ACPI_CNTL, SCLK_ACPI_DIV(dividers.post_div), ~SCLK_ACPI_DIV_MASK);
800 WREG32_P(CG_ACPI_VOLTAGE_CNTL, 0, ~ACPI_VOLTAGE_EN);
801 }
802
803 static void sumo_program_bootup_state(struct radeon_device *rdev)
804 {
805 struct sumo_power_info *pi = sumo_get_pi(rdev);
806 u32 dpm_ctrl4 = RREG32(CG_SCLK_DPM_CTRL_4);
807 u32 i;
808
809 sumo_program_power_level(rdev, &pi->boot_pl, 0);
810
811 dpm_ctrl4 &= 0xFFFFFF00;
812 WREG32(CG_SCLK_DPM_CTRL_4, dpm_ctrl4);
813
814 for (i = 1; i < 8; i++)
815 sumo_power_level_enable(rdev, i, false);
816 }
817
818 static void sumo_set_uvd_clock_before_set_eng_clock(struct radeon_device *rdev,
819 struct radeon_ps *new_rps,
820 struct radeon_ps *old_rps)
821 {
822 struct sumo_ps *new_ps = sumo_get_ps(new_rps);
823 struct sumo_ps *current_ps = sumo_get_ps(old_rps);
824
825 if ((new_rps->vclk == old_rps->vclk) &&
826 (new_rps->dclk == old_rps->dclk))
827 return;
828
829 if (new_ps->levels[new_ps->num_levels - 1].sclk >=
830 current_ps->levels[current_ps->num_levels - 1].sclk)
831 return;
832
833 radeon_set_uvd_clocks(rdev, new_rps->vclk, new_rps->dclk);
834 }
835
836 static void sumo_set_uvd_clock_after_set_eng_clock(struct radeon_device *rdev,
837 struct radeon_ps *new_rps,
838 struct radeon_ps *old_rps)
839 {
840 struct sumo_ps *new_ps = sumo_get_ps(new_rps);
841 struct sumo_ps *current_ps = sumo_get_ps(old_rps);
842
843 if ((new_rps->vclk == old_rps->vclk) &&
844 (new_rps->dclk == old_rps->dclk))
845 return;
846
847 if (new_ps->levels[new_ps->num_levels - 1].sclk <
848 current_ps->levels[current_ps->num_levels - 1].sclk)
849 return;
850
851 radeon_set_uvd_clocks(rdev, new_rps->vclk, new_rps->dclk);
852 }
853
854 void sumo_take_smu_control(struct radeon_device *rdev, bool enable)
855 {
856 /* This bit selects who handles display phy powergating.
857 * Clear the bit to let atom handle it.
858 * Set it to let the driver handle it.
859 * For now we just let atom handle it.
860 */
861 #if 0
862 u32 v = RREG32(DOUT_SCRATCH3);
863
864 if (enable)
865 v |= 0x4;
866 else
867 v &= 0xFFFFFFFB;
868
869 WREG32(DOUT_SCRATCH3, v);
870 #endif
871 }
872
873 static void sumo_enable_sclk_ds(struct radeon_device *rdev, bool enable)
874 {
875 if (enable) {
876 u32 deep_sleep_cntl = RREG32(DEEP_SLEEP_CNTL);
877 u32 deep_sleep_cntl2 = RREG32(DEEP_SLEEP_CNTL2);
878 u32 t = 1;
879
880 deep_sleep_cntl &= ~R_DIS;
881 deep_sleep_cntl &= ~HS_MASK;
882 deep_sleep_cntl |= HS(t > 4095 ? 4095 : t);
883
884 deep_sleep_cntl2 |= LB_UFP_EN;
885 deep_sleep_cntl2 &= INOUT_C_MASK;
886 deep_sleep_cntl2 |= INOUT_C(0xf);
887
888 WREG32(DEEP_SLEEP_CNTL2, deep_sleep_cntl2);
889 WREG32(DEEP_SLEEP_CNTL, deep_sleep_cntl);
890 } else
891 WREG32_P(DEEP_SLEEP_CNTL, 0, ~ENABLE_DS);
892 }
893
894 static void sumo_program_bootup_at(struct radeon_device *rdev)
895 {
896 WREG32_P(CG_AT_0, CG_R(0xffff), ~CG_R_MASK);
897 WREG32_P(CG_AT_0, CG_L(0), ~CG_L_MASK);
898 }
899
900 static void sumo_reset_am(struct radeon_device *rdev)
901 {
902 WREG32_P(SCLK_PWRMGT_CNTL, FIR_RESET, ~FIR_RESET);
903 }
904
905 static void sumo_start_am(struct radeon_device *rdev)
906 {
907 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_RESET);
908 }
909
910 static void sumo_program_ttp(struct radeon_device *rdev)
911 {
912 u32 xclk = sumo_get_xclk(rdev);
913 u32 p, u;
914 u32 cg_sclk_dpm_ctrl_5 = RREG32(CG_SCLK_DPM_CTRL_5);
915
916 r600_calculate_u_and_p(1000,
917 xclk, 16, &p, &u);
918
919 cg_sclk_dpm_ctrl_5 &= ~(TT_TP_MASK | TT_TU_MASK);
920 cg_sclk_dpm_ctrl_5 |= TT_TP(p) | TT_TU(u);
921
922 WREG32(CG_SCLK_DPM_CTRL_5, cg_sclk_dpm_ctrl_5);
923 }
924
925 static void sumo_program_ttt(struct radeon_device *rdev)
926 {
927 u32 cg_sclk_dpm_ctrl_3 = RREG32(CG_SCLK_DPM_CTRL_3);
928 struct sumo_power_info *pi = sumo_get_pi(rdev);
929
930 cg_sclk_dpm_ctrl_3 &= ~(GNB_TT_MASK | GNB_THERMTHRO_MASK);
931 cg_sclk_dpm_ctrl_3 |= GNB_TT(pi->thermal_auto_throttling + 49);
932
933 WREG32(CG_SCLK_DPM_CTRL_3, cg_sclk_dpm_ctrl_3);
934 }
935
936
937 static void sumo_enable_voltage_scaling(struct radeon_device *rdev, bool enable)
938 {
939 if (enable) {
940 WREG32_P(CG_DPM_VOLTAGE_CNTL, DPM_VOLTAGE_EN, ~DPM_VOLTAGE_EN);
941 WREG32_P(CG_CG_VOLTAGE_CNTL, 0, ~CG_VOLTAGE_EN);
942 } else {
943 WREG32_P(CG_CG_VOLTAGE_CNTL, CG_VOLTAGE_EN, ~CG_VOLTAGE_EN);
944 WREG32_P(CG_DPM_VOLTAGE_CNTL, 0, ~DPM_VOLTAGE_EN);
945 }
946 }
947
948 static void sumo_override_cnb_thermal_events(struct radeon_device *rdev)
949 {
950 WREG32_P(CG_SCLK_DPM_CTRL_3, CNB_THERMTHRO_MASK_SCLK,
951 ~CNB_THERMTHRO_MASK_SCLK);
952 }
953
954 static void sumo_program_dc_hto(struct radeon_device *rdev)
955 {
956 u32 cg_sclk_dpm_ctrl_4 = RREG32(CG_SCLK_DPM_CTRL_4);
957 u32 p, u;
958 u32 xclk = sumo_get_xclk(rdev);
959
960 r600_calculate_u_and_p(100000,
961 xclk, 14, &p, &u);
962
963 cg_sclk_dpm_ctrl_4 &= ~(DC_HDC_MASK | DC_HU_MASK);
964 cg_sclk_dpm_ctrl_4 |= DC_HDC(p) | DC_HU(u);
965
966 WREG32(CG_SCLK_DPM_CTRL_4, cg_sclk_dpm_ctrl_4);
967 }
968
969 static void sumo_force_nbp_state(struct radeon_device *rdev,
970 struct radeon_ps *rps)
971 {
972 struct sumo_power_info *pi = sumo_get_pi(rdev);
973 struct sumo_ps *new_ps = sumo_get_ps(rps);
974
975 if (!pi->driver_nbps_policy_disable) {
976 if (new_ps->flags & SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE)
977 WREG32_P(CG_SCLK_DPM_CTRL_3, FORCE_NB_PSTATE_1, ~FORCE_NB_PSTATE_1);
978 else
979 WREG32_P(CG_SCLK_DPM_CTRL_3, 0, ~FORCE_NB_PSTATE_1);
980 }
981 }
982
983 u32 sumo_get_sleep_divider_from_id(u32 id)
984 {
985 return 1 << id;
986 }
987
988 u32 sumo_get_sleep_divider_id_from_clock(struct radeon_device *rdev,
989 u32 sclk,
990 u32 min_sclk_in_sr)
991 {
992 struct sumo_power_info *pi = sumo_get_pi(rdev);
993 u32 i;
994 u32 temp;
995 u32 min = (min_sclk_in_sr > SUMO_MINIMUM_ENGINE_CLOCK) ?
996 min_sclk_in_sr : SUMO_MINIMUM_ENGINE_CLOCK;
997
998 if (sclk < min)
999 return 0;
1000
1001 if (!pi->enable_sclk_ds)
1002 return 0;
1003
1004 for (i = SUMO_MAX_DEEPSLEEP_DIVIDER_ID; ; i--) {
1005 temp = sclk / sumo_get_sleep_divider_from_id(i);
1006
1007 if (temp >= min || i == 0)
1008 break;
1009 }
1010 return i;
1011 }
1012
1013 static u32 sumo_get_valid_engine_clock(struct radeon_device *rdev,
1014 u32 lower_limit)
1015 {
1016 struct sumo_power_info *pi = sumo_get_pi(rdev);
1017 u32 i;
1018
1019 for (i = 0; i < pi->sys_info.sclk_voltage_mapping_table.num_max_dpm_entries; i++) {
1020 if (pi->sys_info.sclk_voltage_mapping_table.entries[i].sclk_frequency >= lower_limit)
1021 return pi->sys_info.sclk_voltage_mapping_table.entries[i].sclk_frequency;
1022 }
1023
1024 return pi->sys_info.sclk_voltage_mapping_table.entries[pi->sys_info.sclk_voltage_mapping_table.num_max_dpm_entries - 1].sclk_frequency;
1025 }
1026
1027 static void sumo_patch_thermal_state(struct radeon_device *rdev,
1028 struct sumo_ps *ps,
1029 struct sumo_ps *current_ps)
1030 {
1031 struct sumo_power_info *pi = sumo_get_pi(rdev);
1032 u32 sclk_in_sr = pi->sys_info.min_sclk; /* ??? */
1033 u32 current_vddc;
1034 u32 current_sclk;
1035 u32 current_index = 0;
1036
1037 if (current_ps) {
1038 current_vddc = current_ps->levels[current_index].vddc_index;
1039 current_sclk = current_ps->levels[current_index].sclk;
1040 } else {
1041 current_vddc = pi->boot_pl.vddc_index;
1042 current_sclk = pi->boot_pl.sclk;
1043 }
1044
1045 ps->levels[0].vddc_index = current_vddc;
1046
1047 if (ps->levels[0].sclk > current_sclk)
1048 ps->levels[0].sclk = current_sclk;
1049
1050 ps->levels[0].ss_divider_index =
1051 sumo_get_sleep_divider_id_from_clock(rdev, ps->levels[0].sclk, sclk_in_sr);
1052
1053 ps->levels[0].ds_divider_index =
1054 sumo_get_sleep_divider_id_from_clock(rdev, ps->levels[0].sclk, SUMO_MINIMUM_ENGINE_CLOCK);
1055
1056 if (ps->levels[0].ds_divider_index > ps->levels[0].ss_divider_index + 1)
1057 ps->levels[0].ds_divider_index = ps->levels[0].ss_divider_index + 1;
1058
1059 if (ps->levels[0].ss_divider_index == ps->levels[0].ds_divider_index) {
1060 if (ps->levels[0].ss_divider_index > 1)
1061 ps->levels[0].ss_divider_index = ps->levels[0].ss_divider_index - 1;
1062 }
1063
1064 if (ps->levels[0].ss_divider_index == 0)
1065 ps->levels[0].ds_divider_index = 0;
1066
1067 if (ps->levels[0].ds_divider_index == 0)
1068 ps->levels[0].ss_divider_index = 0;
1069 }
1070
1071 static void sumo_apply_state_adjust_rules(struct radeon_device *rdev,
1072 struct radeon_ps *new_rps,
1073 struct radeon_ps *old_rps)
1074 {
1075 struct sumo_ps *ps = sumo_get_ps(new_rps);
1076 struct sumo_ps *current_ps = sumo_get_ps(old_rps);
1077 struct sumo_power_info *pi = sumo_get_pi(rdev);
1078 u32 min_voltage = 0; /* ??? */
1079 u32 min_sclk = pi->sys_info.min_sclk; /* XXX check against disp reqs */
1080 u32 sclk_in_sr = pi->sys_info.min_sclk; /* ??? */
1081 u32 i;
1082
1083 if (new_rps->class & ATOM_PPLIB_CLASSIFICATION_THERMAL)
1084 return sumo_patch_thermal_state(rdev, ps, current_ps);
1085
1086 if (pi->enable_boost) {
1087 if (new_rps->class & ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE)
1088 ps->flags |= SUMO_POWERSTATE_FLAGS_BOOST_STATE;
1089 }
1090
1091 if ((new_rps->class & ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) ||
1092 (new_rps->class & ATOM_PPLIB_CLASSIFICATION_SDSTATE) ||
1093 (new_rps->class & ATOM_PPLIB_CLASSIFICATION_HDSTATE))
1094 ps->flags |= SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE;
1095
1096 for (i = 0; i < ps->num_levels; i++) {
1097 if (ps->levels[i].vddc_index < min_voltage)
1098 ps->levels[i].vddc_index = min_voltage;
1099
1100 if (ps->levels[i].sclk < min_sclk)
1101 ps->levels[i].sclk =
1102 sumo_get_valid_engine_clock(rdev, min_sclk);
1103
1104 ps->levels[i].ss_divider_index =
1105 sumo_get_sleep_divider_id_from_clock(rdev, ps->levels[i].sclk, sclk_in_sr);
1106
1107 ps->levels[i].ds_divider_index =
1108 sumo_get_sleep_divider_id_from_clock(rdev, ps->levels[i].sclk, SUMO_MINIMUM_ENGINE_CLOCK);
1109
1110 if (ps->levels[i].ds_divider_index > ps->levels[i].ss_divider_index + 1)
1111 ps->levels[i].ds_divider_index = ps->levels[i].ss_divider_index + 1;
1112
1113 if (ps->levels[i].ss_divider_index == ps->levels[i].ds_divider_index) {
1114 if (ps->levels[i].ss_divider_index > 1)
1115 ps->levels[i].ss_divider_index = ps->levels[i].ss_divider_index - 1;
1116 }
1117
1118 if (ps->levels[i].ss_divider_index == 0)
1119 ps->levels[i].ds_divider_index = 0;
1120
1121 if (ps->levels[i].ds_divider_index == 0)
1122 ps->levels[i].ss_divider_index = 0;
1123
1124 if (ps->flags & SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE)
1125 ps->levels[i].allow_gnb_slow = 1;
1126 else if ((new_rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE) ||
1127 (new_rps->class2 & ATOM_PPLIB_CLASSIFICATION2_MVC))
1128 ps->levels[i].allow_gnb_slow = 0;
1129 else if (i == ps->num_levels - 1)
1130 ps->levels[i].allow_gnb_slow = 0;
1131 else
1132 ps->levels[i].allow_gnb_slow = 1;
1133 }
1134 }
1135
1136 static void sumo_cleanup_asic(struct radeon_device *rdev)
1137 {
1138 sumo_take_smu_control(rdev, false);
1139 }
1140
1141 static void sumo_uvd_init(struct radeon_device *rdev)
1142 {
1143 u32 tmp;
1144
1145 tmp = RREG32(CG_VCLK_CNTL);
1146 tmp &= ~VCLK_DIR_CNTL_EN;
1147 WREG32(CG_VCLK_CNTL, tmp);
1148
1149 tmp = RREG32(CG_DCLK_CNTL);
1150 tmp &= ~DCLK_DIR_CNTL_EN;
1151 WREG32(CG_DCLK_CNTL, tmp);
1152
1153 /* 100 Mhz */
1154 radeon_set_uvd_clocks(rdev, 10000, 10000);
1155 }
1156
1157 static int sumo_set_thermal_temperature_range(struct radeon_device *rdev,
1158 int min_temp, int max_temp)
1159 {
1160 int low_temp = 0 * 1000;
1161 int high_temp = 255 * 1000;
1162
1163 if (low_temp < min_temp)
1164 low_temp = min_temp;
1165 if (high_temp > max_temp)
1166 high_temp = max_temp;
1167 if (high_temp < low_temp) {
1168 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp);
1169 return -EINVAL;
1170 }
1171
1172 WREG32_P(CG_THERMAL_INT, DIG_THERM_INTH(49 + (high_temp / 1000)), ~DIG_THERM_INTH_MASK);
1173 WREG32_P(CG_THERMAL_INT, DIG_THERM_INTL(49 + (low_temp / 1000)), ~DIG_THERM_INTL_MASK);
1174
1175 rdev->pm.dpm.thermal.min_temp = low_temp;
1176 rdev->pm.dpm.thermal.max_temp = high_temp;
1177
1178 return 0;
1179 }
1180
1181 static void sumo_update_current_ps(struct radeon_device *rdev,
1182 struct radeon_ps *rps)
1183 {
1184 struct sumo_ps *new_ps = sumo_get_ps(rps);
1185 struct sumo_power_info *pi = sumo_get_pi(rdev);
1186
1187 pi->current_rps = *rps;
1188 pi->current_ps = *new_ps;
1189 pi->current_rps.ps_priv = &pi->current_ps;
1190 }
1191
1192 static void sumo_update_requested_ps(struct radeon_device *rdev,
1193 struct radeon_ps *rps)
1194 {
1195 struct sumo_ps *new_ps = sumo_get_ps(rps);
1196 struct sumo_power_info *pi = sumo_get_pi(rdev);
1197
1198 pi->requested_rps = *rps;
1199 pi->requested_ps = *new_ps;
1200 pi->requested_rps.ps_priv = &pi->requested_ps;
1201 }
1202
1203 int sumo_dpm_enable(struct radeon_device *rdev)
1204 {
1205 struct sumo_power_info *pi = sumo_get_pi(rdev);
1206
1207 if (sumo_dpm_enabled(rdev))
1208 return -EINVAL;
1209
1210 sumo_enable_clock_power_gating(rdev);
1211 sumo_program_bootup_state(rdev);
1212 sumo_init_bsp(rdev);
1213 sumo_reset_am(rdev);
1214 sumo_program_tp(rdev);
1215 sumo_program_bootup_at(rdev);
1216 sumo_start_am(rdev);
1217 if (pi->enable_auto_thermal_throttling) {
1218 sumo_program_ttp(rdev);
1219 sumo_program_ttt(rdev);
1220 }
1221 sumo_program_dc_hto(rdev);
1222 sumo_program_power_level_enter_state(rdev);
1223 sumo_enable_voltage_scaling(rdev, true);
1224 sumo_program_sstp(rdev);
1225 sumo_program_vc(rdev, SUMO_VRC_DFLT);
1226 sumo_override_cnb_thermal_events(rdev);
1227 sumo_start_dpm(rdev);
1228 sumo_wait_for_level_0(rdev);
1229 if (pi->enable_sclk_ds)
1230 sumo_enable_sclk_ds(rdev, true);
1231 if (pi->enable_boost)
1232 sumo_enable_boost_timer(rdev);
1233
1234 if (rdev->irq.installed &&
1235 r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) {
1236 sumo_set_thermal_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
1237 rdev->irq.dpm_thermal = true;
1238 radeon_irq_set(rdev);
1239 }
1240
1241 sumo_update_current_ps(rdev, rdev->pm.dpm.boot_ps);
1242
1243 return 0;
1244 }
1245
1246 void sumo_dpm_disable(struct radeon_device *rdev)
1247 {
1248 struct sumo_power_info *pi = sumo_get_pi(rdev);
1249
1250 if (!sumo_dpm_enabled(rdev))
1251 return;
1252 sumo_disable_clock_power_gating(rdev);
1253 if (pi->enable_sclk_ds)
1254 sumo_enable_sclk_ds(rdev, false);
1255 sumo_clear_vc(rdev);
1256 sumo_wait_for_level_0(rdev);
1257 sumo_stop_dpm(rdev);
1258 sumo_enable_voltage_scaling(rdev, false);
1259
1260 if (rdev->irq.installed &&
1261 r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) {
1262 rdev->irq.dpm_thermal = false;
1263 radeon_irq_set(rdev);
1264 }
1265
1266 sumo_update_current_ps(rdev, rdev->pm.dpm.boot_ps);
1267 }
1268
1269 int sumo_dpm_pre_set_power_state(struct radeon_device *rdev)
1270 {
1271 struct sumo_power_info *pi = sumo_get_pi(rdev);
1272 struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps;
1273 struct radeon_ps *new_ps = &requested_ps;
1274
1275 sumo_update_requested_ps(rdev, new_ps);
1276
1277 if (pi->enable_dynamic_patch_ps)
1278 sumo_apply_state_adjust_rules(rdev,
1279 &pi->requested_rps,
1280 &pi->current_rps);
1281
1282 return 0;
1283 }
1284
1285 int sumo_dpm_set_power_state(struct radeon_device *rdev)
1286 {
1287 struct sumo_power_info *pi = sumo_get_pi(rdev);
1288 struct radeon_ps *new_ps = &pi->requested_rps;
1289 struct radeon_ps *old_ps = &pi->current_rps;
1290
1291 if (pi->enable_dpm)
1292 sumo_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps);
1293 if (pi->enable_boost) {
1294 sumo_enable_boost(rdev, new_ps, false);
1295 sumo_patch_boost_state(rdev, new_ps);
1296 }
1297 if (pi->enable_dpm) {
1298 sumo_pre_notify_alt_vddnb_change(rdev, new_ps, old_ps);
1299 sumo_enable_power_level_0(rdev);
1300 sumo_set_forced_level_0(rdev);
1301 sumo_set_forced_mode_enabled(rdev);
1302 sumo_wait_for_level_0(rdev);
1303 sumo_program_power_levels_0_to_n(rdev, new_ps, old_ps);
1304 sumo_program_wl(rdev, new_ps);
1305 sumo_program_bsp(rdev, new_ps);
1306 sumo_program_at(rdev, new_ps);
1307 sumo_force_nbp_state(rdev, new_ps);
1308 sumo_set_forced_mode_disabled(rdev);
1309 sumo_set_forced_mode_enabled(rdev);
1310 sumo_set_forced_mode_disabled(rdev);
1311 sumo_post_notify_alt_vddnb_change(rdev, new_ps, old_ps);
1312 }
1313 if (pi->enable_boost)
1314 sumo_enable_boost(rdev, new_ps, true);
1315 if (pi->enable_dpm)
1316 sumo_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps);
1317
1318 return 0;
1319 }
1320
1321 void sumo_dpm_post_set_power_state(struct radeon_device *rdev)
1322 {
1323 struct sumo_power_info *pi = sumo_get_pi(rdev);
1324 struct radeon_ps *new_ps = &pi->requested_rps;
1325
1326 sumo_update_current_ps(rdev, new_ps);
1327 }
1328
1329 void sumo_dpm_reset_asic(struct radeon_device *rdev)
1330 {
1331 sumo_program_bootup_state(rdev);
1332 sumo_enable_power_level_0(rdev);
1333 sumo_set_forced_level_0(rdev);
1334 sumo_set_forced_mode_enabled(rdev);
1335 sumo_wait_for_level_0(rdev);
1336 sumo_set_forced_mode_disabled(rdev);
1337 sumo_set_forced_mode_enabled(rdev);
1338 sumo_set_forced_mode_disabled(rdev);
1339 }
1340
1341 void sumo_dpm_setup_asic(struct radeon_device *rdev)
1342 {
1343 struct sumo_power_info *pi = sumo_get_pi(rdev);
1344
1345 sumo_initialize_m3_arb(rdev);
1346 pi->fw_version = sumo_get_running_fw_version(rdev);
1347 DRM_INFO("Found smc ucode version: 0x%08x\n", pi->fw_version);
1348 sumo_program_acpi_power_level(rdev);
1349 sumo_enable_acpi_pm(rdev);
1350 sumo_take_smu_control(rdev, true);
1351 sumo_uvd_init(rdev);
1352 }
1353
1354 void sumo_dpm_display_configuration_changed(struct radeon_device *rdev)
1355 {
1356
1357 }
1358
1359 union power_info {
1360 struct _ATOM_POWERPLAY_INFO info;
1361 struct _ATOM_POWERPLAY_INFO_V2 info_2;
1362 struct _ATOM_POWERPLAY_INFO_V3 info_3;
1363 struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
1364 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
1365 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
1366 };
1367
1368 union pplib_clock_info {
1369 struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
1370 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
1371 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
1372 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
1373 };
1374
1375 union pplib_power_state {
1376 struct _ATOM_PPLIB_STATE v1;
1377 struct _ATOM_PPLIB_STATE_V2 v2;
1378 };
1379
1380 static void sumo_patch_boot_state(struct radeon_device *rdev,
1381 struct sumo_ps *ps)
1382 {
1383 struct sumo_power_info *pi = sumo_get_pi(rdev);
1384
1385 ps->num_levels = 1;
1386 ps->flags = 0;
1387 ps->levels[0] = pi->boot_pl;
1388 }
1389
1390 static void sumo_parse_pplib_non_clock_info(struct radeon_device *rdev,
1391 struct radeon_ps *rps,
1392 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info,
1393 u8 table_rev)
1394 {
1395 struct sumo_ps *ps = sumo_get_ps(rps);
1396
1397 rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);
1398 rps->class = le16_to_cpu(non_clock_info->usClassification);
1399 rps->class2 = le16_to_cpu(non_clock_info->usClassification2);
1400
1401 if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {
1402 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
1403 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
1404 } else {
1405 rps->vclk = 0;
1406 rps->dclk = 0;
1407 }
1408
1409 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {
1410 rdev->pm.dpm.boot_ps = rps;
1411 sumo_patch_boot_state(rdev, ps);
1412 }
1413 if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
1414 rdev->pm.dpm.uvd_ps = rps;
1415 }
1416
1417 static void sumo_parse_pplib_clock_info(struct radeon_device *rdev,
1418 struct radeon_ps *rps, int index,
1419 union pplib_clock_info *clock_info)
1420 {
1421 struct sumo_power_info *pi = sumo_get_pi(rdev);
1422 struct sumo_ps *ps = sumo_get_ps(rps);
1423 struct sumo_pl *pl = &ps->levels[index];
1424 u32 sclk;
1425
1426 sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow);
1427 sclk |= clock_info->sumo.ucEngineClockHigh << 16;
1428 pl->sclk = sclk;
1429 pl->vddc_index = clock_info->sumo.vddcIndex;
1430 pl->sclk_dpm_tdp_limit = clock_info->sumo.tdpLimit;
1431
1432 ps->num_levels = index + 1;
1433
1434 if (pi->enable_sclk_ds) {
1435 pl->ds_divider_index = 5;
1436 pl->ss_divider_index = 4;
1437 }
1438 }
1439
1440 static int sumo_parse_power_table(struct radeon_device *rdev)
1441 {
1442 struct radeon_mode_info *mode_info = &rdev->mode_info;
1443 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
1444 union pplib_power_state *power_state;
1445 int i, j, k, non_clock_array_index, clock_array_index;
1446 union pplib_clock_info *clock_info;
1447 struct _StateArray *state_array;
1448 struct _ClockInfoArray *clock_info_array;
1449 struct _NonClockInfoArray *non_clock_info_array;
1450 union power_info *power_info;
1451 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
1452 u16 data_offset;
1453 u8 frev, crev;
1454 u8 *power_state_offset;
1455 struct sumo_ps *ps;
1456
1457 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
1458 &frev, &crev, &data_offset))
1459 return -EINVAL;
1460 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
1461
1462 state_array = (struct _StateArray *)
1463 (mode_info->atom_context->bios + data_offset +
1464 le16_to_cpu(power_info->pplib.usStateArrayOffset));
1465 clock_info_array = (struct _ClockInfoArray *)
1466 (mode_info->atom_context->bios + data_offset +
1467 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
1468 non_clock_info_array = (struct _NonClockInfoArray *)
1469 (mode_info->atom_context->bios + data_offset +
1470 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
1471
1472 rdev->pm.dpm.ps = kzalloc(sizeof(struct radeon_ps) *
1473 state_array->ucNumEntries, GFP_KERNEL);
1474 if (!rdev->pm.dpm.ps)
1475 return -ENOMEM;
1476 power_state_offset = (u8 *)state_array->states;
1477 rdev->pm.dpm.platform_caps = le32_to_cpu(power_info->pplib.ulPlatformCaps);
1478 rdev->pm.dpm.backbias_response_time = le16_to_cpu(power_info->pplib.usBackbiasTime);
1479 rdev->pm.dpm.voltage_response_time = le16_to_cpu(power_info->pplib.usVoltageTime);
1480 for (i = 0; i < state_array->ucNumEntries; i++) {
1481 power_state = (union pplib_power_state *)power_state_offset;
1482 non_clock_array_index = power_state->v2.nonClockInfoIndex;
1483 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
1484 &non_clock_info_array->nonClockInfo[non_clock_array_index];
1485 if (!rdev->pm.power_state[i].clock_info)
1486 return -EINVAL;
1487 ps = kzalloc(sizeof(struct sumo_ps), GFP_KERNEL);
1488 if (ps == NULL) {
1489 kfree(rdev->pm.dpm.ps);
1490 return -ENOMEM;
1491 }
1492 rdev->pm.dpm.ps[i].ps_priv = ps;
1493 k = 0;
1494 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
1495 clock_array_index = power_state->v2.clockInfoIndex[j];
1496 if (k >= SUMO_MAX_HARDWARE_POWERLEVELS)
1497 break;
1498 clock_info = (union pplib_clock_info *)
1499 &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize];
1500 sumo_parse_pplib_clock_info(rdev,
1501 &rdev->pm.dpm.ps[i], k,
1502 clock_info);
1503 k++;
1504 }
1505 sumo_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i],
1506 non_clock_info,
1507 non_clock_info_array->ucEntrySize);
1508 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
1509 }
1510 rdev->pm.dpm.num_ps = state_array->ucNumEntries;
1511 return 0;
1512 }
1513
1514 u32 sumo_convert_vid2_to_vid7(struct radeon_device *rdev,
1515 struct sumo_vid_mapping_table *vid_mapping_table,
1516 u32 vid_2bit)
1517 {
1518 u32 i;
1519
1520 for (i = 0; i < vid_mapping_table->num_entries; i++) {
1521 if (vid_mapping_table->entries[i].vid_2bit == vid_2bit)
1522 return vid_mapping_table->entries[i].vid_7bit;
1523 }
1524
1525 return vid_mapping_table->entries[vid_mapping_table->num_entries - 1].vid_7bit;
1526 }
1527
1528 static u16 sumo_convert_voltage_index_to_value(struct radeon_device *rdev,
1529 u32 vid_2bit)
1530 {
1531 struct sumo_power_info *pi = sumo_get_pi(rdev);
1532 u32 vid_7bit = sumo_convert_vid2_to_vid7(rdev, &pi->sys_info.vid_mapping_table, vid_2bit);
1533
1534 if (vid_7bit > 0x7C)
1535 return 0;
1536
1537 return (15500 - vid_7bit * 125 + 5) / 10;
1538 }
1539
1540 static void sumo_construct_display_voltage_mapping_table(struct radeon_device *rdev,
1541 struct sumo_disp_clock_voltage_mapping_table *disp_clk_voltage_mapping_table,
1542 ATOM_CLK_VOLT_CAPABILITY *table)
1543 {
1544 u32 i;
1545
1546 for (i = 0; i < SUMO_MAX_NUMBER_VOLTAGES; i++) {
1547 if (table[i].ulMaximumSupportedCLK == 0)
1548 break;
1549
1550 disp_clk_voltage_mapping_table->display_clock_frequency[i] =
1551 table[i].ulMaximumSupportedCLK;
1552 }
1553
1554 disp_clk_voltage_mapping_table->num_max_voltage_levels = i;
1555
1556 if (disp_clk_voltage_mapping_table->num_max_voltage_levels == 0) {
1557 disp_clk_voltage_mapping_table->display_clock_frequency[0] = 80000;
1558 disp_clk_voltage_mapping_table->num_max_voltage_levels = 1;
1559 }
1560 }
1561
1562 void sumo_construct_sclk_voltage_mapping_table(struct radeon_device *rdev,
1563 struct sumo_sclk_voltage_mapping_table *sclk_voltage_mapping_table,
1564 ATOM_AVAILABLE_SCLK_LIST *table)
1565 {
1566 u32 i;
1567 u32 n = 0;
1568 u32 prev_sclk = 0;
1569
1570 for (i = 0; i < SUMO_MAX_HARDWARE_POWERLEVELS; i++) {
1571 if (table[i].ulSupportedSCLK > prev_sclk) {
1572 sclk_voltage_mapping_table->entries[n].sclk_frequency =
1573 table[i].ulSupportedSCLK;
1574 sclk_voltage_mapping_table->entries[n].vid_2bit =
1575 table[i].usVoltageIndex;
1576 prev_sclk = table[i].ulSupportedSCLK;
1577 n++;
1578 }
1579 }
1580
1581 sclk_voltage_mapping_table->num_max_dpm_entries = n;
1582 }
1583
1584 void sumo_construct_vid_mapping_table(struct radeon_device *rdev,
1585 struct sumo_vid_mapping_table *vid_mapping_table,
1586 ATOM_AVAILABLE_SCLK_LIST *table)
1587 {
1588 u32 i, j;
1589
1590 for (i = 0; i < SUMO_MAX_HARDWARE_POWERLEVELS; i++) {
1591 if (table[i].ulSupportedSCLK != 0) {
1592 vid_mapping_table->entries[table[i].usVoltageIndex].vid_7bit =
1593 table[i].usVoltageID;
1594 vid_mapping_table->entries[table[i].usVoltageIndex].vid_2bit =
1595 table[i].usVoltageIndex;
1596 }
1597 }
1598
1599 for (i = 0; i < SUMO_MAX_NUMBER_VOLTAGES; i++) {
1600 if (vid_mapping_table->entries[i].vid_7bit == 0) {
1601 for (j = i + 1; j < SUMO_MAX_NUMBER_VOLTAGES; j++) {
1602 if (vid_mapping_table->entries[j].vid_7bit != 0) {
1603 vid_mapping_table->entries[i] =
1604 vid_mapping_table->entries[j];
1605 vid_mapping_table->entries[j].vid_7bit = 0;
1606 break;
1607 }
1608 }
1609
1610 if (j == SUMO_MAX_NUMBER_VOLTAGES)
1611 break;
1612 }
1613 }
1614
1615 vid_mapping_table->num_entries = i;
1616 }
1617
1618 union igp_info {
1619 struct _ATOM_INTEGRATED_SYSTEM_INFO info;
1620 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
1621 struct _ATOM_INTEGRATED_SYSTEM_INFO_V5 info_5;
1622 struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 info_6;
1623 };
1624
1625 static int sumo_parse_sys_info_table(struct radeon_device *rdev)
1626 {
1627 struct sumo_power_info *pi = sumo_get_pi(rdev);
1628 struct radeon_mode_info *mode_info = &rdev->mode_info;
1629 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1630 union igp_info *igp_info;
1631 u8 frev, crev;
1632 u16 data_offset;
1633 int i;
1634
1635 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1636 &frev, &crev, &data_offset)) {
1637 igp_info = (union igp_info *)(mode_info->atom_context->bios +
1638 data_offset);
1639
1640 if (crev != 6) {
1641 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
1642 return -EINVAL;
1643 }
1644 pi->sys_info.bootup_sclk = le32_to_cpu(igp_info->info_6.ulBootUpEngineClock);
1645 pi->sys_info.min_sclk = le32_to_cpu(igp_info->info_6.ulMinEngineClock);
1646 pi->sys_info.bootup_uma_clk = le32_to_cpu(igp_info->info_6.ulBootUpUMAClock);
1647 pi->sys_info.bootup_nb_voltage_index =
1648 le16_to_cpu(igp_info->info_6.usBootUpNBVoltage);
1649 if (igp_info->info_6.ucHtcTmpLmt == 0)
1650 pi->sys_info.htc_tmp_lmt = 203;
1651 else
1652 pi->sys_info.htc_tmp_lmt = igp_info->info_6.ucHtcTmpLmt;
1653 if (igp_info->info_6.ucHtcHystLmt == 0)
1654 pi->sys_info.htc_hyst_lmt = 5;
1655 else
1656 pi->sys_info.htc_hyst_lmt = igp_info->info_6.ucHtcHystLmt;
1657 if (pi->sys_info.htc_tmp_lmt <= pi->sys_info.htc_hyst_lmt) {
1658 DRM_ERROR("The htcTmpLmt should be larger than htcHystLmt.\n");
1659 }
1660 for (i = 0; i < NUMBER_OF_M3ARB_PARAM_SETS; i++) {
1661 pi->sys_info.csr_m3_arb_cntl_default[i] =
1662 le32_to_cpu(igp_info->info_6.ulCSR_M3_ARB_CNTL_DEFAULT[i]);
1663 pi->sys_info.csr_m3_arb_cntl_uvd[i] =
1664 le32_to_cpu(igp_info->info_6.ulCSR_M3_ARB_CNTL_UVD[i]);
1665 pi->sys_info.csr_m3_arb_cntl_fs3d[i] =
1666 le32_to_cpu(igp_info->info_6.ulCSR_M3_ARB_CNTL_FS3D[i]);
1667 }
1668 pi->sys_info.sclk_dpm_boost_margin =
1669 le32_to_cpu(igp_info->info_6.SclkDpmBoostMargin);
1670 pi->sys_info.sclk_dpm_throttle_margin =
1671 le32_to_cpu(igp_info->info_6.SclkDpmThrottleMargin);
1672 pi->sys_info.sclk_dpm_tdp_limit_pg =
1673 le16_to_cpu(igp_info->info_6.SclkDpmTdpLimitPG);
1674 pi->sys_info.gnb_tdp_limit = le16_to_cpu(igp_info->info_6.GnbTdpLimit);
1675 pi->sys_info.sclk_dpm_tdp_limit_boost =
1676 le16_to_cpu(igp_info->info_6.SclkDpmTdpLimitBoost);
1677 pi->sys_info.boost_sclk = le32_to_cpu(igp_info->info_6.ulBoostEngineCLock);
1678 pi->sys_info.boost_vid_2bit = igp_info->info_6.ulBoostVid_2bit;
1679 if (igp_info->info_6.EnableBoost)
1680 pi->sys_info.enable_boost = true;
1681 else
1682 pi->sys_info.enable_boost = false;
1683 sumo_construct_display_voltage_mapping_table(rdev,
1684 &pi->sys_info.disp_clk_voltage_mapping_table,
1685 igp_info->info_6.sDISPCLK_Voltage);
1686 sumo_construct_sclk_voltage_mapping_table(rdev,
1687 &pi->sys_info.sclk_voltage_mapping_table,
1688 igp_info->info_6.sAvail_SCLK);
1689 sumo_construct_vid_mapping_table(rdev, &pi->sys_info.vid_mapping_table,
1690 igp_info->info_6.sAvail_SCLK);
1691
1692 }
1693 return 0;
1694 }
1695
1696 static void sumo_construct_boot_and_acpi_state(struct radeon_device *rdev)
1697 {
1698 struct sumo_power_info *pi = sumo_get_pi(rdev);
1699
1700 pi->boot_pl.sclk = pi->sys_info.bootup_sclk;
1701 pi->boot_pl.vddc_index = pi->sys_info.bootup_nb_voltage_index;
1702 pi->boot_pl.ds_divider_index = 0;
1703 pi->boot_pl.ss_divider_index = 0;
1704 pi->boot_pl.allow_gnb_slow = 1;
1705 pi->acpi_pl = pi->boot_pl;
1706 pi->current_ps.num_levels = 1;
1707 pi->current_ps.levels[0] = pi->boot_pl;
1708 }
1709
1710 int sumo_dpm_init(struct radeon_device *rdev)
1711 {
1712 struct sumo_power_info *pi;
1713 u32 hw_rev = (RREG32(HW_REV) & ATI_REV_ID_MASK) >> ATI_REV_ID_SHIFT;
1714 int ret;
1715
1716 pi = kzalloc(sizeof(struct sumo_power_info), GFP_KERNEL);
1717 if (pi == NULL)
1718 return -ENOMEM;
1719 rdev->pm.dpm.priv = pi;
1720
1721 pi->driver_nbps_policy_disable = false;
1722 if ((rdev->family == CHIP_PALM) && (hw_rev < 3))
1723 pi->disable_gfx_power_gating_in_uvd = true;
1724 else
1725 pi->disable_gfx_power_gating_in_uvd = false;
1726 pi->enable_alt_vddnb = true;
1727 pi->enable_sclk_ds = true;
1728 pi->enable_dynamic_m3_arbiter = false;
1729 pi->enable_dynamic_patch_ps = true;
1730 pi->enable_gfx_power_gating = true;
1731 pi->enable_gfx_clock_gating = true;
1732 pi->enable_mg_clock_gating = true;
1733 pi->enable_auto_thermal_throttling = true;
1734
1735 ret = sumo_parse_sys_info_table(rdev);
1736 if (ret)
1737 return ret;
1738
1739 sumo_construct_boot_and_acpi_state(rdev);
1740
1741 ret = sumo_parse_power_table(rdev);
1742 if (ret)
1743 return ret;
1744
1745 pi->pasi = CYPRESS_HASI_DFLT;
1746 pi->asi = RV770_ASI_DFLT;
1747 pi->thermal_auto_throttling = pi->sys_info.htc_tmp_lmt;
1748 pi->enable_boost = pi->sys_info.enable_boost;
1749 pi->enable_dpm = true;
1750
1751 return 0;
1752 }
1753
1754 void sumo_dpm_print_power_state(struct radeon_device *rdev,
1755 struct radeon_ps *rps)
1756 {
1757 int i;
1758 struct sumo_ps *ps = sumo_get_ps(rps);
1759
1760 r600_dpm_print_class_info(rps->class, rps->class2);
1761 r600_dpm_print_cap_info(rps->caps);
1762 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
1763 for (i = 0; i < ps->num_levels; i++) {
1764 struct sumo_pl *pl = &ps->levels[i];
1765 printk("\t\tpower level %d sclk: %u vddc: %u\n",
1766 i, pl->sclk,
1767 sumo_convert_voltage_index_to_value(rdev, pl->vddc_index));
1768 }
1769 r600_dpm_print_ps_status(rdev, rps);
1770 }
1771
1772 void sumo_dpm_fini(struct radeon_device *rdev)
1773 {
1774 int i;
1775
1776 sumo_cleanup_asic(rdev); /* ??? */
1777
1778 for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
1779 kfree(rdev->pm.dpm.ps[i].ps_priv);
1780 }
1781 kfree(rdev->pm.dpm.ps);
1782 kfree(rdev->pm.dpm.priv);
1783 }
1784
1785 u32 sumo_dpm_get_sclk(struct radeon_device *rdev, bool low)
1786 {
1787 struct sumo_power_info *pi = sumo_get_pi(rdev);
1788 struct sumo_ps *requested_state = sumo_get_ps(&pi->requested_rps);
1789
1790 if (low)
1791 return requested_state->levels[0].sclk;
1792 else
1793 return requested_state->levels[requested_state->num_levels - 1].sclk;
1794 }
1795
1796 u32 sumo_dpm_get_mclk(struct radeon_device *rdev, bool low)
1797 {
1798 struct sumo_power_info *pi = sumo_get_pi(rdev);
1799
1800 return pi->sys_info.bootup_uma_clk;
1801 }
Linux kernel - Deliverables
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