2 * Copyright 2012 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
28 #include "cypress_dpm.h"
32 #define SUMO_MAX_DEEPSLEEP_DIVIDER_ID 5
33 #define SUMO_MINIMUM_ENGINE_CLOCK 800
34 #define BOOST_DPM_LEVEL 7
36 static const u32 sumo_utc
[SUMO_PM_NUMBER_OF_TC
] =
55 static const u32 sumo_dtc
[SUMO_PM_NUMBER_OF_TC
] =
74 struct sumo_ps
*sumo_get_ps(struct radeon_ps
*rps
)
76 struct sumo_ps
*ps
= rps
->ps_priv
;
81 struct sumo_power_info
*sumo_get_pi(struct radeon_device
*rdev
)
83 struct sumo_power_info
*pi
= rdev
->pm
.dpm
.priv
;
88 u32
sumo_get_xclk(struct radeon_device
*rdev
)
90 return rdev
->clock
.spll
.reference_freq
;
93 static void sumo_gfx_clockgating_enable(struct radeon_device
*rdev
, bool enable
)
96 WREG32_P(SCLK_PWRMGT_CNTL
, DYN_GFX_CLK_OFF_EN
, ~DYN_GFX_CLK_OFF_EN
);
98 WREG32_P(SCLK_PWRMGT_CNTL
, 0, ~DYN_GFX_CLK_OFF_EN
);
99 WREG32_P(SCLK_PWRMGT_CNTL
, GFX_CLK_FORCE_ON
, ~GFX_CLK_FORCE_ON
);
100 WREG32_P(SCLK_PWRMGT_CNTL
, 0, ~GFX_CLK_FORCE_ON
);
101 RREG32(GB_ADDR_CONFIG
);
105 #define CGCG_CGTT_LOCAL0_MASK 0xE5BFFFFF
106 #define CGCG_CGTT_LOCAL1_MASK 0xEFFF07FF
108 static void sumo_mg_clockgating_enable(struct radeon_device
*rdev
, bool enable
)
113 local0
= RREG32(CG_CGTT_LOCAL_0
);
114 local1
= RREG32(CG_CGTT_LOCAL_1
);
117 WREG32(CG_CGTT_LOCAL_0
, (0 & CGCG_CGTT_LOCAL0_MASK
) | (local0
& ~CGCG_CGTT_LOCAL0_MASK
) );
118 WREG32(CG_CGTT_LOCAL_1
, (0 & CGCG_CGTT_LOCAL1_MASK
) | (local1
& ~CGCG_CGTT_LOCAL1_MASK
) );
120 WREG32(CG_CGTT_LOCAL_0
, (0xFFFFFFFF & CGCG_CGTT_LOCAL0_MASK
) | (local0
& ~CGCG_CGTT_LOCAL0_MASK
) );
121 WREG32(CG_CGTT_LOCAL_1
, (0xFFFFCFFF & CGCG_CGTT_LOCAL1_MASK
) | (local1
& ~CGCG_CGTT_LOCAL1_MASK
) );
125 static void sumo_program_git(struct radeon_device
*rdev
)
128 u32 xclk
= sumo_get_xclk(rdev
);
130 r600_calculate_u_and_p(SUMO_GICST_DFLT
,
133 WREG32_P(CG_GIT
, CG_GICST(p
), ~CG_GICST_MASK
);
136 static void sumo_program_grsd(struct radeon_device
*rdev
)
139 u32 xclk
= sumo_get_xclk(rdev
);
140 u32 grs
= 256 * 25 / 100;
142 r600_calculate_u_and_p(1, xclk
, 14, &p
, &u
);
144 WREG32(CG_GCOOR
, PHC(grs
) | SDC(p
) | SU(u
));
147 static void sumo_gfx_clockgating_initialize(struct radeon_device
*rdev
)
149 sumo_program_git(rdev
);
150 sumo_program_grsd(rdev
);
153 static void sumo_gfx_powergating_initialize(struct radeon_device
*rdev
)
155 u32 rcu_pwr_gating_cntl
;
159 u32 xclk
= sumo_get_xclk(rdev
);
161 if (rdev
->family
== CHIP_PALM
) {
166 p_p
= 50 + 1000/200 + 6 * 32;
175 WREG32(CG_SCRATCH2
, 0x01B60A17);
177 r600_calculate_u_and_p(SUMO_GFXPOWERGATINGT_DFLT
,
180 WREG32_P(CG_PWR_GATING_CNTL
, PGP(p
) | PGU(u
),
181 ~(PGP_MASK
| PGU_MASK
));
183 r600_calculate_u_and_p(SUMO_VOLTAGEDROPT_DFLT
,
186 WREG32_P(CG_CG_VOLTAGE_CNTL
, PGP(p
) | PGU(u
),
187 ~(PGP_MASK
| PGU_MASK
));
189 if (rdev
->family
== CHIP_PALM
) {
190 WREG32_RCU(RCU_PWR_GATING_SEQ0
, 0x10103210);
191 WREG32_RCU(RCU_PWR_GATING_SEQ1
, 0x10101010);
193 WREG32_RCU(RCU_PWR_GATING_SEQ0
, 0x76543210);
194 WREG32_RCU(RCU_PWR_GATING_SEQ1
, 0xFEDCBA98);
197 rcu_pwr_gating_cntl
= RREG32_RCU(RCU_PWR_GATING_CNTL
);
198 rcu_pwr_gating_cntl
&=
199 ~(RSVD_MASK
| PCV_MASK
| PGS_MASK
);
200 rcu_pwr_gating_cntl
|= PCV(p_c
) | PGS(1) | PWR_GATING_EN
;
201 if (rdev
->family
== CHIP_PALM
) {
202 rcu_pwr_gating_cntl
&= ~PCP_MASK
;
203 rcu_pwr_gating_cntl
|= PCP(0x77);
205 WREG32_RCU(RCU_PWR_GATING_CNTL
, rcu_pwr_gating_cntl
);
207 rcu_pwr_gating_cntl
= RREG32_RCU(RCU_PWR_GATING_CNTL_2
);
208 rcu_pwr_gating_cntl
&= ~(MPPU_MASK
| MPPD_MASK
);
209 rcu_pwr_gating_cntl
|= MPPU(p_p
) | MPPD(50);
210 WREG32_RCU(RCU_PWR_GATING_CNTL_2
, rcu_pwr_gating_cntl
);
212 rcu_pwr_gating_cntl
= RREG32_RCU(RCU_PWR_GATING_CNTL_3
);
213 rcu_pwr_gating_cntl
&= ~(DPPU_MASK
| DPPD_MASK
);
214 rcu_pwr_gating_cntl
|= DPPU(d_p
) | DPPD(50);
215 WREG32_RCU(RCU_PWR_GATING_CNTL_3
, rcu_pwr_gating_cntl
);
217 rcu_pwr_gating_cntl
= RREG32_RCU(RCU_PWR_GATING_CNTL_4
);
218 rcu_pwr_gating_cntl
&= ~(RT_MASK
| IT_MASK
);
219 rcu_pwr_gating_cntl
|= RT(r_t
) | IT(i_t
);
220 WREG32_RCU(RCU_PWR_GATING_CNTL_4
, rcu_pwr_gating_cntl
);
222 if (rdev
->family
== CHIP_PALM
)
223 WREG32_RCU(RCU_PWR_GATING_CNTL_5
, 0xA02);
225 sumo_smu_pg_init(rdev
);
227 rcu_pwr_gating_cntl
= RREG32_RCU(RCU_PWR_GATING_CNTL
);
228 rcu_pwr_gating_cntl
&=
229 ~(RSVD_MASK
| PCV_MASK
| PGS_MASK
);
230 rcu_pwr_gating_cntl
|= PCV(p_c
) | PGS(4) | PWR_GATING_EN
;
231 if (rdev
->family
== CHIP_PALM
) {
232 rcu_pwr_gating_cntl
&= ~PCP_MASK
;
233 rcu_pwr_gating_cntl
|= PCP(0x77);
235 WREG32_RCU(RCU_PWR_GATING_CNTL
, rcu_pwr_gating_cntl
);
237 if (rdev
->family
== CHIP_PALM
) {
238 rcu_pwr_gating_cntl
= RREG32_RCU(RCU_PWR_GATING_CNTL_2
);
239 rcu_pwr_gating_cntl
&= ~(MPPU_MASK
| MPPD_MASK
);
240 rcu_pwr_gating_cntl
|= MPPU(113) | MPPD(50);
241 WREG32_RCU(RCU_PWR_GATING_CNTL_2
, rcu_pwr_gating_cntl
);
243 rcu_pwr_gating_cntl
= RREG32_RCU(RCU_PWR_GATING_CNTL_3
);
244 rcu_pwr_gating_cntl
&= ~(DPPU_MASK
| DPPD_MASK
);
245 rcu_pwr_gating_cntl
|= DPPU(16) | DPPD(50);
246 WREG32_RCU(RCU_PWR_GATING_CNTL_3
, rcu_pwr_gating_cntl
);
249 sumo_smu_pg_init(rdev
);
251 rcu_pwr_gating_cntl
= RREG32_RCU(RCU_PWR_GATING_CNTL
);
252 rcu_pwr_gating_cntl
&=
253 ~(RSVD_MASK
| PCV_MASK
| PGS_MASK
);
254 rcu_pwr_gating_cntl
|= PGS(5) | PWR_GATING_EN
;
256 if (rdev
->family
== CHIP_PALM
) {
257 rcu_pwr_gating_cntl
|= PCV(4);
258 rcu_pwr_gating_cntl
&= ~PCP_MASK
;
259 rcu_pwr_gating_cntl
|= PCP(0x77);
261 rcu_pwr_gating_cntl
|= PCV(11);
262 WREG32_RCU(RCU_PWR_GATING_CNTL
, rcu_pwr_gating_cntl
);
264 if (rdev
->family
== CHIP_PALM
) {
265 rcu_pwr_gating_cntl
= RREG32_RCU(RCU_PWR_GATING_CNTL_2
);
266 rcu_pwr_gating_cntl
&= ~(MPPU_MASK
| MPPD_MASK
);
267 rcu_pwr_gating_cntl
|= MPPU(113) | MPPD(50);
268 WREG32_RCU(RCU_PWR_GATING_CNTL_2
, rcu_pwr_gating_cntl
);
270 rcu_pwr_gating_cntl
= RREG32_RCU(RCU_PWR_GATING_CNTL_3
);
271 rcu_pwr_gating_cntl
&= ~(DPPU_MASK
| DPPD_MASK
);
272 rcu_pwr_gating_cntl
|= DPPU(22) | DPPD(50);
273 WREG32_RCU(RCU_PWR_GATING_CNTL_3
, rcu_pwr_gating_cntl
);
276 sumo_smu_pg_init(rdev
);
279 static void sumo_gfx_powergating_enable(struct radeon_device
*rdev
, bool enable
)
282 WREG32_P(CG_PWR_GATING_CNTL
, DYN_PWR_DOWN_EN
, ~DYN_PWR_DOWN_EN
);
284 WREG32_P(CG_PWR_GATING_CNTL
, 0, ~DYN_PWR_DOWN_EN
);
285 RREG32(GB_ADDR_CONFIG
);
289 static int sumo_enable_clock_power_gating(struct radeon_device
*rdev
)
291 struct sumo_power_info
*pi
= sumo_get_pi(rdev
);
293 if (pi
->enable_gfx_clock_gating
)
294 sumo_gfx_clockgating_initialize(rdev
);
295 if (pi
->enable_gfx_power_gating
)
296 sumo_gfx_powergating_initialize(rdev
);
297 if (pi
->enable_mg_clock_gating
)
298 sumo_mg_clockgating_enable(rdev
, true);
299 if (pi
->enable_gfx_clock_gating
)
300 sumo_gfx_clockgating_enable(rdev
, true);
301 if (pi
->enable_gfx_power_gating
)
302 sumo_gfx_powergating_enable(rdev
, true);
307 static void sumo_disable_clock_power_gating(struct radeon_device
*rdev
)
309 struct sumo_power_info
*pi
= sumo_get_pi(rdev
);
311 if (pi
->enable_gfx_clock_gating
)
312 sumo_gfx_clockgating_enable(rdev
, false);
313 if (pi
->enable_gfx_power_gating
)
314 sumo_gfx_powergating_enable(rdev
, false);
315 if (pi
->enable_mg_clock_gating
)
316 sumo_mg_clockgating_enable(rdev
, false);
319 static void sumo_calculate_bsp(struct radeon_device
*rdev
,
322 struct sumo_power_info
*pi
= sumo_get_pi(rdev
);
323 u32 xclk
= sumo_get_xclk(rdev
);
325 pi
->pasi
= 65535 * 100 / high_clk
;
326 pi
->asi
= 65535 * 100 / high_clk
;
328 r600_calculate_u_and_p(pi
->asi
,
329 xclk
, 16, &pi
->bsp
, &pi
->bsu
);
331 r600_calculate_u_and_p(pi
->pasi
,
332 xclk
, 16, &pi
->pbsp
, &pi
->pbsu
);
334 pi
->dsp
= BSP(pi
->bsp
) | BSU(pi
->bsu
);
335 pi
->psp
= BSP(pi
->pbsp
) | BSU(pi
->pbsu
);
338 static void sumo_init_bsp(struct radeon_device
*rdev
)
340 struct sumo_power_info
*pi
= sumo_get_pi(rdev
);
342 WREG32(CG_BSP_0
, pi
->psp
);
346 static void sumo_program_bsp(struct radeon_device
*rdev
)
348 struct sumo_power_info
*pi
= sumo_get_pi(rdev
);
349 struct sumo_ps
*ps
= sumo_get_ps(rdev
->pm
.dpm
.requested_ps
);
351 u32 highest_engine_clock
= ps
->levels
[ps
->num_levels
- 1].sclk
;
353 if (ps
->flags
& SUMO_POWERSTATE_FLAGS_BOOST_STATE
)
354 highest_engine_clock
= pi
->boost_pl
.sclk
;
356 sumo_calculate_bsp(rdev
, highest_engine_clock
);
358 for (i
= 0; i
< ps
->num_levels
- 1; i
++)
359 WREG32(CG_BSP_0
+ (i
* 4), pi
->dsp
);
361 WREG32(CG_BSP_0
+ (i
* 4), pi
->psp
);
363 if (ps
->flags
& SUMO_POWERSTATE_FLAGS_BOOST_STATE
)
364 WREG32(CG_BSP_0
+ (BOOST_DPM_LEVEL
* 4), pi
->psp
);
367 static void sumo_write_at(struct radeon_device
*rdev
,
368 u32 index
, u32 value
)
371 WREG32(CG_AT_0
, value
);
373 WREG32(CG_AT_1
, value
);
375 WREG32(CG_AT_2
, value
);
377 WREG32(CG_AT_3
, value
);
379 WREG32(CG_AT_4
, value
);
381 WREG32(CG_AT_5
, value
);
383 WREG32(CG_AT_6
, value
);
385 WREG32(CG_AT_7
, value
);
388 static void sumo_program_at(struct radeon_device
*rdev
)
390 struct sumo_power_info
*pi
= sumo_get_pi(rdev
);
391 struct sumo_ps
*ps
= sumo_get_ps(rdev
->pm
.dpm
.requested_ps
);
396 u32 r
[SUMO_MAX_HARDWARE_POWERLEVELS
];
397 u32 l
[SUMO_MAX_HARDWARE_POWERLEVELS
];
411 for (i
= 0; i
< ps
->num_levels
; i
++) {
412 asi
= (i
== ps
->num_levels
- 1) ? pi
->pasi
: pi
->asi
;
414 m_a
= asi
* ps
->levels
[i
].sclk
/ 100;
416 a_t
= CG_R(m_a
* r
[i
] / 100) | CG_L(m_a
* l
[i
] / 100);
418 sumo_write_at(rdev
, i
, a_t
);
421 if (ps
->flags
& SUMO_POWERSTATE_FLAGS_BOOST_STATE
) {
424 m_a
= asi
* pi
->boost_pl
.sclk
/ 100;
426 a_t
= CG_R(m_a
* r
[ps
->num_levels
- 1] / 100) |
427 CG_L(m_a
* l
[ps
->num_levels
- 1] / 100);
429 sumo_write_at(rdev
, BOOST_DPM_LEVEL
, a_t
);
433 static void sumo_program_tp(struct radeon_device
*rdev
)
436 enum r600_td td
= R600_TD_DFLT
;
438 for (i
= 0; i
< SUMO_PM_NUMBER_OF_TC
; i
++) {
439 WREG32_P(CG_FFCT_0
+ (i
* 4), UTC_0(sumo_utc
[i
]), ~UTC_0_MASK
);
440 WREG32_P(CG_FFCT_0
+ (i
* 4), DTC_0(sumo_dtc
[i
]), ~DTC_0_MASK
);
443 if (td
== R600_TD_AUTO
)
444 WREG32_P(SCLK_PWRMGT_CNTL
, 0, ~FIR_FORCE_TREND_SEL
);
446 WREG32_P(SCLK_PWRMGT_CNTL
, FIR_FORCE_TREND_SEL
, ~FIR_FORCE_TREND_SEL
);
448 if (td
== R600_TD_UP
)
449 WREG32_P(SCLK_PWRMGT_CNTL
, 0, ~FIR_TREND_MODE
);
451 if (td
== R600_TD_DOWN
)
452 WREG32_P(SCLK_PWRMGT_CNTL
, FIR_TREND_MODE
, ~FIR_TREND_MODE
);
455 static void sumo_program_vc(struct radeon_device
*rdev
)
457 WREG32(CG_FTV
, SUMO_VRC_DFLT
);
460 static void sumo_clear_vc(struct radeon_device
*rdev
)
465 static void sumo_program_sstp(struct radeon_device
*rdev
)
468 u32 xclk
= sumo_get_xclk(rdev
);
470 r600_calculate_u_and_p(SUMO_SST_DFLT
,
473 WREG32(CG_SSP
, SSTU(u
) | SST(p
));
476 static void sumo_set_divider_value(struct radeon_device
*rdev
,
477 u32 index
, u32 divider
)
479 u32 reg_index
= index
/ 4;
480 u32 field_index
= index
% 4;
482 if (field_index
== 0)
483 WREG32_P(CG_SCLK_DPM_CTRL
+ (reg_index
* 4),
484 SCLK_FSTATE_0_DIV(divider
), ~SCLK_FSTATE_0_DIV_MASK
);
485 else if (field_index
== 1)
486 WREG32_P(CG_SCLK_DPM_CTRL
+ (reg_index
* 4),
487 SCLK_FSTATE_1_DIV(divider
), ~SCLK_FSTATE_1_DIV_MASK
);
488 else if (field_index
== 2)
489 WREG32_P(CG_SCLK_DPM_CTRL
+ (reg_index
* 4),
490 SCLK_FSTATE_2_DIV(divider
), ~SCLK_FSTATE_2_DIV_MASK
);
491 else if (field_index
== 3)
492 WREG32_P(CG_SCLK_DPM_CTRL
+ (reg_index
* 4),
493 SCLK_FSTATE_3_DIV(divider
), ~SCLK_FSTATE_3_DIV_MASK
);
496 static void sumo_set_ds_dividers(struct radeon_device
*rdev
,
497 u32 index
, u32 divider
)
499 struct sumo_power_info
*pi
= sumo_get_pi(rdev
);
501 if (pi
->enable_sclk_ds
) {
502 u32 dpm_ctrl
= RREG32(CG_SCLK_DPM_CTRL_6
);
504 dpm_ctrl
&= ~(0x7 << (index
* 3));
505 dpm_ctrl
|= (divider
<< (index
* 3));
506 WREG32(CG_SCLK_DPM_CTRL_6
, dpm_ctrl
);
510 static void sumo_set_ss_dividers(struct radeon_device
*rdev
,
511 u32 index
, u32 divider
)
513 struct sumo_power_info
*pi
= sumo_get_pi(rdev
);
515 if (pi
->enable_sclk_ds
) {
516 u32 dpm_ctrl
= RREG32(CG_SCLK_DPM_CTRL_11
);
518 dpm_ctrl
&= ~(0x7 << (index
* 3));
519 dpm_ctrl
|= (divider
<< (index
* 3));
520 WREG32(CG_SCLK_DPM_CTRL_11
, dpm_ctrl
);
524 static void sumo_set_vid(struct radeon_device
*rdev
, u32 index
, u32 vid
)
526 u32 voltage_cntl
= RREG32(CG_DPM_VOLTAGE_CNTL
);
528 voltage_cntl
&= ~(DPM_STATE0_LEVEL_MASK
<< (index
* 2));
529 voltage_cntl
|= (vid
<< (DPM_STATE0_LEVEL_SHIFT
+ index
* 2));
530 WREG32(CG_DPM_VOLTAGE_CNTL
, voltage_cntl
);
533 static void sumo_set_allos_gnb_slow(struct radeon_device
*rdev
, u32 index
, u32 gnb_slow
)
535 struct sumo_power_info
*pi
= sumo_get_pi(rdev
);
537 u32 cg_sclk_dpm_ctrl_3
;
539 if (pi
->driver_nbps_policy_disable
)
542 cg_sclk_dpm_ctrl_3
= RREG32(CG_SCLK_DPM_CTRL_3
);
543 cg_sclk_dpm_ctrl_3
&= ~(GNB_SLOW_FSTATE_0_MASK
<< index
);
544 cg_sclk_dpm_ctrl_3
|= (temp
<< (GNB_SLOW_FSTATE_0_SHIFT
+ index
));
546 WREG32(CG_SCLK_DPM_CTRL_3
, cg_sclk_dpm_ctrl_3
);
549 static void sumo_program_power_level(struct radeon_device
*rdev
,
550 struct sumo_pl
*pl
, u32 index
)
552 struct sumo_power_info
*pi
= sumo_get_pi(rdev
);
554 struct atom_clock_dividers dividers
;
555 u32 ds_en
= RREG32(DEEP_SLEEP_CNTL
) & ENABLE_DS
;
557 ret
= radeon_atom_get_clock_dividers(rdev
, COMPUTE_ENGINE_PLL_PARAM
,
558 pl
->sclk
, false, ÷rs
);
562 sumo_set_divider_value(rdev
, index
, dividers
.post_div
);
564 sumo_set_vid(rdev
, index
, pl
->vddc_index
);
566 if (pl
->ss_divider_index
== 0 || pl
->ds_divider_index
== 0) {
568 WREG32_P(DEEP_SLEEP_CNTL
, 0, ~ENABLE_DS
);
570 sumo_set_ss_dividers(rdev
, index
, pl
->ss_divider_index
);
571 sumo_set_ds_dividers(rdev
, index
, pl
->ds_divider_index
);
574 WREG32_P(DEEP_SLEEP_CNTL
, ENABLE_DS
, ~ENABLE_DS
);
577 sumo_set_allos_gnb_slow(rdev
, index
, pl
->allow_gnb_slow
);
579 if (pi
->enable_boost
)
580 sumo_set_tdp_limit(rdev
, index
, pl
->sclk_dpm_tdp_limit
);
583 static void sumo_power_level_enable(struct radeon_device
*rdev
, u32 index
, bool enable
)
585 u32 reg_index
= index
/ 4;
586 u32 field_index
= index
% 4;
588 if (field_index
== 0)
589 WREG32_P(CG_SCLK_DPM_CTRL
+ (reg_index
* 4),
590 enable
? SCLK_FSTATE_0_VLD
: 0, ~SCLK_FSTATE_0_VLD
);
591 else if (field_index
== 1)
592 WREG32_P(CG_SCLK_DPM_CTRL
+ (reg_index
* 4),
593 enable
? SCLK_FSTATE_1_VLD
: 0, ~SCLK_FSTATE_1_VLD
);
594 else if (field_index
== 2)
595 WREG32_P(CG_SCLK_DPM_CTRL
+ (reg_index
* 4),
596 enable
? SCLK_FSTATE_2_VLD
: 0, ~SCLK_FSTATE_2_VLD
);
597 else if (field_index
== 3)
598 WREG32_P(CG_SCLK_DPM_CTRL
+ (reg_index
* 4),
599 enable
? SCLK_FSTATE_3_VLD
: 0, ~SCLK_FSTATE_3_VLD
);
602 static bool sumo_dpm_enabled(struct radeon_device
*rdev
)
604 if (RREG32(CG_SCLK_DPM_CTRL_3
) & DPM_SCLK_ENABLE
)
610 static void sumo_start_dpm(struct radeon_device
*rdev
)
612 WREG32_P(CG_SCLK_DPM_CTRL_3
, DPM_SCLK_ENABLE
, ~DPM_SCLK_ENABLE
);
615 static void sumo_stop_dpm(struct radeon_device
*rdev
)
617 WREG32_P(CG_SCLK_DPM_CTRL_3
, 0, ~DPM_SCLK_ENABLE
);
620 static void sumo_set_forced_mode(struct radeon_device
*rdev
, bool enable
)
623 WREG32_P(CG_SCLK_DPM_CTRL_3
, FORCE_SCLK_STATE_EN
, ~FORCE_SCLK_STATE_EN
);
625 WREG32_P(CG_SCLK_DPM_CTRL_3
, 0, ~FORCE_SCLK_STATE_EN
);
628 static void sumo_set_forced_mode_enabled(struct radeon_device
*rdev
)
632 sumo_set_forced_mode(rdev
, true);
633 for (i
= 0; i
< rdev
->usec_timeout
; i
++) {
634 if (RREG32(CG_SCLK_STATUS
) & SCLK_OVERCLK_DETECT
)
640 static void sumo_wait_for_level_0(struct radeon_device
*rdev
)
644 for (i
= 0; i
< rdev
->usec_timeout
; i
++) {
645 if ((RREG32(TARGET_AND_CURRENT_PROFILE_INDEX
) & CURR_SCLK_INDEX_MASK
) == 0)
649 for (i
= 0; i
< rdev
->usec_timeout
; i
++) {
650 if ((RREG32(TARGET_AND_CURRENT_PROFILE_INDEX
) & CURR_INDEX_MASK
) == 0)
656 static void sumo_set_forced_mode_disabled(struct radeon_device
*rdev
)
658 sumo_set_forced_mode(rdev
, false);
661 static void sumo_enable_power_level_0(struct radeon_device
*rdev
)
663 sumo_power_level_enable(rdev
, 0, true);
666 static void sumo_patch_boost_state(struct radeon_device
*rdev
)
668 struct sumo_power_info
*pi
= sumo_get_pi(rdev
);
669 struct sumo_ps
*new_ps
= sumo_get_ps(rdev
->pm
.dpm
.requested_ps
);
671 if (new_ps
->flags
& SUMO_POWERSTATE_FLAGS_BOOST_STATE
) {
672 pi
->boost_pl
= new_ps
->levels
[new_ps
->num_levels
- 1];
673 pi
->boost_pl
.sclk
= pi
->sys_info
.boost_sclk
;
674 pi
->boost_pl
.vddc_index
= pi
->sys_info
.boost_vid_2bit
;
675 pi
->boost_pl
.sclk_dpm_tdp_limit
= pi
->sys_info
.sclk_dpm_tdp_limit_boost
;
679 static void sumo_pre_notify_alt_vddnb_change(struct radeon_device
*rdev
)
681 struct sumo_ps
*new_ps
= sumo_get_ps(rdev
->pm
.dpm
.requested_ps
);
682 struct sumo_ps
*old_ps
= sumo_get_ps(rdev
->pm
.dpm
.current_ps
);
687 nbps1_old
= (old_ps
->flags
& SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE
) ? 1 : 0;
689 nbps1_new
= (new_ps
->flags
& SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE
) ? 1 : 0;
691 if (nbps1_old
== 1 && nbps1_new
== 0)
692 sumo_smu_notify_alt_vddnb_change(rdev
, 0, 0);
695 static void sumo_post_notify_alt_vddnb_change(struct radeon_device
*rdev
)
697 struct sumo_ps
*new_ps
= sumo_get_ps(rdev
->pm
.dpm
.requested_ps
);
698 struct sumo_ps
*old_ps
= sumo_get_ps(rdev
->pm
.dpm
.current_ps
);
703 nbps1_old
= (old_ps
->flags
& SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE
)? 1 : 0;
705 nbps1_new
= (new_ps
->flags
& SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE
)? 1 : 0;
707 if (nbps1_old
== 0 && nbps1_new
== 1)
708 sumo_smu_notify_alt_vddnb_change(rdev
, 1, 1);
711 static void sumo_enable_boost(struct radeon_device
*rdev
, bool enable
)
713 struct sumo_ps
*new_ps
= sumo_get_ps(rdev
->pm
.dpm
.requested_ps
);
716 if (new_ps
->flags
& SUMO_POWERSTATE_FLAGS_BOOST_STATE
)
717 sumo_boost_state_enable(rdev
, true);
719 sumo_boost_state_enable(rdev
, false);
722 static void sumo_update_current_power_levels(struct radeon_device
*rdev
)
724 struct sumo_ps
*new_ps
= sumo_get_ps(rdev
->pm
.dpm
.requested_ps
);
725 struct sumo_power_info
*pi
= sumo_get_pi(rdev
);
727 pi
->current_ps
= *new_ps
;
730 static void sumo_set_forced_level(struct radeon_device
*rdev
, u32 index
)
732 WREG32_P(CG_SCLK_DPM_CTRL_3
, FORCE_SCLK_STATE(index
), ~FORCE_SCLK_STATE_MASK
);
735 static void sumo_set_forced_level_0(struct radeon_device
*rdev
)
737 sumo_set_forced_level(rdev
, 0);
740 static void sumo_program_wl(struct radeon_device
*rdev
)
742 struct sumo_ps
*new_ps
= sumo_get_ps(rdev
->pm
.dpm
.requested_ps
);
743 u32 dpm_ctrl4
= RREG32(CG_SCLK_DPM_CTRL_4
);
745 dpm_ctrl4
&= 0xFFFFFF00;
746 dpm_ctrl4
|= (1 << (new_ps
->num_levels
- 1));
748 if (new_ps
->flags
& SUMO_POWERSTATE_FLAGS_BOOST_STATE
)
749 dpm_ctrl4
|= (1 << BOOST_DPM_LEVEL
);
751 WREG32(CG_SCLK_DPM_CTRL_4
, dpm_ctrl4
);
754 static void sumo_program_power_levels_0_to_n(struct radeon_device
*rdev
)
756 struct sumo_power_info
*pi
= sumo_get_pi(rdev
);
757 struct sumo_ps
*new_ps
= sumo_get_ps(rdev
->pm
.dpm
.requested_ps
);
758 struct sumo_ps
*old_ps
= sumo_get_ps(rdev
->pm
.dpm
.current_ps
);
760 u32 n_current_state_levels
= (old_ps
== NULL
) ? 1 : old_ps
->num_levels
;
762 for (i
= 0; i
< new_ps
->num_levels
; i
++) {
763 sumo_program_power_level(rdev
, &new_ps
->levels
[i
], i
);
764 sumo_power_level_enable(rdev
, i
, true);
767 for (i
= new_ps
->num_levels
; i
< n_current_state_levels
; i
++)
768 sumo_power_level_enable(rdev
, i
, false);
770 if (new_ps
->flags
& SUMO_POWERSTATE_FLAGS_BOOST_STATE
)
771 sumo_program_power_level(rdev
, &pi
->boost_pl
, BOOST_DPM_LEVEL
);
774 static void sumo_enable_acpi_pm(struct radeon_device
*rdev
)
776 WREG32_P(GENERAL_PWRMGT
, STATIC_PM_EN
, ~STATIC_PM_EN
);
779 static void sumo_program_power_level_enter_state(struct radeon_device
*rdev
)
781 WREG32_P(CG_SCLK_DPM_CTRL_5
, SCLK_FSTATE_BOOTUP(0), ~SCLK_FSTATE_BOOTUP_MASK
);
784 static void sumo_program_acpi_power_level(struct radeon_device
*rdev
)
786 struct sumo_power_info
*pi
= sumo_get_pi(rdev
);
787 struct atom_clock_dividers dividers
;
790 ret
= radeon_atom_get_clock_dividers(rdev
, COMPUTE_ENGINE_PLL_PARAM
,
796 WREG32_P(CG_ACPI_CNTL
, SCLK_ACPI_DIV(dividers
.post_div
), ~SCLK_ACPI_DIV_MASK
);
797 WREG32_P(CG_ACPI_VOLTAGE_CNTL
, 0, ~ACPI_VOLTAGE_EN
);
800 static void sumo_program_bootup_state(struct radeon_device
*rdev
)
802 struct sumo_power_info
*pi
= sumo_get_pi(rdev
);
803 u32 dpm_ctrl4
= RREG32(CG_SCLK_DPM_CTRL_4
);
806 sumo_program_power_level(rdev
, &pi
->boot_pl
, 0);
808 dpm_ctrl4
&= 0xFFFFFF00;
809 WREG32(CG_SCLK_DPM_CTRL_4
, dpm_ctrl4
);
811 for (i
= 1; i
< 8; i
++)
812 sumo_power_level_enable(rdev
, i
, false);
815 static void sumo_take_smu_control(struct radeon_device
*rdev
, bool enable
)
817 u32 v
= RREG32(DOUT_SCRATCH3
);
824 WREG32(DOUT_SCRATCH3
, v
);
827 static void sumo_enable_sclk_ds(struct radeon_device
*rdev
, bool enable
)
830 u32 deep_sleep_cntl
= RREG32(DEEP_SLEEP_CNTL
);
831 u32 deep_sleep_cntl2
= RREG32(DEEP_SLEEP_CNTL2
);
834 deep_sleep_cntl
&= ~R_DIS
;
835 deep_sleep_cntl
&= ~HS_MASK
;
836 deep_sleep_cntl
|= HS(t
> 4095 ? 4095 : t
);
838 deep_sleep_cntl2
|= LB_UFP_EN
;
839 deep_sleep_cntl2
&= INOUT_C_MASK
;
840 deep_sleep_cntl2
|= INOUT_C(0xf);
842 WREG32(DEEP_SLEEP_CNTL2
, deep_sleep_cntl2
);
843 WREG32(DEEP_SLEEP_CNTL
, deep_sleep_cntl
);
845 WREG32_P(DEEP_SLEEP_CNTL
, 0, ~ENABLE_DS
);
848 static void sumo_program_bootup_at(struct radeon_device
*rdev
)
850 WREG32_P(CG_AT_0
, CG_R(0xffff), ~CG_R_MASK
);
851 WREG32_P(CG_AT_0
, CG_L(0), ~CG_L_MASK
);
854 static void sumo_reset_am(struct radeon_device
*rdev
)
856 WREG32_P(SCLK_PWRMGT_CNTL
, FIR_RESET
, ~FIR_RESET
);
859 static void sumo_start_am(struct radeon_device
*rdev
)
861 WREG32_P(SCLK_PWRMGT_CNTL
, 0, ~FIR_RESET
);
864 static void sumo_program_ttp(struct radeon_device
*rdev
)
866 u32 xclk
= sumo_get_xclk(rdev
);
868 u32 cg_sclk_dpm_ctrl_5
= RREG32(CG_SCLK_DPM_CTRL_5
);
870 r600_calculate_u_and_p(1000,
873 cg_sclk_dpm_ctrl_5
&= ~(TT_TP_MASK
| TT_TU_MASK
);
874 cg_sclk_dpm_ctrl_5
|= TT_TP(p
) | TT_TU(u
);
876 WREG32(CG_SCLK_DPM_CTRL_5
, cg_sclk_dpm_ctrl_5
);
879 static void sumo_program_ttt(struct radeon_device
*rdev
)
881 u32 cg_sclk_dpm_ctrl_3
= RREG32(CG_SCLK_DPM_CTRL_3
);
882 struct sumo_power_info
*pi
= sumo_get_pi(rdev
);
884 cg_sclk_dpm_ctrl_3
&= ~(GNB_TT_MASK
| GNB_THERMTHRO_MASK
);
885 cg_sclk_dpm_ctrl_3
|= GNB_TT(pi
->thermal_auto_throttling
+ 49);
887 WREG32(CG_SCLK_DPM_CTRL_3
, cg_sclk_dpm_ctrl_3
);
891 static void sumo_enable_voltage_scaling(struct radeon_device
*rdev
, bool enable
)
894 WREG32_P(CG_DPM_VOLTAGE_CNTL
, DPM_VOLTAGE_EN
, ~DPM_VOLTAGE_EN
);
895 WREG32_P(CG_CG_VOLTAGE_CNTL
, 0, ~CG_VOLTAGE_EN
);
897 WREG32_P(CG_CG_VOLTAGE_CNTL
, CG_VOLTAGE_EN
, ~CG_VOLTAGE_EN
);
898 WREG32_P(CG_DPM_VOLTAGE_CNTL
, 0, ~DPM_VOLTAGE_EN
);
902 static void sumo_override_cnb_thermal_events(struct radeon_device
*rdev
)
904 WREG32_P(CG_SCLK_DPM_CTRL_3
, CNB_THERMTHRO_MASK_SCLK
,
905 ~CNB_THERMTHRO_MASK_SCLK
);
908 static void sumo_program_dc_hto(struct radeon_device
*rdev
)
910 u32 cg_sclk_dpm_ctrl_4
= RREG32(CG_SCLK_DPM_CTRL_4
);
912 u32 xclk
= sumo_get_xclk(rdev
);
914 r600_calculate_u_and_p(100000,
917 cg_sclk_dpm_ctrl_4
&= ~(DC_HDC_MASK
| DC_HU_MASK
);
918 cg_sclk_dpm_ctrl_4
|= DC_HDC(p
) | DC_HU(u
);
920 WREG32(CG_SCLK_DPM_CTRL_4
, cg_sclk_dpm_ctrl_4
);
923 static void sumo_force_nbp_state(struct radeon_device
*rdev
)
925 struct sumo_power_info
*pi
= sumo_get_pi(rdev
);
926 struct sumo_ps
*new_ps
= sumo_get_ps(rdev
->pm
.dpm
.requested_ps
);
928 if (!pi
->driver_nbps_policy_disable
) {
929 if (new_ps
->flags
& SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE
)
930 WREG32_P(CG_SCLK_DPM_CTRL_3
, FORCE_NB_PSTATE_1
, ~FORCE_NB_PSTATE_1
);
932 WREG32_P(CG_SCLK_DPM_CTRL_3
, 0, ~FORCE_NB_PSTATE_1
);
936 static u32
sumo_get_sleep_divider_from_id(u32 id
)
941 static u32
sumo_get_sleep_divider_id_from_clock(struct radeon_device
*rdev
,
945 struct sumo_power_info
*pi
= sumo_get_pi(rdev
);
948 u32 min
= (min_sclk_in_sr
> SUMO_MINIMUM_ENGINE_CLOCK
) ?
949 min_sclk_in_sr
: SUMO_MINIMUM_ENGINE_CLOCK
;
954 if (!pi
->enable_sclk_ds
)
957 for (i
= SUMO_MAX_DEEPSLEEP_DIVIDER_ID
; ; i
--) {
958 temp
= sclk
/ sumo_get_sleep_divider_from_id(i
);
960 if (temp
>= min
|| i
== 0)
966 static u32
sumo_get_valid_engine_clock(struct radeon_device
*rdev
,
969 struct sumo_power_info
*pi
= sumo_get_pi(rdev
);
972 for (i
= 0; i
< pi
->sys_info
.sclk_voltage_mapping_table
.num_max_dpm_entries
; i
++) {
973 if (pi
->sys_info
.sclk_voltage_mapping_table
.entries
[i
].sclk_frequency
>= lower_limit
)
974 return pi
->sys_info
.sclk_voltage_mapping_table
.entries
[i
].sclk_frequency
;
977 return pi
->sys_info
.sclk_voltage_mapping_table
.entries
[pi
->sys_info
.sclk_voltage_mapping_table
.num_max_dpm_entries
- 1].sclk_frequency
;
980 static void sumo_patch_thermal_state(struct radeon_device
*rdev
,
982 struct sumo_ps
*current_ps
)
984 struct sumo_power_info
*pi
= sumo_get_pi(rdev
);
985 u32 sclk_in_sr
= pi
->sys_info
.min_sclk
; /* ??? */
988 u32 current_index
= 0;
991 current_vddc
= current_ps
->levels
[current_index
].vddc_index
;
992 current_sclk
= current_ps
->levels
[current_index
].sclk
;
994 current_vddc
= pi
->boot_pl
.vddc_index
;
995 current_sclk
= pi
->boot_pl
.sclk
;
998 ps
->levels
[0].vddc_index
= current_vddc
;
1000 if (ps
->levels
[0].sclk
> current_sclk
)
1001 ps
->levels
[0].sclk
= current_sclk
;
1003 ps
->levels
[0].ss_divider_index
=
1004 sumo_get_sleep_divider_id_from_clock(rdev
, ps
->levels
[0].sclk
, sclk_in_sr
);
1006 ps
->levels
[0].ds_divider_index
=
1007 sumo_get_sleep_divider_id_from_clock(rdev
, ps
->levels
[0].sclk
, SUMO_MINIMUM_ENGINE_CLOCK
);
1009 if (ps
->levels
[0].ds_divider_index
> ps
->levels
[0].ss_divider_index
+ 1)
1010 ps
->levels
[0].ds_divider_index
= ps
->levels
[0].ss_divider_index
+ 1;
1012 if (ps
->levels
[0].ss_divider_index
== ps
->levels
[0].ds_divider_index
) {
1013 if (ps
->levels
[0].ss_divider_index
> 1)
1014 ps
->levels
[0].ss_divider_index
= ps
->levels
[0].ss_divider_index
- 1;
1017 if (ps
->levels
[0].ss_divider_index
== 0)
1018 ps
->levels
[0].ds_divider_index
= 0;
1020 if (ps
->levels
[0].ds_divider_index
== 0)
1021 ps
->levels
[0].ss_divider_index
= 0;
1024 static void sumo_apply_state_adjust_rules(struct radeon_device
*rdev
)
1026 struct radeon_ps
*rps
= rdev
->pm
.dpm
.requested_ps
;
1027 struct sumo_ps
*ps
= sumo_get_ps(rps
);
1028 struct sumo_ps
*current_ps
= sumo_get_ps(rdev
->pm
.dpm
.current_ps
);
1029 struct sumo_power_info
*pi
= sumo_get_pi(rdev
);
1030 u32 min_voltage
= 0; /* ??? */
1031 u32 min_sclk
= pi
->sys_info
.min_sclk
; /* XXX check against disp reqs */
1032 u32 sclk_in_sr
= pi
->sys_info
.min_sclk
; /* ??? */
1035 if (rps
->class & ATOM_PPLIB_CLASSIFICATION_THERMAL
)
1036 return sumo_patch_thermal_state(rdev
, ps
, current_ps
);
1038 if (pi
->enable_boost
) {
1039 if (rps
->class & ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE
)
1040 ps
->flags
|= SUMO_POWERSTATE_FLAGS_BOOST_STATE
;
1043 if ((rps
->class & ATOM_PPLIB_CLASSIFICATION_UI_BATTERY
) ||
1044 (rps
->class & ATOM_PPLIB_CLASSIFICATION_SDSTATE
) ||
1045 (rps
->class & ATOM_PPLIB_CLASSIFICATION_HDSTATE
))
1046 ps
->flags
|= SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE
;
1048 for (i
= 0; i
< ps
->num_levels
; i
++) {
1049 if (ps
->levels
[i
].vddc_index
< min_voltage
)
1050 ps
->levels
[i
].vddc_index
= min_voltage
;
1052 if (ps
->levels
[i
].sclk
< min_sclk
)
1053 ps
->levels
[i
].sclk
=
1054 sumo_get_valid_engine_clock(rdev
, min_sclk
);
1056 ps
->levels
[i
].ss_divider_index
=
1057 sumo_get_sleep_divider_id_from_clock(rdev
, ps
->levels
[i
].sclk
, sclk_in_sr
);
1059 ps
->levels
[i
].ds_divider_index
=
1060 sumo_get_sleep_divider_id_from_clock(rdev
, ps
->levels
[i
].sclk
, SUMO_MINIMUM_ENGINE_CLOCK
);
1062 if (ps
->levels
[i
].ds_divider_index
> ps
->levels
[i
].ss_divider_index
+ 1)
1063 ps
->levels
[i
].ds_divider_index
= ps
->levels
[i
].ss_divider_index
+ 1;
1065 if (ps
->levels
[i
].ss_divider_index
== ps
->levels
[i
].ds_divider_index
) {
1066 if (ps
->levels
[i
].ss_divider_index
> 1)
1067 ps
->levels
[i
].ss_divider_index
= ps
->levels
[i
].ss_divider_index
- 1;
1070 if (ps
->levels
[i
].ss_divider_index
== 0)
1071 ps
->levels
[i
].ds_divider_index
= 0;
1073 if (ps
->levels
[i
].ds_divider_index
== 0)
1074 ps
->levels
[i
].ss_divider_index
= 0;
1076 if (ps
->flags
& SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE
)
1077 ps
->levels
[i
].allow_gnb_slow
= 1;
1078 else if ((rps
->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE
) ||
1079 (rps
->class2
& ATOM_PPLIB_CLASSIFICATION2_MVC
))
1080 ps
->levels
[i
].allow_gnb_slow
= 0;
1081 else if (i
== ps
->num_levels
- 1)
1082 ps
->levels
[i
].allow_gnb_slow
= 0;
1084 ps
->levels
[i
].allow_gnb_slow
= 1;
1088 static void sumo_cleanup_asic(struct radeon_device
*rdev
)
1090 sumo_take_smu_control(rdev
, false);
1093 static int sumo_set_thermal_temperature_range(struct radeon_device
*rdev
,
1094 int min_temp
, int max_temp
)
1096 int low_temp
= 0 * 1000;
1097 int high_temp
= 255 * 1000;
1099 if (low_temp
< min_temp
)
1100 low_temp
= min_temp
;
1101 if (high_temp
> max_temp
)
1102 high_temp
= max_temp
;
1103 if (high_temp
< low_temp
) {
1104 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp
, high_temp
);
1108 WREG32_P(CG_THERMAL_INT
, DIG_THERM_INTH(49 + (high_temp
/ 1000)), ~DIG_THERM_INTH_MASK
);
1109 WREG32_P(CG_THERMAL_INT
, DIG_THERM_INTL(49 + (low_temp
/ 1000)), ~DIG_THERM_INTL_MASK
);
1111 rdev
->pm
.dpm
.thermal
.min_temp
= low_temp
;
1112 rdev
->pm
.dpm
.thermal
.max_temp
= high_temp
;
1117 int sumo_dpm_enable(struct radeon_device
*rdev
)
1119 struct sumo_power_info
*pi
= sumo_get_pi(rdev
);
1121 if (sumo_dpm_enabled(rdev
))
1124 sumo_enable_clock_power_gating(rdev
);
1125 sumo_program_bootup_state(rdev
);
1126 sumo_init_bsp(rdev
);
1127 sumo_reset_am(rdev
);
1128 sumo_program_tp(rdev
);
1129 sumo_program_bootup_at(rdev
);
1130 sumo_start_am(rdev
);
1131 if (pi
->enable_auto_thermal_throttling
) {
1132 sumo_program_ttp(rdev
);
1133 sumo_program_ttt(rdev
);
1135 sumo_program_dc_hto(rdev
);
1136 sumo_program_power_level_enter_state(rdev
);
1137 sumo_enable_voltage_scaling(rdev
, true);
1138 sumo_program_sstp(rdev
);
1139 sumo_program_vc(rdev
);
1140 sumo_override_cnb_thermal_events(rdev
);
1141 sumo_start_dpm(rdev
);
1142 sumo_wait_for_level_0(rdev
);
1143 if (pi
->enable_sclk_ds
)
1144 sumo_enable_sclk_ds(rdev
, true);
1145 if (pi
->enable_boost
)
1146 sumo_enable_boost_timer(rdev
);
1148 if (rdev
->irq
.installed
&&
1149 r600_is_internal_thermal_sensor(rdev
->pm
.int_thermal_type
)) {
1150 sumo_set_thermal_temperature_range(rdev
, R600_TEMP_RANGE_MIN
, R600_TEMP_RANGE_MAX
);
1151 rdev
->irq
.dpm_thermal
= true;
1152 radeon_irq_set(rdev
);
1158 void sumo_dpm_disable(struct radeon_device
*rdev
)
1160 struct sumo_power_info
*pi
= sumo_get_pi(rdev
);
1162 if (!sumo_dpm_enabled(rdev
))
1164 sumo_disable_clock_power_gating(rdev
);
1165 if (pi
->enable_sclk_ds
)
1166 sumo_enable_sclk_ds(rdev
, false);
1167 sumo_clear_vc(rdev
);
1168 sumo_wait_for_level_0(rdev
);
1169 sumo_stop_dpm(rdev
);
1170 sumo_enable_voltage_scaling(rdev
, false);
1172 if (rdev
->irq
.installed
&&
1173 r600_is_internal_thermal_sensor(rdev
->pm
.int_thermal_type
)) {
1174 rdev
->irq
.dpm_thermal
= false;
1175 radeon_irq_set(rdev
);
1179 int sumo_dpm_set_power_state(struct radeon_device
*rdev
)
1181 struct sumo_power_info
*pi
= sumo_get_pi(rdev
);
1183 if (pi
->enable_dynamic_patch_ps
)
1184 sumo_apply_state_adjust_rules(rdev
);
1185 sumo_update_current_power_levels(rdev
);
1186 if (pi
->enable_boost
) {
1187 sumo_enable_boost(rdev
, false);
1188 sumo_patch_boost_state(rdev
);
1190 if (pi
->enable_dpm
) {
1191 sumo_pre_notify_alt_vddnb_change(rdev
);
1192 sumo_enable_power_level_0(rdev
);
1193 sumo_set_forced_level_0(rdev
);
1194 sumo_set_forced_mode_enabled(rdev
);
1195 sumo_wait_for_level_0(rdev
);
1196 sumo_program_power_levels_0_to_n(rdev
);
1197 sumo_program_wl(rdev
);
1198 sumo_program_bsp(rdev
);
1199 sumo_program_at(rdev
);
1200 sumo_force_nbp_state(rdev
);
1201 sumo_set_forced_mode_disabled(rdev
);
1202 sumo_set_forced_mode_enabled(rdev
);
1203 sumo_set_forced_mode_disabled(rdev
);
1204 sumo_post_notify_alt_vddnb_change(rdev
);
1206 if (pi
->enable_boost
)
1207 sumo_enable_boost(rdev
, true);
1212 void sumo_dpm_reset_asic(struct radeon_device
*rdev
)
1214 sumo_program_bootup_state(rdev
);
1215 sumo_enable_power_level_0(rdev
);
1216 sumo_set_forced_level_0(rdev
);
1217 sumo_set_forced_mode_enabled(rdev
);
1218 sumo_wait_for_level_0(rdev
);
1219 sumo_set_forced_mode_disabled(rdev
);
1220 sumo_set_forced_mode_enabled(rdev
);
1221 sumo_set_forced_mode_disabled(rdev
);
1224 void sumo_dpm_setup_asic(struct radeon_device
*rdev
)
1226 struct sumo_power_info
*pi
= sumo_get_pi(rdev
);
1228 sumo_initialize_m3_arb(rdev
);
1229 pi
->fw_version
= sumo_get_running_fw_version(rdev
);
1230 DRM_INFO("Found smc ucode version: 0x%08x\n", pi
->fw_version
);
1231 sumo_program_acpi_power_level(rdev
);
1232 sumo_enable_acpi_pm(rdev
);
1233 sumo_take_smu_control(rdev
, true);
1236 void sumo_dpm_display_configuration_changed(struct radeon_device
*rdev
)
1242 struct _ATOM_POWERPLAY_INFO info
;
1243 struct _ATOM_POWERPLAY_INFO_V2 info_2
;
1244 struct _ATOM_POWERPLAY_INFO_V3 info_3
;
1245 struct _ATOM_PPLIB_POWERPLAYTABLE pplib
;
1246 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2
;
1247 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3
;
1250 union pplib_clock_info
{
1251 struct _ATOM_PPLIB_R600_CLOCK_INFO r600
;
1252 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780
;
1253 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen
;
1254 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo
;
1257 union pplib_power_state
{
1258 struct _ATOM_PPLIB_STATE v1
;
1259 struct _ATOM_PPLIB_STATE_V2 v2
;
1262 static void sumo_patch_boot_state(struct radeon_device
*rdev
,
1265 struct sumo_power_info
*pi
= sumo_get_pi(rdev
);
1269 ps
->levels
[0] = pi
->boot_pl
;
1272 static void sumo_parse_pplib_non_clock_info(struct radeon_device
*rdev
,
1273 struct radeon_ps
*rps
,
1274 struct _ATOM_PPLIB_NONCLOCK_INFO
*non_clock_info
,
1277 struct sumo_ps
*ps
= sumo_get_ps(rps
);
1279 rps
->caps
= le32_to_cpu(non_clock_info
->ulCapsAndSettings
);
1280 rps
->class = le16_to_cpu(non_clock_info
->usClassification
);
1281 rps
->class2
= le16_to_cpu(non_clock_info
->usClassification2
);
1283 if (ATOM_PPLIB_NONCLOCKINFO_VER1
< table_rev
) {
1284 rps
->vclk
= le32_to_cpu(non_clock_info
->ulVCLK
);
1285 rps
->dclk
= le32_to_cpu(non_clock_info
->ulDCLK
);
1291 if (rps
->class & ATOM_PPLIB_CLASSIFICATION_BOOT
) {
1292 rdev
->pm
.dpm
.boot_ps
= rps
;
1293 sumo_patch_boot_state(rdev
, ps
);
1295 if (rps
->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE
)
1296 rdev
->pm
.dpm
.uvd_ps
= rps
;
1299 static void sumo_parse_pplib_clock_info(struct radeon_device
*rdev
,
1300 struct radeon_ps
*rps
, int index
,
1301 union pplib_clock_info
*clock_info
)
1303 struct sumo_power_info
*pi
= sumo_get_pi(rdev
);
1304 struct sumo_ps
*ps
= sumo_get_ps(rps
);
1305 struct sumo_pl
*pl
= &ps
->levels
[index
];
1308 sclk
= le16_to_cpu(clock_info
->sumo
.usEngineClockLow
);
1309 sclk
|= clock_info
->sumo
.ucEngineClockHigh
<< 16;
1311 pl
->vddc_index
= clock_info
->sumo
.vddcIndex
;
1312 pl
->sclk_dpm_tdp_limit
= clock_info
->sumo
.tdpLimit
;
1314 ps
->num_levels
= index
+ 1;
1316 if (pi
->enable_sclk_ds
) {
1317 pl
->ds_divider_index
= 5;
1318 pl
->ss_divider_index
= 4;
1322 static int sumo_parse_power_table(struct radeon_device
*rdev
)
1324 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
1325 struct _ATOM_PPLIB_NONCLOCK_INFO
*non_clock_info
;
1326 union pplib_power_state
*power_state
;
1327 int i
, j
, k
, non_clock_array_index
, clock_array_index
;
1328 union pplib_clock_info
*clock_info
;
1329 struct _StateArray
*state_array
;
1330 struct _ClockInfoArray
*clock_info_array
;
1331 struct _NonClockInfoArray
*non_clock_info_array
;
1332 union power_info
*power_info
;
1333 int index
= GetIndexIntoMasterTable(DATA
, PowerPlayInfo
);
1336 u8
*power_state_offset
;
1339 if (!atom_parse_data_header(mode_info
->atom_context
, index
, NULL
,
1340 &frev
, &crev
, &data_offset
))
1342 power_info
= (union power_info
*)(mode_info
->atom_context
->bios
+ data_offset
);
1344 state_array
= (struct _StateArray
*)
1345 (mode_info
->atom_context
->bios
+ data_offset
+
1346 le16_to_cpu(power_info
->pplib
.usStateArrayOffset
));
1347 clock_info_array
= (struct _ClockInfoArray
*)
1348 (mode_info
->atom_context
->bios
+ data_offset
+
1349 le16_to_cpu(power_info
->pplib
.usClockInfoArrayOffset
));
1350 non_clock_info_array
= (struct _NonClockInfoArray
*)
1351 (mode_info
->atom_context
->bios
+ data_offset
+
1352 le16_to_cpu(power_info
->pplib
.usNonClockInfoArrayOffset
));
1354 rdev
->pm
.dpm
.ps
= kzalloc(sizeof(struct radeon_ps
) *
1355 state_array
->ucNumEntries
, GFP_KERNEL
);
1356 if (!rdev
->pm
.dpm
.ps
)
1358 power_state_offset
= (u8
*)state_array
->states
;
1359 rdev
->pm
.dpm
.platform_caps
= le32_to_cpu(power_info
->pplib
.ulPlatformCaps
);
1360 rdev
->pm
.dpm
.backbias_response_time
= le16_to_cpu(power_info
->pplib
.usBackbiasTime
);
1361 rdev
->pm
.dpm
.voltage_response_time
= le16_to_cpu(power_info
->pplib
.usVoltageTime
);
1362 for (i
= 0; i
< state_array
->ucNumEntries
; i
++) {
1363 power_state
= (union pplib_power_state
*)power_state_offset
;
1364 non_clock_array_index
= power_state
->v2
.nonClockInfoIndex
;
1365 non_clock_info
= (struct _ATOM_PPLIB_NONCLOCK_INFO
*)
1366 &non_clock_info_array
->nonClockInfo
[non_clock_array_index
];
1367 if (!rdev
->pm
.power_state
[i
].clock_info
)
1369 ps
= kzalloc(sizeof(struct sumo_ps
), GFP_KERNEL
);
1371 kfree(rdev
->pm
.dpm
.ps
);
1374 rdev
->pm
.dpm
.ps
[i
].ps_priv
= ps
;
1376 for (j
= 0; j
< power_state
->v2
.ucNumDPMLevels
; j
++) {
1377 clock_array_index
= power_state
->v2
.clockInfoIndex
[j
];
1378 if (k
>= SUMO_MAX_HARDWARE_POWERLEVELS
)
1380 clock_info
= (union pplib_clock_info
*)
1381 &clock_info_array
->clockInfo
[clock_array_index
* clock_info_array
->ucEntrySize
];
1382 sumo_parse_pplib_clock_info(rdev
,
1383 &rdev
->pm
.dpm
.ps
[i
], k
,
1387 sumo_parse_pplib_non_clock_info(rdev
, &rdev
->pm
.dpm
.ps
[i
],
1389 non_clock_info_array
->ucEntrySize
);
1390 power_state_offset
+= 2 + power_state
->v2
.ucNumDPMLevels
;
1392 rdev
->pm
.dpm
.num_ps
= state_array
->ucNumEntries
;
1396 static u32
sumo_convert_vid2_to_vid7(struct radeon_device
*rdev
, u32 vid_2bit
)
1398 struct sumo_power_info
*pi
= sumo_get_pi(rdev
);
1401 for (i
= 0; i
< pi
->sys_info
.vid_mapping_table
.num_entries
; i
++) {
1402 if (pi
->sys_info
.vid_mapping_table
.entries
[i
].vid_2bit
== vid_2bit
)
1403 return pi
->sys_info
.vid_mapping_table
.entries
[i
].vid_7bit
;
1406 return pi
->sys_info
.vid_mapping_table
.entries
[pi
->sys_info
.vid_mapping_table
.num_entries
- 1].vid_7bit
;
1409 static u16
sumo_convert_voltage_index_to_value(struct radeon_device
*rdev
,
1412 u32 vid_7bit
= sumo_convert_vid2_to_vid7(rdev
, vid_2bit
);
1414 if (vid_7bit
> 0x7C)
1417 return (15500 - vid_7bit
* 125 + 5) / 10;
1420 static void sumo_construct_display_voltage_mapping_table(struct radeon_device
*rdev
,
1421 ATOM_CLK_VOLT_CAPABILITY
*table
)
1423 struct sumo_power_info
*pi
= sumo_get_pi(rdev
);
1426 for (i
= 0; i
< SUMO_MAX_NUMBER_VOLTAGES
; i
++) {
1427 if (table
[i
].ulMaximumSupportedCLK
== 0)
1430 pi
->sys_info
.disp_clk_voltage_mapping_table
.display_clock_frequency
[i
] =
1431 table
[i
].ulMaximumSupportedCLK
;
1434 pi
->sys_info
.disp_clk_voltage_mapping_table
.num_max_voltage_levels
= i
;
1436 if (pi
->sys_info
.disp_clk_voltage_mapping_table
.num_max_voltage_levels
== 0) {
1437 pi
->sys_info
.disp_clk_voltage_mapping_table
.display_clock_frequency
[0] = 80000;
1438 pi
->sys_info
.disp_clk_voltage_mapping_table
.num_max_voltage_levels
= 1;
1442 static void sumo_construct_sclk_voltage_mapping_table(struct radeon_device
*rdev
,
1443 ATOM_AVAILABLE_SCLK_LIST
*table
)
1445 struct sumo_power_info
*pi
= sumo_get_pi(rdev
);
1450 for (i
= 0; i
< SUMO_MAX_HARDWARE_POWERLEVELS
; i
++) {
1451 if (table
[i
].ulSupportedSCLK
> prev_sclk
) {
1452 pi
->sys_info
.sclk_voltage_mapping_table
.entries
[n
].sclk_frequency
=
1453 table
[i
].ulSupportedSCLK
;
1454 pi
->sys_info
.sclk_voltage_mapping_table
.entries
[n
].vid_2bit
=
1455 table
[i
].usVoltageIndex
;
1456 prev_sclk
= table
[i
].ulSupportedSCLK
;
1461 pi
->sys_info
.sclk_voltage_mapping_table
.num_max_dpm_entries
= n
;
1464 static void sumo_construct_vid_mapping_table(struct radeon_device
*rdev
,
1465 ATOM_AVAILABLE_SCLK_LIST
*table
)
1467 struct sumo_power_info
*pi
= sumo_get_pi(rdev
);
1470 for (i
= 0; i
< SUMO_MAX_HARDWARE_POWERLEVELS
; i
++) {
1471 if (table
[i
].ulSupportedSCLK
!= 0) {
1472 pi
->sys_info
.vid_mapping_table
.entries
[table
[i
].usVoltageIndex
].vid_7bit
=
1473 table
[i
].usVoltageID
;
1474 pi
->sys_info
.vid_mapping_table
.entries
[table
[i
].usVoltageIndex
].vid_2bit
=
1475 table
[i
].usVoltageIndex
;
1479 for (i
= 0; i
< SUMO_MAX_NUMBER_VOLTAGES
; i
++) {
1480 if (pi
->sys_info
.vid_mapping_table
.entries
[i
].vid_7bit
== 0) {
1481 for (j
= i
+ 1; j
< SUMO_MAX_NUMBER_VOLTAGES
; j
++) {
1482 if (pi
->sys_info
.vid_mapping_table
.entries
[j
].vid_7bit
!= 0) {
1483 pi
->sys_info
.vid_mapping_table
.entries
[i
] =
1484 pi
->sys_info
.vid_mapping_table
.entries
[j
];
1485 pi
->sys_info
.vid_mapping_table
.entries
[j
].vid_7bit
= 0;
1490 if (j
== SUMO_MAX_NUMBER_VOLTAGES
)
1495 pi
->sys_info
.vid_mapping_table
.num_entries
= i
;
1499 struct _ATOM_INTEGRATED_SYSTEM_INFO info
;
1500 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2
;
1501 struct _ATOM_INTEGRATED_SYSTEM_INFO_V5 info_5
;
1502 struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 info_6
;
1505 static int sumo_parse_sys_info_table(struct radeon_device
*rdev
)
1507 struct sumo_power_info
*pi
= sumo_get_pi(rdev
);
1508 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
1509 int index
= GetIndexIntoMasterTable(DATA
, IntegratedSystemInfo
);
1510 union igp_info
*igp_info
;
1515 if (atom_parse_data_header(mode_info
->atom_context
, index
, NULL
,
1516 &frev
, &crev
, &data_offset
)) {
1517 igp_info
= (union igp_info
*)(mode_info
->atom_context
->bios
+
1521 DRM_ERROR("Unsupported IGP table: %d %d\n", frev
, crev
);
1524 pi
->sys_info
.bootup_sclk
= le32_to_cpu(igp_info
->info_6
.ulBootUpEngineClock
);
1525 pi
->sys_info
.min_sclk
= le32_to_cpu(igp_info
->info_6
.ulMinEngineClock
);
1526 pi
->sys_info
.bootup_uma_clk
= le32_to_cpu(igp_info
->info_6
.ulBootUpUMAClock
);
1527 pi
->sys_info
.bootup_nb_voltage_index
=
1528 le16_to_cpu(igp_info
->info_6
.usBootUpNBVoltage
);
1529 if (igp_info
->info_6
.ucHtcTmpLmt
== 0)
1530 pi
->sys_info
.htc_tmp_lmt
= 203;
1532 pi
->sys_info
.htc_tmp_lmt
= igp_info
->info_6
.ucHtcTmpLmt
;
1533 if (igp_info
->info_6
.ucHtcHystLmt
== 0)
1534 pi
->sys_info
.htc_hyst_lmt
= 5;
1536 pi
->sys_info
.htc_hyst_lmt
= igp_info
->info_6
.ucHtcHystLmt
;
1537 if (pi
->sys_info
.htc_tmp_lmt
<= pi
->sys_info
.htc_hyst_lmt
) {
1538 DRM_ERROR("The htcTmpLmt should be larger than htcHystLmt.\n");
1540 for (i
= 0; i
< NUMBER_OF_M3ARB_PARAM_SETS
; i
++) {
1541 pi
->sys_info
.csr_m3_arb_cntl_default
[i
] =
1542 le32_to_cpu(igp_info
->info_6
.ulCSR_M3_ARB_CNTL_DEFAULT
[i
]);
1543 pi
->sys_info
.csr_m3_arb_cntl_uvd
[i
] =
1544 le32_to_cpu(igp_info
->info_6
.ulCSR_M3_ARB_CNTL_UVD
[i
]);
1545 pi
->sys_info
.csr_m3_arb_cntl_fs3d
[i
] =
1546 le32_to_cpu(igp_info
->info_6
.ulCSR_M3_ARB_CNTL_FS3D
[i
]);
1548 pi
->sys_info
.sclk_dpm_boost_margin
=
1549 le32_to_cpu(igp_info
->info_6
.SclkDpmBoostMargin
);
1550 pi
->sys_info
.sclk_dpm_throttle_margin
=
1551 le32_to_cpu(igp_info
->info_6
.SclkDpmThrottleMargin
);
1552 pi
->sys_info
.sclk_dpm_tdp_limit_pg
=
1553 le16_to_cpu(igp_info
->info_6
.SclkDpmTdpLimitPG
);
1554 pi
->sys_info
.gnb_tdp_limit
= le16_to_cpu(igp_info
->info_6
.GnbTdpLimit
);
1555 pi
->sys_info
.sclk_dpm_tdp_limit_boost
=
1556 le16_to_cpu(igp_info
->info_6
.SclkDpmTdpLimitBoost
);
1557 pi
->sys_info
.boost_sclk
= le32_to_cpu(igp_info
->info_6
.ulBoostEngineCLock
);
1558 pi
->sys_info
.boost_vid_2bit
= igp_info
->info_6
.ulBoostVid_2bit
;
1559 if (igp_info
->info_6
.EnableBoost
)
1560 pi
->sys_info
.enable_boost
= true;
1562 pi
->sys_info
.enable_boost
= false;
1563 sumo_construct_display_voltage_mapping_table(rdev
,
1564 igp_info
->info_6
.sDISPCLK_Voltage
);
1565 sumo_construct_sclk_voltage_mapping_table(rdev
,
1566 igp_info
->info_6
.sAvail_SCLK
);
1567 sumo_construct_vid_mapping_table(rdev
, igp_info
->info_6
.sAvail_SCLK
);
1573 static void sumo_construct_boot_and_acpi_state(struct radeon_device
*rdev
)
1575 struct sumo_power_info
*pi
= sumo_get_pi(rdev
);
1577 pi
->boot_pl
.sclk
= pi
->sys_info
.bootup_sclk
;
1578 pi
->boot_pl
.vddc_index
= pi
->sys_info
.bootup_nb_voltage_index
;
1579 pi
->boot_pl
.ds_divider_index
= 0;
1580 pi
->boot_pl
.ss_divider_index
= 0;
1581 pi
->boot_pl
.allow_gnb_slow
= 1;
1582 pi
->acpi_pl
= pi
->boot_pl
;
1583 pi
->current_ps
.num_levels
= 1;
1584 pi
->current_ps
.levels
[0] = pi
->boot_pl
;
1587 int sumo_dpm_init(struct radeon_device
*rdev
)
1589 struct sumo_power_info
*pi
;
1590 u32 hw_rev
= (RREG32(HW_REV
) & ATI_REV_ID_MASK
) >> ATI_REV_ID_SHIFT
;
1593 pi
= kzalloc(sizeof(struct sumo_power_info
), GFP_KERNEL
);
1596 rdev
->pm
.dpm
.priv
= pi
;
1598 pi
->driver_nbps_policy_disable
= false;
1599 if ((rdev
->family
== CHIP_PALM
) && (hw_rev
< 3))
1600 pi
->disable_gfx_power_gating_in_uvd
= true;
1602 pi
->disable_gfx_power_gating_in_uvd
= false;
1603 pi
->enable_alt_vddnb
= true;
1604 pi
->enable_sclk_ds
= true;
1605 pi
->enable_dynamic_m3_arbiter
= false;
1606 pi
->enable_dynamic_patch_ps
= true;
1607 pi
->enable_gfx_power_gating
= true;
1608 pi
->enable_gfx_clock_gating
= true;
1609 pi
->enable_mg_clock_gating
= true;
1610 pi
->enable_auto_thermal_throttling
= true;
1612 ret
= sumo_parse_sys_info_table(rdev
);
1616 sumo_construct_boot_and_acpi_state(rdev
);
1618 ret
= sumo_parse_power_table(rdev
);
1622 pi
->pasi
= CYPRESS_HASI_DFLT
;
1623 pi
->asi
= RV770_ASI_DFLT
;
1624 pi
->thermal_auto_throttling
= pi
->sys_info
.htc_tmp_lmt
;
1625 pi
->enable_boost
= pi
->sys_info
.enable_boost
;
1626 pi
->enable_dpm
= true;
1631 void sumo_dpm_print_power_state(struct radeon_device
*rdev
,
1632 struct radeon_ps
*rps
)
1635 struct sumo_ps
*ps
= sumo_get_ps(rps
);
1637 r600_dpm_print_class_info(rps
->class, rps
->class2
);
1638 r600_dpm_print_cap_info(rps
->caps
);
1639 printk("\tuvd vclk: %d dclk: %d\n", rps
->vclk
, rps
->dclk
);
1640 for (i
= 0; i
< ps
->num_levels
; i
++) {
1641 struct sumo_pl
*pl
= &ps
->levels
[i
];
1642 printk("\t\tpower level %d sclk: %u vddc: %u\n",
1644 sumo_convert_voltage_index_to_value(rdev
, pl
->vddc_index
));
1646 r600_dpm_print_ps_status(rdev
, rps
);
1649 void sumo_dpm_fini(struct radeon_device
*rdev
)
1653 sumo_cleanup_asic(rdev
); /* ??? */
1655 for (i
= 0; i
< rdev
->pm
.dpm
.num_ps
; i
++) {
1656 kfree(rdev
->pm
.dpm
.ps
[i
].ps_priv
);
1658 kfree(rdev
->pm
.dpm
.ps
);
1659 kfree(rdev
->pm
.dpm
.priv
);
1662 u32
sumo_dpm_get_sclk(struct radeon_device
*rdev
, bool low
)
1664 struct sumo_ps
*requested_state
= sumo_get_ps(rdev
->pm
.dpm
.requested_ps
);
1667 return requested_state
->levels
[0].sclk
;
1669 return requested_state
->levels
[requested_state
->num_levels
- 1].sclk
;
1672 u32
sumo_dpm_get_mclk(struct radeon_device
*rdev
, bool low
)
1674 struct sumo_power_info
*pi
= sumo_get_pi(rdev
);
1676 return pi
->sys_info
.bootup_uma_clk
;