drivers/gpu/drm/radeon/sumo_smc.c

   1 /*
   2  * Copyright 2012 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/firmware.h>
  25 #include "drmP.h"
  26 #include "radeon.h"
  27 #include "sumod.h"
  28 #include "sumo_dpm.h"
  29 #include "ppsmc.h"
  30 #include "radeon_ucode.h"
  31
  32 #define SUMO_SMU_SERVICE_ROUTINE_PG_INIT        1
  33 #define SUMO_SMU_SERVICE_ROUTINE_ALTVDDNB_NOTIFY  27
  34 #define SUMO_SMU_SERVICE_ROUTINE_GFX_SRV_ID_20  20
  35
  36 struct sumo_ps *sumo_get_ps(struct radeon_ps *rps);
  37 struct sumo_power_info *sumo_get_pi(struct radeon_device *rdev);
  38
  39 static void sumo_send_msg_to_smu(struct radeon_device *rdev, u32 id)
  40 {
  41         u32 gfx_int_req;
  42         int i;
  43
  44         for (i = 0; i < rdev->usec_timeout; i++) {
  45                 if (RREG32(GFX_INT_STATUS) & INT_DONE)
  46                         break;
  47                 udelay(1);
  48         }
  49
  50         gfx_int_req = SERV_INDEX(id) | INT_REQ;
  51         WREG32(GFX_INT_REQ, gfx_int_req);
  52
  53         for (i = 0; i < rdev->usec_timeout; i++) {
  54                 if (RREG32(GFX_INT_REQ) & INT_REQ)
  55                         break;
  56                 udelay(1);
  57         }
  58
  59         for (i = 0; i < rdev->usec_timeout; i++) {
  60                 if (RREG32(GFX_INT_STATUS) & INT_ACK)
  61                         break;
  62                 udelay(1);
  63         }
  64
  65         for (i = 0; i < rdev->usec_timeout; i++) {
  66                 if (RREG32(GFX_INT_STATUS) & INT_DONE)
  67                         break;
  68                 udelay(1);
  69         }
  70
  71         gfx_int_req &= ~INT_REQ;
  72         WREG32(GFX_INT_REQ, gfx_int_req);
  73 }
  74
  75 void sumo_initialize_m3_arb(struct radeon_device *rdev)
  76 {
  77         struct sumo_power_info *pi = sumo_get_pi(rdev);
  78         u32 i;
  79
  80         if (!pi->enable_dynamic_m3_arbiter)
  81                 return;
  82
  83         for (i = 0; i < NUMBER_OF_M3ARB_PARAM_SETS; i++)
  84                 WREG32_RCU(MCU_M3ARB_PARAMS + (i * 4),
  85                            pi->sys_info.csr_m3_arb_cntl_default[i]);
  86
  87         for (; i < NUMBER_OF_M3ARB_PARAM_SETS * 2; i++)
  88                 WREG32_RCU(MCU_M3ARB_PARAMS + (i * 4),
  89                            pi->sys_info.csr_m3_arb_cntl_uvd[i % NUMBER_OF_M3ARB_PARAM_SETS]);
  90
  91         for (; i < NUMBER_OF_M3ARB_PARAM_SETS * 3; i++)
  92                 WREG32_RCU(MCU_M3ARB_PARAMS + (i * 4),
  93                            pi->sys_info.csr_m3_arb_cntl_fs3d[i % NUMBER_OF_M3ARB_PARAM_SETS]);
  94 }
  95
  96 static bool sumo_is_alt_vddnb_supported(struct radeon_device *rdev)
  97 {
  98         struct sumo_power_info *pi = sumo_get_pi(rdev);
  99         bool return_code = false;
 100
 101         if (!pi->enable_alt_vddnb)
 102                 return return_code;
 103
 104         if ((rdev->family == CHIP_SUMO) || (rdev->family == CHIP_SUMO2)) {
 105                 if (pi->fw_version >= 0x00010C00)
 106                         return_code = true;
 107         }
 108
 109         return return_code;
 110 }
 111
 112 void sumo_smu_notify_alt_vddnb_change(struct radeon_device *rdev,
 113                                       bool powersaving, bool force_nbps1)
 114 {
 115         u32 param = 0;
 116
 117         if (!sumo_is_alt_vddnb_supported(rdev))
 118                 return;
 119
 120         if (powersaving)
 121                 param |= 1;
 122
 123         if (force_nbps1)
 124                 param |= 2;
 125
 126         WREG32_RCU(RCU_ALTVDDNB_NOTIFY, param);
 127
 128         sumo_send_msg_to_smu(rdev, SUMO_SMU_SERVICE_ROUTINE_ALTVDDNB_NOTIFY);
 129 }
 130
 131 void sumo_smu_pg_init(struct radeon_device *rdev)
 132 {
 133         sumo_send_msg_to_smu(rdev, SUMO_SMU_SERVICE_ROUTINE_PG_INIT);
 134 }
 135
 136 static u32 sumo_power_of_4(u32 unit)
 137 {
 138         u32 ret = 1;
 139         u32 i;
 140
 141         for (i = 0; i < unit; i++)
 142                 ret *= 4;
 143
 144         return ret;
 145 }
 146
 147 void sumo_enable_boost_timer(struct radeon_device *rdev)
 148 {
 149         struct sumo_power_info *pi = sumo_get_pi(rdev);
 150         u32 period, unit, timer_value;
 151         u32 xclk = sumo_get_xclk(rdev);
 152
 153         unit = (RREG32_RCU(RCU_LCLK_SCALING_CNTL) & LCLK_SCALING_TIMER_PRESCALER_MASK)
 154                 >> LCLK_SCALING_TIMER_PRESCALER_SHIFT;
 155
 156         period = 100 * (xclk / 100 / sumo_power_of_4(unit));
 157
 158         timer_value = (period << 16) | (unit << 4);
 159
 160         WREG32_RCU(RCU_GNB_PWR_REP_TIMER_CNTL, timer_value);
 161         WREG32_RCU(RCU_BOOST_MARGIN, pi->sys_info.sclk_dpm_boost_margin);
 162         WREG32_RCU(RCU_THROTTLE_MARGIN, pi->sys_info.sclk_dpm_throttle_margin);
 163         WREG32_RCU(GNB_TDP_LIMIT, pi->sys_info.gnb_tdp_limit);
 164         WREG32_RCU(RCU_SclkDpmTdpLimitPG, pi->sys_info.sclk_dpm_tdp_limit_pg);
 165
 166         sumo_send_msg_to_smu(rdev, SUMO_SMU_SERVICE_ROUTINE_GFX_SRV_ID_20);
 167 }
 168
 169 void sumo_set_tdp_limit(struct radeon_device *rdev, u32 index, u32 tdp_limit)
 170 {
 171         u32 regoffset = 0;
 172         u32 shift = 0;
 173         u32 mask = 0xFFF;
 174         u32 sclk_dpm_tdp_limit;
 175
 176         switch (index) {
 177         case 0:
 178                 regoffset = RCU_SclkDpmTdpLimit01;
 179                 shift = 16;
 180                 break;
 181         case 1:
 182                 regoffset = RCU_SclkDpmTdpLimit01;
 183                 shift = 0;
 184                 break;
 185         case 2:
 186                 regoffset = RCU_SclkDpmTdpLimit23;
 187                 shift = 16;
 188                 break;
 189         case 3:
 190                 regoffset = RCU_SclkDpmTdpLimit23;
 191                 shift = 0;
 192                 break;
 193         case 4:
 194                 regoffset = RCU_SclkDpmTdpLimit47;
 195                 shift = 16;
 196                 break;
 197         case 7:
 198                 regoffset = RCU_SclkDpmTdpLimit47;
 199                 shift = 0;
 200                 break;
 201         default:
 202                 break;
 203         }
 204
 205         sclk_dpm_tdp_limit = RREG32_RCU(regoffset);
 206         sclk_dpm_tdp_limit &= ~(mask << shift);
 207         sclk_dpm_tdp_limit |= (tdp_limit << shift);
 208         WREG32_RCU(regoffset, sclk_dpm_tdp_limit);
 209 }
 210
 211 void sumo_boost_state_enable(struct radeon_device *rdev, bool enable)
 212 {
 213         u32 boost_disable = RREG32_RCU(RCU_GPU_BOOST_DISABLE);
 214
 215         boost_disable &= 0xFFFFFFFE;
 216         boost_disable |= (enable ? 0 : 1);
 217         WREG32_RCU(RCU_GPU_BOOST_DISABLE, boost_disable);
 218 }
 219
 220 u32 sumo_get_running_fw_version(struct radeon_device *rdev)
 221 {
 222         return RREG32_RCU(RCU_FW_VERSION);
 223 }
 224