drivers/gpu/drm/rcar-du/rcar_du_group.c

   1 /*
   2  * rcar_du_group.c  --  R-Car Display Unit Channels Pair
   3  *
   4  * Copyright (C) 2013-2014 Renesas Electronics Corporation
   5  *
   6  * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  */
  13
  14 /*
  15  * The R8A7779 DU is split in per-CRTC resources (scan-out engine, blending
  16  * unit, timings generator, ...) and device-global resources (start/stop
  17  * control, planes, ...) shared between the two CRTCs.
  18  *
  19  * The R8A7790 introduced a third CRTC with its own set of global resources.
  20  * This would be modeled as two separate DU device instances if it wasn't for
  21  * a handful or resources that are shared between the three CRTCs (mostly
  22  * related to input and output routing). For this reason the R8A7790 DU must be
  23  * modeled as a single device with three CRTCs, two sets of "semi-global"
  24  * resources, and a few device-global resources.
  25  *
  26  * The rcar_du_group object is a driver specific object, without any real
  27  * counterpart in the DU documentation, that models those semi-global resources.
  28  */
  29
  30 #include <linux/clk.h>
  31 #include <linux/io.h>
  32
  33 #include "rcar_du_drv.h"
  34 #include "rcar_du_group.h"
  35 #include "rcar_du_regs.h"
  36
  37 u32 rcar_du_group_read(struct rcar_du_group *rgrp, u32 reg)
  38 {
  39         return rcar_du_read(rgrp->dev, rgrp->mmio_offset + reg);
  40 }
  41
  42 void rcar_du_group_write(struct rcar_du_group *rgrp, u32 reg, u32 data)
  43 {
  44         rcar_du_write(rgrp->dev, rgrp->mmio_offset + reg, data);
  45 }
  46
  47 static void rcar_du_group_setup_pins(struct rcar_du_group *rgrp)
  48 {
  49         u32 defr6 = DEFR6_CODE | DEFR6_ODPM12_DISP;
  50
  51         if (rgrp->num_crtcs > 1)
  52                 defr6 |= DEFR6_ODPM22_DISP;
  53
  54         rcar_du_group_write(rgrp, DEFR6, defr6);
  55 }
  56
  57 static void rcar_du_group_setup_defr8(struct rcar_du_group *rgrp)
  58 {
  59         u32 defr8 = DEFR8_CODE | DEFR8_DEFE8;
  60
  61         /* The DEFR8 register for the first group also controls RGB output
  62          * routing to DPAD0 and VSPD1 routing to DU0/1/2 for DU instances that
  63          * support it.
  64          */
  65         if (rgrp->index == 0) {
  66                 if (rgrp->dev->info->routes[RCAR_DU_OUTPUT_DPAD0].possible_crtcs > 1)
  67                         defr8 |= DEFR8_DRGBS_DU(rgrp->dev->dpad0_source);
  68                 if (rgrp->dev->vspd1_sink == 2)
  69                         defr8 |= DEFR8_VSCS;
  70         }
  71
  72         rcar_du_group_write(rgrp, DEFR8, defr8);
  73 }
  74
  75 static void rcar_du_group_setup(struct rcar_du_group *rgrp)
  76 {
  77         /* Enable extended features */
  78         rcar_du_group_write(rgrp, DEFR, DEFR_CODE | DEFR_DEFE);
  79         rcar_du_group_write(rgrp, DEFR2, DEFR2_CODE | DEFR2_DEFE2G);
  80         rcar_du_group_write(rgrp, DEFR3, DEFR3_CODE | DEFR3_DEFE3);
  81         rcar_du_group_write(rgrp, DEFR4, DEFR4_CODE);
  82         rcar_du_group_write(rgrp, DEFR5, DEFR5_CODE | DEFR5_DEFE5);
  83
  84         rcar_du_group_setup_pins(rgrp);
  85
  86         if (rcar_du_has(rgrp->dev, RCAR_DU_FEATURE_EXT_CTRL_REGS)) {
  87                 rcar_du_group_setup_defr8(rgrp);
  88
  89                 /* Configure input dot clock routing. We currently hardcode the
  90                  * configuration to routing DOTCLKINn to DUn.
  91                  */
  92                 rcar_du_group_write(rgrp, DIDSR, DIDSR_CODE |
  93                                     DIDSR_LCDS_DCLKIN(2) |
  94                                     DIDSR_LCDS_DCLKIN(1) |
  95                                     DIDSR_LCDS_DCLKIN(0) |
  96                                     DIDSR_PDCS_CLK(2, 0) |
  97                                     DIDSR_PDCS_CLK(1, 0) |
  98                                     DIDSR_PDCS_CLK(0, 0));
  99         }
 100
 101         /* Use DS1PR and DS2PR to configure planes priorities and connects the
 102          * superposition 0 to DU0 pins. DU1 pins will be configured dynamically.
 103          */
 104         rcar_du_group_write(rgrp, DORCR, DORCR_PG1D_DS1 | DORCR_DPRS);
 105
 106         /* Apply planes to CRTCs association. */
 107         mutex_lock(&rgrp->lock);
 108         rcar_du_group_write(rgrp, DPTSR, (rgrp->dptsr_planes << 16) |
 109                             rgrp->dptsr_planes);
 110         mutex_unlock(&rgrp->lock);
 111 }
 112
 113 /*
 114  * rcar_du_group_get - Acquire a reference to the DU channels group
 115  *
 116  * Acquiring the first reference setups core registers. A reference must be held
 117  * before accessing any hardware registers.
 118  *
 119  * This function must be called with the DRM mode_config lock held.
 120  *
 121  * Return 0 in case of success or a negative error code otherwise.
 122  */
 123 int rcar_du_group_get(struct rcar_du_group *rgrp)
 124 {
 125         if (rgrp->use_count)
 126                 goto done;
 127
 128         rcar_du_group_setup(rgrp);
 129
 130 done:
 131         rgrp->use_count++;
 132         return 0;
 133 }
 134
 135 /*
 136  * rcar_du_group_put - Release a reference to the DU
 137  *
 138  * This function must be called with the DRM mode_config lock held.
 139  */
 140 void rcar_du_group_put(struct rcar_du_group *rgrp)
 141 {
 142         --rgrp->use_count;
 143 }
 144
 145 static void __rcar_du_group_start_stop(struct rcar_du_group *rgrp, bool start)
 146 {
 147         rcar_du_group_write(rgrp, DSYSR,
 148                 (rcar_du_group_read(rgrp, DSYSR) & ~(DSYSR_DRES | DSYSR_DEN)) |
 149                 (start ? DSYSR_DEN : DSYSR_DRES));
 150 }
 151
 152 void rcar_du_group_start_stop(struct rcar_du_group *rgrp, bool start)
 153 {
 154         /* Many of the configuration bits are only updated when the display
 155          * reset (DRES) bit in DSYSR is set to 1, disabling *both* CRTCs. Some
 156          * of those bits could be pre-configured, but others (especially the
 157          * bits related to plane assignment to display timing controllers) need
 158          * to be modified at runtime.
 159          *
 160          * Restart the display controller if a start is requested. Sorry for the
 161          * flicker. It should be possible to move most of the "DRES-update" bits
 162          * setup to driver initialization time and minimize the number of cases
 163          * when the display controller will have to be restarted.
 164          */
 165         if (start) {
 166                 if (rgrp->used_crtcs++ != 0)
 167                         __rcar_du_group_start_stop(rgrp, false);
 168                 __rcar_du_group_start_stop(rgrp, true);
 169         } else {
 170                 if (--rgrp->used_crtcs == 0)
 171                         __rcar_du_group_start_stop(rgrp, false);
 172         }
 173 }
 174
 175 void rcar_du_group_restart(struct rcar_du_group *rgrp)
 176 {
 177         rgrp->need_restart = false;
 178
 179         __rcar_du_group_start_stop(rgrp, false);
 180         __rcar_du_group_start_stop(rgrp, true);
 181 }
 182
 183 int rcar_du_set_dpad0_vsp1_routing(struct rcar_du_device *rcdu)
 184 {
 185         int ret;
 186
 187         if (!rcar_du_has(rcdu, RCAR_DU_FEATURE_EXT_CTRL_REGS))
 188                 return 0;
 189
 190         /* RGB output routing to DPAD0 and VSP1D routing to DU0/1/2 are
 191          * configured in the DEFR8 register of the first group. As this function
 192          * can be called with the DU0 and DU1 CRTCs disabled, we need to enable
 193          * the first group clock before accessing the register.
 194          */
 195         ret = clk_prepare_enable(rcdu->crtcs[0].clock);
 196         if (ret < 0)
 197                 return ret;
 198
 199         rcar_du_group_setup_defr8(&rcdu->groups[0]);
 200
 201         clk_disable_unprepare(rcdu->crtcs[0].clock);
 202
 203         return 0;
 204 }
 205
 206 int rcar_du_group_set_routing(struct rcar_du_group *rgrp)
 207 {
 208         struct rcar_du_crtc *crtc0 = &rgrp->dev->crtcs[rgrp->index * 2];
 209         u32 dorcr = rcar_du_group_read(rgrp, DORCR);
 210
 211         dorcr &= ~(DORCR_PG2T | DORCR_DK2S | DORCR_PG2D_MASK);
 212
 213         /* Set the DPAD1 pins sources. Select CRTC 0 if explicitly requested and
 214          * CRTC 1 in all other cases to avoid cloning CRTC 0 to DPAD0 and DPAD1
 215          * by default.
 216          */
 217         if (crtc0->outputs & BIT(RCAR_DU_OUTPUT_DPAD1))
 218                 dorcr |= DORCR_PG2D_DS1;
 219         else
 220                 dorcr |= DORCR_PG2T | DORCR_DK2S | DORCR_PG2D_DS2;
 221
 222         rcar_du_group_write(rgrp, DORCR, dorcr);
 223
 224         return rcar_du_set_dpad0_vsp1_routing(rgrp->dev);
 225 }